1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 # Select 32 or 64 bit !! 2 config MIPS
3 config 64BIT !! 3 bool
4 bool "64-bit kernel" if "$(ARCH)" = "x !! 4 default y
5 default "$(ARCH)" != "i386" !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 help !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 Say yes to build a 64-bit kernel - f !! 7 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
8 Say no to build a 32-bit kernel - fo <<
9 <<
10 config X86_32 <<
11 def_bool y <<
12 depends on !64BIT <<
13 # Options that are inherently 32-bit k <<
14 select ARCH_WANT_IPC_PARSE_VERSION <<
15 select CLKSRC_I8253 <<
16 select CLONE_BACKWARDS <<
17 select GENERIC_VDSO_32 <<
18 select HAVE_DEBUG_STACKOVERFLOW <<
19 select KMAP_LOCAL <<
20 select MODULES_USE_ELF_REL <<
21 select OLD_SIGACTION <<
22 select ARCH_SPLIT_ARG64 <<
23 <<
24 config X86_64 <<
25 def_bool y <<
26 depends on 64BIT <<
27 # Options that are inherently 64-bit k <<
28 select ARCH_HAS_GIGANTIC_PAGE <<
29 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
30 select ARCH_SUPPORTS_PER_VMA_LOCK <<
31 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
32 select HAVE_ARCH_SOFT_DIRTY <<
33 select MODULES_USE_ELF_RELA <<
34 select NEED_DMA_MAP_STATE <<
35 select SWIOTLB <<
36 select ARCH_HAS_ELFCORE_COMPAT <<
37 select ZONE_DMA32 <<
38 select EXECMEM if DYNAMIC_FTRACE <<
39 <<
40 config FORCE_DYNAMIC_FTRACE <<
41 def_bool y <<
42 depends on X86_32 <<
43 depends on FUNCTION_TRACER <<
44 select DYNAMIC_FTRACE <<
45 help <<
46 We keep the static function tracing <<
47 in order to test the non static func <<
48 generic code, as other architectures <<
49 only need to keep it around for x86_ <<
50 for x86_32. For x86_32, force DYNAMI <<
51 # <<
52 # Arch settings <<
53 # <<
54 # ( Note that options that are marked 'if X86_ <<
55 # ported to 32-bit as well. ) <<
56 # <<
57 config X86 <<
58 def_bool y <<
59 # <<
60 # Note: keep this list sorted alphabet <<
61 # <<
62 select ACPI_LEGACY_TABLES_LOOKUP <<
63 select ACPI_SYSTEM_POWER_STATES_SUPPOR <<
64 select ACPI_HOTPLUG_CPU <<
65 select ARCH_32BIT_OFF_T <<
66 select ARCH_CLOCKSOURCE_INIT <<
67 select ARCH_CONFIGURES_CPU_MITIGATIONS <<
68 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
69 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
70 select ARCH_ENABLE_MEMORY_HOTPLUG if X <<
71 select ARCH_ENABLE_MEMORY_HOTREMOVE if <<
72 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
73 select ARCH_ENABLE_THP_MIGRATION if X8 <<
74 select ARCH_HAS_ACPI_TABLE_UPGRADE <<
75 select ARCH_HAS_CACHE_LINE_SIZE <<
76 select ARCH_HAS_CPU_CACHE_INVALIDATE_M <<
77 select ARCH_HAS_CPU_FINALIZE_INIT <<
78 select ARCH_HAS_CPU_PASID <<
79 select ARCH_HAS_CURRENT_STACK_POINTER <<
80 select ARCH_HAS_DEBUG_VIRTUAL <<
81 select ARCH_HAS_DEBUG_VM_PGTABLE <<
82 select ARCH_HAS_DEVMEM_IS_ALLOWED <<
83 select ARCH_HAS_DMA_OPS <<
84 select ARCH_HAS_EARLY_DEBUG <<
85 select ARCH_HAS_ELF_RANDOMIZE <<
86 select ARCH_HAS_FAST_MULTIPLIER <<
87 select ARCH_HAS_FORTIFY_SOURCE 8 select ARCH_HAS_FORTIFY_SOURCE
>> 9 select ARCH_HAS_KCOV
>> 10 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
>> 11 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
>> 12 select ARCH_HAS_STRNCPY_FROM_USER
>> 13 select ARCH_HAS_STRNLEN_USER
>> 14 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 15 select ARCH_HAS_UBSAN_SANITIZE_ALL
88 select ARCH_HAS_GCOV_PROFILE_ALL 16 select ARCH_HAS_GCOV_PROFILE_ALL
89 select ARCH_HAS_KCOV !! 17 select ARCH_KEEP_MEMBLOCK
90 select ARCH_HAS_KERNEL_FPU_SUPPORT !! 18 select ARCH_SUPPORTS_UPROBES
91 select ARCH_HAS_MEM_ENCRYPT <<
92 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
93 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
94 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
95 select ARCH_HAS_PMEM_API <<
96 select ARCH_HAS_PTE_DEVMAP <<
97 select ARCH_HAS_PTE_SPECIAL <<
98 select ARCH_HAS_HW_PTE_YOUNG <<
99 select ARCH_HAS_NONLEAF_PMD_YOUNG <<
100 select ARCH_HAS_UACCESS_FLUSHCACHE <<
101 select ARCH_HAS_COPY_MC <<
102 select ARCH_HAS_SET_MEMORY <<
103 select ARCH_HAS_SET_DIRECT_MAP <<
104 select ARCH_HAS_STRICT_KERNEL_RWX <<
105 select ARCH_HAS_STRICT_MODULE_RWX <<
106 select ARCH_HAS_SYNC_CORE_BEFORE_USERM <<
107 select ARCH_HAS_SYSCALL_WRAPPER <<
108 select ARCH_HAS_UBSAN <<
109 select ARCH_HAS_DEBUG_WX <<
110 select ARCH_HAS_ZONE_DMA_SET if EXPERT <<
111 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
112 select ARCH_HAVE_EXTRA_ELF_NOTES <<
113 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
114 select ARCH_MIGHT_HAVE_ACPI_PDC <<
115 select ARCH_MIGHT_HAVE_PC_PARPORT <<
116 select ARCH_MIGHT_HAVE_PC_SERIO <<
117 select ARCH_STACKWALK <<
118 select ARCH_SUPPORTS_ACPI <<
119 select ARCH_SUPPORTS_ATOMIC_RMW <<
120 select ARCH_SUPPORTS_DEBUG_PAGEALLOC <<
121 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
122 select ARCH_SUPPORTS_NUMA_BALANCING <<
123 select ARCH_SUPPORTS_KMAP_LOCAL_FORCE_ <<
124 select ARCH_SUPPORTS_CFI_CLANG <<
125 select ARCH_USES_CFI_TRAPS <<
126 select ARCH_SUPPORTS_LTO_CLANG <<
127 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
128 select ARCH_SUPPORTS_RT <<
129 select ARCH_USE_BUILTIN_BSWAP 19 select ARCH_USE_BUILTIN_BSWAP
130 select ARCH_USE_CMPXCHG_LOCKREF !! 20 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
131 select ARCH_USE_MEMTEST 21 select ARCH_USE_MEMTEST
132 select ARCH_USE_QUEUED_RWLOCKS 22 select ARCH_USE_QUEUED_RWLOCKS
133 select ARCH_USE_QUEUED_SPINLOCKS 23 select ARCH_USE_QUEUED_SPINLOCKS
134 select ARCH_USE_SYM_ANNOTATIONS !! 24 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
135 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU !! 25 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
136 select ARCH_WANT_DEFAULT_BPF_JIT !! 26 select ARCH_WANT_IPC_PARSE_VERSION
137 select ARCH_WANTS_DYNAMIC_TASK_STRUCT <<
138 select ARCH_WANTS_NO_INSTR <<
139 select ARCH_WANT_GENERAL_HUGETLB <<
140 select ARCH_WANT_HUGE_PMD_SHARE <<
141 select ARCH_WANT_LD_ORPHAN_WARN 27 select ARCH_WANT_LD_ORPHAN_WARN
142 select ARCH_WANT_OPTIMIZE_DAX_VMEMMAP <<
143 select ARCH_WANT_OPTIMIZE_HUGETLB_VMEM <<
144 select ARCH_WANTS_THP_SWAP <<
145 select ARCH_HAS_PARANOID_L1D_FLUSH <<
146 select BUILDTIME_TABLE_SORT 28 select BUILDTIME_TABLE_SORT
147 select CLKEVT_I8253 !! 29 select CLONE_BACKWARDS
148 select CLOCKSOURCE_VALIDATE_LAST_CYCLE !! 30 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
149 select CLOCKSOURCE_WATCHDOG !! 31 select CPU_PM if CPU_IDLE
150 # Word-size accesses may read uninitia !! 32 select GENERIC_ATOMIC64 if !64BIT
151 # in strings and cause false KMSAN rep <<
152 select DCACHE_WORD_ACCESS <<
153 select DYNAMIC_SIGFRAME <<
154 select EDAC_ATOMIC_SCRUB <<
155 select EDAC_SUPPORT <<
156 select GENERIC_CLOCKEVENTS_BROADCAST <<
157 select GENERIC_CLOCKEVENTS_BROADCAST_I <<
158 select GENERIC_CLOCKEVENTS_MIN_ADJUST <<
159 select GENERIC_CMOS_UPDATE 33 select GENERIC_CMOS_UPDATE
160 select GENERIC_CPU_AUTOPROBE 34 select GENERIC_CPU_AUTOPROBE
161 select GENERIC_CPU_DEVICES !! 35 select GENERIC_FIND_FIRST_BIT
162 select GENERIC_CPU_VULNERABILITIES !! 36 select GENERIC_GETTIMEOFDAY
163 select GENERIC_EARLY_IOREMAP <<
164 select GENERIC_ENTRY <<
165 select GENERIC_IOMAP 37 select GENERIC_IOMAP
166 select GENERIC_IRQ_EFFECTIVE_AFF_MASK <<
167 select GENERIC_IRQ_MATRIX_ALLOCATOR <<
168 select GENERIC_IRQ_MIGRATION <<
169 select GENERIC_IRQ_PROBE 38 select GENERIC_IRQ_PROBE
170 select GENERIC_IRQ_RESERVATION_MODE <<
171 select GENERIC_IRQ_SHOW 39 select GENERIC_IRQ_SHOW
172 select GENERIC_PENDING_IRQ !! 40 select GENERIC_ISA_DMA if EISA
173 select GENERIC_PTDUMP !! 41 select GENERIC_LIB_ASHLDI3
>> 42 select GENERIC_LIB_ASHRDI3
>> 43 select GENERIC_LIB_CMPDI2
>> 44 select GENERIC_LIB_LSHRDI3
>> 45 select GENERIC_LIB_UCMPDI2
>> 46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
174 select GENERIC_SMP_IDLE_THREAD 47 select GENERIC_SMP_IDLE_THREAD
175 select GENERIC_TIME_VSYSCALL 48 select GENERIC_TIME_VSYSCALL
176 select GENERIC_GETTIMEOFDAY !! 49 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
177 select GENERIC_VDSO_TIME_NS !! 50 select HAVE_ARCH_COMPILER_H
178 select GENERIC_VDSO_OVERFLOW_PROTECT <<
179 select GUP_GET_PXX_LOW_HIGH <<
180 select HARDIRQS_SW_RESEND <<
181 select HARDLOCKUP_CHECK_TIMESTAMP <<
182 select HAS_IOPORT <<
183 select HAVE_ACPI_APEI <<
184 select HAVE_ACPI_APEI_NMI <<
185 select HAVE_ALIGNED_STRUCT_PAGE <<
186 select HAVE_ARCH_AUDITSYSCALL <<
187 select HAVE_ARCH_HUGE_VMAP <<
188 select HAVE_ARCH_HUGE_VMALLOC <<
189 select HAVE_ARCH_JUMP_LABEL 51 select HAVE_ARCH_JUMP_LABEL
190 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 52 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
191 select HAVE_ARCH_KASAN !! 53 select HAVE_ARCH_MMAP_RND_BITS if MMU
192 select HAVE_ARCH_KASAN_VMALLOC !! 54 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
193 select HAVE_ARCH_KFENCE <<
194 select HAVE_ARCH_KMSAN <<
195 select HAVE_ARCH_KGDB <<
196 select HAVE_ARCH_MMAP_RND_BITS <<
197 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
198 select HAVE_ARCH_COMPAT_MMAP_BASES <<
199 select HAVE_ARCH_PREL32_RELOCATIONS <<
200 select HAVE_ARCH_SECCOMP_FILTER 55 select HAVE_ARCH_SECCOMP_FILTER
201 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
202 select HAVE_ARCH_STACKLEAK <<
203 select HAVE_ARCH_TRACEHOOK 56 select HAVE_ARCH_TRACEHOOK
204 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 57 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
205 select HAVE_ARCH_TRANSPARENT_HUGEPAGE_ <<
206 select HAVE_ARCH_USERFAULTFD_WP <<
207 select HAVE_ARCH_USERFAULTFD_MINOR <<
208 select HAVE_ARCH_VMAP_STACK <<
209 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
210 select HAVE_ARCH_WITHIN_STACK_FRAMES <<
211 select HAVE_ASM_MODVERSIONS 58 select HAVE_ASM_MODVERSIONS
212 select HAVE_CMPXCHG_DOUBLE !! 59 select HAVE_CONTEXT_TRACKING
213 select HAVE_CMPXCHG_LOCAL !! 60 select HAVE_TIF_NOHZ
214 select HAVE_CONTEXT_TRACKING_USER <<
215 select HAVE_CONTEXT_TRACKING_USER_OFFS <<
216 select HAVE_C_RECORDMCOUNT 61 select HAVE_C_RECORDMCOUNT
217 select HAVE_OBJTOOL_MCOUNT <<
218 select HAVE_OBJTOOL_NOP_MCOUNT <<
219 select HAVE_BUILDTIME_MCOUNT_SORT <<
220 select HAVE_DEBUG_KMEMLEAK 62 select HAVE_DEBUG_KMEMLEAK
>> 63 select HAVE_DEBUG_STACKOVERFLOW
221 select HAVE_DMA_CONTIGUOUS 64 select HAVE_DMA_CONTIGUOUS
222 select HAVE_DYNAMIC_FTRACE 65 select HAVE_DYNAMIC_FTRACE
223 select HAVE_DYNAMIC_FTRACE_WITH_REGS !! 66 select HAVE_EBPF_JIT if !CPU_MICROMIPS && \
224 select HAVE_DYNAMIC_FTRACE_WITH_ARGS !! 67 !CPU_DADDI_WORKAROUNDS && \
225 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT !! 68 !CPU_R4000_WORKAROUNDS && \
226 select HAVE_SAMPLE_FTRACE_DIRECT !! 69 !CPU_R4400_WORKAROUNDS
227 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
228 select HAVE_EBPF_JIT <<
229 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
230 select HAVE_EISA <<
231 select HAVE_EXIT_THREAD 70 select HAVE_EXIT_THREAD
232 select HAVE_GUP_FAST !! 71 select HAVE_FAST_GUP
233 select HAVE_FENTRY <<
234 select HAVE_FTRACE_MCOUNT_RECORD 72 select HAVE_FTRACE_MCOUNT_RECORD
235 select HAVE_FUNCTION_GRAPH_RETVAL !! 73 select HAVE_FUNCTION_GRAPH_TRACER
236 select HAVE_FUNCTION_GRAPH_TRACER <<
237 select HAVE_FUNCTION_TRACER 74 select HAVE_FUNCTION_TRACER
238 select HAVE_GCC_PLUGINS 75 select HAVE_GCC_PLUGINS
239 select HAVE_HW_BREAKPOINT !! 76 select HAVE_GENERIC_VDSO
240 select HAVE_IOREMAP_PROT 77 select HAVE_IOREMAP_PROT
241 select HAVE_IRQ_EXIT_ON_IRQ_STACK !! 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
242 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_IRQ_TIME_ACCOUNTING
243 select HAVE_JUMP_LABEL_HACK <<
244 select HAVE_KERNEL_BZIP2 <<
245 select HAVE_KERNEL_GZIP <<
246 select HAVE_KERNEL_LZ4 <<
247 select HAVE_KERNEL_LZMA <<
248 select HAVE_KERNEL_LZO <<
249 select HAVE_KERNEL_XZ <<
250 select HAVE_KERNEL_ZSTD <<
251 select HAVE_KPROBES 80 select HAVE_KPROBES
252 select HAVE_KPROBES_ON_FTRACE <<
253 select HAVE_FUNCTION_ERROR_INJECTION <<
254 select HAVE_KRETPROBES 81 select HAVE_KRETPROBES
255 select HAVE_RETHOOK !! 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
256 select HAVE_LIVEPATCH <<
257 select HAVE_MIXED_BREAKPOINTS_REGS <<
258 select HAVE_MOD_ARCH_SPECIFIC 83 select HAVE_MOD_ARCH_SPECIFIC
259 select HAVE_MOVE_PMD <<
260 select HAVE_MOVE_PUD <<
261 select HAVE_NOINSTR_HACK <<
262 select HAVE_NMI 84 select HAVE_NMI
263 select HAVE_NOINSTR_VALIDATION <<
264 select HAVE_OBJTOOL <<
265 select HAVE_OPTPROBES <<
266 select HAVE_PAGE_SIZE_4KB <<
267 select HAVE_PCSPKR_PLATFORM <<
268 select HAVE_PERF_EVENTS 85 select HAVE_PERF_EVENTS
269 select HAVE_PERF_EVENTS_NMI <<
270 select HAVE_HARDLOCKUP_DETECTOR_PERF <<
271 select HAVE_PCI <<
272 select HAVE_PERF_REGS 86 select HAVE_PERF_REGS
273 select HAVE_PERF_USER_STACK_DUMP 87 select HAVE_PERF_USER_STACK_DUMP
274 select MMU_GATHER_RCU_TABLE_FREE <<
275 select MMU_GATHER_MERGE_VMAS <<
276 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
277 select HAVE_REGS_AND_STACK_ACCESS_API 88 select HAVE_REGS_AND_STACK_ACCESS_API
278 select HAVE_RELIABLE_STACKTRACE <<
279 select HAVE_FUNCTION_ARG_ACCESS_API <<
280 select HAVE_SETUP_PER_CPU_AREA <<
281 select HAVE_SOFTIRQ_ON_OWN_STACK <<
282 select HAVE_STACKPROTECTOR <<
283 select HAVE_STACK_VALIDATION <<
284 select HAVE_STATIC_CALL <<
285 select HAVE_STATIC_CALL_INLINE <<
286 select HAVE_PREEMPT_DYNAMIC_CALL <<
287 select HAVE_RSEQ 89 select HAVE_RSEQ
288 select HAVE_RUST !! 90 select HAVE_SPARSE_SYSCALL_NR
>> 91 select HAVE_STACKPROTECTOR
289 select HAVE_SYSCALL_TRACEPOINTS 92 select HAVE_SYSCALL_TRACEPOINTS
290 select HAVE_UACCESS_VALIDATION !! 93 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
291 select HAVE_UNSTABLE_SCHED_CLOCK <<
292 select HAVE_USER_RETURN_NOTIFIER <<
293 select HAVE_GENERIC_VDSO <<
294 select VDSO_GETRANDOM <<
295 select HOTPLUG_PARALLEL <<
296 select HOTPLUG_SMT <<
297 select HOTPLUG_SPLIT_STARTUP <<
298 select IRQ_FORCED_THREADING 94 select IRQ_FORCED_THREADING
299 select LOCK_MM_AND_FIND_VMA !! 95 select ISA if EISA
300 select NEED_PER_CPU_EMBED_FIRST_CHUNK !! 96 select MODULES_USE_ELF_REL if MODULES
301 select NEED_PER_CPU_PAGE_FIRST_CHUNK !! 97 select MODULES_USE_ELF_RELA if MODULES && 64BIT
302 select NEED_SG_DMA_LENGTH !! 98 select PERF_USE_VMALLOC
303 select NUMA_MEMBLKS !! 99 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
304 select PCI_DOMAINS <<
305 select PCI_LOCKLESS_CONFIG <<
306 select PERF_EVENTS <<
307 select RTC_LIB 100 select RTC_LIB
308 select RTC_MC146818_LIB <<
309 select SPARSE_IRQ <<
310 select SYSCTL_EXCEPTION_TRACE 101 select SYSCTL_EXCEPTION_TRACE
311 select THREAD_INFO_IN_TASK <<
312 select TRACE_IRQFLAGS_SUPPORT 102 select TRACE_IRQFLAGS_SUPPORT
313 select TRACE_IRQFLAGS_NMI_SUPPORT !! 103 select VIRT_TO_BUS
314 select USER_STACKTRACE_SUPPORT !! 104 select ARCH_HAS_ELFCORE_COMPAT
315 select HAVE_ARCH_KCSAN <<
316 select PROC_PID_ARCH_STATUS <<
317 select HAVE_ARCH_NODE_DEV_GROUP <<
318 select FUNCTION_ALIGNMENT_16B <<
319 select FUNCTION_ALIGNMENT_4B <<
320 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
321 select HAVE_DYNAMIC_FTRACE_NO_PATCHABL <<
322 105
323 config INSTRUCTION_DECODER !! 106 config MIPS_FIXUP_BIGPHYS_ADDR
324 def_bool y !! 107 bool
325 depends on KPROBES || PERF_EVENTS || U <<
326 108
327 config OUTPUT_FORMAT !! 109 config MIPS_GENERIC
328 string !! 110 bool
329 default "elf32-i386" if X86_32 <<
330 default "elf64-x86-64" if X86_64 <<
331 111
332 config LOCKDEP_SUPPORT !! 112 config MACH_INGENIC
333 def_bool y !! 113 bool
>> 114 select SYS_SUPPORTS_32BIT_KERNEL
>> 115 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 116 select SYS_SUPPORTS_ZBOOT
>> 117 select DMA_NONCOHERENT
>> 118 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 119 select IRQ_MIPS_CPU
>> 120 select PINCTRL
>> 121 select GPIOLIB
>> 122 select COMMON_CLK
>> 123 select GENERIC_IRQ_CHIP
>> 124 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 125 select USE_OF
>> 126 select CPU_SUPPORTS_CPUFREQ
>> 127 select MIPS_EXTERNAL_TIMER
334 128
335 config STACKTRACE_SUPPORT !! 129 menu "Machine selection"
336 def_bool y <<
337 130
338 config MMU !! 131 choice
339 def_bool y !! 132 prompt "System type"
>> 133 default MIPS_GENERIC_KERNEL
340 134
341 config ARCH_MMAP_RND_BITS_MIN !! 135 config MIPS_GENERIC_KERNEL
342 default 28 if 64BIT !! 136 bool "Generic board-agnostic MIPS kernel"
343 default 8 !! 137 select ARCH_HAS_SETUP_DMA_OPS
>> 138 select MIPS_GENERIC
>> 139 select BOOT_RAW
>> 140 select BUILTIN_DTB
>> 141 select CEVT_R4K
>> 142 select CLKSRC_MIPS_GIC
>> 143 select COMMON_CLK
>> 144 select CPU_MIPSR2_IRQ_EI
>> 145 select CPU_MIPSR2_IRQ_VI
>> 146 select CSRC_R4K
>> 147 select DMA_NONCOHERENT
>> 148 select HAVE_PCI
>> 149 select IRQ_MIPS_CPU
>> 150 select MIPS_AUTO_PFN_OFFSET
>> 151 select MIPS_CPU_SCACHE
>> 152 select MIPS_GIC
>> 153 select MIPS_L1_CACHE_SHIFT_7
>> 154 select NO_EXCEPT_FILL
>> 155 select PCI_DRIVERS_GENERIC
>> 156 select SMP_UP if SMP
>> 157 select SWAP_IO_SPACE
>> 158 select SYS_HAS_CPU_MIPS32_R1
>> 159 select SYS_HAS_CPU_MIPS32_R2
>> 160 select SYS_HAS_CPU_MIPS32_R6
>> 161 select SYS_HAS_CPU_MIPS64_R1
>> 162 select SYS_HAS_CPU_MIPS64_R2
>> 163 select SYS_HAS_CPU_MIPS64_R6
>> 164 select SYS_SUPPORTS_32BIT_KERNEL
>> 165 select SYS_SUPPORTS_64BIT_KERNEL
>> 166 select SYS_SUPPORTS_BIG_ENDIAN
>> 167 select SYS_SUPPORTS_HIGHMEM
>> 168 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 169 select SYS_SUPPORTS_MICROMIPS
>> 170 select SYS_SUPPORTS_MIPS16
>> 171 select SYS_SUPPORTS_MIPS_CPS
>> 172 select SYS_SUPPORTS_MULTITHREADING
>> 173 select SYS_SUPPORTS_RELOCATABLE
>> 174 select SYS_SUPPORTS_SMARTMIPS
>> 175 select SYS_SUPPORTS_ZBOOT
>> 176 select UHI_BOOT
>> 177 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 178 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 179 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 180 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 181 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 182 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 183 select USE_OF
>> 184 help
>> 185 Select this to build a kernel which aims to support multiple boards,
>> 186 generally using a flattened device tree passed from the bootloader
>> 187 using the boot protocol defined in the UHI (Unified Hosting
>> 188 Interface) specification.
344 189
345 config ARCH_MMAP_RND_BITS_MAX !! 190 config MIPS_ALCHEMY
346 default 32 if 64BIT !! 191 bool "Alchemy processor based machines"
347 default 16 !! 192 select PHYS_ADDR_T_64BIT
>> 193 select CEVT_R4K
>> 194 select CSRC_R4K
>> 195 select IRQ_MIPS_CPU
>> 196 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 197 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 198 select SYS_HAS_CPU_MIPS32_R1
>> 199 select SYS_SUPPORTS_32BIT_KERNEL
>> 200 select SYS_SUPPORTS_APM_EMULATION
>> 201 select GPIOLIB
>> 202 select SYS_SUPPORTS_ZBOOT
>> 203 select COMMON_CLK
348 204
349 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 205 config AR7
350 default 8 !! 206 bool "Texas Instruments AR7"
>> 207 select BOOT_ELF32
>> 208 select COMMON_CLK
>> 209 select DMA_NONCOHERENT
>> 210 select CEVT_R4K
>> 211 select CSRC_R4K
>> 212 select IRQ_MIPS_CPU
>> 213 select NO_EXCEPT_FILL
>> 214 select SWAP_IO_SPACE
>> 215 select SYS_HAS_CPU_MIPS32_R1
>> 216 select SYS_HAS_EARLY_PRINTK
>> 217 select SYS_SUPPORTS_32BIT_KERNEL
>> 218 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 219 select SYS_SUPPORTS_MIPS16
>> 220 select SYS_SUPPORTS_ZBOOT_UART16550
>> 221 select GPIOLIB
>> 222 select VLYNQ
>> 223 help
>> 224 Support for the Texas Instruments AR7 System-on-a-Chip
>> 225 family: TNETD7100, 7200 and 7300.
351 226
352 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 227 config ATH25
353 default 16 !! 228 bool "Atheros AR231x/AR531x SoC support"
>> 229 select CEVT_R4K
>> 230 select CSRC_R4K
>> 231 select DMA_NONCOHERENT
>> 232 select IRQ_MIPS_CPU
>> 233 select IRQ_DOMAIN
>> 234 select SYS_HAS_CPU_MIPS32_R1
>> 235 select SYS_SUPPORTS_BIG_ENDIAN
>> 236 select SYS_SUPPORTS_32BIT_KERNEL
>> 237 select SYS_HAS_EARLY_PRINTK
>> 238 help
>> 239 Support for Atheros AR231x and Atheros AR531x based boards
>> 240
>> 241 config ATH79
>> 242 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 243 select ARCH_HAS_RESET_CONTROLLER
>> 244 select BOOT_RAW
>> 245 select CEVT_R4K
>> 246 select CSRC_R4K
>> 247 select DMA_NONCOHERENT
>> 248 select GPIOLIB
>> 249 select PINCTRL
>> 250 select COMMON_CLK
>> 251 select IRQ_MIPS_CPU
>> 252 select SYS_HAS_CPU_MIPS32_R2
>> 253 select SYS_HAS_EARLY_PRINTK
>> 254 select SYS_SUPPORTS_32BIT_KERNEL
>> 255 select SYS_SUPPORTS_BIG_ENDIAN
>> 256 select SYS_SUPPORTS_MIPS16
>> 257 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 258 select USE_OF
>> 259 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 260 help
>> 261 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 262
>> 263 config BMIPS_GENERIC
>> 264 bool "Broadcom Generic BMIPS kernel"
>> 265 select ARCH_HAS_RESET_CONTROLLER
>> 266 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 267 select ARCH_HAS_PHYS_TO_DMA
>> 268 select BOOT_RAW
>> 269 select NO_EXCEPT_FILL
>> 270 select USE_OF
>> 271 select CEVT_R4K
>> 272 select CSRC_R4K
>> 273 select SYNC_R4K
>> 274 select COMMON_CLK
>> 275 select BCM6345_L1_IRQ
>> 276 select BCM7038_L1_IRQ
>> 277 select BCM7120_L2_IRQ
>> 278 select BRCMSTB_L2_IRQ
>> 279 select IRQ_MIPS_CPU
>> 280 select DMA_NONCOHERENT
>> 281 select SYS_SUPPORTS_32BIT_KERNEL
>> 282 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 283 select SYS_SUPPORTS_BIG_ENDIAN
>> 284 select SYS_SUPPORTS_HIGHMEM
>> 285 select SYS_HAS_CPU_BMIPS32_3300
>> 286 select SYS_HAS_CPU_BMIPS4350
>> 287 select SYS_HAS_CPU_BMIPS4380
>> 288 select SYS_HAS_CPU_BMIPS5000
>> 289 select SWAP_IO_SPACE
>> 290 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 291 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 292 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 293 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 294 select HARDIRQS_SW_RESEND
>> 295 select HAVE_PCI
>> 296 select PCI_DRIVERS_GENERIC
>> 297 help
>> 298 Build a generic DT-based kernel image that boots on select
>> 299 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 300 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 301 must be set appropriately for your board.
>> 302
>> 303 config BCM47XX
>> 304 bool "Broadcom BCM47XX based boards"
>> 305 select BOOT_RAW
>> 306 select CEVT_R4K
>> 307 select CSRC_R4K
>> 308 select DMA_NONCOHERENT
>> 309 select HAVE_PCI
>> 310 select IRQ_MIPS_CPU
>> 311 select SYS_HAS_CPU_MIPS32_R1
>> 312 select NO_EXCEPT_FILL
>> 313 select SYS_SUPPORTS_32BIT_KERNEL
>> 314 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 315 select SYS_SUPPORTS_MIPS16
>> 316 select SYS_SUPPORTS_ZBOOT
>> 317 select SYS_HAS_EARLY_PRINTK
>> 318 select USE_GENERIC_EARLY_PRINTK_8250
>> 319 select GPIOLIB
>> 320 select LEDS_GPIO_REGISTER
>> 321 select BCM47XX_NVRAM
>> 322 select BCM47XX_SPROM
>> 323 select BCM47XX_SSB if !BCM47XX_BCMA
>> 324 help
>> 325 Support for BCM47XX based boards
>> 326
>> 327 config BCM63XX
>> 328 bool "Broadcom BCM63XX based boards"
>> 329 select BOOT_RAW
>> 330 select CEVT_R4K
>> 331 select CSRC_R4K
>> 332 select SYNC_R4K
>> 333 select DMA_NONCOHERENT
>> 334 select IRQ_MIPS_CPU
>> 335 select SYS_SUPPORTS_32BIT_KERNEL
>> 336 select SYS_SUPPORTS_BIG_ENDIAN
>> 337 select SYS_HAS_EARLY_PRINTK
>> 338 select SYS_HAS_CPU_BMIPS32_3300
>> 339 select SYS_HAS_CPU_BMIPS4350
>> 340 select SYS_HAS_CPU_BMIPS4380
>> 341 select SWAP_IO_SPACE
>> 342 select GPIOLIB
>> 343 select MIPS_L1_CACHE_SHIFT_4
>> 344 select HAVE_LEGACY_CLK
>> 345 help
>> 346 Support for BCM63XX based boards
354 347
355 config SBUS !! 348 config MIPS_COBALT
356 bool !! 349 bool "Cobalt Server"
>> 350 select CEVT_R4K
>> 351 select CSRC_R4K
>> 352 select CEVT_GT641XX
>> 353 select DMA_NONCOHERENT
>> 354 select FORCE_PCI
>> 355 select I8253
>> 356 select I8259
>> 357 select IRQ_MIPS_CPU
>> 358 select IRQ_GT641XX
>> 359 select PCI_GT64XXX_PCI0
>> 360 select SYS_HAS_CPU_NEVADA
>> 361 select SYS_HAS_EARLY_PRINTK
>> 362 select SYS_SUPPORTS_32BIT_KERNEL
>> 363 select SYS_SUPPORTS_64BIT_KERNEL
>> 364 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 365 select USE_GENERIC_EARLY_PRINTK_8250
>> 366
>> 367 config MACH_DECSTATION
>> 368 bool "DECstations"
>> 369 select BOOT_ELF32
>> 370 select CEVT_DS1287
>> 371 select CEVT_R4K if CPU_R4X00
>> 372 select CSRC_IOASIC
>> 373 select CSRC_R4K if CPU_R4X00
>> 374 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 375 select CPU_R4000_WORKAROUNDS if 64BIT
>> 376 select CPU_R4400_WORKAROUNDS if 64BIT
>> 377 select DMA_NONCOHERENT
>> 378 select NO_IOPORT_MAP
>> 379 select IRQ_MIPS_CPU
>> 380 select SYS_HAS_CPU_R3000
>> 381 select SYS_HAS_CPU_R4X00
>> 382 select SYS_SUPPORTS_32BIT_KERNEL
>> 383 select SYS_SUPPORTS_64BIT_KERNEL
>> 384 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 385 select SYS_SUPPORTS_128HZ
>> 386 select SYS_SUPPORTS_256HZ
>> 387 select SYS_SUPPORTS_1024HZ
>> 388 select MIPS_L1_CACHE_SHIFT_4
>> 389 help
>> 390 This enables support for DEC's MIPS based workstations. For details
>> 391 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 392 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 393
>> 394 If you have one of the following DECstation Models you definitely
>> 395 want to choose R4xx0 for the CPU Type:
>> 396
>> 397 DECstation 5000/50
>> 398 DECstation 5000/150
>> 399 DECstation 5000/260
>> 400 DECsystem 5900/260
>> 401
>> 402 otherwise choose R3000.
>> 403
>> 404 config MACH_JAZZ
>> 405 bool "Jazz family of machines"
>> 406 select ARC_MEMORY
>> 407 select ARC_PROMLIB
>> 408 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 409 select ARCH_MIGHT_HAVE_PC_SERIO
>> 410 select DMA_OPS
>> 411 select FW_ARC
>> 412 select FW_ARC32
>> 413 select ARCH_MAY_HAVE_PC_FDC
>> 414 select CEVT_R4K
>> 415 select CSRC_R4K
>> 416 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 417 select GENERIC_ISA_DMA
>> 418 select HAVE_PCSPKR_PLATFORM
>> 419 select IRQ_MIPS_CPU
>> 420 select I8253
>> 421 select I8259
>> 422 select ISA
>> 423 select SYS_HAS_CPU_R4X00
>> 424 select SYS_SUPPORTS_32BIT_KERNEL
>> 425 select SYS_SUPPORTS_64BIT_KERNEL
>> 426 select SYS_SUPPORTS_100HZ
>> 427 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 428 help
>> 429 This a family of machines based on the MIPS R4030 chipset which was
>> 430 used by several vendors to build RISC/os and Windows NT workstations.
>> 431 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 432 Olivetti M700-10 workstations.
>> 433
>> 434 config MACH_INGENIC_SOC
>> 435 bool "Ingenic SoC based machines"
>> 436 select MIPS_GENERIC
>> 437 select MACH_INGENIC
>> 438 select SYS_SUPPORTS_ZBOOT_UART16550
>> 439 select CPU_SUPPORTS_CPUFREQ
>> 440 select MIPS_EXTERNAL_TIMER
>> 441
>> 442 config LANTIQ
>> 443 bool "Lantiq based platforms"
>> 444 select DMA_NONCOHERENT
>> 445 select IRQ_MIPS_CPU
>> 446 select CEVT_R4K
>> 447 select CSRC_R4K
>> 448 select SYS_HAS_CPU_MIPS32_R1
>> 449 select SYS_HAS_CPU_MIPS32_R2
>> 450 select SYS_SUPPORTS_BIG_ENDIAN
>> 451 select SYS_SUPPORTS_32BIT_KERNEL
>> 452 select SYS_SUPPORTS_MIPS16
>> 453 select SYS_SUPPORTS_MULTITHREADING
>> 454 select SYS_SUPPORTS_VPE_LOADER
>> 455 select SYS_HAS_EARLY_PRINTK
>> 456 select GPIOLIB
>> 457 select SWAP_IO_SPACE
>> 458 select BOOT_RAW
>> 459 select HAVE_LEGACY_CLK
>> 460 select USE_OF
>> 461 select PINCTRL
>> 462 select PINCTRL_LANTIQ
>> 463 select ARCH_HAS_RESET_CONTROLLER
>> 464 select RESET_CONTROLLER
357 465
358 config GENERIC_ISA_DMA !! 466 config MACH_LOONGSON32
359 def_bool y !! 467 bool "Loongson 32-bit family of machines"
360 depends on ISA_DMA_API !! 468 select SYS_SUPPORTS_ZBOOT
>> 469 help
>> 470 This enables support for the Loongson-1 family of machines.
361 471
362 config GENERIC_CSUM !! 472 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 473 the Institute of Computing Technology (ICT), Chinese Academy of
>> 474 Sciences (CAS).
>> 475
>> 476 config MACH_LOONGSON2EF
>> 477 bool "Loongson-2E/F family of machines"
>> 478 select SYS_SUPPORTS_ZBOOT
>> 479 help
>> 480 This enables the support of early Loongson-2E/F family of machines.
>> 481
>> 482 config MACH_LOONGSON64
>> 483 bool "Loongson 64-bit family of machines"
>> 484 select ARCH_SPARSEMEM_ENABLE
>> 485 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 486 select ARCH_MIGHT_HAVE_PC_SERIO
>> 487 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 488 select BOOT_ELF32
>> 489 select BOARD_SCACHE
>> 490 select CSRC_R4K
>> 491 select CEVT_R4K
>> 492 select CPU_HAS_WB
>> 493 select FORCE_PCI
>> 494 select ISA
>> 495 select I8259
>> 496 select IRQ_MIPS_CPU
>> 497 select NO_EXCEPT_FILL
>> 498 select NR_CPUS_DEFAULT_64
>> 499 select USE_GENERIC_EARLY_PRINTK_8250
>> 500 select PCI_DRIVERS_GENERIC
>> 501 select SYS_HAS_CPU_LOONGSON64
>> 502 select SYS_HAS_EARLY_PRINTK
>> 503 select SYS_SUPPORTS_SMP
>> 504 select SYS_SUPPORTS_HOTPLUG_CPU
>> 505 select SYS_SUPPORTS_NUMA
>> 506 select SYS_SUPPORTS_64BIT_KERNEL
>> 507 select SYS_SUPPORTS_HIGHMEM
>> 508 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 509 select SYS_SUPPORTS_ZBOOT
>> 510 select SYS_SUPPORTS_RELOCATABLE
>> 511 select ZONE_DMA32
>> 512 select COMMON_CLK
>> 513 select USE_OF
>> 514 select BUILTIN_DTB
>> 515 select PCI_HOST_GENERIC
>> 516 help
>> 517 This enables the support of Loongson-2/3 family of machines.
>> 518
>> 519 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 520 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 521 and Loongson-2F which will be removed), developed by the Institute
>> 522 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 523
>> 524 config MIPS_MALTA
>> 525 bool "MIPS Malta board"
>> 526 select ARCH_MAY_HAVE_PC_FDC
>> 527 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 528 select ARCH_MIGHT_HAVE_PC_SERIO
>> 529 select BOOT_ELF32
>> 530 select BOOT_RAW
>> 531 select BUILTIN_DTB
>> 532 select CEVT_R4K
>> 533 select CLKSRC_MIPS_GIC
>> 534 select COMMON_CLK
>> 535 select CSRC_R4K
>> 536 select DMA_NONCOHERENT
>> 537 select GENERIC_ISA_DMA
>> 538 select HAVE_PCSPKR_PLATFORM
>> 539 select HAVE_PCI
>> 540 select I8253
>> 541 select I8259
>> 542 select IRQ_MIPS_CPU
>> 543 select MIPS_BONITO64
>> 544 select MIPS_CPU_SCACHE
>> 545 select MIPS_GIC
>> 546 select MIPS_L1_CACHE_SHIFT_6
>> 547 select MIPS_MSC
>> 548 select PCI_GT64XXX_PCI0
>> 549 select SMP_UP if SMP
>> 550 select SWAP_IO_SPACE
>> 551 select SYS_HAS_CPU_MIPS32_R1
>> 552 select SYS_HAS_CPU_MIPS32_R2
>> 553 select SYS_HAS_CPU_MIPS32_R3_5
>> 554 select SYS_HAS_CPU_MIPS32_R5
>> 555 select SYS_HAS_CPU_MIPS32_R6
>> 556 select SYS_HAS_CPU_MIPS64_R1
>> 557 select SYS_HAS_CPU_MIPS64_R2
>> 558 select SYS_HAS_CPU_MIPS64_R6
>> 559 select SYS_HAS_CPU_NEVADA
>> 560 select SYS_HAS_CPU_RM7000
>> 561 select SYS_SUPPORTS_32BIT_KERNEL
>> 562 select SYS_SUPPORTS_64BIT_KERNEL
>> 563 select SYS_SUPPORTS_BIG_ENDIAN
>> 564 select SYS_SUPPORTS_HIGHMEM
>> 565 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 566 select SYS_SUPPORTS_MICROMIPS
>> 567 select SYS_SUPPORTS_MIPS16
>> 568 select SYS_SUPPORTS_MIPS_CMP
>> 569 select SYS_SUPPORTS_MIPS_CPS
>> 570 select SYS_SUPPORTS_MULTITHREADING
>> 571 select SYS_SUPPORTS_RELOCATABLE
>> 572 select SYS_SUPPORTS_SMARTMIPS
>> 573 select SYS_SUPPORTS_VPE_LOADER
>> 574 select SYS_SUPPORTS_ZBOOT
>> 575 select USE_OF
>> 576 select WAR_ICACHE_REFILLS
>> 577 select ZONE_DMA32 if 64BIT
>> 578 help
>> 579 This enables support for the MIPS Technologies Malta evaluation
>> 580 board.
>> 581
>> 582 config MACH_PIC32
>> 583 bool "Microchip PIC32 Family"
>> 584 help
>> 585 This enables support for the Microchip PIC32 family of platforms.
>> 586
>> 587 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 588 microcontrollers.
>> 589
>> 590 config MACH_VR41XX
>> 591 bool "NEC VR4100 series based machines"
>> 592 select CEVT_R4K
>> 593 select CSRC_R4K
>> 594 select SYS_HAS_CPU_VR41XX
>> 595 select SYS_SUPPORTS_MIPS16
>> 596 select GPIOLIB
>> 597
>> 598 config MACH_NINTENDO64
>> 599 bool "Nintendo 64 console"
>> 600 select CEVT_R4K
>> 601 select CSRC_R4K
>> 602 select SYS_HAS_CPU_R4300
>> 603 select SYS_SUPPORTS_BIG_ENDIAN
>> 604 select SYS_SUPPORTS_ZBOOT
>> 605 select SYS_SUPPORTS_32BIT_KERNEL
>> 606 select SYS_SUPPORTS_64BIT_KERNEL
>> 607 select DMA_NONCOHERENT
>> 608 select IRQ_MIPS_CPU
>> 609
>> 610 config RALINK
>> 611 bool "Ralink based machines"
>> 612 select CEVT_R4K
>> 613 select COMMON_CLK
>> 614 select CSRC_R4K
>> 615 select BOOT_RAW
>> 616 select DMA_NONCOHERENT
>> 617 select IRQ_MIPS_CPU
>> 618 select USE_OF
>> 619 select SYS_HAS_CPU_MIPS32_R1
>> 620 select SYS_HAS_CPU_MIPS32_R2
>> 621 select SYS_SUPPORTS_32BIT_KERNEL
>> 622 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 623 select SYS_SUPPORTS_MIPS16
>> 624 select SYS_SUPPORTS_ZBOOT
>> 625 select SYS_HAS_EARLY_PRINTK
>> 626 select ARCH_HAS_RESET_CONTROLLER
>> 627 select RESET_CONTROLLER
>> 628
>> 629 config MACH_REALTEK_RTL
>> 630 bool "Realtek RTL838x/RTL839x based machines"
>> 631 select MIPS_GENERIC
>> 632 select DMA_NONCOHERENT
>> 633 select IRQ_MIPS_CPU
>> 634 select CSRC_R4K
>> 635 select CEVT_R4K
>> 636 select SYS_HAS_CPU_MIPS32_R1
>> 637 select SYS_HAS_CPU_MIPS32_R2
>> 638 select SYS_SUPPORTS_BIG_ENDIAN
>> 639 select SYS_SUPPORTS_32BIT_KERNEL
>> 640 select SYS_SUPPORTS_MIPS16
>> 641 select SYS_SUPPORTS_MULTITHREADING
>> 642 select SYS_SUPPORTS_VPE_LOADER
>> 643 select SYS_HAS_EARLY_PRINTK
>> 644 select SYS_HAS_EARLY_PRINTK_8250
>> 645 select USE_GENERIC_EARLY_PRINTK_8250
>> 646 select BOOT_RAW
>> 647 select PINCTRL
>> 648 select USE_OF
>> 649
>> 650 config SGI_IP22
>> 651 bool "SGI IP22 (Indy/Indigo2)"
>> 652 select ARC_MEMORY
>> 653 select ARC_PROMLIB
>> 654 select FW_ARC
>> 655 select FW_ARC32
>> 656 select ARCH_MIGHT_HAVE_PC_SERIO
>> 657 select BOOT_ELF32
>> 658 select CEVT_R4K
>> 659 select CSRC_R4K
>> 660 select DEFAULT_SGI_PARTITION
>> 661 select DMA_NONCOHERENT
>> 662 select HAVE_EISA
>> 663 select I8253
>> 664 select I8259
>> 665 select IP22_CPU_SCACHE
>> 666 select IRQ_MIPS_CPU
>> 667 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 668 select SGI_HAS_I8042
>> 669 select SGI_HAS_INDYDOG
>> 670 select SGI_HAS_HAL2
>> 671 select SGI_HAS_SEEQ
>> 672 select SGI_HAS_WD93
>> 673 select SGI_HAS_ZILOG
>> 674 select SWAP_IO_SPACE
>> 675 select SYS_HAS_CPU_R4X00
>> 676 select SYS_HAS_CPU_R5000
>> 677 select SYS_HAS_EARLY_PRINTK
>> 678 select SYS_SUPPORTS_32BIT_KERNEL
>> 679 select SYS_SUPPORTS_64BIT_KERNEL
>> 680 select SYS_SUPPORTS_BIG_ENDIAN
>> 681 select WAR_R4600_V1_INDEX_ICACHEOP
>> 682 select WAR_R4600_V1_HIT_CACHEOP
>> 683 select WAR_R4600_V2_HIT_CACHEOP
>> 684 select MIPS_L1_CACHE_SHIFT_7
>> 685 help
>> 686 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 687 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 688 that runs on these, say Y here.
>> 689
>> 690 config SGI_IP27
>> 691 bool "SGI IP27 (Origin200/2000)"
>> 692 select ARCH_HAS_PHYS_TO_DMA
>> 693 select ARCH_SPARSEMEM_ENABLE
>> 694 select FW_ARC
>> 695 select FW_ARC64
>> 696 select ARC_CMDLINE_ONLY
>> 697 select BOOT_ELF64
>> 698 select DEFAULT_SGI_PARTITION
>> 699 select FORCE_PCI
>> 700 select SYS_HAS_EARLY_PRINTK
>> 701 select HAVE_PCI
>> 702 select IRQ_MIPS_CPU
>> 703 select IRQ_DOMAIN_HIERARCHY
>> 704 select NR_CPUS_DEFAULT_64
>> 705 select PCI_DRIVERS_GENERIC
>> 706 select PCI_XTALK_BRIDGE
>> 707 select SYS_HAS_CPU_R10000
>> 708 select SYS_SUPPORTS_64BIT_KERNEL
>> 709 select SYS_SUPPORTS_BIG_ENDIAN
>> 710 select SYS_SUPPORTS_NUMA
>> 711 select SYS_SUPPORTS_SMP
>> 712 select WAR_R10000_LLSC
>> 713 select MIPS_L1_CACHE_SHIFT_7
>> 714 select NUMA
>> 715 help
>> 716 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 717 workstations. To compile a Linux kernel that runs on these, say Y
>> 718 here.
>> 719
>> 720 config SGI_IP28
>> 721 bool "SGI IP28 (Indigo2 R10k)"
>> 722 select ARC_MEMORY
>> 723 select ARC_PROMLIB
>> 724 select FW_ARC
>> 725 select FW_ARC64
>> 726 select ARCH_MIGHT_HAVE_PC_SERIO
>> 727 select BOOT_ELF64
>> 728 select CEVT_R4K
>> 729 select CSRC_R4K
>> 730 select DEFAULT_SGI_PARTITION
>> 731 select DMA_NONCOHERENT
>> 732 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 733 select IRQ_MIPS_CPU
>> 734 select HAVE_EISA
>> 735 select I8253
>> 736 select I8259
>> 737 select SGI_HAS_I8042
>> 738 select SGI_HAS_INDYDOG
>> 739 select SGI_HAS_HAL2
>> 740 select SGI_HAS_SEEQ
>> 741 select SGI_HAS_WD93
>> 742 select SGI_HAS_ZILOG
>> 743 select SWAP_IO_SPACE
>> 744 select SYS_HAS_CPU_R10000
>> 745 select SYS_HAS_EARLY_PRINTK
>> 746 select SYS_SUPPORTS_64BIT_KERNEL
>> 747 select SYS_SUPPORTS_BIG_ENDIAN
>> 748 select WAR_R10000_LLSC
>> 749 select MIPS_L1_CACHE_SHIFT_7
>> 750 help
>> 751 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 752 kernel that runs on these, say Y here.
>> 753
>> 754 config SGI_IP30
>> 755 bool "SGI IP30 (Octane/Octane2)"
>> 756 select ARCH_HAS_PHYS_TO_DMA
>> 757 select FW_ARC
>> 758 select FW_ARC64
>> 759 select BOOT_ELF64
>> 760 select CEVT_R4K
>> 761 select CSRC_R4K
>> 762 select FORCE_PCI
>> 763 select SYNC_R4K if SMP
>> 764 select ZONE_DMA32
>> 765 select HAVE_PCI
>> 766 select IRQ_MIPS_CPU
>> 767 select IRQ_DOMAIN_HIERARCHY
>> 768 select NR_CPUS_DEFAULT_2
>> 769 select PCI_DRIVERS_GENERIC
>> 770 select PCI_XTALK_BRIDGE
>> 771 select SYS_HAS_EARLY_PRINTK
>> 772 select SYS_HAS_CPU_R10000
>> 773 select SYS_SUPPORTS_64BIT_KERNEL
>> 774 select SYS_SUPPORTS_BIG_ENDIAN
>> 775 select SYS_SUPPORTS_SMP
>> 776 select WAR_R10000_LLSC
>> 777 select MIPS_L1_CACHE_SHIFT_7
>> 778 select ARC_MEMORY
>> 779 help
>> 780 These are the SGI Octane and Octane2 graphics workstations. To
>> 781 compile a Linux kernel that runs on these, say Y here.
>> 782
>> 783 config SGI_IP32
>> 784 bool "SGI IP32 (O2)"
>> 785 select ARC_MEMORY
>> 786 select ARC_PROMLIB
>> 787 select ARCH_HAS_PHYS_TO_DMA
>> 788 select FW_ARC
>> 789 select FW_ARC32
>> 790 select BOOT_ELF32
>> 791 select CEVT_R4K
>> 792 select CSRC_R4K
>> 793 select DMA_NONCOHERENT
>> 794 select HAVE_PCI
>> 795 select IRQ_MIPS_CPU
>> 796 select R5000_CPU_SCACHE
>> 797 select RM7000_CPU_SCACHE
>> 798 select SYS_HAS_CPU_R5000
>> 799 select SYS_HAS_CPU_R10000 if BROKEN
>> 800 select SYS_HAS_CPU_RM7000
>> 801 select SYS_HAS_CPU_NEVADA
>> 802 select SYS_SUPPORTS_64BIT_KERNEL
>> 803 select SYS_SUPPORTS_BIG_ENDIAN
>> 804 select WAR_ICACHE_REFILLS
>> 805 help
>> 806 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 807
>> 808 config SIBYTE_CRHINE
>> 809 bool "Sibyte BCM91120C-CRhine"
>> 810 select BOOT_ELF32
>> 811 select SIBYTE_BCM1120
>> 812 select SWAP_IO_SPACE
>> 813 select SYS_HAS_CPU_SB1
>> 814 select SYS_SUPPORTS_BIG_ENDIAN
>> 815 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 816
>> 817 config SIBYTE_CARMEL
>> 818 bool "Sibyte BCM91120x-Carmel"
>> 819 select BOOT_ELF32
>> 820 select SIBYTE_BCM1120
>> 821 select SWAP_IO_SPACE
>> 822 select SYS_HAS_CPU_SB1
>> 823 select SYS_SUPPORTS_BIG_ENDIAN
>> 824 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 825
>> 826 config SIBYTE_CRHONE
>> 827 bool "Sibyte BCM91125C-CRhone"
>> 828 select BOOT_ELF32
>> 829 select SIBYTE_BCM1125
>> 830 select SWAP_IO_SPACE
>> 831 select SYS_HAS_CPU_SB1
>> 832 select SYS_SUPPORTS_BIG_ENDIAN
>> 833 select SYS_SUPPORTS_HIGHMEM
>> 834 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 835
>> 836 config SIBYTE_RHONE
>> 837 bool "Sibyte BCM91125E-Rhone"
>> 838 select BOOT_ELF32
>> 839 select SIBYTE_BCM1125H
>> 840 select SWAP_IO_SPACE
>> 841 select SYS_HAS_CPU_SB1
>> 842 select SYS_SUPPORTS_BIG_ENDIAN
>> 843 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 844
>> 845 config SIBYTE_SWARM
>> 846 bool "Sibyte BCM91250A-SWARM"
>> 847 select BOOT_ELF32
>> 848 select HAVE_PATA_PLATFORM
>> 849 select SIBYTE_SB1250
>> 850 select SWAP_IO_SPACE
>> 851 select SYS_HAS_CPU_SB1
>> 852 select SYS_SUPPORTS_BIG_ENDIAN
>> 853 select SYS_SUPPORTS_HIGHMEM
>> 854 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 855 select ZONE_DMA32 if 64BIT
>> 856 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 857
>> 858 config SIBYTE_LITTLESUR
>> 859 bool "Sibyte BCM91250C2-LittleSur"
>> 860 select BOOT_ELF32
>> 861 select HAVE_PATA_PLATFORM
>> 862 select SIBYTE_SB1250
>> 863 select SWAP_IO_SPACE
>> 864 select SYS_HAS_CPU_SB1
>> 865 select SYS_SUPPORTS_BIG_ENDIAN
>> 866 select SYS_SUPPORTS_HIGHMEM
>> 867 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 868 select ZONE_DMA32 if 64BIT
>> 869
>> 870 config SIBYTE_SENTOSA
>> 871 bool "Sibyte BCM91250E-Sentosa"
>> 872 select BOOT_ELF32
>> 873 select SIBYTE_SB1250
>> 874 select SWAP_IO_SPACE
>> 875 select SYS_HAS_CPU_SB1
>> 876 select SYS_SUPPORTS_BIG_ENDIAN
>> 877 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 878 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 879
>> 880 config SIBYTE_BIGSUR
>> 881 bool "Sibyte BCM91480B-BigSur"
>> 882 select BOOT_ELF32
>> 883 select NR_CPUS_DEFAULT_4
>> 884 select SIBYTE_BCM1x80
>> 885 select SWAP_IO_SPACE
>> 886 select SYS_HAS_CPU_SB1
>> 887 select SYS_SUPPORTS_BIG_ENDIAN
>> 888 select SYS_SUPPORTS_HIGHMEM
>> 889 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 890 select ZONE_DMA32 if 64BIT
>> 891 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 892
>> 893 config SNI_RM
>> 894 bool "SNI RM200/300/400"
>> 895 select ARC_MEMORY
>> 896 select ARC_PROMLIB
>> 897 select FW_ARC if CPU_LITTLE_ENDIAN
>> 898 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 899 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 900 select ARCH_MAY_HAVE_PC_FDC
>> 901 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 902 select ARCH_MIGHT_HAVE_PC_SERIO
>> 903 select BOOT_ELF32
>> 904 select CEVT_R4K
>> 905 select CSRC_R4K
>> 906 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 907 select DMA_NONCOHERENT
>> 908 select GENERIC_ISA_DMA
>> 909 select HAVE_EISA
>> 910 select HAVE_PCSPKR_PLATFORM
>> 911 select HAVE_PCI
>> 912 select IRQ_MIPS_CPU
>> 913 select I8253
>> 914 select I8259
>> 915 select ISA
>> 916 select MIPS_L1_CACHE_SHIFT_6
>> 917 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 918 select SYS_HAS_CPU_R4X00
>> 919 select SYS_HAS_CPU_R5000
>> 920 select SYS_HAS_CPU_R10000
>> 921 select R5000_CPU_SCACHE
>> 922 select SYS_HAS_EARLY_PRINTK
>> 923 select SYS_SUPPORTS_32BIT_KERNEL
>> 924 select SYS_SUPPORTS_64BIT_KERNEL
>> 925 select SYS_SUPPORTS_BIG_ENDIAN
>> 926 select SYS_SUPPORTS_HIGHMEM
>> 927 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 928 select WAR_R4600_V2_HIT_CACHEOP
>> 929 help
>> 930 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 931 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 932 Technology and now in turn merged with Fujitsu. Say Y here to
>> 933 support this machine type.
>> 934
>> 935 config MACH_TX39XX
>> 936 bool "Toshiba TX39 series based machines"
>> 937
>> 938 config MACH_TX49XX
>> 939 bool "Toshiba TX49 series based machines"
>> 940 select WAR_TX49XX_ICACHE_INDEX_INV
>> 941
>> 942 config MIKROTIK_RB532
>> 943 bool "Mikrotik RB532 boards"
>> 944 select CEVT_R4K
>> 945 select CSRC_R4K
>> 946 select DMA_NONCOHERENT
>> 947 select HAVE_PCI
>> 948 select IRQ_MIPS_CPU
>> 949 select SYS_HAS_CPU_MIPS32_R1
>> 950 select SYS_SUPPORTS_32BIT_KERNEL
>> 951 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 952 select SWAP_IO_SPACE
>> 953 select BOOT_RAW
>> 954 select GPIOLIB
>> 955 select MIPS_L1_CACHE_SHIFT_4
>> 956 help
>> 957 Support the Mikrotik(tm) RouterBoard 532 series,
>> 958 based on the IDT RC32434 SoC.
>> 959
>> 960 config CAVIUM_OCTEON_SOC
>> 961 bool "Cavium Networks Octeon SoC based boards"
>> 962 select CEVT_R4K
>> 963 select ARCH_HAS_PHYS_TO_DMA
>> 964 select HAVE_RAPIDIO
>> 965 select PHYS_ADDR_T_64BIT
>> 966 select SYS_SUPPORTS_64BIT_KERNEL
>> 967 select SYS_SUPPORTS_BIG_ENDIAN
>> 968 select EDAC_SUPPORT
>> 969 select EDAC_ATOMIC_SCRUB
>> 970 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 971 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 972 select SYS_HAS_EARLY_PRINTK
>> 973 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 974 select HAVE_PCI
>> 975 select HAVE_PLAT_DELAY
>> 976 select HAVE_PLAT_FW_INIT_CMDLINE
>> 977 select HAVE_PLAT_MEMCPY
>> 978 select ZONE_DMA32
>> 979 select GPIOLIB
>> 980 select USE_OF
>> 981 select ARCH_SPARSEMEM_ENABLE
>> 982 select SYS_SUPPORTS_SMP
>> 983 select NR_CPUS_DEFAULT_64
>> 984 select MIPS_NR_CPU_NR_MAP_1024
>> 985 select BUILTIN_DTB
>> 986 select MTD
>> 987 select MTD_COMPLEX_MAPPINGS
>> 988 select SWIOTLB
>> 989 select SYS_SUPPORTS_RELOCATABLE
>> 990 help
>> 991 This option supports all of the Octeon reference boards from Cavium
>> 992 Networks. It builds a kernel that dynamically determines the Octeon
>> 993 CPU type and supports all known board reference implementations.
>> 994 Some of the supported boards are:
>> 995 EBT3000
>> 996 EBH3000
>> 997 EBH3100
>> 998 Thunder
>> 999 Kodama
>> 1000 Hikari
>> 1001 Say Y here for most Octeon reference boards.
>> 1002
>> 1003 endchoice
>> 1004
>> 1005 source "arch/mips/alchemy/Kconfig"
>> 1006 source "arch/mips/ath25/Kconfig"
>> 1007 source "arch/mips/ath79/Kconfig"
>> 1008 source "arch/mips/bcm47xx/Kconfig"
>> 1009 source "arch/mips/bcm63xx/Kconfig"
>> 1010 source "arch/mips/bmips/Kconfig"
>> 1011 source "arch/mips/generic/Kconfig"
>> 1012 source "arch/mips/ingenic/Kconfig"
>> 1013 source "arch/mips/jazz/Kconfig"
>> 1014 source "arch/mips/lantiq/Kconfig"
>> 1015 source "arch/mips/pic32/Kconfig"
>> 1016 source "arch/mips/ralink/Kconfig"
>> 1017 source "arch/mips/sgi-ip27/Kconfig"
>> 1018 source "arch/mips/sibyte/Kconfig"
>> 1019 source "arch/mips/txx9/Kconfig"
>> 1020 source "arch/mips/vr41xx/Kconfig"
>> 1021 source "arch/mips/cavium-octeon/Kconfig"
>> 1022 source "arch/mips/loongson2ef/Kconfig"
>> 1023 source "arch/mips/loongson32/Kconfig"
>> 1024 source "arch/mips/loongson64/Kconfig"
>> 1025
>> 1026 endmenu
>> 1027
>> 1028 config GENERIC_HWEIGHT
363 bool 1029 bool
364 default y if KMSAN || KASAN !! 1030 default y
365 1031
366 config GENERIC_BUG !! 1032 config GENERIC_CALIBRATE_DELAY
367 def_bool y !! 1033 bool
368 depends on BUG !! 1034 default y
369 select GENERIC_BUG_RELATIVE_POINTERS i !! 1035
>> 1036 config SCHED_OMIT_FRAME_POINTER
>> 1037 bool
>> 1038 default y
370 1039
371 config GENERIC_BUG_RELATIVE_POINTERS !! 1040 #
>> 1041 # Select some configuration options automatically based on user selections.
>> 1042 #
>> 1043 config FW_ARC
372 bool 1044 bool
373 1045
374 config ARCH_MAY_HAVE_PC_FDC 1046 config ARCH_MAY_HAVE_PC_FDC
375 def_bool y !! 1047 bool
376 depends on ISA_DMA_API <<
377 1048
378 config GENERIC_CALIBRATE_DELAY !! 1049 config BOOT_RAW
379 def_bool y !! 1050 bool
380 1051
381 config ARCH_HAS_CPU_RELAX !! 1052 config CEVT_BCM1480
382 def_bool y !! 1053 bool
383 1054
384 config ARCH_HIBERNATION_POSSIBLE !! 1055 config CEVT_DS1287
385 def_bool y !! 1056 bool
386 1057
387 config ARCH_SUSPEND_POSSIBLE !! 1058 config CEVT_GT641XX
388 def_bool y !! 1059 bool
389 1060
390 config AUDIT_ARCH !! 1061 config CEVT_R4K
391 def_bool y if X86_64 !! 1062 bool
392 1063
393 config KASAN_SHADOW_OFFSET !! 1064 config CEVT_SB1250
394 hex !! 1065 bool
395 depends on KASAN <<
396 default 0xdffffc0000000000 <<
397 1066
398 config HAVE_INTEL_TXT !! 1067 config CEVT_TXX9
399 def_bool y !! 1068 bool
400 depends on INTEL_IOMMU && ACPI <<
401 1069
402 config X86_64_SMP !! 1070 config CSRC_BCM1480
403 def_bool y !! 1071 bool
404 depends on X86_64 && SMP !! 1072
>> 1073 config CSRC_IOASIC
>> 1074 bool
>> 1075
>> 1076 config CSRC_R4K
>> 1077 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1078 bool
>> 1079
>> 1080 config CSRC_SB1250
>> 1081 bool
>> 1082
>> 1083 config MIPS_CLOCK_VSYSCALL
>> 1084 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1085
>> 1086 config GPIO_TXX9
>> 1087 select GPIOLIB
>> 1088 bool
>> 1089
>> 1090 config FW_CFE
>> 1091 bool
405 1092
406 config ARCH_SUPPORTS_UPROBES 1093 config ARCH_SUPPORTS_UPROBES
407 def_bool y !! 1094 bool
408 1095
409 config FIX_EARLYCON_MEM !! 1096 config DMA_PERDEV_COHERENT
410 def_bool y !! 1097 bool
>> 1098 select ARCH_HAS_SETUP_DMA_OPS
>> 1099 select DMA_NONCOHERENT
411 1100
412 config DYNAMIC_PHYSICAL_MASK !! 1101 config DMA_NONCOHERENT
413 bool 1102 bool
>> 1103 #
>> 1104 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1105 # Attribute bits. It is believed that the uncached access through
>> 1106 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1107 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1108 # significant advantages.
>> 1109 #
>> 1110 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1111 select ARCH_HAS_DMA_PREP_COHERENT
>> 1112 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1113 select ARCH_HAS_DMA_SET_UNCACHED
>> 1114 select DMA_NONCOHERENT_MMAP
>> 1115 select NEED_DMA_MAP_STATE
414 1116
415 config PGTABLE_LEVELS !! 1117 config SYS_HAS_EARLY_PRINTK
416 int !! 1118 bool
417 default 5 if X86_5LEVEL <<
418 default 4 if X86_64 <<
419 default 3 if X86_PAE <<
420 default 2 <<
421 1119
422 config CC_HAS_SANE_STACKPROTECTOR !! 1120 config SYS_SUPPORTS_HOTPLUG_CPU
423 bool 1121 bool
424 default $(success,$(srctree)/scripts/g <<
425 default $(success,$(srctree)/scripts/g <<
426 help <<
427 We have to make sure stack protector <<
428 the compiler produces broken code or <<
429 the segment on 32-bit kernels. <<
430 1122
431 menu "Processor type and features" !! 1123 config MIPS_BONITO64
>> 1124 bool
432 1125
433 config SMP !! 1126 config MIPS_MSC
434 bool "Symmetric multi-processing suppo !! 1127 bool
435 help <<
436 This enables support for systems wit <<
437 a system with only one CPU, say N. I <<
438 than one CPU, say Y. <<
439 1128
440 If you say N here, the kernel will r !! 1129 config SYNC_R4K
441 machines, but will use only one CPU !! 1130 bool
442 you say Y here, the kernel will run <<
443 uniprocessor machines. On a uniproce <<
444 will run faster if you say N here. <<
445 1131
446 Note that if you say Y here and choo !! 1132 config NO_IOPORT_MAP
447 "Pentium" under "Processor family", !! 1133 def_bool n
448 architectures. Similarly, multiproce <<
449 architecture may not work on all Pen <<
450 1134
451 People using multiprocessor machines !! 1135 config GENERIC_CSUM
452 Y to "Enhanced Real Time Clock Suppo !! 1136 def_bool CPU_NO_LOAD_STORE_LR
453 Management" code will be disabled if <<
454 1137
455 See also <file:Documentation/arch/x8 !! 1138 config GENERIC_ISA_DMA
456 <file:Documentation/admin-guide/lock !! 1139 bool
457 <http://www.tldp.org/docs.html#howto !! 1140 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1141 select ISA_DMA_API
458 1142
459 If you don't know what to do here, s !! 1143 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1144 bool
>> 1145 select GENERIC_ISA_DMA
460 1146
461 config X86_X2APIC !! 1147 config HAVE_PLAT_DELAY
462 bool "Support x2apic" !! 1148 bool
463 depends on X86_LOCAL_APIC && X86_64 && <<
464 help <<
465 This enables x2apic support on CPUs <<
466 <<
467 This allows 32-bit apic IDs (so it c <<
468 and accesses the local apic via MSRs <<
469 <<
470 Some Intel systems circa 2022 and la <<
471 and can not fall back to the legacy <<
472 enabled in the BIOS. They will boot <<
473 without enabling this option. <<
474 1149
475 If you don't know what to do here, s !! 1150 config HAVE_PLAT_FW_INIT_CMDLINE
>> 1151 bool
476 1152
477 config X86_POSTED_MSI !! 1153 config HAVE_PLAT_MEMCPY
478 bool "Enable MSI and MSI-x delivery by !! 1154 bool
479 depends on X86_64 && IRQ_REMAP <<
480 help <<
481 This enables MSIs that are under int <<
482 posted interrupts to the host kernel <<
483 potentially be improved by coalescin <<
484 frequency bursts. <<
485 1155
486 If you don't know what to do here, s !! 1156 config ISA_DMA_API
>> 1157 bool
487 1158
488 config X86_MPPARSE !! 1159 config SYS_SUPPORTS_RELOCATABLE
489 bool "Enable MPS table" if ACPI !! 1160 bool
490 default y <<
491 depends on X86_LOCAL_APIC <<
492 help 1161 help
493 For old smp systems that do not have !! 1162 Selected if the platform supports relocating the kernel.
494 (esp with 64bit cpus) with acpi supp !! 1163 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1164 to allow access to command line and entropy sources.
495 1165
496 config X86_CPU_RESCTRL !! 1166 #
497 bool "x86 CPU resource control support !! 1167 # Endianness selection. Sufficiently obscure so many users don't know what to
498 depends on X86 && (CPU_SUP_INTEL || CP !! 1168 # answer,so we try hard to limit the available choices. Also the use of a
499 select KERNFS !! 1169 # choice statement should be more obvious to the user.
500 select PROC_CPU_RESCTRL if PRO !! 1170 #
>> 1171 choice
>> 1172 prompt "Endianness selection"
501 help 1173 help
502 Enable x86 CPU resource control supp !! 1174 Some MIPS machines can be configured for either little or big endian
>> 1175 byte order. These modes require different kernels and a different
>> 1176 Linux distribution. In general there is one preferred byteorder for a
>> 1177 particular system but some systems are just as commonly used in the
>> 1178 one or the other endianness.
>> 1179
>> 1180 config CPU_BIG_ENDIAN
>> 1181 bool "Big endian"
>> 1182 depends on SYS_SUPPORTS_BIG_ENDIAN
>> 1183
>> 1184 config CPU_LITTLE_ENDIAN
>> 1185 bool "Little endian"
>> 1186 depends on SYS_SUPPORTS_LITTLE_ENDIAN
503 1187
504 Provide support for the allocation a !! 1188 endchoice
505 usage by the CPU. <<
506 1189
507 Intel calls this Intel Resource Dire !! 1190 config EXPORT_UASM
508 (Intel(R) RDT). More information abo !! 1191 bool
509 Intel x86 Architecture Software Deve <<
510 1192
511 AMD calls this AMD Platform Quality !! 1193 config SYS_SUPPORTS_APM_EMULATION
512 More information about AMD QoS can b !! 1194 bool
513 Platform Quality of Service Extensio <<
514 1195
515 Say N if unsure. !! 1196 config SYS_SUPPORTS_BIG_ENDIAN
>> 1197 bool
516 1198
517 config X86_FRED !! 1199 config SYS_SUPPORTS_LITTLE_ENDIAN
518 bool "Flexible Return and Event Delive !! 1200 bool
519 depends on X86_64 <<
520 help <<
521 When enabled, try to use Flexible Re <<
522 instead of the legacy SYSCALL/SYSENT <<
523 ring transitions and exception/inter <<
524 system supports it. <<
525 1201
526 config X86_BIGSMP !! 1202 config MIPS_HUGE_TLB_SUPPORT
527 bool "Support for big SMP systems with !! 1203 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
528 depends on SMP && X86_32 <<
529 help <<
530 This option is needed for the system <<
531 1204
532 config X86_EXTENDED_PLATFORM !! 1205 config IRQ_MSP_SLP
533 bool "Support for extended (non-PC) x8 !! 1206 bool
534 default y <<
535 help <<
536 If you disable this option then the <<
537 standard PC platforms. (which covers <<
538 systems out there.) <<
539 <<
540 If you enable this option then you'l <<
541 for the following non-PC x86 platfor <<
542 CONFIG_64BIT. <<
543 <<
544 32-bit platforms (CONFIG_64BIT=n): <<
545 Goldfish (Android emulator) <<
546 AMD Elan <<
547 RDC R-321x SoC <<
548 SGI 320/540 (Visual Workstatio <<
549 STA2X11-based (e.g. Northville <<
550 Moorestown MID devices <<
551 <<
552 64-bit platforms (CONFIG_64BIT=y): <<
553 Numascale NumaChip <<
554 ScaleMP vSMP <<
555 SGI Ultraviolet <<
556 <<
557 If you have one of these systems, or <<
558 generic distribution kernel, say Y h <<
559 <<
560 # This is an alphabetically sorted list of 64 <<
561 # Please maintain the alphabetic order if and <<
562 config X86_NUMACHIP <<
563 bool "Numascale NumaChip" <<
564 depends on X86_64 <<
565 depends on X86_EXTENDED_PLATFORM <<
566 depends on NUMA <<
567 depends on SMP <<
568 depends on X86_X2APIC <<
569 depends on PCI_MMCONFIG <<
570 help <<
571 Adds support for Numascale NumaChip <<
572 enable more than ~168 cores. <<
573 If you don't have one of these, you <<
574 <<
575 config X86_VSMP <<
576 bool "ScaleMP vSMP" <<
577 select HYPERVISOR_GUEST <<
578 select PARAVIRT <<
579 depends on X86_64 && PCI <<
580 depends on X86_EXTENDED_PLATFORM <<
581 depends on SMP <<
582 help <<
583 Support for ScaleMP vSMP systems. S <<
584 supposed to run on these EM64T-based <<
585 if you have one of these machines. <<
586 <<
587 config X86_UV <<
588 bool "SGI Ultraviolet" <<
589 depends on X86_64 <<
590 depends on X86_EXTENDED_PLATFORM <<
591 depends on NUMA <<
592 depends on EFI <<
593 depends on KEXEC_CORE <<
594 depends on X86_X2APIC <<
595 depends on PCI <<
596 help <<
597 This option is needed in order to su <<
598 If you don't have one of these, you <<
599 <<
600 # Following is an alphabetically sorted list o <<
601 # Please maintain the alphabetic order if and <<
602 <<
603 config X86_GOLDFISH <<
604 bool "Goldfish (Virtual Platform)" <<
605 depends on X86_EXTENDED_PLATFORM <<
606 help <<
607 Enable support for the Goldfish virt <<
608 for Android development. Unless you <<
609 Goldfish emulator say N here. <<
610 <<
611 config X86_INTEL_CE <<
612 bool "CE4100 TV platform" <<
613 depends on PCI <<
614 depends on PCI_GODIRECT <<
615 depends on X86_IO_APIC <<
616 depends on X86_32 <<
617 depends on X86_EXTENDED_PLATFORM <<
618 select X86_REBOOTFIXUPS <<
619 select OF <<
620 select OF_EARLY_FLATTREE <<
621 help <<
622 Select for the Intel CE media proces <<
623 This option compiles in support for <<
624 boxes and media devices. <<
625 <<
626 config X86_INTEL_MID <<
627 bool "Intel MID platform support" <<
628 depends on X86_EXTENDED_PLATFORM <<
629 depends on X86_PLATFORM_DEVICES <<
630 depends on PCI <<
631 depends on X86_64 || (PCI_GOANY && X86 <<
632 depends on X86_IO_APIC <<
633 select I2C <<
634 select DW_APB_TIMER <<
635 select INTEL_SCU_PCI <<
636 help <<
637 Select to build a kernel capable of <<
638 Internet Device) platform systems wh <<
639 interfaces. If you are building for <<
640 <<
641 Intel MID platforms are based on an <<
642 consume less power than most of the <<
643 <<
644 config X86_INTEL_QUARK <<
645 bool "Intel Quark platform support" <<
646 depends on X86_32 <<
647 depends on X86_EXTENDED_PLATFORM <<
648 depends on X86_PLATFORM_DEVICES <<
649 depends on X86_TSC <<
650 depends on PCI <<
651 depends on PCI_GOANY <<
652 depends on X86_IO_APIC <<
653 select IOSF_MBI <<
654 select INTEL_IMR <<
655 select COMMON_CLK <<
656 help <<
657 Select to include support for Quark <<
658 Say Y here if you have a Quark based <<
659 compatible Intel Galileo. <<
660 <<
661 config X86_INTEL_LPSS <<
662 bool "Intel Low Power Subsystem Suppor <<
663 depends on X86 && ACPI && PCI <<
664 select COMMON_CLK <<
665 select PINCTRL <<
666 select IOSF_MBI <<
667 help <<
668 Select to build support for Intel Lo <<
669 found on Intel Lynxpoint PCH. Select <<
670 things like clock tree (common clock <<
671 which are needed by the LPSS periphe <<
672 <<
673 config X86_AMD_PLATFORM_DEVICE <<
674 bool "AMD ACPI2Platform devices suppor <<
675 depends on ACPI <<
676 select COMMON_CLK <<
677 select PINCTRL <<
678 help <<
679 Select to interpret AMD specific ACP <<
680 such as I2C, UART, GPIO found on AMD <<
681 I2C and UART depend on COMMON_CLK to <<
682 implemented under PINCTRL subsystem. <<
683 <<
684 config IOSF_MBI <<
685 tristate "Intel SoC IOSF Sideband supp <<
686 depends on PCI <<
687 help <<
688 This option enables sideband registe <<
689 platforms. On these platforms the IO <<
690 MSR's for some register accesses, mo <<
691 and power. Drivers may query the ava <<
692 determine if they need the sideband <<
693 platforms. The sideband is available <<
694 This list is not meant to be exclusi <<
695 - BayTrail <<
696 - Braswell <<
697 - Quark <<
698 <<
699 You should say Y if you are running <<
700 <<
701 config IOSF_MBI_DEBUG <<
702 bool "Enable IOSF sideband access thro <<
703 depends on IOSF_MBI && DEBUG_FS <<
704 help <<
705 Select this option to expose the IOS <<
706 MDR, MCRX) through debugfs to write <<
707 different units on the SoC. This is <<
708 state information for debug and anal <<
709 mechanism, users of this option woul <<
710 device they want to access. <<
711 <<
712 If you don't require the option or a <<
713 <<
714 config X86_RDC321X <<
715 bool "RDC R-321x SoC" <<
716 depends on X86_32 <<
717 depends on X86_EXTENDED_PLATFORM <<
718 select M486 <<
719 select X86_REBOOTFIXUPS <<
720 help <<
721 This option is needed for RDC R-321x <<
722 as R-8610-(G). <<
723 If you don't have one of these chips <<
724 <<
725 config X86_32_NON_STANDARD <<
726 bool "Support non-standard 32-bit SMP <<
727 depends on X86_32 && SMP <<
728 depends on X86_EXTENDED_PLATFORM <<
729 help <<
730 This option compiles in the bigsmp a <<
731 subarchitectures. It is intended fo <<
732 kernel. If you select them all, kern <<
733 one and will fallback to default. <<
734 1207
735 # Alphabetically sorted list of Non standard 3 !! 1208 config IRQ_MSP_CIC
>> 1209 bool
736 1210
737 config X86_SUPPORTS_MEMORY_FAILURE !! 1211 config IRQ_TXX9
738 def_bool y !! 1212 bool
739 # MCE code calls memory_failure(): <<
740 depends on X86_MCE <<
741 # On 32-bit this adds too big of NODES <<
742 # On 32-bit SPARSEMEM adds too big of <<
743 depends on X86_64 || !SPARSEMEM <<
744 select ARCH_SUPPORTS_MEMORY_FAILURE <<
745 <<
746 config STA2X11 <<
747 bool "STA2X11 Companion Chip Support" <<
748 depends on X86_32_NON_STANDARD && PCI <<
749 select SWIOTLB <<
750 select MFD_STA2X11 <<
751 select GPIOLIB <<
752 help <<
753 This adds support for boards based o <<
754 a.k.a. "ConneXt". The chip is used i <<
755 PC chipset, so all "standard" periph <<
756 option is selected the kernel will s <<
757 standard PC machines. <<
758 <<
759 config X86_32_IRIS <<
760 tristate "Eurobraille/Iris poweroff mo <<
761 depends on X86_32 <<
762 help <<
763 The Iris machines from EuroBraille d <<
764 to shut themselves down properly. A <<
765 needed to do so, which is what this <<
766 kernel shutdown. <<
767 1213
768 This is only for Iris machines from !! 1214 config IRQ_GT641XX
>> 1215 bool
769 1216
770 If unused, say N. !! 1217 config PCI_GT64XXX_PCI0
>> 1218 bool
771 1219
772 config SCHED_OMIT_FRAME_POINTER !! 1220 config PCI_XTALK_BRIDGE
773 def_bool y !! 1221 bool
774 prompt "Single-depth WCHAN output" <<
775 depends on X86 <<
776 help <<
777 Calculate simpler /proc/<PID>/wchan <<
778 is disabled then wchan values will r <<
779 caller function. This provides more <<
780 at the expense of slightly more sche <<
781 1222
782 If in doubt, say "Y". !! 1223 config NO_EXCEPT_FILL
>> 1224 bool
783 1225
784 menuconfig HYPERVISOR_GUEST !! 1226 config MIPS_SPRAM
785 bool "Linux guest support" !! 1227 bool
786 help <<
787 Say Y here to enable options for run <<
788 visors. This option enables basic hy <<
789 setup. <<
790 1228
791 If you say N, all options in this su !! 1229 config SWAP_IO_SPACE
792 disabled, and Linux guest support wo !! 1230 bool
793 1231
794 if HYPERVISOR_GUEST !! 1232 config SGI_HAS_INDYDOG
>> 1233 bool
795 1234
796 config PARAVIRT !! 1235 config SGI_HAS_HAL2
797 bool "Enable paravirtualization code" !! 1236 bool
798 depends on HAVE_STATIC_CALL <<
799 help <<
800 This changes the kernel so it can mo <<
801 under a hypervisor, potentially impr <<
802 over full virtualization. However, <<
803 the kernel is theoretically slower a <<
804 1237
805 config PARAVIRT_XXL !! 1238 config SGI_HAS_SEEQ
806 bool 1239 bool
807 1240
808 config PARAVIRT_DEBUG !! 1241 config SGI_HAS_WD93
809 bool "paravirt-ops debugging" !! 1242 bool
810 depends on PARAVIRT && DEBUG_KERNEL <<
811 help <<
812 Enable to debug paravirt_ops interna <<
813 a paravirt_op is missing when it is <<
814 1243
815 config PARAVIRT_SPINLOCKS !! 1244 config SGI_HAS_ZILOG
816 bool "Paravirtualization layer for spi !! 1245 bool
817 depends on PARAVIRT && SMP <<
818 help <<
819 Paravirtualized spinlocks allow a pv <<
820 spinlock implementation with somethi <<
821 (for example, block the virtual CPU <<
822 1246
823 It has a minimal impact on native ke !! 1247 config SGI_HAS_I8042
824 benefit on paravirtualized KVM / Xen !! 1248 bool
825 1249
826 If you are unsure how to answer this !! 1250 config DEFAULT_SGI_PARTITION
>> 1251 bool
827 1252
828 config X86_HV_CALLBACK_VECTOR !! 1253 config FW_ARC32
829 def_bool n !! 1254 bool
830 1255
831 source "arch/x86/xen/Kconfig" !! 1256 config FW_SNIPROM
>> 1257 bool
832 1258
833 config KVM_GUEST !! 1259 config BOOT_ELF32
834 bool "KVM Guest support (including kvm !! 1260 bool
835 depends on PARAVIRT <<
836 select PARAVIRT_CLOCK <<
837 select ARCH_CPUIDLE_HALTPOLL <<
838 select X86_HV_CALLBACK_VECTOR <<
839 default y <<
840 help <<
841 This option enables various optimiza <<
842 hypervisor. It includes a paravirtua <<
843 of relying on a PIT (or probably oth <<
844 underlying device model, the host pr <<
845 timing infrastructure such as time o <<
846 1261
847 config ARCH_CPUIDLE_HALTPOLL !! 1262 config MIPS_L1_CACHE_SHIFT_4
848 def_bool n !! 1263 bool
849 prompt "Disable host haltpoll when loa <<
850 help <<
851 If virtualized under KVM, disable ho <<
852 1264
853 config PVH !! 1265 config MIPS_L1_CACHE_SHIFT_5
854 bool "Support for running PVH guests" !! 1266 bool
855 help <<
856 This option enables the PVH entry po <<
857 as specified in the x86/HVM direct b <<
858 <<
859 config PARAVIRT_TIME_ACCOUNTING <<
860 bool "Paravirtual steal time accountin <<
861 depends on PARAVIRT <<
862 help <<
863 Select this option to enable fine gr <<
864 accounting. Time spent executing oth <<
865 the current vCPU is discounted from <<
866 that, there can be a small performan <<
867 <<
868 If in doubt, say N here. <<
869 <<
870 config PARAVIRT_CLOCK <<
871 bool <<
872 <<
873 config JAILHOUSE_GUEST <<
874 bool "Jailhouse non-root cell support" <<
875 depends on X86_64 && PCI <<
876 select X86_PM_TIMER <<
877 help <<
878 This option allows to run Linux as g <<
879 cell. You can leave this option disa <<
880 Jailhouse and run Linux afterwards i <<
881 <<
882 config ACRN_GUEST <<
883 bool "ACRN Guest support" <<
884 depends on X86_64 <<
885 select X86_HV_CALLBACK_VECTOR <<
886 help <<
887 This option allows to run Linux as g <<
888 a flexible, lightweight reference op <<
889 real-time and safety-criticality in <<
890 IOT with small footprint and real-ti <<
891 found in https://projectacrn.org/. <<
892 <<
893 config INTEL_TDX_GUEST <<
894 bool "Intel TDX (Trust Domain Extensio <<
895 depends on X86_64 && CPU_SUP_INTEL <<
896 depends on X86_X2APIC <<
897 depends on EFI_STUB <<
898 select ARCH_HAS_CC_PLATFORM <<
899 select X86_MEM_ENCRYPT <<
900 select X86_MCE <<
901 select UNACCEPTED_MEMORY <<
902 help <<
903 Support running as a guest under Int <<
904 the guest kernel can not boot or run <<
905 TDX includes memory encryption and i <<
906 which protect the confidentiality an <<
907 memory contents and CPU state. TDX g <<
908 some attacks from the VMM. <<
909 <<
910 endif # HYPERVISOR_GUEST <<
911 <<
912 source "arch/x86/Kconfig.cpu" <<
913 <<
914 config HPET_TIMER <<
915 def_bool X86_64 <<
916 prompt "HPET Timer Support" if X86_32 <<
917 help <<
918 Use the IA-PC HPET (High Precision E <<
919 time in preference to the PIT and RT <<
920 present. <<
921 HPET is the next generation timer re <<
922 The HPET provides a stable time base <<
923 systems, unlike the TSC, but it is m <<
924 as it is off-chip. The interface us <<
925 in the HPET spec, revision 1. <<
926 <<
927 You can safely choose Y here. Howev <<
928 activated if the platform and the BI <<
929 Otherwise the 8254 will be used for <<
930 1267
931 Choose N to continue using the legac !! 1268 config MIPS_L1_CACHE_SHIFT_6
>> 1269 bool
932 1270
933 config HPET_EMULATE_RTC !! 1271 config MIPS_L1_CACHE_SHIFT_7
934 def_bool y !! 1272 bool
935 depends on HPET_TIMER && (RTC_DRV_CMOS <<
936 1273
937 # Mark as expert because too many people got i !! 1274 config MIPS_L1_CACHE_SHIFT
938 # The code disables itself when not needed. !! 1275 int
939 config DMI !! 1276 default "7" if MIPS_L1_CACHE_SHIFT_7
940 default y !! 1277 default "6" if MIPS_L1_CACHE_SHIFT_6
941 select DMI_SCAN_MACHINE_NON_EFI_FALLBA !! 1278 default "5" if MIPS_L1_CACHE_SHIFT_5
942 bool "Enable DMI scanning" if EXPERT !! 1279 default "4" if MIPS_L1_CACHE_SHIFT_4
943 help !! 1280 default "5"
944 Enabled scanning of DMI to identify <<
945 here unless you have verified that y <<
946 affected by entries in the DMI black <<
947 BIOS code. <<
948 1281
949 config GART_IOMMU !! 1282 config ARC_CMDLINE_ONLY
950 bool "Old AMD GART IOMMU support" !! 1283 bool
951 select IOMMU_HELPER <<
952 select SWIOTLB <<
953 depends on X86_64 && PCI && AMD_NB <<
954 help <<
955 Provides a driver for older AMD Athl <<
956 GART based hardware IOMMUs. <<
957 1284
958 The GART supports full DMA access fo !! 1285 config ARC_CONSOLE
959 limitations, on systems with more th !! 1286 bool "ARC console support"
960 for USB, sound, many IDE/SATA chipse !! 1287 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
961 1288
962 Newer systems typically have a moder !! 1289 config ARC_MEMORY
963 the CONFIG_AMD_IOMMU=y config option !! 1290 bool
964 1291
965 In normal configurations this driver !! 1292 config ARC_PROMLIB
966 there's more than 3 GB of memory and !! 1293 bool
967 32-bit limited device. <<
968 1294
969 If unsure, say Y. !! 1295 config FW_ARC64
>> 1296 bool
970 1297
971 config BOOT_VESA_SUPPORT !! 1298 config BOOT_ELF64
972 bool 1299 bool
>> 1300
>> 1301 menu "CPU selection"
>> 1302
>> 1303 choice
>> 1304 prompt "CPU type"
>> 1305 default CPU_R4X00
>> 1306
>> 1307 config CPU_LOONGSON64
>> 1308 bool "Loongson 64-bit CPU"
>> 1309 depends on SYS_HAS_CPU_LOONGSON64
>> 1310 select ARCH_HAS_PHYS_TO_DMA
>> 1311 select CPU_MIPSR2
>> 1312 select CPU_HAS_PREFETCH
>> 1313 select CPU_SUPPORTS_64BIT_KERNEL
>> 1314 select CPU_SUPPORTS_HIGHMEM
>> 1315 select CPU_SUPPORTS_HUGEPAGES
>> 1316 select CPU_SUPPORTS_MSA
>> 1317 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1318 select CPU_MIPSR2_IRQ_VI
>> 1319 select WEAK_ORDERING
>> 1320 select WEAK_REORDERING_BEYOND_LLSC
>> 1321 select MIPS_ASID_BITS_VARIABLE
>> 1322 select MIPS_PGD_C0_CONTEXT
>> 1323 select MIPS_L1_CACHE_SHIFT_6
>> 1324 select MIPS_FP_SUPPORT
>> 1325 select GPIOLIB
>> 1326 select SWIOTLB
>> 1327 select HAVE_KVM
973 help 1328 help
974 If true, at least one selected frame !! 1329 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
975 of VESA video modes set at an early !! 1330 cores implements the MIPS64R2 instruction set with many extensions,
>> 1331 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1332 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1333 Loongson-2E/2F is not covered here and will be removed in future.
976 1334
977 config MAXSMP !! 1335 config LOONGSON3_ENHANCEMENT
978 bool "Enable Maximum number of SMP Pro !! 1336 bool "New Loongson-3 CPU Enhancements"
979 depends on X86_64 && SMP && DEBUG_KERN !! 1337 default n
980 select CPUMASK_OFFSTACK !! 1338 depends on CPU_LOONGSON64
981 help 1339 help
982 Enable maximum number of CPUS and NU !! 1340 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
983 If unsure, say N. !! 1341 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1342 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1343 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1344 Fast TLB refill support, etc.
984 1345
985 # !! 1346 This option enable those enhancements which are not probed at run
986 # The maximum number of CPUs supported: !! 1347 time. If you want a generic kernel to run on all Loongson 3 machines,
987 # !! 1348 please say 'N' here. If you want a high-performance kernel to run on
988 # The main config value is NR_CPUS, which defa !! 1349 new Loongson-3 machines only, please say 'Y' here.
989 # and which can be configured interactively in <<
990 # [NR_CPUS_RANGE_BEGIN ... NR_CPUS_RANGE_END] <<
991 # <<
992 # The ranges are different on 32-bit and 64-bi <<
993 # hardware capabilities and scalability featur <<
994 # <<
995 # ( If MAXSMP is enabled we just use the highe <<
996 # interactive configuration. ) <<
997 # <<
998 1350
999 config NR_CPUS_RANGE_BEGIN !! 1351 config CPU_LOONGSON3_WORKAROUNDS
1000 int !! 1352 bool "Old Loongson-3 LLSC Workarounds"
1001 default NR_CPUS_RANGE_END if MAXSMP !! 1353 default y if SMP
1002 default 1 if !SMP !! 1354 depends on CPU_LOONGSON64
1003 default 2 !! 1355 help
>> 1356 Loongson-3 processors have the llsc issues which require workarounds.
>> 1357 Without workarounds the system may hang unexpectedly.
1004 1358
1005 config NR_CPUS_RANGE_END !! 1359 Newer Loongson-3 will fix these issues and no workarounds are needed.
1006 int !! 1360 The workarounds have no significant side effect on them but may
1007 depends on X86_32 !! 1361 decrease the performance of the system so this option should be
1008 default 64 if SMP && X86_BIGSMP !! 1362 disabled unless the kernel is intended to be run on old systems.
1009 default 8 if SMP && !X86_BIGSMP <<
1010 default 1 if !SMP <<
1011 1363
1012 config NR_CPUS_RANGE_END !! 1364 If unsure, please say Y.
1013 int <<
1014 depends on X86_64 <<
1015 default 8192 if SMP && CPUMASK_OFFST <<
1016 default 512 if SMP && !CPUMASK_OFFS <<
1017 default 1 if !SMP <<
1018 1365
1019 config NR_CPUS_DEFAULT !! 1366 config CPU_LOONGSON3_CPUCFG_EMULATION
1020 int !! 1367 bool "Emulate the CPUCFG instruction on older Loongson cores"
1021 depends on X86_32 !! 1368 default y
1022 default 32 if X86_BIGSMP !! 1369 depends on CPU_LOONGSON64
1023 default 8 if SMP !! 1370 help
1024 default 1 if !SMP !! 1371 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1372 userland to query CPU capabilities, much like CPUID on x86. This
>> 1373 option provides emulation of the instruction on older Loongson
>> 1374 cores, back to Loongson-3A1000.
1025 1375
1026 config NR_CPUS_DEFAULT !! 1376 If unsure, please say Y.
1027 int <<
1028 depends on X86_64 <<
1029 default 8192 if MAXSMP <<
1030 default 64 if SMP <<
1031 default 1 if !SMP <<
1032 1377
1033 config NR_CPUS !! 1378 config CPU_LOONGSON2E
1034 int "Maximum number of CPUs" if SMP & !! 1379 bool "Loongson 2E"
1035 range NR_CPUS_RANGE_BEGIN NR_CPUS_RAN !! 1380 depends on SYS_HAS_CPU_LOONGSON2E
1036 default NR_CPUS_DEFAULT !! 1381 select CPU_LOONGSON2EF
1037 help 1382 help
1038 This allows you to specify the maxi !! 1383 The Loongson 2E processor implements the MIPS III instruction set
1039 kernel will support. If CPUMASK_OF !! 1384 with many extensions.
1040 supported value is 8192, otherwise <<
1041 minimum value which makes sense is <<
1042 1385
1043 This is purely to save memory: each !! 1386 It has an internal FPGA northbridge, which is compatible to
1044 to the kernel image. !! 1387 bonito64.
1045 1388
1046 config SCHED_CLUSTER !! 1389 config CPU_LOONGSON2F
1047 bool "Cluster scheduler support" !! 1390 bool "Loongson 2F"
1048 depends on SMP !! 1391 depends on SYS_HAS_CPU_LOONGSON2F
1049 default y !! 1392 select CPU_LOONGSON2EF
>> 1393 select GPIOLIB
1050 help 1394 help
1051 Cluster scheduler support improves !! 1395 The Loongson 2F processor implements the MIPS III instruction set
1052 making when dealing with machines t !! 1396 with many extensions.
1053 Cluster usually means a couple of C <<
1054 by sharing mid-level caches, last-l <<
1055 busses. <<
1056 1397
1057 config SCHED_SMT !! 1398 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1058 def_bool y if SMP !! 1399 have a similar programming interface with FPGA northbridge used in
>> 1400 Loongson2E.
>> 1401
>> 1402 config CPU_LOONGSON1B
>> 1403 bool "Loongson 1B"
>> 1404 depends on SYS_HAS_CPU_LOONGSON1B
>> 1405 select CPU_LOONGSON32
>> 1406 select LEDS_GPIO_REGISTER
>> 1407 help
>> 1408 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1409 Release 1 instruction set and part of the MIPS32 Release 2
>> 1410 instruction set.
>> 1411
>> 1412 config CPU_LOONGSON1C
>> 1413 bool "Loongson 1C"
>> 1414 depends on SYS_HAS_CPU_LOONGSON1C
>> 1415 select CPU_LOONGSON32
>> 1416 select LEDS_GPIO_REGISTER
>> 1417 help
>> 1418 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1419 Release 1 instruction set and part of the MIPS32 Release 2
>> 1420 instruction set.
>> 1421
>> 1422 config CPU_MIPS32_R1
>> 1423 bool "MIPS32 Release 1"
>> 1424 depends on SYS_HAS_CPU_MIPS32_R1
>> 1425 select CPU_HAS_PREFETCH
>> 1426 select CPU_SUPPORTS_32BIT_KERNEL
>> 1427 select CPU_SUPPORTS_HIGHMEM
>> 1428 help
>> 1429 Choose this option to build a kernel for release 1 or later of the
>> 1430 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1431 MIPS processor are based on a MIPS32 processor. If you know the
>> 1432 specific type of processor in your system, choose those that one
>> 1433 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1434 Release 2 of the MIPS32 architecture is available since several
>> 1435 years so chances are you even have a MIPS32 Release 2 processor
>> 1436 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1437 performance.
1059 1438
1060 config SCHED_MC !! 1439 config CPU_MIPS32_R2
1061 def_bool y !! 1440 bool "MIPS32 Release 2"
1062 prompt "Multi-core scheduler support" !! 1441 depends on SYS_HAS_CPU_MIPS32_R2
1063 depends on SMP !! 1442 select CPU_HAS_PREFETCH
>> 1443 select CPU_SUPPORTS_32BIT_KERNEL
>> 1444 select CPU_SUPPORTS_HIGHMEM
>> 1445 select CPU_SUPPORTS_MSA
>> 1446 select HAVE_KVM
>> 1447 help
>> 1448 Choose this option to build a kernel for release 2 or later of the
>> 1449 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1450 MIPS processor are based on a MIPS32 processor. If you know the
>> 1451 specific type of processor in your system, choose those that one
>> 1452 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1453
>> 1454 config CPU_MIPS32_R5
>> 1455 bool "MIPS32 Release 5"
>> 1456 depends on SYS_HAS_CPU_MIPS32_R5
>> 1457 select CPU_HAS_PREFETCH
>> 1458 select CPU_SUPPORTS_32BIT_KERNEL
>> 1459 select CPU_SUPPORTS_HIGHMEM
>> 1460 select CPU_SUPPORTS_MSA
>> 1461 select HAVE_KVM
>> 1462 select MIPS_O32_FP64_SUPPORT
>> 1463 help
>> 1464 Choose this option to build a kernel for release 5 or later of the
>> 1465 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1466 family, are based on a MIPS32r5 processor. If you own an older
>> 1467 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1468
>> 1469 config CPU_MIPS32_R6
>> 1470 bool "MIPS32 Release 6"
>> 1471 depends on SYS_HAS_CPU_MIPS32_R6
>> 1472 select CPU_HAS_PREFETCH
>> 1473 select CPU_NO_LOAD_STORE_LR
>> 1474 select CPU_SUPPORTS_32BIT_KERNEL
>> 1475 select CPU_SUPPORTS_HIGHMEM
>> 1476 select CPU_SUPPORTS_MSA
>> 1477 select HAVE_KVM
>> 1478 select MIPS_O32_FP64_SUPPORT
>> 1479 help
>> 1480 Choose this option to build a kernel for release 6 or later of the
>> 1481 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1482 family, are based on a MIPS32r6 processor. If you own an older
>> 1483 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1484
>> 1485 config CPU_MIPS64_R1
>> 1486 bool "MIPS64 Release 1"
>> 1487 depends on SYS_HAS_CPU_MIPS64_R1
>> 1488 select CPU_HAS_PREFETCH
>> 1489 select CPU_SUPPORTS_32BIT_KERNEL
>> 1490 select CPU_SUPPORTS_64BIT_KERNEL
>> 1491 select CPU_SUPPORTS_HIGHMEM
>> 1492 select CPU_SUPPORTS_HUGEPAGES
>> 1493 help
>> 1494 Choose this option to build a kernel for release 1 or later of the
>> 1495 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1496 MIPS processor are based on a MIPS64 processor. If you know the
>> 1497 specific type of processor in your system, choose those that one
>> 1498 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1499 Release 2 of the MIPS64 architecture is available since several
>> 1500 years so chances are you even have a MIPS64 Release 2 processor
>> 1501 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1502 performance.
>> 1503
>> 1504 config CPU_MIPS64_R2
>> 1505 bool "MIPS64 Release 2"
>> 1506 depends on SYS_HAS_CPU_MIPS64_R2
>> 1507 select CPU_HAS_PREFETCH
>> 1508 select CPU_SUPPORTS_32BIT_KERNEL
>> 1509 select CPU_SUPPORTS_64BIT_KERNEL
>> 1510 select CPU_SUPPORTS_HIGHMEM
>> 1511 select CPU_SUPPORTS_HUGEPAGES
>> 1512 select CPU_SUPPORTS_MSA
>> 1513 select HAVE_KVM
>> 1514 help
>> 1515 Choose this option to build a kernel for release 2 or later of the
>> 1516 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1517 MIPS processor are based on a MIPS64 processor. If you know the
>> 1518 specific type of processor in your system, choose those that one
>> 1519 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1520
>> 1521 config CPU_MIPS64_R5
>> 1522 bool "MIPS64 Release 5"
>> 1523 depends on SYS_HAS_CPU_MIPS64_R5
>> 1524 select CPU_HAS_PREFETCH
>> 1525 select CPU_SUPPORTS_32BIT_KERNEL
>> 1526 select CPU_SUPPORTS_64BIT_KERNEL
>> 1527 select CPU_SUPPORTS_HIGHMEM
>> 1528 select CPU_SUPPORTS_HUGEPAGES
>> 1529 select CPU_SUPPORTS_MSA
>> 1530 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1531 select HAVE_KVM
>> 1532 help
>> 1533 Choose this option to build a kernel for release 5 or later of the
>> 1534 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1535 release partly implementing release 6 features. Though there is no
>> 1536 any hardware known to be based on this release.
>> 1537
>> 1538 config CPU_MIPS64_R6
>> 1539 bool "MIPS64 Release 6"
>> 1540 depends on SYS_HAS_CPU_MIPS64_R6
>> 1541 select CPU_HAS_PREFETCH
>> 1542 select CPU_NO_LOAD_STORE_LR
>> 1543 select CPU_SUPPORTS_32BIT_KERNEL
>> 1544 select CPU_SUPPORTS_64BIT_KERNEL
>> 1545 select CPU_SUPPORTS_HIGHMEM
>> 1546 select CPU_SUPPORTS_HUGEPAGES
>> 1547 select CPU_SUPPORTS_MSA
>> 1548 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1549 select HAVE_KVM
>> 1550 help
>> 1551 Choose this option to build a kernel for release 6 or later of the
>> 1552 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1553 family, are based on a MIPS64r6 processor. If you own an older
>> 1554 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1555
>> 1556 config CPU_P5600
>> 1557 bool "MIPS Warrior P5600"
>> 1558 depends on SYS_HAS_CPU_P5600
>> 1559 select CPU_HAS_PREFETCH
>> 1560 select CPU_SUPPORTS_32BIT_KERNEL
>> 1561 select CPU_SUPPORTS_HIGHMEM
>> 1562 select CPU_SUPPORTS_MSA
>> 1563 select CPU_SUPPORTS_CPUFREQ
>> 1564 select CPU_MIPSR2_IRQ_VI
>> 1565 select CPU_MIPSR2_IRQ_EI
>> 1566 select HAVE_KVM
>> 1567 select MIPS_O32_FP64_SUPPORT
>> 1568 help
>> 1569 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1570 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1571 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1572 level features like up to six P5600 calculation cores, CM2 with L2
>> 1573 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1574 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1575 eJTAG and PDtrace.
>> 1576
>> 1577 config CPU_R3000
>> 1578 bool "R3000"
>> 1579 depends on SYS_HAS_CPU_R3000
>> 1580 select CPU_HAS_WB
>> 1581 select CPU_R3K_TLB
>> 1582 select CPU_SUPPORTS_32BIT_KERNEL
>> 1583 select CPU_SUPPORTS_HIGHMEM
>> 1584 help
>> 1585 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1586 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1587 *not* work on R4000 machines and vice versa. However, since most
>> 1588 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1589 might be a safe bet. If the resulting kernel does not work,
>> 1590 try to recompile with R3000.
>> 1591
>> 1592 config CPU_TX39XX
>> 1593 bool "R39XX"
>> 1594 depends on SYS_HAS_CPU_TX39XX
>> 1595 select CPU_SUPPORTS_32BIT_KERNEL
>> 1596 select CPU_R3K_TLB
>> 1597
>> 1598 config CPU_VR41XX
>> 1599 bool "R41xx"
>> 1600 depends on SYS_HAS_CPU_VR41XX
>> 1601 select CPU_SUPPORTS_32BIT_KERNEL
>> 1602 select CPU_SUPPORTS_64BIT_KERNEL
>> 1603 help
>> 1604 The options selects support for the NEC VR4100 series of processors.
>> 1605 Only choose this option if you have one of these processors as a
>> 1606 kernel built with this option will not run on any other type of
>> 1607 processor or vice versa.
>> 1608
>> 1609 config CPU_R4300
>> 1610 bool "R4300"
>> 1611 depends on SYS_HAS_CPU_R4300
>> 1612 select CPU_SUPPORTS_32BIT_KERNEL
>> 1613 select CPU_SUPPORTS_64BIT_KERNEL
>> 1614 select CPU_HAS_LOAD_STORE_LR
>> 1615 help
>> 1616 MIPS Technologies R4300-series processors.
>> 1617
>> 1618 config CPU_R4X00
>> 1619 bool "R4x00"
>> 1620 depends on SYS_HAS_CPU_R4X00
>> 1621 select CPU_SUPPORTS_32BIT_KERNEL
>> 1622 select CPU_SUPPORTS_64BIT_KERNEL
>> 1623 select CPU_SUPPORTS_HUGEPAGES
>> 1624 help
>> 1625 MIPS Technologies R4000-series processors other than 4300, including
>> 1626 the R4000, R4400, R4600, and 4700.
>> 1627
>> 1628 config CPU_TX49XX
>> 1629 bool "R49XX"
>> 1630 depends on SYS_HAS_CPU_TX49XX
>> 1631 select CPU_HAS_PREFETCH
>> 1632 select CPU_SUPPORTS_32BIT_KERNEL
>> 1633 select CPU_SUPPORTS_64BIT_KERNEL
>> 1634 select CPU_SUPPORTS_HUGEPAGES
>> 1635
>> 1636 config CPU_R5000
>> 1637 bool "R5000"
>> 1638 depends on SYS_HAS_CPU_R5000
>> 1639 select CPU_SUPPORTS_32BIT_KERNEL
>> 1640 select CPU_SUPPORTS_64BIT_KERNEL
>> 1641 select CPU_SUPPORTS_HUGEPAGES
>> 1642 help
>> 1643 MIPS Technologies R5000-series processors other than the Nevada.
>> 1644
>> 1645 config CPU_R5500
>> 1646 bool "R5500"
>> 1647 depends on SYS_HAS_CPU_R5500
>> 1648 select CPU_SUPPORTS_32BIT_KERNEL
>> 1649 select CPU_SUPPORTS_64BIT_KERNEL
>> 1650 select CPU_SUPPORTS_HUGEPAGES
>> 1651 help
>> 1652 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1653 instruction set.
>> 1654
>> 1655 config CPU_NEVADA
>> 1656 bool "RM52xx"
>> 1657 depends on SYS_HAS_CPU_NEVADA
>> 1658 select CPU_SUPPORTS_32BIT_KERNEL
>> 1659 select CPU_SUPPORTS_64BIT_KERNEL
>> 1660 select CPU_SUPPORTS_HUGEPAGES
>> 1661 help
>> 1662 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1663
>> 1664 config CPU_R10000
>> 1665 bool "R10000"
>> 1666 depends on SYS_HAS_CPU_R10000
>> 1667 select CPU_HAS_PREFETCH
>> 1668 select CPU_SUPPORTS_32BIT_KERNEL
>> 1669 select CPU_SUPPORTS_64BIT_KERNEL
>> 1670 select CPU_SUPPORTS_HIGHMEM
>> 1671 select CPU_SUPPORTS_HUGEPAGES
>> 1672 help
>> 1673 MIPS Technologies R10000-series processors.
>> 1674
>> 1675 config CPU_RM7000
>> 1676 bool "RM7000"
>> 1677 depends on SYS_HAS_CPU_RM7000
>> 1678 select CPU_HAS_PREFETCH
>> 1679 select CPU_SUPPORTS_32BIT_KERNEL
>> 1680 select CPU_SUPPORTS_64BIT_KERNEL
>> 1681 select CPU_SUPPORTS_HIGHMEM
>> 1682 select CPU_SUPPORTS_HUGEPAGES
>> 1683
>> 1684 config CPU_SB1
>> 1685 bool "SB1"
>> 1686 depends on SYS_HAS_CPU_SB1
>> 1687 select CPU_SUPPORTS_32BIT_KERNEL
>> 1688 select CPU_SUPPORTS_64BIT_KERNEL
>> 1689 select CPU_SUPPORTS_HIGHMEM
>> 1690 select CPU_SUPPORTS_HUGEPAGES
>> 1691 select WEAK_ORDERING
>> 1692
>> 1693 config CPU_CAVIUM_OCTEON
>> 1694 bool "Cavium Octeon processor"
>> 1695 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1696 select CPU_HAS_PREFETCH
>> 1697 select CPU_SUPPORTS_64BIT_KERNEL
>> 1698 select WEAK_ORDERING
>> 1699 select CPU_SUPPORTS_HIGHMEM
>> 1700 select CPU_SUPPORTS_HUGEPAGES
>> 1701 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1702 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1703 select MIPS_L1_CACHE_SHIFT_7
>> 1704 select HAVE_KVM
>> 1705 help
>> 1706 The Cavium Octeon processor is a highly integrated chip containing
>> 1707 many ethernet hardware widgets for networking tasks. The processor
>> 1708 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1709 Full details can be found at http://www.caviumnetworks.com.
>> 1710
>> 1711 config CPU_BMIPS
>> 1712 bool "Broadcom BMIPS"
>> 1713 depends on SYS_HAS_CPU_BMIPS
>> 1714 select CPU_MIPS32
>> 1715 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1716 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1717 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1718 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1719 select CPU_SUPPORTS_32BIT_KERNEL
>> 1720 select DMA_NONCOHERENT
>> 1721 select IRQ_MIPS_CPU
>> 1722 select SWAP_IO_SPACE
>> 1723 select WEAK_ORDERING
>> 1724 select CPU_SUPPORTS_HIGHMEM
>> 1725 select CPU_HAS_PREFETCH
>> 1726 select CPU_SUPPORTS_CPUFREQ
>> 1727 select MIPS_EXTERNAL_TIMER
>> 1728 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
1064 help 1729 help
1065 Multi-core scheduler support improv !! 1730 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
1066 making when dealing with multi-core <<
1067 increased overhead in some places. <<
1068 1731
1069 config SCHED_MC_PRIO !! 1732 endchoice
1070 bool "CPU core priorities scheduler s !! 1733
1071 depends on SCHED_MC !! 1734 config CPU_MIPS32_3_5_FEATURES
1072 select X86_INTEL_PSTATE if CPU_SUP_IN !! 1735 bool "MIPS32 Release 3.5 Features"
1073 select X86_AMD_PSTATE if CPU_SUP_AMD !! 1736 depends on SYS_HAS_CPU_MIPS32_R3_5
1074 select CPU_FREQ !! 1737 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1738 CPU_P5600
>> 1739 help
>> 1740 Choose this option to build a kernel for release 2 or later of the
>> 1741 MIPS32 architecture including features from the 3.5 release such as
>> 1742 support for Enhanced Virtual Addressing (EVA).
>> 1743
>> 1744 config CPU_MIPS32_3_5_EVA
>> 1745 bool "Enhanced Virtual Addressing (EVA)"
>> 1746 depends on CPU_MIPS32_3_5_FEATURES
>> 1747 select EVA
>> 1748 default y
>> 1749 help
>> 1750 Choose this option if you want to enable the Enhanced Virtual
>> 1751 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1752 One of its primary benefits is an increase in the maximum size
>> 1753 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1754
>> 1755 config CPU_MIPS32_R5_FEATURES
>> 1756 bool "MIPS32 Release 5 Features"
>> 1757 depends on SYS_HAS_CPU_MIPS32_R5
>> 1758 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1759 help
>> 1760 Choose this option to build a kernel for release 2 or later of the
>> 1761 MIPS32 architecture including features from release 5 such as
>> 1762 support for Extended Physical Addressing (XPA).
>> 1763
>> 1764 config CPU_MIPS32_R5_XPA
>> 1765 bool "Extended Physical Addressing (XPA)"
>> 1766 depends on CPU_MIPS32_R5_FEATURES
>> 1767 depends on !EVA
>> 1768 depends on !PAGE_SIZE_4KB
>> 1769 depends on SYS_SUPPORTS_HIGHMEM
>> 1770 select XPA
>> 1771 select HIGHMEM
>> 1772 select PHYS_ADDR_T_64BIT
>> 1773 default n
>> 1774 help
>> 1775 Choose this option if you want to enable the Extended Physical
>> 1776 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1777 benefit is to increase physical addressing equal to or greater
>> 1778 than 40 bits. Note that this has the side effect of turning on
>> 1779 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1780 If unsure, say 'N' here.
>> 1781
>> 1782 if CPU_LOONGSON2F
>> 1783 config CPU_NOP_WORKAROUNDS
>> 1784 bool
>> 1785
>> 1786 config CPU_JUMP_WORKAROUNDS
>> 1787 bool
>> 1788
>> 1789 config CPU_LOONGSON2F_WORKAROUNDS
>> 1790 bool "Loongson 2F Workarounds"
1075 default y 1791 default y
>> 1792 select CPU_NOP_WORKAROUNDS
>> 1793 select CPU_JUMP_WORKAROUNDS
1076 help 1794 help
1077 Intel Turbo Boost Max Technology 3. !! 1795 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1078 core ordering determined at manufac !! 1796 require workarounds. Without workarounds the system may hang
1079 certain cores to reach higher turbo !! 1797 unexpectedly. For more information please refer to the gas
1080 single threaded workloads) than oth !! 1798 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1799
>> 1800 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1801 are needed. The workarounds have no significant side effect on them
>> 1802 but may decrease the performance of the system so this option should
>> 1803 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1804 systems.
1081 1805
1082 Enabling this kernel feature teache !! 1806 If unsure, please say Y.
1083 the TBM3 (aka ITMT) priority order !! 1807 endif # CPU_LOONGSON2F
1084 scheduler's CPU selection logic acc <<
1085 overall system performance can be a <<
1086 1808
1087 This feature will have no effect on !! 1809 config SYS_SUPPORTS_ZBOOT
>> 1810 bool
>> 1811 select HAVE_KERNEL_GZIP
>> 1812 select HAVE_KERNEL_BZIP2
>> 1813 select HAVE_KERNEL_LZ4
>> 1814 select HAVE_KERNEL_LZMA
>> 1815 select HAVE_KERNEL_LZO
>> 1816 select HAVE_KERNEL_XZ
>> 1817 select HAVE_KERNEL_ZSTD
1088 1818
1089 If unsure say Y here. !! 1819 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1820 bool
>> 1821 select SYS_SUPPORTS_ZBOOT
1090 1822
1091 config UP_LATE_INIT !! 1823 config SYS_SUPPORTS_ZBOOT_UART_PROM
1092 def_bool y !! 1824 bool
1093 depends on !SMP && X86_LOCAL_APIC !! 1825 select SYS_SUPPORTS_ZBOOT
1094 1826
1095 config X86_UP_APIC !! 1827 config CPU_LOONGSON2EF
1096 bool "Local APIC support on uniproces !! 1828 bool
1097 default PCI_MSI !! 1829 select CPU_SUPPORTS_32BIT_KERNEL
1098 depends on X86_32 && !SMP && !X86_32_ !! 1830 select CPU_SUPPORTS_64BIT_KERNEL
1099 help !! 1831 select CPU_SUPPORTS_HIGHMEM
1100 A local APIC (Advanced Programmable !! 1832 select CPU_SUPPORTS_HUGEPAGES
1101 integrated interrupt controller in !! 1833 select ARCH_HAS_PHYS_TO_DMA
1102 system which has a processor with a <<
1103 enable and use it. If you say Y her <<
1104 have a local APIC, then the kernel <<
1105 all. The local APIC supports CPU-ge <<
1106 performance counters), and the NMI <<
1107 lockups. <<
1108 <<
1109 config X86_UP_IOAPIC <<
1110 bool "IO-APIC support on uniprocessor <<
1111 depends on X86_UP_APIC <<
1112 help <<
1113 An IO-APIC (I/O Advanced Programmab <<
1114 SMP-capable replacement for PC-styl <<
1115 SMP systems and many recent uniproc <<
1116 <<
1117 If you have a single-CPU system wit <<
1118 to use it. If you say Y here even t <<
1119 an IO-APIC, then the kernel will st <<
1120 1834
1121 config X86_LOCAL_APIC !! 1835 config CPU_LOONGSON32
1122 def_bool y !! 1836 bool
1123 depends on X86_64 || SMP || X86_32_NO !! 1837 select CPU_MIPS32
1124 select IRQ_DOMAIN_HIERARCHY !! 1838 select CPU_MIPSR2
>> 1839 select CPU_HAS_PREFETCH
>> 1840 select CPU_SUPPORTS_32BIT_KERNEL
>> 1841 select CPU_SUPPORTS_HIGHMEM
>> 1842 select CPU_SUPPORTS_CPUFREQ
1125 1843
1126 config ACPI_MADT_WAKEUP !! 1844 config CPU_BMIPS32_3300
1127 def_bool y !! 1845 select SMP_UP if SMP
1128 depends on X86_64 !! 1846 bool
1129 depends on ACPI <<
1130 depends on SMP <<
1131 depends on X86_LOCAL_APIC <<
1132 1847
1133 config X86_IO_APIC !! 1848 config CPU_BMIPS4350
1134 def_bool y !! 1849 bool
1135 depends on X86_LOCAL_APIC || X86_UP_I !! 1850 select SYS_SUPPORTS_SMP
>> 1851 select SYS_SUPPORTS_HOTPLUG_CPU
1136 1852
1137 config X86_REROUTE_FOR_BROKEN_BOOT_IRQS !! 1853 config CPU_BMIPS4380
1138 bool "Reroute for broken boot IRQs" !! 1854 bool
1139 depends on X86_IO_APIC !! 1855 select MIPS_L1_CACHE_SHIFT_6
1140 help !! 1856 select SYS_SUPPORTS_SMP
1141 This option enables a workaround th !! 1857 select SYS_SUPPORTS_HOTPLUG_CPU
1142 spurious interrupts. This is recomm !! 1858 select CPU_HAS_RIXI
1143 interrupt handling is used on syste <<
1144 superfluous "boot interrupts" canno <<
1145 <<
1146 Some chipsets generate a legacy INT <<
1147 entry in the chipset's IO-APIC is m <<
1148 kernel does during interrupt handli <<
1149 boot IRQ generation cannot be disab <<
1150 the original IRQ line masked so tha <<
1151 IRQ" is delivered to the CPUs. The <<
1152 kernel to set up the IRQ handler on <<
1153 way only one interrupt is delivered <<
1154 the spurious second interrupt may c <<
1155 down (vital) interrupt lines. <<
1156 <<
1157 Only affects "broken" chipsets. Int <<
1158 increased on these systems. <<
1159 <<
1160 config X86_MCE <<
1161 bool "Machine Check / overheating rep <<
1162 select GENERIC_ALLOCATOR <<
1163 default y <<
1164 help <<
1165 Machine Check support allows the pr <<
1166 kernel if it detects a problem (e.g <<
1167 The action the kernel takes depends <<
1168 ranging from warning messages to ha <<
1169 <<
1170 config X86_MCELOG_LEGACY <<
1171 bool "Support for deprecated /dev/mce <<
1172 depends on X86_MCE <<
1173 help <<
1174 Enable support for /dev/mcelog whic <<
1175 userspace logging daemon. Consider <<
1176 rasdaemon solution. <<
1177 1859
1178 config X86_MCE_INTEL !! 1860 config CPU_BMIPS5000
1179 def_bool y !! 1861 bool
1180 prompt "Intel MCE features" !! 1862 select MIPS_CPU_SCACHE
1181 depends on X86_MCE && X86_LOCAL_APIC !! 1863 select MIPS_L1_CACHE_SHIFT_7
1182 help !! 1864 select SYS_SUPPORTS_SMP
1183 Additional support for intel specif !! 1865 select SYS_SUPPORTS_HOTPLUG_CPU
1184 the thermal monitor. !! 1866 select CPU_HAS_RIXI
1185 1867
1186 config X86_MCE_AMD !! 1868 config SYS_HAS_CPU_LOONGSON64
1187 def_bool y !! 1869 bool
1188 prompt "AMD MCE features" !! 1870 select CPU_SUPPORTS_CPUFREQ
1189 depends on X86_MCE && X86_LOCAL_APIC !! 1871 select CPU_HAS_RIXI
1190 help <<
1191 Additional support for AMD specific <<
1192 the DRAM Error Threshold. <<
1193 1872
1194 config X86_ANCIENT_MCE !! 1873 config SYS_HAS_CPU_LOONGSON2E
1195 bool "Support for old Pentium 5 / Win !! 1874 bool
1196 depends on X86_32 && X86_MCE <<
1197 help <<
1198 Include support for machine check h <<
1199 systems. These typically need to be <<
1200 line. <<
1201 1875
1202 config X86_MCE_THRESHOLD !! 1876 config SYS_HAS_CPU_LOONGSON2F
1203 depends on X86_MCE_AMD || X86_MCE_INT !! 1877 bool
1204 def_bool y !! 1878 select CPU_SUPPORTS_CPUFREQ
>> 1879 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1205 1880
1206 config X86_MCE_INJECT !! 1881 config SYS_HAS_CPU_LOONGSON1B
1207 depends on X86_MCE && X86_LOCAL_APIC !! 1882 bool
1208 tristate "Machine check injector supp <<
1209 help <<
1210 Provide support for injecting machi <<
1211 If you don't know what a machine ch <<
1212 QA it is safe to say n. <<
1213 1883
1214 source "arch/x86/events/Kconfig" !! 1884 config SYS_HAS_CPU_LOONGSON1C
>> 1885 bool
1215 1886
1216 config X86_LEGACY_VM86 !! 1887 config SYS_HAS_CPU_MIPS32_R1
1217 bool "Legacy VM86 support" !! 1888 bool
1218 depends on X86_32 <<
1219 help <<
1220 This option allows user programs to <<
1221 mode, which is an 80286-era approxi <<
1222 1889
1223 Some very old versions of X and/or !! 1890 config SYS_HAS_CPU_MIPS32_R2
1224 for user mode setting. Similarly, !! 1891 bool
1225 available to accelerate real mode D <<
1226 recent version of DOSEMU, X, or vbe <<
1227 functional even without kernel VM86 <<
1228 fall back to software emulation. Ne <<
1229 a 16-bit DOS program where 16-bit p <<
1230 mode might be faster than emulation <<
1231 enable this option. <<
1232 1892
1233 Note that any app that works on a 6 !! 1893 config SYS_HAS_CPU_MIPS32_R3_5
1234 need this option, as 64-bit kernels !! 1894 bool
1235 V8086 mode. This option is also unr <<
1236 mode and is not needed to run most <<
1237 1895
1238 Enabling this option increases the !! 1896 config SYS_HAS_CPU_MIPS32_R5
1239 and slows down exception handling a !! 1897 bool
>> 1898 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1240 1899
1241 If unsure, say N here. !! 1900 config SYS_HAS_CPU_MIPS32_R6
>> 1901 bool
>> 1902 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1242 1903
1243 config VM86 !! 1904 config SYS_HAS_CPU_MIPS64_R1
1244 bool 1905 bool
1245 default X86_LEGACY_VM86 <<
1246 1906
1247 config X86_16BIT !! 1907 config SYS_HAS_CPU_MIPS64_R2
1248 bool "Enable support for 16-bit segme !! 1908 bool
1249 default y <<
1250 depends on MODIFY_LDT_SYSCALL <<
1251 help <<
1252 This option is required by programs <<
1253 protected mode legacy code on x86 p <<
1254 this option saves about 300 bytes o <<
1255 plus 16K runtime memory on x86-64, <<
1256 1909
1257 config X86_ESPFIX32 !! 1910 config SYS_HAS_CPU_MIPS64_R5
1258 def_bool y !! 1911 bool
1259 depends on X86_16BIT && X86_32 !! 1912 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1260 1913
1261 config X86_ESPFIX64 !! 1914 config SYS_HAS_CPU_MIPS64_R6
1262 def_bool y !! 1915 bool
1263 depends on X86_16BIT && X86_64 !! 1916 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1264 1917
1265 config X86_VSYSCALL_EMULATION !! 1918 config SYS_HAS_CPU_P5600
1266 bool "Enable vsyscall emulation" if E !! 1919 bool
1267 default y !! 1920 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1268 depends on X86_64 <<
1269 help <<
1270 This enables emulation of the legac <<
1271 it is roughly equivalent to booting <<
1272 that it will also disable the helpf <<
1273 tries to use a vsyscall. With this <<
1274 programs will just segfault, citing <<
1275 0xffffffffff600?00. <<
1276 1921
1277 This option is required by many pro !! 1922 config SYS_HAS_CPU_R3000
1278 care should be used even with newer !! 1923 bool
1279 1924
1280 Disabling this option saves about 7 !! 1925 config SYS_HAS_CPU_TX39XX
1281 possibly 4K of additional runtime p !! 1926 bool
1282 1927
1283 config X86_IOPL_IOPERM !! 1928 config SYS_HAS_CPU_VR41XX
1284 bool "IOPERM and IOPL Emulation" !! 1929 bool
1285 default y <<
1286 help <<
1287 This enables the ioperm() and iopl( <<
1288 for legacy applications. <<
1289 1930
1290 Legacy IOPL support is an overbroad !! 1931 config SYS_HAS_CPU_R4300
1291 space aside of accessing all 65536 !! 1932 bool
1292 interrupts. To gain this access the <<
1293 capabilities and permission from po <<
1294 modules. <<
1295 <<
1296 The emulation restricts the functio <<
1297 only allowing the full range I/O po <<
1298 ability to disable interrupts from <<
1299 granted if the hardware IOPL mechan <<
1300 <<
1301 config TOSHIBA <<
1302 tristate "Toshiba Laptop support" <<
1303 depends on X86_32 <<
1304 help <<
1305 This adds a driver to safely access <<
1306 the CPU on Toshiba portables with a <<
1307 not work on models with a Phoenix B <<
1308 is used to set the BIOS and power s <<
1309 <<
1310 For information on utilities to mak <<
1311 Toshiba Linux utilities web site at <<
1312 <http://www.buzzard.org.uk/toshiba/ <<
1313 <<
1314 Say Y if you intend to run this ker <<
1315 Say N otherwise. <<
1316 <<
1317 config X86_REBOOTFIXUPS <<
1318 bool "Enable X86 board specific fixup <<
1319 depends on X86_32 <<
1320 help <<
1321 This enables chipset and/or board s <<
1322 in order to get reboot to work corr <<
1323 some combinations of hardware and B <<
1324 this config is intended, is when re <<
1325 system. <<
1326 <<
1327 Currently, the only fixup is for th <<
1328 CS5530A and CS5536 chipsets and the <<
1329 <<
1330 Say Y if you want to enable the fix <<
1331 enable this option even if you don' <<
1332 Say N otherwise. <<
1333 1933
1334 config MICROCODE !! 1934 config SYS_HAS_CPU_R4X00
1335 def_bool y !! 1935 bool
1336 depends on CPU_SUP_AMD || CPU_SUP_INT <<
1337 1936
1338 config MICROCODE_INITRD32 !! 1937 config SYS_HAS_CPU_TX49XX
1339 def_bool y !! 1938 bool
1340 depends on MICROCODE && X86_32 && BLK <<
1341 1939
1342 config MICROCODE_LATE_LOADING !! 1940 config SYS_HAS_CPU_R5000
1343 bool "Late microcode loading (DANGERO !! 1941 bool
1344 default n <<
1345 depends on MICROCODE && SMP <<
1346 help <<
1347 Loading microcode late, when the sy <<
1348 is a tricky business and should be <<
1349 of synchronizing all cores and SMT <<
1350 not guarantee that cores might not <<
1351 use this at your own risk. Late loa <<
1352 microcode header indicates that it <<
1353 minimal revision check. This minima <<
1354 the kernel command line with "micro <<
1355 1942
1356 config MICROCODE_LATE_FORCE_MINREV !! 1943 config SYS_HAS_CPU_R5500
1357 bool "Enforce late microcode loading !! 1944 bool
1358 default n <<
1359 depends on MICROCODE_LATE_LOADING <<
1360 help <<
1361 To prevent that users load microcod <<
1362 in use features, newer microcode pa <<
1363 in the microcode header, which tell <<
1364 revision must be active in the CPU <<
1365 late into the running system. If di <<
1366 be enforced but the kernel will be <<
1367 revision check fails. <<
1368 <<
1369 This minimal revision check can als <<
1370 "microcode.minrev" parameter on the <<
1371 <<
1372 If unsure say Y. <<
1373 <<
1374 config X86_MSR <<
1375 tristate "/dev/cpu/*/msr - Model-spec <<
1376 help <<
1377 This device gives privileged proces <<
1378 Model-Specific Registers (MSRs). I <<
1379 major 202 and minors 0 to 31 for /d <<
1380 MSR accesses are directed to a spec <<
1381 systems. <<
1382 1945
1383 config X86_CPUID !! 1946 config SYS_HAS_CPU_NEVADA
1384 tristate "/dev/cpu/*/cpuid - CPU info !! 1947 bool
1385 help <<
1386 This device gives processes access <<
1387 be executed on a specific processor <<
1388 with major 203 and minors 0 to 31 f <<
1389 /dev/cpu/31/cpuid. <<
1390 1948
1391 choice !! 1949 config SYS_HAS_CPU_R10000
1392 prompt "High Memory Support" !! 1950 bool
1393 default HIGHMEM4G !! 1951 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1394 depends on X86_32 <<
1395 <<
1396 config NOHIGHMEM <<
1397 bool "off" <<
1398 help <<
1399 Linux can use up to 64 Gigabytes of <<
1400 However, the address space of 32-bi <<
1401 Gigabytes large. That means that, i <<
1402 physical memory, not all of it can <<
1403 kernel. The physical memory that's <<
1404 "high memory". <<
1405 <<
1406 If you are compiling a kernel which <<
1407 more than 1 Gigabyte total physical <<
1408 choice and suitable for most users) <<
1409 split: 3GB are mapped so that each <<
1410 space and the remaining part of the <<
1411 by the kernel to permanently map as <<
1412 possible. <<
1413 <<
1414 If the machine has between 1 and 4 <<
1415 answer "4GB" here. <<
1416 <<
1417 If more than 4 Gigabytes is used th <<
1418 selection turns Intel PAE (Physical <<
1419 PAE implements 3-level paging on IA <<
1420 supported by Linux, PAE mode is imp <<
1421 processors (Pentium Pro and better) <<
1422 then the kernel will not boot on CP <<
1423 <<
1424 The actual amount of total physical <<
1425 auto detected or can be forced by u <<
1426 such as "mem=256M". (Try "man bootp <<
1427 your boot loader (lilo or loadlin) <<
1428 kernel at boot time.) <<
1429 <<
1430 If unsure, say "off". <<
1431 <<
1432 config HIGHMEM4G <<
1433 bool "4GB" <<
1434 help <<
1435 Select this if you have a 32-bit pr <<
1436 gigabytes of physical RAM. <<
1437 <<
1438 config HIGHMEM64G <<
1439 bool "64GB" <<
1440 depends on X86_HAVE_PAE <<
1441 select X86_PAE <<
1442 help <<
1443 Select this if you have a 32-bit pr <<
1444 gigabytes of physical RAM. <<
1445 1952
1446 endchoice !! 1953 config SYS_HAS_CPU_RM7000
>> 1954 bool
1447 1955
1448 choice !! 1956 config SYS_HAS_CPU_SB1
1449 prompt "Memory split" if EXPERT !! 1957 bool
1450 default VMSPLIT_3G <<
1451 depends on X86_32 <<
1452 help <<
1453 Select the desired split between ke <<
1454 <<
1455 If the address range available to t <<
1456 physical memory installed, the rema <<
1457 as "high memory". Accessing high me <<
1458 than low memory, as it needs to be <<
1459 Note that increasing the kernel add <<
1460 available to user programs, making <<
1461 tighter. Selecting anything other <<
1462 will also likely make your kernel i <<
1463 kernel modules. <<
1464 <<
1465 If you are not absolutely sure what <<
1466 option alone! <<
1467 <<
1468 config VMSPLIT_3G <<
1469 bool "3G/1G user/kernel split <<
1470 config VMSPLIT_3G_OPT <<
1471 depends on !X86_PAE <<
1472 bool "3G/1G user/kernel split <<
1473 config VMSPLIT_2G <<
1474 bool "2G/2G user/kernel split <<
1475 config VMSPLIT_2G_OPT <<
1476 depends on !X86_PAE <<
1477 bool "2G/2G user/kernel split <<
1478 config VMSPLIT_1G <<
1479 bool "1G/3G user/kernel split <<
1480 endchoice <<
1481 1958
1482 config PAGE_OFFSET !! 1959 config SYS_HAS_CPU_CAVIUM_OCTEON
1483 hex !! 1960 bool
1484 default 0xB0000000 if VMSPLIT_3G_OPT <<
1485 default 0x80000000 if VMSPLIT_2G <<
1486 default 0x78000000 if VMSPLIT_2G_OPT <<
1487 default 0x40000000 if VMSPLIT_1G <<
1488 default 0xC0000000 <<
1489 depends on X86_32 <<
1490 1961
1491 config HIGHMEM !! 1962 config SYS_HAS_CPU_BMIPS
1492 def_bool y !! 1963 bool
1493 depends on X86_32 && (HIGHMEM64G || H <<
1494 1964
1495 config X86_PAE !! 1965 config SYS_HAS_CPU_BMIPS32_3300
1496 bool "PAE (Physical Address Extension !! 1966 bool
1497 depends on X86_32 && X86_HAVE_PAE !! 1967 select SYS_HAS_CPU_BMIPS
1498 select PHYS_ADDR_T_64BIT <<
1499 select SWIOTLB <<
1500 help <<
1501 PAE is required for NX support, and <<
1502 larger swapspace support for non-ov <<
1503 has the cost of more pagetable look <<
1504 consumes more pagetable space per p <<
1505 1968
1506 config X86_5LEVEL !! 1969 config SYS_HAS_CPU_BMIPS4350
1507 bool "Enable 5-level page tables supp !! 1970 bool
1508 default y !! 1971 select SYS_HAS_CPU_BMIPS
1509 select DYNAMIC_MEMORY_LAYOUT <<
1510 select SPARSEMEM_VMEMMAP <<
1511 depends on X86_64 <<
1512 help <<
1513 5-level paging enables access to la <<
1514 up to 128 PiB of virtual address sp <<
1515 physical address space. <<
1516 1972
1517 It will be supported by future Inte !! 1973 config SYS_HAS_CPU_BMIPS4380
>> 1974 bool
>> 1975 select SYS_HAS_CPU_BMIPS
1518 1976
1519 A kernel with the option enabled ca !! 1977 config SYS_HAS_CPU_BMIPS5000
1520 support 4- or 5-level paging. !! 1978 bool
>> 1979 select SYS_HAS_CPU_BMIPS
>> 1980 select ARCH_HAS_SYNC_DMA_FOR_CPU
1521 1981
1522 See Documentation/arch/x86/x86_64/5 !! 1982 #
1523 information. !! 1983 # CPU may reorder R->R, R->W, W->R, W->W
>> 1984 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1985 #
>> 1986 config WEAK_ORDERING
>> 1987 bool
1524 1988
1525 Say N if unsure. !! 1989 #
>> 1990 # CPU may reorder reads and writes beyond LL/SC
>> 1991 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 1992 #
>> 1993 config WEAK_REORDERING_BEYOND_LLSC
>> 1994 bool
>> 1995 endmenu
1526 1996
1527 config X86_DIRECT_GBPAGES !! 1997 #
1528 def_bool y !! 1998 # These two indicate any level of the MIPS32 and MIPS64 architecture
1529 depends on X86_64 !! 1999 #
1530 help !! 2000 config CPU_MIPS32
1531 Certain kernel features effectively !! 2001 bool
1532 linear 1 GB mappings (even if the C !! 2002 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
1533 supports them), so don't confuse th !! 2003 CPU_MIPS32_R6 || CPU_P5600
1534 that we have them enabled. <<
1535 <<
1536 config X86_CPA_STATISTICS <<
1537 bool "Enable statistic for Change Pag <<
1538 depends on DEBUG_FS <<
1539 help <<
1540 Expose statistics about the Change <<
1541 helps to determine the effectivenes <<
1542 page mappings when mapping protecti <<
1543 <<
1544 config X86_MEM_ENCRYPT <<
1545 select ARCH_HAS_FORCE_DMA_UNENCRYPTED <<
1546 select DYNAMIC_PHYSICAL_MASK <<
1547 def_bool n <<
1548 2004
1549 config AMD_MEM_ENCRYPT !! 2005 config CPU_MIPS64
1550 bool "AMD Secure Memory Encryption (S !! 2006 bool
1551 depends on X86_64 && CPU_SUP_AMD !! 2007 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
1552 depends on EFI_STUB !! 2008 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1553 select DMA_COHERENT_POOL <<
1554 select ARCH_USE_MEMREMAP_PROT <<
1555 select INSTRUCTION_DECODER <<
1556 select ARCH_HAS_CC_PLATFORM <<
1557 select X86_MEM_ENCRYPT <<
1558 select UNACCEPTED_MEMORY <<
1559 help <<
1560 Say yes to enable support for the e <<
1561 This requires an AMD processor that <<
1562 Encryption (SME). <<
1563 2009
1564 # Common NUMA Features !! 2010 #
1565 config NUMA !! 2011 # These indicate the revision of the architecture
1566 bool "NUMA Memory Allocation and Sche !! 2012 #
1567 depends on SMP !! 2013 config CPU_MIPSR1
1568 depends on X86_64 || (X86_32 && HIGHM !! 2014 bool
1569 default y if X86_BIGSMP !! 2015 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1570 select USE_PERCPU_NUMA_NODE_ID !! 2016
1571 select OF_NUMA if OF !! 2017 config CPU_MIPSR2
>> 2018 bool
>> 2019 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2020 select CPU_HAS_RIXI
>> 2021 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2022 select MIPS_SPRAM
>> 2023
>> 2024 config CPU_MIPSR5
>> 2025 bool
>> 2026 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2027 select CPU_HAS_RIXI
>> 2028 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2029 select MIPS_SPRAM
>> 2030
>> 2031 config CPU_MIPSR6
>> 2032 bool
>> 2033 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2034 select CPU_HAS_RIXI
>> 2035 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2036 select HAVE_ARCH_BITREVERSE
>> 2037 select MIPS_ASID_BITS_VARIABLE
>> 2038 select MIPS_CRC_SUPPORT
>> 2039 select MIPS_SPRAM
>> 2040
>> 2041 config TARGET_ISA_REV
>> 2042 int
>> 2043 default 1 if CPU_MIPSR1
>> 2044 default 2 if CPU_MIPSR2
>> 2045 default 5 if CPU_MIPSR5
>> 2046 default 6 if CPU_MIPSR6
>> 2047 default 0
1572 help 2048 help
1573 Enable NUMA (Non-Uniform Memory Acc !! 2049 Reflects the ISA revision being targeted by the kernel build. This
>> 2050 is effectively the Kconfig equivalent of MIPS_ISA_REV.
>> 2051
>> 2052 config EVA
>> 2053 bool
1574 2054
1575 The kernel will try to allocate mem !! 2055 config XPA
1576 local memory controller of the CPU !! 2056 bool
1577 NUMA awareness to the kernel. <<
1578 2057
1579 For 64-bit this is recommended if t !! 2058 config SYS_SUPPORTS_32BIT_KERNEL
1580 (or later), AMD Opteron, or EM64T N !! 2059 bool
>> 2060 config SYS_SUPPORTS_64BIT_KERNEL
>> 2061 bool
>> 2062 config CPU_SUPPORTS_32BIT_KERNEL
>> 2063 bool
>> 2064 config CPU_SUPPORTS_64BIT_KERNEL
>> 2065 bool
>> 2066 config CPU_SUPPORTS_CPUFREQ
>> 2067 bool
>> 2068 config CPU_SUPPORTS_ADDRWINCFG
>> 2069 bool
>> 2070 config CPU_SUPPORTS_HUGEPAGES
>> 2071 bool
>> 2072 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2073 config MIPS_PGD_C0_CONTEXT
>> 2074 bool
>> 2075 depends on 64BIT
>> 2076 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1581 2077
1582 For 32-bit this is only needed if y !! 2078 #
1583 kernel on a 64-bit NUMA platform. !! 2079 # Set to y for ptrace access to watch registers.
>> 2080 #
>> 2081 config HARDWARE_WATCHPOINTS
>> 2082 bool
>> 2083 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1584 2084
1585 Otherwise, you should say N. !! 2085 menu "Kernel type"
1586 2086
1587 config AMD_NUMA !! 2087 choice
1588 def_bool y !! 2088 prompt "Kernel code model"
1589 prompt "Old style AMD Opteron NUMA de !! 2089 help
1590 depends on X86_64 && NUMA && PCI !! 2090 You should only select this option if you have a workload that
>> 2091 actually benefits from 64-bit processing or if your machine has
>> 2092 large memory. You will only be presented a single option in this
>> 2093 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2094
>> 2095 config 32BIT
>> 2096 bool "32-bit kernel"
>> 2097 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2098 select TRAD_SIGNALS
1591 help 2099 help
1592 Enable AMD NUMA node topology detec !! 2100 Select this option if you want to build a 32-bit kernel.
1593 you have a multi processor AMD syst <<
1594 read the NUMA configuration directl <<
1595 of Opteron. It is recommended to us <<
1596 which also takes priority if both a <<
1597 2101
1598 config X86_64_ACPI_NUMA !! 2102 config 64BIT
1599 def_bool y !! 2103 bool "64-bit kernel"
1600 prompt "ACPI NUMA detection" !! 2104 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1601 depends on X86_64 && NUMA && ACPI && <<
1602 select ACPI_NUMA <<
1603 help 2105 help
1604 Enable ACPI SRAT based node topolog !! 2106 Select this option if you want to build a 64-bit kernel.
1605 2107
1606 config NODES_SHIFT !! 2108 endchoice
1607 int "Maximum NUMA Nodes (as a power o !! 2109
1608 range 1 10 !! 2110 config MIPS_VA_BITS_48
1609 default "10" if MAXSMP !! 2111 bool "48 bits virtual memory"
1610 default "6" if X86_64 !! 2112 depends on 64BIT
1611 default "3" <<
1612 depends on NUMA <<
1613 help 2113 help
1614 Specify the maximum number of NUMA !! 2114 Support a maximum at least 48 bits of application virtual
1615 system. Increases memory reserved !! 2115 memory. Default is 40 bits or less, depending on the CPU.
>> 2116 For page sizes 16k and above, this option results in a small
>> 2117 memory overhead for page tables. For 4k page size, a fourth
>> 2118 level of page tables is added which imposes both a memory
>> 2119 overhead as well as slower TLB fault handling.
1616 2120
1617 config ARCH_FLATMEM_ENABLE !! 2121 If unsure, say N.
1618 def_bool y <<
1619 depends on X86_32 && !NUMA <<
1620 2122
1621 config ARCH_SPARSEMEM_ENABLE !! 2123 choice
1622 def_bool y !! 2124 prompt "Kernel page size"
1623 depends on X86_64 || NUMA || X86_32 | !! 2125 default PAGE_SIZE_4KB
1624 select SPARSEMEM_STATIC if X86_32 <<
1625 select SPARSEMEM_VMEMMAP_ENABLE if X8 <<
1626 2126
1627 config ARCH_SPARSEMEM_DEFAULT !! 2127 config PAGE_SIZE_4KB
1628 def_bool X86_64 || (NUMA && X86_32) !! 2128 bool "4kB"
>> 2129 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2130 help
>> 2131 This option select the standard 4kB Linux page size. On some
>> 2132 R3000-family processors this is the only available page size. Using
>> 2133 4kB page size will minimize memory consumption and is therefore
>> 2134 recommended for low memory systems.
>> 2135
>> 2136 config PAGE_SIZE_8KB
>> 2137 bool "8kB"
>> 2138 depends on CPU_CAVIUM_OCTEON
>> 2139 depends on !MIPS_VA_BITS_48
>> 2140 help
>> 2141 Using 8kB page size will result in higher performance kernel at
>> 2142 the price of higher memory consumption. This option is available
>> 2143 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2144 distribution to support this.
>> 2145
>> 2146 config PAGE_SIZE_16KB
>> 2147 bool "16kB"
>> 2148 depends on !CPU_R3000 && !CPU_TX39XX
>> 2149 help
>> 2150 Using 16kB page size will result in higher performance kernel at
>> 2151 the price of higher memory consumption. This option is available on
>> 2152 all non-R3000 family processors. Note that you will need a suitable
>> 2153 Linux distribution to support this.
>> 2154
>> 2155 config PAGE_SIZE_32KB
>> 2156 bool "32kB"
>> 2157 depends on CPU_CAVIUM_OCTEON
>> 2158 depends on !MIPS_VA_BITS_48
>> 2159 help
>> 2160 Using 32kB page size will result in higher performance kernel at
>> 2161 the price of higher memory consumption. This option is available
>> 2162 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2163 distribution to support this.
>> 2164
>> 2165 config PAGE_SIZE_64KB
>> 2166 bool "64kB"
>> 2167 depends on !CPU_R3000 && !CPU_TX39XX
>> 2168 help
>> 2169 Using 64kB page size will result in higher performance kernel at
>> 2170 the price of higher memory consumption. This option is available on
>> 2171 all non-R3000 family processor. Not that at the time of this
>> 2172 writing this option is still high experimental.
1629 2173
1630 config ARCH_SELECT_MEMORY_MODEL !! 2174 endchoice
1631 def_bool y <<
1632 depends on ARCH_SPARSEMEM_ENABLE && A <<
1633 2175
1634 config ARCH_MEMORY_PROBE !! 2176 config FORCE_MAX_ZONEORDER
1635 bool "Enable sysfs memory/probe inter !! 2177 int "Maximum zone order"
1636 depends on MEMORY_HOTPLUG !! 2178 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1637 help !! 2179 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1638 This option enables a sysfs memory/ !! 2180 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1639 See Documentation/admin-guide/mm/me !! 2181 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
1640 If you are unsure how to answer thi !! 2182 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2183 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2184 range 0 64
>> 2185 default "11"
>> 2186 help
>> 2187 The kernel memory allocator divides physically contiguous memory
>> 2188 blocks into "zones", where each zone is a power of two number of
>> 2189 pages. This option selects the largest power of two that the kernel
>> 2190 keeps in the memory allocator. If you need to allocate very large
>> 2191 blocks of physically contiguous memory, then you may need to
>> 2192 increase this value.
1641 2193
1642 config ARCH_PROC_KCORE_TEXT !! 2194 This config option is actually maximum order plus one. For example,
1643 def_bool y !! 2195 a value of 11 means that the largest free memory block is 2^10 pages.
1644 depends on X86_64 && PROC_KCORE <<
1645 2196
1646 config ILLEGAL_POINTER_VALUE !! 2197 The page size is not necessarily 4KB. Keep this in mind
1647 hex !! 2198 when choosing a value for this option.
1648 default 0 if X86_32 <<
1649 default 0xdead000000000000 if X86_64 <<
1650 <<
1651 config X86_PMEM_LEGACY_DEVICE <<
1652 bool <<
1653 <<
1654 config X86_PMEM_LEGACY <<
1655 tristate "Support non-standard NVDIMM <<
1656 depends on PHYS_ADDR_T_64BIT <<
1657 depends on BLK_DEV <<
1658 select X86_PMEM_LEGACY_DEVICE <<
1659 select NUMA_KEEP_MEMINFO if NUMA <<
1660 select LIBNVDIMM <<
1661 help <<
1662 Treat memory marked using the non-s <<
1663 by the Intel Sandy Bridge-EP refere <<
1664 The kernel will offer these regions <<
1665 they can be used for persistent sto <<
1666 <<
1667 Say Y if unsure. <<
1668 <<
1669 config HIGHPTE <<
1670 bool "Allocate 3rd-level pagetables f <<
1671 depends on HIGHMEM <<
1672 help <<
1673 The VM uses one page table entry fo <<
1674 For systems with a lot of RAM, this <<
1675 low memory. Setting this option wi <<
1676 entries in high memory. <<
1677 <<
1678 config X86_CHECK_BIOS_CORRUPTION <<
1679 bool "Check for low memory corruption <<
1680 help <<
1681 Periodically check for memory corru <<
1682 is suspected to be caused by BIOS. <<
1683 configuration, it is disabled at ru <<
1684 setting "memory_corruption_check=1" <<
1685 line. By default it scans the low <<
1686 seconds; see the memory_corruption_ <<
1687 memory_corruption_check_period para <<
1688 Documentation/admin-guide/kernel-pa <<
1689 <<
1690 When enabled with the default param <<
1691 almost no overhead, as it reserves <<
1692 of memory and scans it infrequently <<
1693 and prevents it from affecting the <<
1694 <<
1695 It is, however, intended as a diagn <<
1696 BIOS-originated corruption always a <<
1697 you can use memmap= to prevent the <<
1698 memory. <<
1699 <<
1700 config X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK <<
1701 bool "Set the default setting of memo <<
1702 depends on X86_CHECK_BIOS_CORRUPTION <<
1703 default y <<
1704 help <<
1705 Set whether the default state of me <<
1706 on or off. <<
1707 2199
1708 config MATH_EMULATION !! 2200 config BOARD_SCACHE
1709 bool 2201 bool
1710 depends on MODIFY_LDT_SYSCALL <<
1711 prompt "Math emulation" if X86_32 && <<
1712 help <<
1713 Linux can emulate a math coprocesso <<
1714 operations) if you don't have one. <<
1715 a math coprocessor built in, 486SX <<
1716 a 487DX or 387, respectively. (The <<
1717 give you some hints here ["man dmes <<
1718 coprocessor or this emulation. <<
1719 <<
1720 If you don't have a math coprocesso <<
1721 say Y here even though you have a c <<
1722 be used nevertheless. (This behavio <<
1723 command line option "no387", which <<
1724 is broken. Try "man bootparam" or s <<
1725 loader (lilo or loadlin) about how <<
1726 boot time.) This means that it is a <<
1727 intend to use this kernel on differ <<
1728 2202
1729 More information about the internal !! 2203 config IP22_CPU_SCACHE
1730 emulation can be found in <file:arc !! 2204 bool
>> 2205 select BOARD_SCACHE
1731 2206
1732 If you are not sure, say Y; apart f !! 2207 #
1733 kernel, it won't hurt. !! 2208 # Support for a MIPS32 / MIPS64 style S-caches
>> 2209 #
>> 2210 config MIPS_CPU_SCACHE
>> 2211 bool
>> 2212 select BOARD_SCACHE
1734 2213
1735 config MTRR !! 2214 config R5000_CPU_SCACHE
1736 def_bool y !! 2215 bool
1737 prompt "MTRR (Memory Type Range Regis !! 2216 select BOARD_SCACHE
>> 2217
>> 2218 config RM7000_CPU_SCACHE
>> 2219 bool
>> 2220 select BOARD_SCACHE
>> 2221
>> 2222 config SIBYTE_DMA_PAGEOPS
>> 2223 bool "Use DMA to clear/copy pages"
>> 2224 depends on CPU_SB1
1738 help 2225 help
1739 On Intel P6 family processors (Pent !! 2226 Instead of using the CPU to zero and copy pages, use a Data Mover
1740 the Memory Type Range Registers (MT !! 2227 channel. These DMA channels are otherwise unused by the standard
1741 processor access to memory ranges. !! 2228 SiByte Linux port. Seems to give a small performance benefit.
1742 a video (VGA) card on a PCI or AGP <<
1743 allows bus write transfers to be co <<
1744 before bursting over the PCI/AGP bu <<
1745 of image write operations 2.5 times <<
1746 /proc/mtrr file which may be used t <<
1747 MTRRs. Typically the X server shoul <<
1748 <<
1749 This code has a reasonably generic <<
1750 control registers on other processo <<
1751 as well: <<
1752 <<
1753 The Cyrix 6x86, 6x86MX and M II pro <<
1754 Registers (ARRs) which provide a si <<
1755 these, the ARRs are used to emulate <<
1756 The AMD K6-2 (stepping 8 and above) <<
1757 MTRRs. The Centaur C6 (WinChip) has <<
1758 write-combining. All of these proce <<
1759 and it makes sense to say Y here if <<
1760 <<
1761 Saying Y here also fixes a problem <<
1762 set the MTRRs for the boot CPU and <<
1763 can lead to all sorts of problems, <<
1764 2229
1765 You can safely say Y even if your m !! 2230 config CPU_HAS_PREFETCH
1766 just add about 9 KB to your kernel. !! 2231 bool
1767 2232
1768 See <file:Documentation/arch/x86/mt !! 2233 config CPU_GENERIC_DUMP_TLB
>> 2234 bool
>> 2235 default y if !(CPU_R3000 || CPU_TX39XX)
1769 2236
1770 config MTRR_SANITIZER !! 2237 config MIPS_FP_SUPPORT
1771 def_bool y !! 2238 bool "Floating Point support" if EXPERT
1772 prompt "MTRR cleanup support" !! 2239 default y
1773 depends on MTRR <<
1774 help 2240 help
1775 Convert MTRR layout from continuous !! 2241 Select y to include support for floating point in the kernel
1776 add writeback entries. !! 2242 including initialization of FPU hardware, FP context save & restore
>> 2243 and emulation of an FPU where necessary. Without this support any
>> 2244 userland program attempting to use floating point instructions will
>> 2245 receive a SIGILL.
1777 2246
1778 Can be disabled with disable_mtrr_c !! 2247 If you know that your userland will not attempt to use floating point
1779 The largest mtrr entry size for a c !! 2248 instructions then you can say n here to shrink the kernel a little.
1780 mtrr_chunk_size. <<
1781 2249
1782 If unsure, say Y. !! 2250 If unsure, say y.
1783 2251
1784 config MTRR_SANITIZER_ENABLE_DEFAULT !! 2252 config CPU_R2300_FPU
1785 int "MTRR cleanup enable value (0-1)" !! 2253 bool
1786 range 0 1 !! 2254 depends on MIPS_FP_SUPPORT
1787 default "0" !! 2255 default y if CPU_R3000 || CPU_TX39XX
1788 depends on MTRR_SANITIZER <<
1789 help <<
1790 Enable mtrr cleanup default value <<
1791 <<
1792 config MTRR_SANITIZER_SPARE_REG_NR_DEFAULT <<
1793 int "MTRR cleanup spare reg num (0-7) <<
1794 range 0 7 <<
1795 default "1" <<
1796 depends on MTRR_SANITIZER <<
1797 help <<
1798 mtrr cleanup spare entries default, <<
1799 mtrr_spare_reg_nr=N on the kernel c <<
1800 2256
1801 config X86_PAT !! 2257 config CPU_R3K_TLB
1802 def_bool y !! 2258 bool
1803 prompt "x86 PAT support" if EXPERT !! 2259
1804 depends on MTRR !! 2260 config CPU_R4K_FPU
1805 select ARCH_USES_PG_ARCH_2 !! 2261 bool
>> 2262 depends on MIPS_FP_SUPPORT
>> 2263 default y if !CPU_R2300_FPU
>> 2264
>> 2265 config CPU_R4K_CACHE_TLB
>> 2266 bool
>> 2267 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2268
>> 2269 config MIPS_MT_SMP
>> 2270 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2271 default y
>> 2272 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2273 select CPU_MIPSR2_IRQ_VI
>> 2274 select CPU_MIPSR2_IRQ_EI
>> 2275 select SYNC_R4K
>> 2276 select MIPS_MT
>> 2277 select SMP
>> 2278 select SMP_UP
>> 2279 select SYS_SUPPORTS_SMP
>> 2280 select SYS_SUPPORTS_SCHED_SMT
>> 2281 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2282 help
>> 2283 This is a kernel model which is known as SMVP. This is supported
>> 2284 on cores with the MT ASE and uses the available VPEs to implement
>> 2285 virtual processors which supports SMP. This is equivalent to the
>> 2286 Intel Hyperthreading feature. For further information go to
>> 2287 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2288
>> 2289 config MIPS_MT
>> 2290 bool
>> 2291
>> 2292 config SCHED_SMT
>> 2293 bool "SMT (multithreading) scheduler support"
>> 2294 depends on SYS_SUPPORTS_SCHED_SMT
>> 2295 default n
1806 help 2296 help
1807 Use PAT attributes to setup page le !! 2297 SMT scheduler support improves the CPU scheduler's decision making
>> 2298 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2299 increased overhead in some places. If unsure say N here.
1808 2300
1809 PATs are the modern equivalents of !! 2301 config SYS_SUPPORTS_SCHED_SMT
1810 flexible than MTRRs. !! 2302 bool
1811 2303
1812 Say N here if you see bootup proble !! 2304 config SYS_SUPPORTS_MULTITHREADING
1813 spontaneous reboots) or a non-worki !! 2305 bool
1814 2306
1815 If unsure, say Y. !! 2307 config MIPS_MT_FPAFF
>> 2308 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2309 default y
>> 2310 depends on MIPS_MT_SMP
1816 2311
1817 config X86_UMIP !! 2312 config MIPSR2_TO_R6_EMULATOR
1818 def_bool y !! 2313 bool "MIPS R2-to-R6 emulator"
1819 prompt "User Mode Instruction Prevent !! 2314 depends on CPU_MIPSR6
>> 2315 depends on MIPS_FP_SUPPORT
>> 2316 default y
1820 help 2317 help
1821 User Mode Instruction Prevention (U !! 2318 Choose this option if you want to run non-R6 MIPS userland code.
1822 some x86 processors. If enabled, a !! 2319 Even if you say 'Y' here, the emulator will still be disabled by
1823 issued if the SGDT, SLDT, SIDT, SMS !! 2320 default. You can enable it using the 'mipsr2emu' kernel option.
1824 executed in user mode. These instru !! 2321 The only reason this is a build-time option is to save ~14K from the
1825 information about the hardware stat !! 2322 final kernel image.
1826 <<
1827 The vast majority of applications d <<
1828 For the very few that do, software <<
1829 specific cases in protected and vir <<
1830 results are dummy. <<
1831 <<
1832 config CC_HAS_IBT <<
1833 # GCC >= 9 and binutils >= 2.29 <<
1834 # Retpoline check to work around http <<
1835 # Clang/LLVM >= 14 <<
1836 # https://github.com/llvm/llvm-projec <<
1837 # https://github.com/llvm/llvm-projec <<
1838 def_bool ((CC_IS_GCC && $(cc-option, <<
1839 (CC_IS_CLANG && CLANG_VERSI <<
1840 $(as-instr,endbr64) <<
1841 2323
1842 config X86_CET !! 2324 config SYS_SUPPORTS_VPE_LOADER
1843 def_bool n !! 2325 bool
>> 2326 depends on SYS_SUPPORTS_MULTITHREADING
1844 help 2327 help
1845 CET features configured (Shadow sta !! 2328 Indicates that the platform supports the VPE loader, and provides
>> 2329 physical_memsize.
1846 2330
1847 config X86_KERNEL_IBT !! 2331 config MIPS_VPE_LOADER
1848 prompt "Indirect Branch Tracking" !! 2332 bool "VPE loader support."
1849 def_bool y !! 2333 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
1850 depends on X86_64 && CC_HAS_IBT && HA !! 2334 select CPU_MIPSR2_IRQ_VI
1851 # https://github.com/llvm/llvm-projec !! 2335 select CPU_MIPSR2_IRQ_EI
1852 depends on !LD_IS_LLD || LLD_VERSION !! 2336 select MIPS_MT
1853 select OBJTOOL !! 2337 help
1854 select X86_CET !! 2338 Includes a loader for loading an elf relocatable object
1855 help !! 2339 onto another VPE and running it.
1856 Build the kernel with support for I <<
1857 hardware support course-grain forwa <<
1858 protection. It enforces that all in <<
1859 an ENDBR instruction, as such, the <<
1860 code with them to make this happen. <<
1861 <<
1862 In addition to building the kernel <<
1863 are not indirect call targets, avoi <<
1864 <<
1865 This requires LTO like objtool runs <<
1866 does significantly reduce the numbe <<
1867 kernel image. <<
1868 2340
1869 config X86_INTEL_MEMORY_PROTECTION_KEYS !! 2341 config MIPS_VPE_LOADER_CMP
1870 prompt "Memory Protection Keys" !! 2342 bool
1871 def_bool y !! 2343 default "y"
1872 # Note: only available in 64-bit mode !! 2344 depends on MIPS_VPE_LOADER && MIPS_CMP
1873 depends on X86_64 && (CPU_SUP_INTEL | <<
1874 select ARCH_USES_HIGH_VMA_FLAGS <<
1875 select ARCH_HAS_PKEYS <<
1876 help <<
1877 Memory Protection Keys provides a m <<
1878 page-based protections, but without <<
1879 page tables when an application cha <<
1880 2345
1881 For details, see Documentation/core !! 2346 config MIPS_VPE_LOADER_MT
>> 2347 bool
>> 2348 default "y"
>> 2349 depends on MIPS_VPE_LOADER && !MIPS_CMP
1882 2350
1883 If unsure, say y. !! 2351 config MIPS_VPE_LOADER_TOM
>> 2352 bool "Load VPE program into memory hidden from linux"
>> 2353 depends on MIPS_VPE_LOADER
>> 2354 default y
>> 2355 help
>> 2356 The loader can use memory that is present but has been hidden from
>> 2357 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2358 you to ensure the amount you put in the option and the space your
>> 2359 program requires is less or equal to the amount physically present.
1884 2360
1885 config ARCH_PKEY_BITS !! 2361 config MIPS_VPE_APSP_API
1886 int !! 2362 bool "Enable support for AP/SP API (RTLX)"
1887 default 4 !! 2363 depends on MIPS_VPE_LOADER
1888 2364
1889 choice !! 2365 config MIPS_VPE_APSP_API_CMP
1890 prompt "TSX enable mode" !! 2366 bool
1891 depends on CPU_SUP_INTEL !! 2367 default "y"
1892 default X86_INTEL_TSX_MODE_OFF !! 2368 depends on MIPS_VPE_APSP_API && MIPS_CMP
>> 2369
>> 2370 config MIPS_VPE_APSP_API_MT
>> 2371 bool
>> 2372 default "y"
>> 2373 depends on MIPS_VPE_APSP_API && !MIPS_CMP
>> 2374
>> 2375 config MIPS_CMP
>> 2376 bool "MIPS CMP framework support (DEPRECATED)"
>> 2377 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2378 select SMP
>> 2379 select SYNC_R4K
>> 2380 select SYS_SUPPORTS_SMP
>> 2381 select WEAK_ORDERING
>> 2382 default n
1893 help 2383 help
1894 Intel's TSX (Transactional Synchron !! 2384 Select this if you are using a bootloader which implements the "CMP
1895 allows to optimize locking protocol !! 2385 framework" protocol (ie. YAMON) and want your kernel to make use of
1896 can lead to a noticeable performanc !! 2386 its ability to start secondary CPUs.
>> 2387
>> 2388 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2389 instead of this.
>> 2390
>> 2391 config MIPS_CPS
>> 2392 bool "MIPS Coherent Processing System support"
>> 2393 depends on SYS_SUPPORTS_MIPS_CPS
>> 2394 select MIPS_CM
>> 2395 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2396 select SMP
>> 2397 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2398 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2399 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2400 select SYS_SUPPORTS_SMP
>> 2401 select WEAK_ORDERING
>> 2402 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2403 help
>> 2404 Select this if you wish to run an SMP kernel across multiple cores
>> 2405 within a MIPS Coherent Processing System. When this option is
>> 2406 enabled the kernel will probe for other cores and boot them with
>> 2407 no external assistance. It is safe to enable this when hardware
>> 2408 support is unavailable.
1897 2409
1898 On the other hand it has been shown !! 2410 config MIPS_CPS_PM
1899 to form side channel attacks (e.g. !! 2411 depends on MIPS_CPS
1900 will be more of those attacks disco !! 2412 bool
1901 2413
1902 Therefore TSX is not enabled by def !! 2414 config MIPS_CM
1903 might override this decision by tsx !! 2415 bool
1904 Even with TSX enabled, the kernel w !! 2416 select MIPS_CPC
1905 possible TAA mitigation setting dep <<
1906 for the particular machine. <<
1907 2417
1908 This option allows to set the defau !! 2418 config MIPS_CPC
1909 and =auto. See Documentation/admin- !! 2419 bool
1910 details. <<
1911 2420
1912 Say off if not sure, auto if TSX is !! 2421 config SB1_PASS_2_WORKAROUNDS
1913 platforms or on if TSX is in use an !! 2422 bool
1914 relevant. !! 2423 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2424 default y
1915 2425
1916 config X86_INTEL_TSX_MODE_OFF !! 2426 config SB1_PASS_2_1_WORKAROUNDS
1917 bool "off" !! 2427 bool
1918 help !! 2428 depends on CPU_SB1 && CPU_SB1_PASS_2
1919 TSX is disabled if possible - equal !! 2429 default y
1920 2430
1921 config X86_INTEL_TSX_MODE_ON !! 2431 choice
1922 bool "on" !! 2432 prompt "SmartMIPS or microMIPS ASE support"
>> 2433
>> 2434 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
>> 2435 bool "None"
1923 help 2436 help
1924 TSX is always enabled on TSX capabl !! 2437 Select this if you want neither microMIPS nor SmartMIPS support
1925 line parameter. <<
1926 2438
1927 config X86_INTEL_TSX_MODE_AUTO !! 2439 config CPU_HAS_SMARTMIPS
1928 bool "auto" !! 2440 depends on SYS_SUPPORTS_SMARTMIPS
>> 2441 bool "SmartMIPS"
>> 2442 help
>> 2443 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2444 increased security at both hardware and software level for
>> 2445 smartcards. Enabling this option will allow proper use of the
>> 2446 SmartMIPS instructions by Linux applications. However a kernel with
>> 2447 this option will not work on a MIPS core without SmartMIPS core. If
>> 2448 you don't know you probably don't have SmartMIPS and should say N
>> 2449 here.
>> 2450
>> 2451 config CPU_MICROMIPS
>> 2452 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2453 bool "microMIPS"
1929 help 2454 help
1930 TSX is enabled on TSX capable HW th !! 2455 When this option is enabled the kernel will be built using the
1931 side channel attacks- equals the ts !! 2456 microMIPS ISA
>> 2457
1932 endchoice 2458 endchoice
1933 2459
1934 config X86_SGX !! 2460 config CPU_HAS_MSA
1935 bool "Software Guard eXtensions (SGX) !! 2461 bool "Support for the MIPS SIMD Architecture"
1936 depends on X86_64 && CPU_SUP_INTEL && !! 2462 depends on CPU_SUPPORTS_MSA
1937 depends on CRYPTO=y !! 2463 depends on MIPS_FP_SUPPORT
1938 depends on CRYPTO_SHA256=y !! 2464 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1939 select MMU_NOTIFIER !! 2465 help
1940 select NUMA_KEEP_MEMINFO if NUMA !! 2466 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
1941 select XARRAY_MULTI !! 2467 and a set of SIMD instructions to operate on them. When this option
1942 help !! 2468 is enabled the kernel will support allocating & switching MSA
1943 Intel(R) Software Guard eXtensions !! 2469 vector register contexts. If you know that your kernel will only be
1944 that can be used by applications to !! 2470 running on CPUs which do not support MSA or that your userland will
1945 and data, referred to as enclaves. !! 2471 not be making use of it then you may wish to say N here to reduce
1946 only be accessed by code running wi !! 2472 the size & complexity of your kernel.
1947 outside the enclave, including othe <<
1948 hardware. <<
1949 2473
1950 If unsure, say N. !! 2474 If unsure, say Y.
1951 2475
1952 config X86_USER_SHADOW_STACK !! 2476 config CPU_HAS_WB
1953 bool "X86 userspace shadow stack" !! 2477 bool
1954 depends on AS_WRUSS <<
1955 depends on X86_64 <<
1956 select ARCH_USES_HIGH_VMA_FLAGS <<
1957 select X86_CET <<
1958 help <<
1959 Shadow stack protection is a hardwa <<
1960 return address corruption. This he <<
1961 Applications must be enabled to use <<
1962 get protection "for free". <<
1963 2478
1964 CPUs supporting shadow stacks were !! 2479 config XKS01
>> 2480 bool
1965 2481
1966 See Documentation/arch/x86/shstk.rs !! 2482 config CPU_HAS_DIEI
>> 2483 depends on !CPU_DIEI_BROKEN
>> 2484 bool
1967 2485
1968 If unsure, say N. !! 2486 config CPU_DIEI_BROKEN
>> 2487 bool
1969 2488
1970 config INTEL_TDX_HOST !! 2489 config CPU_HAS_RIXI
1971 bool "Intel Trust Domain Extensions ( !! 2490 bool
1972 depends on CPU_SUP_INTEL <<
1973 depends on X86_64 <<
1974 depends on KVM_INTEL <<
1975 depends on X86_X2APIC <<
1976 select ARCH_KEEP_MEMBLOCK <<
1977 depends on CONTIG_ALLOC <<
1978 depends on !KEXEC_CORE <<
1979 depends on X86_MCE <<
1980 help <<
1981 Intel Trust Domain Extensions (TDX) <<
1982 host and certain physical attacks. <<
1983 support in the host kernel to run c <<
1984 2491
1985 If unsure, say N. !! 2492 config CPU_NO_LOAD_STORE_LR
>> 2493 bool
>> 2494 help
>> 2495 CPU lacks support for unaligned load and store instructions:
>> 2496 LWL, LWR, SWL, SWR (Load/store word left/right).
>> 2497 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2498 systems).
1986 2499
1987 config EFI !! 2500 #
1988 bool "EFI runtime service support" !! 2501 # Vectored interrupt mode is an R2 feature
1989 depends on ACPI !! 2502 #
1990 select UCS2_STRING !! 2503 config CPU_MIPSR2_IRQ_VI
1991 select EFI_RUNTIME_WRAPPERS !! 2504 bool
1992 select ARCH_USE_MEMREMAP_PROT !! 2505
1993 select EFI_RUNTIME_MAP if KEXEC_CORE !! 2506 #
1994 help !! 2507 # Extended interrupt mode is an R2 feature
1995 This enables the kernel to use EFI !! 2508 #
1996 available (such as the EFI variable !! 2509 config CPU_MIPSR2_IRQ_EI
1997 !! 2510 bool
1998 This option is only useful on syste !! 2511
1999 In addition, you should use the lat !! 2512 config CPU_HAS_SYNC
2000 at <http://elilo.sourceforge.net> i !! 2513 bool
2001 of EFI runtime services. However, e !! 2514 depends on !CPU_R3000
2002 resultant kernel should continue to <<
2003 platforms. <<
2004 <<
2005 config EFI_STUB <<
2006 bool "EFI stub support" <<
2007 depends on EFI <<
2008 select RELOCATABLE <<
2009 help <<
2010 This kernel feature allows a bzImag <<
2011 by EFI firmware without the use of <<
2012 <<
2013 See Documentation/admin-guide/efi-s <<
2014 <<
2015 config EFI_HANDOVER_PROTOCOL <<
2016 bool "EFI handover protocol (DEPRECAT <<
2017 depends on EFI_STUB <<
2018 default y 2515 default y
2019 help <<
2020 Select this in order to include sup <<
2021 handover protocol, which defines al <<
2022 EFI stub. This is a practice that <<
2023 specification, and requires a prior <<
2024 bootloader about Linux/x86 specific <<
2025 and initrd, and where in memory tho <<
2026 <<
2027 If in doubt, say Y. Even though the <<
2028 present in upstream GRUB or other b <<
2029 GRUB with numerous downstream patch <<
2030 handover protocol as as result. <<
2031 <<
2032 config EFI_MIXED <<
2033 bool "EFI mixed-mode support" <<
2034 depends on EFI_STUB && X86_64 <<
2035 help <<
2036 Enabling this feature allows a 64-b <<
2037 on a 32-bit firmware, provided that <<
2038 mode. <<
2039 <<
2040 Note that it is not possible to boo <<
2041 kernel via the EFI boot stub - a bo <<
2042 the EFI handover protocol must be u <<
2043 2516
2044 If unsure, say N. !! 2517 #
>> 2518 # CPU non-features
>> 2519 #
>> 2520 config CPU_DADDI_WORKAROUNDS
>> 2521 bool
2045 2522
2046 config EFI_RUNTIME_MAP !! 2523 config CPU_R4000_WORKAROUNDS
2047 bool "Export EFI runtime maps to sysf !! 2524 bool
2048 depends on EFI !! 2525 select CPU_R4400_WORKAROUNDS
2049 help <<
2050 Export EFI runtime memory regions t <<
2051 That memory map is required by the <<
2052 mappings after kexec, but can also <<
2053 2526
2054 See also Documentation/ABI/testing/ !! 2527 config CPU_R4400_WORKAROUNDS
>> 2528 bool
2055 2529
2056 source "kernel/Kconfig.hz" !! 2530 config CPU_R4X00_BUGS64
>> 2531 bool
>> 2532 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
2057 2533
2058 config ARCH_SUPPORTS_KEXEC !! 2534 config MIPS_ASID_SHIFT
2059 def_bool y !! 2535 int
>> 2536 default 6 if CPU_R3000 || CPU_TX39XX
>> 2537 default 0
2060 2538
2061 config ARCH_SUPPORTS_KEXEC_FILE !! 2539 config MIPS_ASID_BITS
2062 def_bool X86_64 !! 2540 int
>> 2541 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2542 default 6 if CPU_R3000 || CPU_TX39XX
>> 2543 default 8
2063 2544
2064 config ARCH_SELECTS_KEXEC_FILE !! 2545 config MIPS_ASID_BITS_VARIABLE
2065 def_bool y !! 2546 bool
2066 depends on KEXEC_FILE <<
2067 select HAVE_IMA_KEXEC if IMA <<
2068 2547
2069 config ARCH_SUPPORTS_KEXEC_PURGATORY !! 2548 config MIPS_CRC_SUPPORT
2070 def_bool y !! 2549 bool
2071 2550
2072 config ARCH_SUPPORTS_KEXEC_SIG !! 2551 # R4600 erratum. Due to the lack of errata information the exact
2073 def_bool y !! 2552 # technical details aren't known. I've experimentally found that disabling
>> 2553 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2554 # with the issue.
>> 2555 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2556 bool
2074 2557
2075 config ARCH_SUPPORTS_KEXEC_SIG_FORCE !! 2558 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
2076 def_bool y !! 2559 #
>> 2560 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2561 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2562 # executed if there is no other dcache activity. If the dcache is
>> 2563 # accessed for another instruction immediately preceding when these
>> 2564 # cache instructions are executing, it is possible that the dcache
>> 2565 # tag match outputs used by these cache instructions will be
>> 2566 # incorrect. These cache instructions should be preceded by at least
>> 2567 # four instructions that are not any kind of load or store
>> 2568 # instruction.
>> 2569 #
>> 2570 # This is not allowed: lw
>> 2571 # nop
>> 2572 # nop
>> 2573 # nop
>> 2574 # cache Hit_Writeback_Invalidate_D
>> 2575 #
>> 2576 # This is allowed: lw
>> 2577 # nop
>> 2578 # nop
>> 2579 # nop
>> 2580 # nop
>> 2581 # cache Hit_Writeback_Invalidate_D
>> 2582 config WAR_R4600_V1_HIT_CACHEOP
>> 2583 bool
2077 2584
2078 config ARCH_SUPPORTS_KEXEC_BZIMAGE_VERIFY_SIG !! 2585 # Writeback and invalidate the primary cache dcache before DMA.
2079 def_bool y !! 2586 #
>> 2587 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2588 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2589 # operate correctly if the internal data cache refill buffer is empty. These
>> 2590 # CACHE instructions should be separated from any potential data cache miss
>> 2591 # by a load instruction to an uncached address to empty the response buffer."
>> 2592 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2593 # in .pdf format.)
>> 2594 config WAR_R4600_V2_HIT_CACHEOP
>> 2595 bool
2080 2596
2081 config ARCH_SUPPORTS_KEXEC_JUMP !! 2597 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
2082 def_bool y !! 2598 # the line which this instruction itself exists, the following
>> 2599 # operation is not guaranteed."
>> 2600 #
>> 2601 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2602 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2603 bool
2083 2604
2084 config ARCH_SUPPORTS_CRASH_DUMP !! 2605 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2085 def_bool X86_64 || (X86_32 && HIGHMEM !! 2606 # opposes it being called that) where invalid instructions in the same
>> 2607 # I-cache line worth of instructions being fetched may case spurious
>> 2608 # exceptions.
>> 2609 config WAR_ICACHE_REFILLS
>> 2610 bool
2086 2611
2087 config ARCH_SUPPORTS_CRASH_HOTPLUG !! 2612 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
2088 def_bool y !! 2613 # may cause ll / sc and lld / scd sequences to execute non-atomically.
>> 2614 config WAR_R10000_LLSC
>> 2615 bool
2089 2616
2090 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2617 # 34K core erratum: "Problems Executing the TLBR Instruction"
2091 def_bool CRASH_RESERVE !! 2618 config WAR_MIPS34K_MISSED_ITLB
>> 2619 bool
2092 2620
2093 config PHYSICAL_START !! 2621 #
2094 hex "Physical address where the kerne !! 2622 # - Highmem only makes sense for the 32-bit kernel.
2095 default "0x1000000" !! 2623 # - The current highmem code will only work properly on physically indexed
2096 help !! 2624 # caches such as R3000, SB1, R7000 or those that look like they're virtually
2097 This gives the physical address whe !! 2625 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2626 # moment we protect the user and offer the highmem option only on machines
>> 2627 # where it's known to be safe. This will not offer highmem on a few systems
>> 2628 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2629 # indexed CPUs but we're playing safe.
>> 2630 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2631 # know they might have memory configurations that could make use of highmem
>> 2632 # support.
>> 2633 #
>> 2634 config HIGHMEM
>> 2635 bool "High Memory Support"
>> 2636 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2637 select KMAP_LOCAL
2098 2638
2099 If the kernel is not relocatable (C !! 2639 config CPU_SUPPORTS_HIGHMEM
2100 will decompress itself to above phy !! 2640 bool
2101 Otherwise, bzImage will run from th <<
2102 by the boot loader. The only except <<
2103 above physical address, in which ca <<
2104 <<
2105 In normal kdump cases one does not <<
2106 as now bzImage can be compiled as a <<
2107 (CONFIG_RELOCATABLE=y) and be used <<
2108 address. This option is mainly usef <<
2109 to use a bzImage for capturing the <<
2110 vmlinux instead. vmlinux is not rel <<
2111 to be specifically compiled to run <<
2112 (normally a reserved region) and th <<
2113 <<
2114 So if you are using bzImage for cap <<
2115 leave the value here unchanged to 0 <<
2116 CONFIG_RELOCATABLE=y. Otherwise if <<
2117 for capturing the crash dump change <<
2118 the reserved region. In other word <<
2119 the "X" value as specified in the " <<
2120 command line boot parameter passed <<
2121 kernel. Please take a look at Docum <<
2122 for more details about crash dumps. <<
2123 <<
2124 Usage of bzImage for capturing the <<
2125 one does not have to build two kern <<
2126 as production kernel and capture ke <<
2127 gone away after relocatable bzImage <<
2128 is present because there are users <<
2129 vmlinux for dump capture. This opti <<
2130 line. <<
2131 2641
2132 Don't change this unless you know w !! 2642 config SYS_SUPPORTS_HIGHMEM
>> 2643 bool
2133 2644
2134 config RELOCATABLE !! 2645 config SYS_SUPPORTS_SMARTMIPS
2135 bool "Build a relocatable kernel" !! 2646 bool
2136 default y <<
2137 help <<
2138 This builds a kernel image that ret <<
2139 so it can be loaded someplace besid <<
2140 The relocations tend to make the ke <<
2141 but are discarded at runtime. <<
2142 2647
2143 One use is for the kexec on panic c !! 2648 config SYS_SUPPORTS_MICROMIPS
2144 must live at a different physical a !! 2649 bool
2145 kernel. <<
2146 <<
2147 Note: If CONFIG_RELOCATABLE=y, then <<
2148 it has been loaded at and the compi <<
2149 (CONFIG_PHYSICAL_START) is used as <<
2150 2650
2151 config RANDOMIZE_BASE !! 2651 config SYS_SUPPORTS_MIPS16
2152 bool "Randomize the address of the ke !! 2652 bool
2153 depends on RELOCATABLE <<
2154 default y <<
2155 help 2653 help
2156 In support of Kernel Address Space !! 2654 This option must be set if a kernel might be executed on a MIPS16-
2157 this randomizes the physical addres !! 2655 enabled CPU even if MIPS16 is not actually being used. In other
2158 is decompressed and the virtual add !! 2656 words, it makes the kernel MIPS16-tolerant.
2159 image is mapped, as a security feat <<
2160 attempts relying on knowledge of th <<
2161 code internals. <<
2162 <<
2163 On 64-bit, the kernel physical and <<
2164 randomized separately. The physical <<
2165 between 16MB and the top of physica <<
2166 virtual address will be randomized <<
2167 of entropy). Note that this also re <<
2168 available to kernel modules from 1. <<
2169 <<
2170 On 32-bit, the kernel physical and <<
2171 randomized together. They will be r <<
2172 512MB (8 bits of entropy). <<
2173 <<
2174 Entropy is generated using the RDRA <<
2175 supported. If RDTSC is supported, i <<
2176 the entropy pool as well. If neithe <<
2177 supported, then entropy is read fro <<
2178 usable entropy is limited by the ke <<
2179 2GB addressing, and that PHYSICAL_A <<
2180 minimum of 2MB. As a result, only 1 <<
2181 theoretically possible, but the imp <<
2182 limited due to memory layouts. <<
2183 2657
2184 If unsure, say Y. !! 2658 config CPU_SUPPORTS_MSA
>> 2659 bool
2185 2660
2186 # Relocation on x86 needs some additional bui !! 2661 config ARCH_FLATMEM_ENABLE
2187 config X86_NEED_RELOCS <<
2188 def_bool y 2662 def_bool y
2189 depends on RANDOMIZE_BASE || (X86_32 !! 2663 depends on !NUMA && !CPU_LOONGSON2EF
2190 2664
2191 config PHYSICAL_ALIGN !! 2665 config ARCH_SPARSEMEM_ENABLE
2192 hex "Alignment value to which kernel !! 2666 bool
2193 default "0x200000" !! 2667 select SPARSEMEM_STATIC if !SGI_IP27
2194 range 0x2000 0x1000000 if X86_32 <<
2195 range 0x200000 0x1000000 if X86_64 <<
2196 help <<
2197 This value puts the alignment restr <<
2198 where kernel is loaded and run from <<
2199 address which meets above alignment <<
2200 2668
2201 If bootloader loads the kernel at a !! 2669 config NUMA
2202 CONFIG_RELOCATABLE is set, kernel w !! 2670 bool "NUMA Support"
2203 address aligned to above value and !! 2671 depends on SYS_SUPPORTS_NUMA
>> 2672 select SMP
>> 2673 help
>> 2674 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2675 Access). This option improves performance on systems with more
>> 2676 than two nodes; on two node systems it is generally better to
>> 2677 leave it disabled; on single node systems leave this option
>> 2678 disabled.
2204 2679
2205 If bootloader loads the kernel at a !! 2680 config SYS_SUPPORTS_NUMA
2206 CONFIG_RELOCATABLE is not set, kern !! 2681 bool
2207 load address and decompress itself <<
2208 compiled for and run from there. Th <<
2209 compiled already meets above alignm <<
2210 end result is that kernel runs from <<
2211 above alignment restrictions. <<
2212 2682
2213 On 32-bit this value must be a mult !! 2683 config HAVE_SETUP_PER_CPU_AREA
2214 this value must be a multiple of 0x !! 2684 def_bool y
>> 2685 depends on NUMA
2215 2686
2216 Don't change this unless you know w !! 2687 config NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2688 def_bool y
>> 2689 depends on NUMA
2217 2690
2218 config DYNAMIC_MEMORY_LAYOUT !! 2691 config RELOCATABLE
2219 bool !! 2692 bool "Relocatable kernel"
>> 2693 depends on SYS_SUPPORTS_RELOCATABLE
>> 2694 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2695 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2696 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2697 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2698 CPU_LOONGSON64
2220 help 2699 help
2221 This option makes base addresses of !! 2700 This builds a kernel image that retains relocation information
2222 __PAGE_OFFSET movable during boot. !! 2701 so it can be loaded someplace besides the default 1MB.
>> 2702 The relocations make the kernel binary about 15% larger,
>> 2703 but are discarded at runtime
2223 2704
2224 config RANDOMIZE_MEMORY !! 2705 config RELOCATION_TABLE_SIZE
2225 bool "Randomize the kernel memory sec !! 2706 hex "Relocation table size"
2226 depends on X86_64 !! 2707 depends on RELOCATABLE
2227 depends on RANDOMIZE_BASE !! 2708 range 0x0 0x01000000
2228 select DYNAMIC_MEMORY_LAYOUT !! 2709 default "0x00200000" if CPU_LOONGSON64
2229 default RANDOMIZE_BASE !! 2710 default "0x00100000"
2230 help 2711 help
2231 Randomizes the base virtual address !! 2712 A table of relocation data will be appended to the kernel binary
2232 (physical memory mapping, vmalloc & !! 2713 and parsed at boot to fix up the relocated kernel.
2233 makes exploits relying on predictab <<
2234 <<
2235 The order of allocations remains un <<
2236 the same way as RANDOMIZE_BASE. Cur <<
2237 configuration have in average 30,00 <<
2238 addresses for each memory section. <<
2239 2714
2240 If unsure, say Y. !! 2715 This option allows the amount of space reserved for the table to be
>> 2716 adjusted, although the default of 1Mb should be ok in most cases.
2241 2717
2242 config RANDOMIZE_MEMORY_PHYSICAL_PADDING !! 2718 The build will fail and a valid size suggested if this is too small.
2243 hex "Physical memory mapping padding" <<
2244 depends on RANDOMIZE_MEMORY <<
2245 default "0xa" if MEMORY_HOTPLUG <<
2246 default "0x0" <<
2247 range 0x1 0x40 if MEMORY_HOTPLUG <<
2248 range 0x0 0x40 <<
2249 help <<
2250 Define the padding in terabytes add <<
2251 memory size during kernel memory ra <<
2252 for memory hotplug support but redu <<
2253 address randomization. <<
2254 2719
2255 If unsure, leave at the default val 2720 If unsure, leave at the default value.
2256 2721
2257 config ADDRESS_MASKING !! 2722 config RANDOMIZE_BASE
2258 bool "Linear Address Masking support" !! 2723 bool "Randomize the address of the kernel image"
2259 depends on X86_64 !! 2724 depends on RELOCATABLE
2260 depends on COMPILE_TEST || !CPU_MITIG <<
2261 help <<
2262 Linear Address Masking (LAM) modifi <<
2263 to 64-bit linear addresses, allowin <<
2264 untranslated address bits for metad <<
2265 <<
2266 The capability can be used for effi <<
2267 implementation and for optimization <<
2268 <<
2269 config HOTPLUG_CPU <<
2270 def_bool y <<
2271 depends on SMP <<
2272 <<
2273 config COMPAT_VDSO <<
2274 def_bool n <<
2275 prompt "Disable the 32-bit vDSO (need <<
2276 depends on COMPAT_32 <<
2277 help 2725 help
2278 Certain buggy versions of glibc wil !! 2726 Randomizes the physical and virtual address at which the
2279 presented with a 32-bit vDSO that i !! 2727 kernel image is loaded, as a security feature that
2280 indicated in its segment table. !! 2728 deters exploit attempts relying on knowledge of the location
2281 !! 2729 of kernel internals.
2282 The bug was introduced by f866314b8 <<
2283 and fixed by 3b3ddb4f7db98ec9e912cc <<
2284 49ad572a70b8aeb91e57483a11dd1b77e31 <<
2285 the only released version with the <<
2286 contains a buggy "glibc 2.3.2". <<
2287 <<
2288 The symptom of the bug is that ever <<
2289 dl_main: Assertion `(void *) ph->p_ <<
2290 <<
2291 Saying Y here changes the default v <<
2292 option from 1 to 0, which turns off <<
2293 This works around the glibc bug but <<
2294 2730
2295 If unsure, say N: if you are compil !! 2731 Entropy is generated using any coprocessor 0 registers available.
2296 are unlikely to be using a buggy ve <<
2297 2732
2298 choice !! 2733 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
2299 prompt "vsyscall table for legacy app <<
2300 depends on X86_64 <<
2301 default LEGACY_VSYSCALL_XONLY <<
2302 help <<
2303 Legacy user code that does not know <<
2304 to be able to issue three syscalls <<
2305 kernel space. Since this location i <<
2306 it can be used to assist security v <<
2307 <<
2308 This setting can be changed at boot <<
2309 line parameter vsyscall=[emulate|xo <<
2310 is deprecated and can only be enabl <<
2311 line. <<
2312 <<
2313 On a system with recent enough glib <<
2314 static binaries, you can say None w <<
2315 to improve security. <<
2316 2734
2317 If unsure, select "Emulate executio !! 2735 If unsure, say N.
2318 2736
2319 config LEGACY_VSYSCALL_XONLY !! 2737 config RANDOMIZE_BASE_MAX_OFFSET
2320 bool "Emulate execution only" !! 2738 hex "Maximum kASLR offset" if EXPERT
2321 help !! 2739 depends on RANDOMIZE_BASE
2322 The kernel traps and emulat !! 2740 range 0x0 0x40000000 if EVA || 64BIT
2323 address mapping and does no !! 2741 range 0x0 0x08000000
2324 configuration is recommende !! 2742 default "0x01000000"
2325 legacy vsyscall area but su !! 2743 help
2326 instrumentation of legacy c !! 2744 When kASLR is active, this provides the maximum offset that will
2327 certain uses of the vsyscal !! 2745 be applied to the kernel image. It should be set according to the
2328 buffer. !! 2746 amount of physical RAM available in the target system minus
>> 2747 PHYSICAL_START and must be a power of 2.
2329 2748
2330 config LEGACY_VSYSCALL_NONE !! 2749 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2331 bool "None" !! 2750 EVA or 64-bit. The default is 16Mb.
2332 help <<
2333 There will be no vsyscall m <<
2334 eliminate any risk of ASLR <<
2335 fixed address mapping. Atte <<
2336 will be reported to dmesg, <<
2337 malicious userspace program <<
2338 2751
2339 endchoice !! 2752 config NODES_SHIFT
>> 2753 int
>> 2754 default "6"
>> 2755 depends on NUMA
2340 2756
2341 config CMDLINE_BOOL !! 2757 config HW_PERF_EVENTS
2342 bool "Built-in kernel command line" !! 2758 bool "Enable hardware performance counter support for perf events"
2343 help !! 2759 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
2344 Allow for specifying boot arguments !! 2760 default y
2345 build time. On some systems (e.g. <<
2346 necessary or convenient to provide <<
2347 kernel boot arguments with the kern <<
2348 to not rely on the boot loader to p <<
2349 <<
2350 To compile command line arguments i <<
2351 set this option to 'Y', then fill i <<
2352 boot arguments in CONFIG_CMDLINE. <<
2353 <<
2354 Systems with fully functional boot <<
2355 should leave this option set to 'N' <<
2356 <<
2357 config CMDLINE <<
2358 string "Built-in kernel command strin <<
2359 depends on CMDLINE_BOOL <<
2360 default "" <<
2361 help <<
2362 Enter arguments here that should be <<
2363 image and used at boot time. If th <<
2364 command line at boot time, it is ap <<
2365 form the full kernel command line, <<
2366 <<
2367 However, you can use the CONFIG_CMD <<
2368 change this behavior. <<
2369 <<
2370 In most cases, the command line (wh <<
2371 by the boot loader) should specify <<
2372 file system. <<
2373 <<
2374 config CMDLINE_OVERRIDE <<
2375 bool "Built-in command line overrides <<
2376 depends on CMDLINE_BOOL && CMDLINE != <<
2377 help 2761 help
2378 Set this option to 'Y' to have the !! 2762 Enable hardware performance counter support for perf events. If
2379 command line, and use ONLY the buil !! 2763 disabled, perf events will use software events only.
2380 <<
2381 This is used to work around broken <<
2382 be set to 'N' under normal conditio <<
2383 2764
2384 config MODIFY_LDT_SYSCALL !! 2765 config DMI
2385 bool "Enable the LDT (local descripto !! 2766 bool "Enable DMI scanning"
>> 2767 depends on MACH_LOONGSON64
>> 2768 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
2386 default y 2769 default y
2387 help 2770 help
2388 Linux can allow user programs to in !! 2771 Enabled scanning of DMI to identify machine quirks. Say Y
2389 Local Descriptor Table (LDT) using !! 2772 here unless you have verified that your setup is not
2390 call. This is required to run 16-b !! 2773 affected by entries in the DMI blacklist. Required by PNP
2391 DOSEMU or some Wine programs. It i !! 2774 BIOS code.
2392 threading libraries. !! 2775
2393 !! 2776 config SMP
2394 Enabling this feature adds a small !! 2777 bool "Multi-Processing support"
2395 context switches and increases the !! 2778 depends on SYS_SUPPORTS_SMP
2396 surface. Disabling it removes the <<
2397 <<
2398 Saying 'N' here may make sense for <<
2399 <<
2400 config STRICT_SIGALTSTACK_SIZE <<
2401 bool "Enforce strict size checking fo <<
2402 depends on DYNAMIC_SIGFRAME <<
2403 help <<
2404 For historical reasons MINSIGSTKSZ <<
2405 already too small with AVX512 suppo <<
2406 enforce strict checking of the siga <<
2407 real size of the FPU frame. This op <<
2408 by default. It can also be controll <<
2409 line option 'strict_sas_size' indep <<
2410 switch. Enabling it might break exi <<
2411 allocate a too small sigaltstack bu <<
2412 never get a signal delivered. <<
2413 <<
2414 Say 'N' unless you want to really e <<
2415 <<
2416 config CFI_AUTO_DEFAULT <<
2417 bool "Attempt to use FineIBT by defau <<
2418 depends on FINEIBT <<
2419 default y <<
2420 help 2779 help
2421 Attempt to use FineIBT by default a !! 2780 This enables support for systems with more than one CPU. If you have
2422 this is the same as booting with "c !! 2781 a system with only one CPU, say N. If you have a system with more
2423 this is the same as booting with "c !! 2782 than one CPU, say Y.
2424 2783
2425 source "kernel/livepatch/Kconfig" !! 2784 If you say N here, the kernel will run on uni- and multiprocessor
>> 2785 machines, but will use only one CPU of a multiprocessor machine. If
>> 2786 you say Y here, the kernel will run on many, but not all,
>> 2787 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2788 will run faster if you say N here.
2426 2789
2427 endmenu !! 2790 People using multiprocessor machines who say Y here should also say
>> 2791 Y to "Enhanced Real Time Clock Support", below.
2428 2792
2429 config CC_HAS_NAMED_AS !! 2793 See also the SMP-HOWTO available at
2430 def_bool $(success,echo 'int __seg_fs !! 2794 <https://www.tldp.org/docs.html#howto>.
2431 depends on CC_IS_GCC <<
2432 2795
2433 config CC_HAS_NAMED_AS_FIXED_SANITIZERS !! 2796 If you don't know what to do here, say N.
2434 def_bool CC_IS_GCC && GCC_VERSION >= <<
2435 2797
2436 config USE_X86_SEG_SUPPORT !! 2798 config HOTPLUG_CPU
2437 def_bool y !! 2799 bool "Support for hot-pluggable CPUs"
2438 depends on CC_HAS_NAMED_AS !! 2800 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
2439 # !! 2801 help
2440 # -fsanitize=kernel-address (KASAN) a !! 2802 Say Y here to allow turning CPUs off and on. CPUs can be
2441 # (KCSAN) are incompatible with named !! 2803 controlled through /sys/devices/system/cpu.
2442 # GCC < 13.3 - see GCC PR sanitizer/1 !! 2804 (Note: power management support will enable this option
2443 # !! 2805 automatically on SMP systems. )
2444 depends on !(KASAN || KCSAN) || CC_HA !! 2806 Say N if you want to disable CPU hotplug.
2445 2807
2446 config CC_HAS_SLS !! 2808 config SMP_UP
2447 def_bool $(cc-option,-mharden-sls=all !! 2809 bool
2448 2810
2449 config CC_HAS_RETURN_THUNK !! 2811 config SYS_SUPPORTS_MIPS_CMP
2450 def_bool $(cc-option,-mfunction-retur !! 2812 bool
2451 2813
2452 config CC_HAS_ENTRY_PADDING !! 2814 config SYS_SUPPORTS_MIPS_CPS
2453 def_bool $(cc-option,-fpatchable-func !! 2815 bool
2454 2816
2455 config FUNCTION_PADDING_CFI !! 2817 config SYS_SUPPORTS_SMP
2456 int !! 2818 bool
2457 default 59 if FUNCTION_ALIGNMENT_64B <<
2458 default 27 if FUNCTION_ALIGNMENT_32B <<
2459 default 11 if FUNCTION_ALIGNMENT_16B <<
2460 default 3 if FUNCTION_ALIGNMENT_8B <<
2461 default 0 <<
2462 <<
2463 # Basically: FUNCTION_ALIGNMENT - 5*CFI_CLANG <<
2464 # except Kconfig can't do arithmetic :/ <<
2465 config FUNCTION_PADDING_BYTES <<
2466 int <<
2467 default FUNCTION_PADDING_CFI if CFI_C <<
2468 default FUNCTION_ALIGNMENT <<
2469 2819
2470 config CALL_PADDING !! 2820 config NR_CPUS_DEFAULT_4
2471 def_bool n !! 2821 bool
2472 depends on CC_HAS_ENTRY_PADDING && OB <<
2473 select FUNCTION_ALIGNMENT_16B <<
2474 2822
2475 config FINEIBT !! 2823 config NR_CPUS_DEFAULT_8
2476 def_bool y !! 2824 bool
2477 depends on X86_KERNEL_IBT && CFI_CLAN <<
2478 select CALL_PADDING <<
2479 2825
2480 config HAVE_CALL_THUNKS !! 2826 config NR_CPUS_DEFAULT_16
2481 def_bool y !! 2827 bool
2482 depends on CC_HAS_ENTRY_PADDING && MI <<
2483 2828
2484 config CALL_THUNKS !! 2829 config NR_CPUS_DEFAULT_32
2485 def_bool n !! 2830 bool
2486 select CALL_PADDING <<
2487 2831
2488 config PREFIX_SYMBOLS !! 2832 config NR_CPUS_DEFAULT_64
2489 def_bool y !! 2833 bool
2490 depends on CALL_PADDING && !CFI_CLANG <<
2491 2834
2492 menuconfig CPU_MITIGATIONS !! 2835 config NR_CPUS
2493 bool "Mitigations for CPU vulnerabili !! 2836 int "Maximum number of CPUs (2-256)"
2494 default y !! 2837 range 2 256
>> 2838 depends on SMP
>> 2839 default "4" if NR_CPUS_DEFAULT_4
>> 2840 default "8" if NR_CPUS_DEFAULT_8
>> 2841 default "16" if NR_CPUS_DEFAULT_16
>> 2842 default "32" if NR_CPUS_DEFAULT_32
>> 2843 default "64" if NR_CPUS_DEFAULT_64
2495 help 2844 help
2496 Say Y here to enable options which !! 2845 This allows you to specify the maximum number of CPUs which this
2497 vulnerabilities (usually related to !! 2846 kernel will support. The maximum supported value is 32 for 32-bit
2498 Mitigations can be disabled or rest !! 2847 kernel and 64 for 64-bit kernels; the minimum value which makes
2499 via the "mitigations" kernel parame !! 2848 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2849 and 2 for all others.
>> 2850
>> 2851 This is purely to save memory - each supported CPU adds
>> 2852 approximately eight kilobytes to the kernel image. For best
>> 2853 performance should round up your number of processors to the next
>> 2854 power of two.
2500 2855
2501 If you say N, all mitigations will !! 2856 config MIPS_PERF_SHARED_TC_COUNTERS
2502 overridden at runtime. !! 2857 bool
>> 2858
>> 2859 config MIPS_NR_CPU_NR_MAP_1024
>> 2860 bool
2503 2861
2504 Say 'Y', unless you really know wha !! 2862 config MIPS_NR_CPU_NR_MAP
>> 2863 int
>> 2864 depends on SMP
>> 2865 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2866 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2505 2867
2506 if CPU_MITIGATIONS !! 2868 #
>> 2869 # Timer Interrupt Frequency Configuration
>> 2870 #
2507 2871
2508 config MITIGATION_PAGE_TABLE_ISOLATION !! 2872 choice
2509 bool "Remove the kernel mapping in us !! 2873 prompt "Timer frequency"
2510 default y !! 2874 default HZ_250
2511 depends on (X86_64 || X86_PAE) <<
2512 help 2875 help
2513 This feature reduces the number of !! 2876 Allows the configuration of the timer frequency.
2514 ensuring that the majority of kerne <<
2515 into userspace. <<
2516 2877
2517 See Documentation/arch/x86/pti.rst !! 2878 config HZ_24
>> 2879 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2518 2880
2519 config MITIGATION_RETPOLINE !! 2881 config HZ_48
2520 bool "Avoid speculative indirect bran !! 2882 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2521 select OBJTOOL if HAVE_OBJTOOL <<
2522 default y <<
2523 help <<
2524 Compile kernel with the retpoline c <<
2525 kernel-to-user data leaks by avoidi <<
2526 branches. Requires a compiler with <<
2527 support for full protection. The ke <<
2528 <<
2529 config MITIGATION_RETHUNK <<
2530 bool "Enable return-thunks" <<
2531 depends on MITIGATION_RETPOLINE && CC <<
2532 select OBJTOOL if HAVE_OBJTOOL <<
2533 default y if X86_64 <<
2534 help <<
2535 Compile the kernel with the return- <<
2536 against kernel-to-user data leaks b <<
2537 Requires a compiler with -mfunction <<
2538 support for full protection. The ke <<
2539 <<
2540 config MITIGATION_UNRET_ENTRY <<
2541 bool "Enable UNRET on kernel entry" <<
2542 depends on CPU_SUP_AMD && MITIGATION_ <<
2543 default y <<
2544 help <<
2545 Compile the kernel with support for <<
2546 2883
2547 config MITIGATION_CALL_DEPTH_TRACKING !! 2884 config HZ_100
2548 bool "Mitigate RSB underflow with cal !! 2885 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2549 depends on CPU_SUP_INTEL && HAVE_CALL <<
2550 select HAVE_DYNAMIC_FTRACE_NO_PATCHAB <<
2551 select CALL_THUNKS <<
2552 default y <<
2553 help <<
2554 Compile the kernel with call depth <<
2555 SKL Return-Speculation-Buffer (RSB) <<
2556 mitigation is off by default and ne <<
2557 kernel command line via the retblee <<
2558 non-affected systems the overhead o <<
2559 the call depth tracking is using ru <<
2560 in a compiler generated padding are <<
2561 increases text size by ~5%. For non <<
2562 is unused. On affected SKL systems <<
2563 performance gain over the IBRS miti <<
2564 <<
2565 config CALL_THUNKS_DEBUG <<
2566 bool "Enable call thunks and call dep <<
2567 depends on MITIGATION_CALL_DEPTH_TRAC <<
2568 select FUNCTION_ALIGNMENT_32B <<
2569 default n <<
2570 help <<
2571 Enable call/ret counters for imbala <<
2572 a noisy dmesg about callthunks gene <<
2573 trouble shooting. The debug prints <<
2574 kernel command line with 'debug-cal <<
2575 Only enable this when you are debug <<
2576 creates a noticeable runtime overhe <<
2577 <<
2578 config MITIGATION_IBPB_ENTRY <<
2579 bool "Enable IBPB on kernel entry" <<
2580 depends on CPU_SUP_AMD && X86_64 <<
2581 default y <<
2582 help <<
2583 Compile the kernel with support for <<
2584 2886
2585 config MITIGATION_IBRS_ENTRY !! 2887 config HZ_128
2586 bool "Enable IBRS on kernel entry" !! 2888 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2587 depends on CPU_SUP_INTEL && X86_64 <<
2588 default y <<
2589 help <<
2590 Compile the kernel with support for <<
2591 This mitigates both spectre_v2 and <<
2592 performance. <<
2593 2889
2594 config MITIGATION_SRSO !! 2890 config HZ_250
2595 bool "Mitigate speculative RAS overfl !! 2891 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2596 depends on CPU_SUP_AMD && X86_64 && M <<
2597 default y <<
2598 help <<
2599 Enable the SRSO mitigation needed o <<
2600 2892
2601 config MITIGATION_SLS !! 2893 config HZ_256
2602 bool "Mitigate Straight-Line-Speculat !! 2894 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2603 depends on CC_HAS_SLS && X86_64 <<
2604 select OBJTOOL if HAVE_OBJTOOL <<
2605 default n <<
2606 help <<
2607 Compile the kernel with straight-li <<
2608 against straight line speculation. <<
2609 larger. <<
2610 <<
2611 config MITIGATION_GDS <<
2612 bool "Mitigate Gather Data Sampling" <<
2613 depends on CPU_SUP_INTEL <<
2614 default y <<
2615 help <<
2616 Enable mitigation for Gather Data S <<
2617 vulnerability which allows unprivil <<
2618 which was previously stored in vect <<
2619 instructions to infer the stale vec <<
2620 <<
2621 config MITIGATION_RFDS <<
2622 bool "RFDS Mitigation" <<
2623 depends on CPU_SUP_INTEL <<
2624 default y <<
2625 help <<
2626 Enable mitigation for Register File <<
2627 RFDS is a hardware vulnerability wh <<
2628 allows unprivileged speculative acc <<
2629 stored in floating point, vector an <<
2630 See also <file:Documentation/admin- <<
2631 <<
2632 config MITIGATION_SPECTRE_BHI <<
2633 bool "Mitigate Spectre-BHB (Branch Hi <<
2634 depends on CPU_SUP_INTEL <<
2635 default y <<
2636 help <<
2637 Enable BHI mitigations. BHI attacks <<
2638 where the branch history buffer is <<
2639 indirect branches. <<
2640 See <file:Documentation/admin-guide <<
2641 <<
2642 config MITIGATION_MDS <<
2643 bool "Mitigate Microarchitectural Dat <<
2644 depends on CPU_SUP_INTEL <<
2645 default y <<
2646 help <<
2647 Enable mitigation for Microarchitec <<
2648 a hardware vulnerability which allo <<
2649 to data which is available in vario <<
2650 See also <file:Documentation/admin- <<
2651 <<
2652 config MITIGATION_TAA <<
2653 bool "Mitigate TSX Asynchronous Abort <<
2654 depends on CPU_SUP_INTEL <<
2655 default y <<
2656 help <<
2657 Enable mitigation for TSX Asynchron <<
2658 vulnerability that allows unprivile <<
2659 which is available in various CPU i <<
2660 asynchronous aborts within an Intel <<
2661 See also <file:Documentation/admin- <<
2662 <<
2663 config MITIGATION_MMIO_STALE_DATA <<
2664 bool "Mitigate MMIO Stale Data hardwa <<
2665 depends on CPU_SUP_INTEL <<
2666 default y <<
2667 help <<
2668 Enable mitigation for MMIO Stale Da <<
2669 Stale Data Vulnerabilities are a cl <<
2670 vulnerabilities that can expose dat <<
2671 attacker to have access to MMIO. <<
2672 See also <<
2673 <file:Documentation/admin-guide/hw- <<
2674 <<
2675 config MITIGATION_L1TF <<
2676 bool "Mitigate L1 Terminal Fault (L1T <<
2677 depends on CPU_SUP_INTEL <<
2678 default y <<
2679 help <<
2680 Mitigate L1 Terminal Fault (L1TF) h <<
2681 hardware vulnerability which allows <<
2682 available in the Level 1 Data Cache <<
2683 See <file:Documentation/admin-guide <<
2684 <<
2685 config MITIGATION_RETBLEED <<
2686 bool "Mitigate RETBleed hardware bug" <<
2687 depends on (CPU_SUP_INTEL && MITIGATI <<
2688 default y <<
2689 help <<
2690 Enable mitigation for RETBleed (Arb <<
2691 with Return Instructions) vulnerabi <<
2692 execution attack which takes advant <<
2693 in many modern microprocessors, sim <<
2694 unprivileged attacker can use these <<
2695 memory security restrictions to gai <<
2696 that would otherwise be inaccessibl <<
2697 2895
2698 config MITIGATION_SPECTRE_V1 !! 2896 config HZ_1000
2699 bool "Mitigate SPECTRE V1 hardware bu !! 2897 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2700 default y <<
2701 help <<
2702 Enable mitigation for Spectre V1 (B <<
2703 class of side channel attacks that <<
2704 execution that bypasses conditional <<
2705 memory access bounds check. <<
2706 See also <file:Documentation/admin- <<
2707 2898
2708 config MITIGATION_SPECTRE_V2 !! 2899 config HZ_1024
2709 bool "Mitigate SPECTRE V2 hardware bu !! 2900 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2710 default y <<
2711 help <<
2712 Enable mitigation for Spectre V2 (B <<
2713 V2 is a class of side channel attac <<
2714 indirect branch predictors inside t <<
2715 attacks, the attacker can steer spe <<
2716 victim to gadget code by poisoning <<
2717 used for predicting indirect branch <<
2718 See also <file:Documentation/admin- <<
2719 <<
2720 config MITIGATION_SRBDS <<
2721 bool "Mitigate Special Register Buffe <<
2722 depends on CPU_SUP_INTEL <<
2723 default y <<
2724 help <<
2725 Enable mitigation for Special Regis <<
2726 SRBDS is a hardware vulnerability t <<
2727 Sampling (MDS) techniques to infer <<
2728 register accesses. An unprivileged <<
2729 from RDRAND and RDSEED executed on <<
2730 using MDS techniques. <<
2731 See also <<
2732 <file:Documentation/admin-guide/hw- <<
2733 2901
2734 config MITIGATION_SSB !! 2902 endchoice
2735 bool "Mitigate Speculative Store Bypa <<
2736 default y <<
2737 help <<
2738 Enable mitigation for Speculative S <<
2739 hardware security vulnerability and <<
2740 of speculative execution in a simil <<
2741 security vulnerabilities. <<
2742 2903
2743 endif !! 2904 config SYS_SUPPORTS_24HZ
>> 2905 bool
2744 2906
2745 config ARCH_HAS_ADD_PAGES !! 2907 config SYS_SUPPORTS_48HZ
2746 def_bool y !! 2908 bool
2747 depends on ARCH_ENABLE_MEMORY_HOTPLUG <<
2748 2909
2749 menu "Power management and ACPI options" !! 2910 config SYS_SUPPORTS_100HZ
>> 2911 bool
2750 2912
2751 config ARCH_HIBERNATION_HEADER !! 2913 config SYS_SUPPORTS_128HZ
2752 def_bool y !! 2914 bool
2753 depends on HIBERNATION <<
2754 2915
2755 source "kernel/power/Kconfig" !! 2916 config SYS_SUPPORTS_250HZ
>> 2917 bool
2756 2918
2757 source "drivers/acpi/Kconfig" !! 2919 config SYS_SUPPORTS_256HZ
>> 2920 bool
2758 2921
2759 config X86_APM_BOOT !! 2922 config SYS_SUPPORTS_1000HZ
2760 def_bool y !! 2923 bool
2761 depends on APM <<
2762 2924
2763 menuconfig APM !! 2925 config SYS_SUPPORTS_1024HZ
2764 tristate "APM (Advanced Power Managem !! 2926 bool
2765 depends on X86_32 && PM_SLEEP <<
2766 help <<
2767 APM is a BIOS specification for sav <<
2768 techniques. This is mostly useful f <<
2769 APM compliant BIOSes. If you say Y <<
2770 reset after a RESUME operation, the <<
2771 battery status information, and use <<
2772 notification of APM "events" (e.g. <<
2773 <<
2774 If you select "Y" here, you can dis <<
2775 BIOS by passing the "apm=off" optio <<
2776 <<
2777 Note that the APM support is almost <<
2778 machines with more than one CPU. <<
2779 <<
2780 In order to use APM, you will need <<
2781 and more information, read <file:Do <<
2782 and the Battery Powered Linux mini- <<
2783 <http://www.tldp.org/docs.html#howt <<
2784 <<
2785 This driver does not spin down disk <<
2786 manpage ("man 8 hdparm") for that), <<
2787 VESA-compliant "green" monitors. <<
2788 <<
2789 This driver does not support the TI <<
2790 486/DX4/75 because they don't have <<
2791 desktop machines also don't have co <<
2792 may cause those machines to panic d <<
2793 <<
2794 Generally, if you don't have a batt <<
2795 much point in using this driver and <<
2796 random kernel OOPSes or reboots tha <<
2797 anything, try disabling/enabling th <<
2798 APM in your BIOS). <<
2799 <<
2800 Some other things you should try wh <<
2801 "weird" problems: <<
2802 <<
2803 1) make sure that you have enough s <<
2804 enabled. <<
2805 2) pass the "idle=poll" option to t <<
2806 3) switch on floating point emulati <<
2807 the "no387" option to the kernel <<
2808 4) pass the "floppy=nodma" option t <<
2809 5) pass the "mem=4M" option to the <<
2810 all but the first 4 MB of RAM) <<
2811 6) make sure that the CPU is not ov <<
2812 7) read the sig11 FAQ at <http://ww <<
2813 8) disable the cache from your BIOS <<
2814 9) install a fan for the video card <<
2815 10) install a better fan for the CP <<
2816 11) exchange RAM chips <<
2817 12) exchange the motherboard. <<
2818 <<
2819 To compile this driver as a module, <<
2820 module will be called apm. <<
2821 <<
2822 if APM <<
2823 <<
2824 config APM_IGNORE_USER_SUSPEND <<
2825 bool "Ignore USER SUSPEND" <<
2826 help <<
2827 This option will ignore USER SUSPEN <<
2828 compliant APM BIOS, you want to say <<
2829 series notebooks, it is necessary t <<
2830 <<
2831 config APM_DO_ENABLE <<
2832 bool "Enable PM at boot time" <<
2833 help <<
2834 Enable APM features at boot time. F <<
2835 specification: "When disabled, the <<
2836 power manage devices, enter the Sta <<
2837 State, or take power saving steps i <<
2838 This driver will make CPU Idle call <<
2839 feature is turned off -- see "Do CP <<
2840 should always save battery power, b <<
2841 will be dependent on your BIOS impl <<
2842 this option off if your computer ha <<
2843 support, or if it beeps continuousl <<
2844 this off if you have a NEC UltraLit <<
2845 T400CDT. This is off by default sin <<
2846 this feature. <<
2847 <<
2848 config APM_CPU_IDLE <<
2849 depends on CPU_IDLE <<
2850 bool "Make CPU Idle calls when idle" <<
2851 help <<
2852 Enable calls to APM CPU Idle/CPU Bu <<
2853 On some machines, this can activate <<
2854 a slowed CPU clock rate, when the m <<
2855 are made after the idle loop has ru <<
2856 333 mS). On some machines, this wil <<
2857 whenever the CPU becomes idle. (On <<
2858 this option does nothing.) <<
2859 <<
2860 config APM_DISPLAY_BLANK <<
2861 bool "Enable console blanking using A <<
2862 help <<
2863 Enable console blanking using the A <<
2864 turn off the LCD backlight when the <<
2865 virtual console blanks the screen. <<
2866 the virtual console screen blanker, <<
2867 when using the X Window system. Thi <<
2868 do with your VESA-compliant power-s <<
2869 option doesn't work for all laptops <<
2870 backlight at all, or it might print <<
2871 especially if you are using gpm. <<
2872 <<
2873 config APM_ALLOW_INTS <<
2874 bool "Allow interrupts during APM BIO <<
2875 help <<
2876 Normally we disable external interr <<
2877 the APM BIOS as a measure to lessen <<
2878 BIOS implementation. The BIOS shou <<
2879 needs to. Unfortunately, some BIOS <<
2880 many of the newer IBM Thinkpads. I <<
2881 suspend, try setting this to Y. Ot <<
2882 2927
2883 endif # APM !! 2928 config SYS_SUPPORTS_ARBIT_HZ
>> 2929 bool
>> 2930 default y if !SYS_SUPPORTS_24HZ && \
>> 2931 !SYS_SUPPORTS_48HZ && \
>> 2932 !SYS_SUPPORTS_100HZ && \
>> 2933 !SYS_SUPPORTS_128HZ && \
>> 2934 !SYS_SUPPORTS_250HZ && \
>> 2935 !SYS_SUPPORTS_256HZ && \
>> 2936 !SYS_SUPPORTS_1000HZ && \
>> 2937 !SYS_SUPPORTS_1024HZ
2884 2938
2885 source "drivers/cpufreq/Kconfig" !! 2939 config HZ
>> 2940 int
>> 2941 default 24 if HZ_24
>> 2942 default 48 if HZ_48
>> 2943 default 100 if HZ_100
>> 2944 default 128 if HZ_128
>> 2945 default 250 if HZ_250
>> 2946 default 256 if HZ_256
>> 2947 default 1000 if HZ_1000
>> 2948 default 1024 if HZ_1024
>> 2949
>> 2950 config SCHED_HRTICK
>> 2951 def_bool HIGH_RES_TIMERS
>> 2952
>> 2953 config KEXEC
>> 2954 bool "Kexec system call"
>> 2955 select KEXEC_CORE
>> 2956 help
>> 2957 kexec is a system call that implements the ability to shutdown your
>> 2958 current kernel, and to start another kernel. It is like a reboot
>> 2959 but it is independent of the system firmware. And like a reboot
>> 2960 you can start any kernel with it, not just Linux.
>> 2961
>> 2962 The name comes from the similarity to the exec system call.
>> 2963
>> 2964 It is an ongoing process to be certain the hardware in a machine
>> 2965 is properly shutdown, so do not be surprised if this code does not
>> 2966 initially work for you. As of this writing the exact hardware
>> 2967 interface is strongly in flux, so no good recommendation can be
>> 2968 made.
>> 2969
>> 2970 config CRASH_DUMP
>> 2971 bool "Kernel crash dumps"
>> 2972 help
>> 2973 Generate crash dump after being started by kexec.
>> 2974 This should be normally only set in special crash dump kernels
>> 2975 which are loaded in the main kernel with kexec-tools into
>> 2976 a specially reserved region and then later executed after
>> 2977 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2978 to a memory address not used by the main kernel or firmware using
>> 2979 PHYSICAL_START.
2886 2980
2887 source "drivers/cpuidle/Kconfig" !! 2981 config PHYSICAL_START
>> 2982 hex "Physical address where the kernel is loaded"
>> 2983 default "0xffffffff84000000"
>> 2984 depends on CRASH_DUMP
>> 2985 help
>> 2986 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2987 If you plan to use kernel for capturing the crash dump change
>> 2988 this value to start of the reserved region (the "X" value as
>> 2989 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2990 passed to the panic-ed kernel).
>> 2991
>> 2992 config MIPS_O32_FP64_SUPPORT
>> 2993 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2994 depends on 32BIT || MIPS32_O32
>> 2995 help
>> 2996 When this is enabled, the kernel will support use of 64-bit floating
>> 2997 point registers with binaries using the O32 ABI along with the
>> 2998 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2999 32-bit MIPS systems this support is at the cost of increasing the
>> 3000 size and complexity of the compiled FPU emulator. Thus if you are
>> 3001 running a MIPS32 system and know that none of your userland binaries
>> 3002 will require 64-bit floating point, you may wish to reduce the size
>> 3003 of your kernel & potentially improve FP emulation performance by
>> 3004 saying N here.
>> 3005
>> 3006 Although binutils currently supports use of this flag the details
>> 3007 concerning its effect upon the O32 ABI in userland are still being
>> 3008 worked on. In order to avoid userland becoming dependent upon current
>> 3009 behaviour before the details have been finalised, this option should
>> 3010 be considered experimental and only enabled by those working upon
>> 3011 said details.
2888 3012
2889 source "drivers/idle/Kconfig" !! 3013 If unsure, say N.
2890 3014
2891 endmenu !! 3015 config USE_OF
>> 3016 bool
>> 3017 select OF
>> 3018 select OF_EARLY_FLATTREE
>> 3019 select IRQ_DOMAIN
2892 3020
2893 menu "Bus options (PCI etc.)" !! 3021 config UHI_BOOT
>> 3022 bool
>> 3023
>> 3024 config BUILTIN_DTB
>> 3025 bool
2894 3026
2895 choice 3027 choice
2896 prompt "PCI access mode" !! 3028 prompt "Kernel appended dtb support" if USE_OF
2897 depends on X86_32 && PCI !! 3029 default MIPS_NO_APPENDED_DTB
2898 default PCI_GOANY !! 3030
2899 help !! 3031 config MIPS_NO_APPENDED_DTB
2900 On PCI systems, the BIOS can be use !! 3032 bool "None"
2901 determine their configuration. Howe !! 3033 help
2902 have BIOS bugs and may crash if thi !! 3034 Do not enable appended dtb support.
2903 PCI-based systems don't have any BI <<
2904 detect the PCI hardware directly wi <<
2905 <<
2906 With this option, you can specify h <<
2907 PCI devices. If you choose "BIOS", <<
2908 if you choose "Direct", the BIOS wo <<
2909 choose "MMConfig", then PCI Express <<
2910 If you choose "Any", the kernel wil <<
2911 direct access method and falls back <<
2912 work. If unsure, go with the defaul <<
2913 <<
2914 config PCI_GOBIOS <<
2915 bool "BIOS" <<
2916 <<
2917 config PCI_GOMMCONFIG <<
2918 bool "MMConfig" <<
2919 <<
2920 config PCI_GODIRECT <<
2921 bool "Direct" <<
2922 <<
2923 config PCI_GOOLPC <<
2924 bool "OLPC XO-1" <<
2925 depends on OLPC <<
2926 3035
2927 config PCI_GOANY !! 3036 config MIPS_ELF_APPENDED_DTB
2928 bool "Any" !! 3037 bool "vmlinux"
>> 3038 help
>> 3039 With this option, the boot code will look for a device tree binary
>> 3040 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3041 it is empty and the DTB can be appended using binutils command
>> 3042 objcopy:
>> 3043
>> 3044 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3045
>> 3046 This is meant as a backward compatibility convenience for those
>> 3047 systems with a bootloader that can't be upgraded to accommodate
>> 3048 the documented boot protocol using a device tree.
2929 3049
>> 3050 config MIPS_RAW_APPENDED_DTB
>> 3051 bool "vmlinux.bin or vmlinuz.bin"
>> 3052 help
>> 3053 With this option, the boot code will look for a device tree binary
>> 3054 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3055 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3056
>> 3057 This is meant as a backward compatibility convenience for those
>> 3058 systems with a bootloader that can't be upgraded to accommodate
>> 3059 the documented boot protocol using a device tree.
>> 3060
>> 3061 Beware that there is very little in terms of protection against
>> 3062 this option being confused by leftover garbage in memory that might
>> 3063 look like a DTB header after a reboot if no actual DTB is appended
>> 3064 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3065 if you don't intend to always append a DTB.
2930 endchoice 3066 endchoice
2931 3067
2932 config PCI_BIOS !! 3068 choice
2933 def_bool y !! 3069 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2934 depends on X86_32 && PCI && (PCI_GOBI !! 3070 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3071 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3072 !CAVIUM_OCTEON_SOC
>> 3073 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3074
>> 3075 config MIPS_CMDLINE_FROM_DTB
>> 3076 depends on USE_OF
>> 3077 bool "Dtb kernel arguments if available"
>> 3078
>> 3079 config MIPS_CMDLINE_DTB_EXTEND
>> 3080 depends on USE_OF
>> 3081 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3082
>> 3083 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3084 bool "Bootloader kernel arguments if available"
>> 3085
>> 3086 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3087 depends on CMDLINE_BOOL
>> 3088 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3089 endchoice
2935 3090
2936 # x86-64 doesn't support PCI BIOS access from !! 3091 endmenu
2937 config PCI_DIRECT <<
2938 def_bool y <<
2939 depends on PCI && (X86_64 || (PCI_GOD <<
2940 3092
2941 config PCI_MMCONFIG !! 3093 config LOCKDEP_SUPPORT
2942 bool "Support mmconfig PCI config spa !! 3094 bool
2943 default y 3095 default y
2944 depends on PCI && (ACPI || JAILHOUSE_ <<
2945 depends on X86_64 || (PCI_GOANY || PC <<
2946 3096
2947 config PCI_OLPC !! 3097 config STACKTRACE_SUPPORT
2948 def_bool y !! 3098 bool
2949 depends on PCI && OLPC && (PCI_GOOLPC !! 3099 default y
2950 3100
2951 config PCI_XEN !! 3101 config PGTABLE_LEVELS
2952 def_bool y !! 3102 int
2953 depends on PCI && XEN !! 3103 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3104 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3105 default 2
2954 3106
2955 config MMCONF_FAM10H !! 3107 config MIPS_AUTO_PFN_OFFSET
2956 def_bool y !! 3108 bool
2957 depends on X86_64 && PCI_MMCONFIG && <<
2958 3109
2959 config PCI_CNB20LE_QUIRK !! 3110 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2960 bool "Read CNB20LE Host Bridge Window <<
2961 depends on PCI <<
2962 help <<
2963 Read the PCI windows out of the CNB <<
2964 PCI hotplug to work on systems with <<
2965 not have ACPI. <<
2966 3111
2967 There's no public spec for this chi !! 3112 config PCI_DRIVERS_GENERIC
2968 is known to be incomplete. !! 3113 select PCI_DOMAINS_GENERIC if PCI
>> 3114 bool
2969 3115
2970 You should say N unless you know yo !! 3116 config PCI_DRIVERS_LEGACY
>> 3117 def_bool !PCI_DRIVERS_GENERIC
>> 3118 select NO_GENERIC_PCI_IOPORT_MAP
>> 3119 select PCI_DOMAINS if PCI
2971 3120
2972 config ISA_BUS !! 3121 #
2973 bool "ISA bus support on modern syste !! 3122 # ISA support is now enabled via select. Too many systems still have the one
2974 help !! 3123 # or other ISA chip on the board that users don't know about so don't expect
2975 Expose ISA bus device drivers and o !! 3124 # users to choose the right thing ...
2976 configuration. Enable this option i !! 3125 #
2977 bus. ISA is an older system, displa !! 3126 config ISA
2978 architectures -- if your target mac !! 3127 bool
2979 not have an ISA bus. <<
2980 3128
2981 If unsure, say N. !! 3129 config TC
>> 3130 bool "TURBOchannel support"
>> 3131 depends on MACH_DECSTATION
>> 3132 help
>> 3133 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3134 processors. TURBOchannel programming specifications are available
>> 3135 at:
>> 3136 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3137 and:
>> 3138 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3139 Linux driver support status is documented at:
>> 3140 <http://www.linux-mips.org/wiki/DECstation>
2982 3141
2983 # x86_64 have no ISA slots, but can have ISA- !! 3142 config MMU
2984 config ISA_DMA_API !! 3143 bool
2985 bool "ISA-style DMA support" if (X86_ <<
2986 default y 3144 default y
2987 help <<
2988 Enables ISA-style DMA support for d <<
2989 If unsure, say Y. <<
2990 3145
2991 if X86_32 !! 3146 config ARCH_MMAP_RND_BITS_MIN
>> 3147 default 12 if 64BIT
>> 3148 default 8
2992 3149
2993 config ISA !! 3150 config ARCH_MMAP_RND_BITS_MAX
2994 bool "ISA support" !! 3151 default 18 if 64BIT
2995 help !! 3152 default 15
2996 Find out whether you have ISA slots <<
2997 name of a bus system, i.e. the way <<
2998 inside your box. Other bus systems <<
2999 (MCA) or VESA. ISA is an older sys <<
3000 newer boards don't support it. If <<
3001 <<
3002 config SCx200 <<
3003 tristate "NatSemi SCx200 support" <<
3004 help <<
3005 This provides basic support for Nat <<
3006 (now AMD's) Geode processors. The <<
3007 PCI-IDs of several on-chip devices, <<
3008 for other scx200_* drivers. <<
3009 <<
3010 If compiled as a module, the driver <<
3011 <<
3012 config SCx200HR_TIMER <<
3013 tristate "NatSemi SCx200 27MHz High-R <<
3014 depends on SCx200 <<
3015 default y <<
3016 help <<
3017 This driver provides a clocksource <<
3018 27MHz high-resolution timer. Its a <<
3019 NSC Geode SC-1100's buggy TSC, whic <<
3020 processor goes idle (as is done by <<
3021 other workaround is idle=poll boot <<
3022 <<
3023 config OLPC <<
3024 bool "One Laptop Per Child support" <<
3025 depends on !X86_PAE <<
3026 select GPIOLIB <<
3027 select OF <<
3028 select OF_PROMTREE <<
3029 select IRQ_DOMAIN <<
3030 select OLPC_EC <<
3031 help <<
3032 Add support for detecting the uniqu <<
3033 XO hardware. <<
3034 3153
3035 config OLPC_XO1_PM !! 3154 config ARCH_MMAP_RND_COMPAT_BITS_MIN
3036 bool "OLPC XO-1 Power Management" !! 3155 default 8
3037 depends on OLPC && MFD_CS5535=y && PM <<
3038 help <<
3039 Add support for poweroff and suspen <<
3040 3156
3041 config OLPC_XO1_RTC !! 3157 config ARCH_MMAP_RND_COMPAT_BITS_MAX
3042 bool "OLPC XO-1 Real Time Clock" !! 3158 default 15
3043 depends on OLPC_XO1_PM && RTC_DRV_CMO <<
3044 help <<
3045 Add support for the XO-1 real time <<
3046 programmable wakeup source. <<
3047 3159
3048 config OLPC_XO1_SCI !! 3160 config I8253
3049 bool "OLPC XO-1 SCI extras" !! 3161 bool
3050 depends on OLPC && OLPC_XO1_PM && GPI !! 3162 select CLKSRC_I8253
3051 depends on INPUT=y !! 3163 select CLKEVT_I8253
3052 select POWER_SUPPLY !! 3164 select MIPS_EXTERNAL_TIMER
3053 help !! 3165 endmenu
3054 Add support for SCI-based features <<
3055 - EC-driven system wakeups <<
3056 - Power button <<
3057 - Ebook switch <<
3058 - Lid switch <<
3059 - AC adapter status updates <<
3060 - Battery status updates <<
3061 3166
3062 config OLPC_XO15_SCI !! 3167 config TRAD_SIGNALS
3063 bool "OLPC XO-1.5 SCI extras" !! 3168 bool
3064 depends on OLPC && ACPI <<
3065 select POWER_SUPPLY <<
3066 help <<
3067 Add support for SCI-based features <<
3068 - EC-driven system wakeups <<
3069 - AC adapter status updates <<
3070 - Battery status updates <<
3071 3169
3072 config GEODE_COMMON !! 3170 config MIPS32_COMPAT
3073 bool 3171 bool
3074 3172
3075 config ALIX !! 3173 config COMPAT
3076 bool "PCEngines ALIX System Support ( !! 3174 bool
3077 select GPIOLIB <<
3078 select GEODE_COMMON <<
3079 help <<
3080 This option enables system support <<
3081 At present this just sets up LEDs f <<
3082 ALIX2/3/6 boards. However, other s <<
3083 get added here. <<
3084 3175
3085 Note: You must still enable the dri !! 3176 config SYSVIPC_COMPAT
3086 (GPIO_CS5535 & LEDS_GPIO) to actual !! 3177 bool
3087 3178
3088 Note: You have to set alix.force=1 !! 3179 config MIPS32_O32
>> 3180 bool "Kernel support for o32 binaries"
>> 3181 depends on 64BIT
>> 3182 select ARCH_WANT_OLD_COMPAT_IPC
>> 3183 select COMPAT
>> 3184 select MIPS32_COMPAT
>> 3185 select SYSVIPC_COMPAT if SYSVIPC
>> 3186 help
>> 3187 Select this option if you want to run o32 binaries. These are pure
>> 3188 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3189 existing binaries are in this format.
3089 3190
3090 config NET5501 !! 3191 If unsure, say Y.
3091 bool "Soekris Engineering net5501 Sys <<
3092 select GPIOLIB <<
3093 select GEODE_COMMON <<
3094 help <<
3095 This option enables system support <<
3096 3192
3097 config GEOS !! 3193 config MIPS32_N32
3098 bool "Traverse Technologies GEOS Syst !! 3194 bool "Kernel support for n32 binaries"
3099 select GPIOLIB !! 3195 depends on 64BIT
3100 select GEODE_COMMON !! 3196 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
3101 depends on DMI !! 3197 select COMPAT
3102 help !! 3198 select MIPS32_COMPAT
3103 This option enables system support !! 3199 select SYSVIPC_COMPAT if SYSVIPC
>> 3200 help
>> 3201 Select this option if you want to run n32 binaries. These are
>> 3202 64-bit binaries using 32-bit quantities for addressing and certain
>> 3203 data that would normally be 64-bit. They are used in special
>> 3204 cases.
3104 3205
3105 config TS5500 !! 3206 If unsure, say N.
3106 bool "Technologic Systems TS-5500 pla <<
3107 depends on MELAN <<
3108 select CHECK_SIGNATURE <<
3109 select NEW_LEDS <<
3110 select LEDS_CLASS <<
3111 help <<
3112 This option enables system support <<
3113 3207
3114 endif # X86_32 !! 3208 menu "Power management options"
3115 3209
3116 config AMD_NB !! 3210 config ARCH_HIBERNATION_POSSIBLE
3117 def_bool y 3211 def_bool y
3118 depends on CPU_SUP_AMD && PCI !! 3212 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3119 3213
3120 endmenu !! 3214 config ARCH_SUSPEND_POSSIBLE
>> 3215 def_bool y
>> 3216 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3121 3217
3122 menu "Binary Emulations" !! 3218 source "kernel/power/Kconfig"
3123 3219
3124 config IA32_EMULATION !! 3220 endmenu
3125 bool "IA32 Emulation" <<
3126 depends on X86_64 <<
3127 select ARCH_WANT_OLD_COMPAT_IPC <<
3128 select BINFMT_ELF <<
3129 select COMPAT_OLD_SIGACTION <<
3130 help <<
3131 Include code to run legacy 32-bit p <<
3132 64-bit kernel. You should likely tu <<
3133 100% sure that you don't have any 3 <<
3134 3221
3135 config IA32_EMULATION_DEFAULT_DISABLED !! 3222 config MIPS_EXTERNAL_TIMER
3136 bool "IA32 emulation disabled by defa !! 3223 bool
3137 default n <<
3138 depends on IA32_EMULATION <<
3139 help <<
3140 Make IA32 emulation disabled by def <<
3141 processes and access to 32-bit sysc <<
3142 default value. <<
3143 <<
3144 config X86_X32_ABI <<
3145 bool "x32 ABI for 64-bit mode" <<
3146 depends on X86_64 <<
3147 # llvm-objcopy does not convert x86_6 <<
3148 # compressed debug sections to x86_x3 <<
3149 # https://github.com/ClangBuiltLinux/ <<
3150 # https://github.com/ClangBuiltLinux/ <<
3151 depends on $(success,$(OBJCOPY) --ver <<
3152 help <<
3153 Include code to run binaries for th <<
3154 for 64-bit processors. An x32 proc <<
3155 full 64-bit register file and wide <<
3156 pointers at 32 bits for smaller mem <<
3157 3224
3158 config COMPAT_32 !! 3225 menu "CPU Power Management"
3159 def_bool y <<
3160 depends on IA32_EMULATION || X86_32 <<
3161 select HAVE_UID16 <<
3162 select OLD_SIGSUSPEND3 <<
3163 3226
3164 config COMPAT !! 3227 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3165 def_bool y !! 3228 source "drivers/cpufreq/Kconfig"
3166 depends on IA32_EMULATION || X86_X32_ !! 3229 endif
3167 3230
3168 config COMPAT_FOR_U64_ALIGNMENT !! 3231 source "drivers/cpuidle/Kconfig"
3169 def_bool y <<
3170 depends on COMPAT <<
3171 3232
3172 endmenu 3233 endmenu
3173 3234
3174 config HAVE_ATOMIC_IOMAP !! 3235 source "arch/mips/kvm/Kconfig"
3175 def_bool y <<
3176 depends on X86_32 <<
3177 <<
3178 source "arch/x86/kvm/Kconfig" <<
3179 3236
3180 source "arch/x86/Kconfig.assembler" !! 3237 source "arch/mips/vdso/Kconfig"
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