1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 # Select 32 or 64 bit !! 2 config MIPS
3 config 64BIT !! 3 bool
4 bool "64-bit kernel" if "$(ARCH)" = "x !! 4 default y
5 default "$(ARCH)" != "i386" !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 help !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 Say yes to build a 64-bit kernel - f !! 7 select ARCH_HAS_CPU_CACHE_ALIASING
8 Say no to build a 32-bit kernel - fo <<
9 <<
10 config X86_32 <<
11 def_bool y <<
12 depends on !64BIT <<
13 # Options that are inherently 32-bit k <<
14 select ARCH_WANT_IPC_PARSE_VERSION <<
15 select CLKSRC_I8253 <<
16 select CLONE_BACKWARDS <<
17 select GENERIC_VDSO_32 <<
18 select HAVE_DEBUG_STACKOVERFLOW <<
19 select KMAP_LOCAL <<
20 select MODULES_USE_ELF_REL <<
21 select OLD_SIGACTION <<
22 select ARCH_SPLIT_ARG64 <<
23 <<
24 config X86_64 <<
25 def_bool y <<
26 depends on 64BIT <<
27 # Options that are inherently 64-bit k <<
28 select ARCH_HAS_GIGANTIC_PAGE <<
29 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
30 select ARCH_SUPPORTS_PER_VMA_LOCK <<
31 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
32 select HAVE_ARCH_SOFT_DIRTY <<
33 select MODULES_USE_ELF_RELA <<
34 select NEED_DMA_MAP_STATE <<
35 select SWIOTLB <<
36 select ARCH_HAS_ELFCORE_COMPAT <<
37 select ZONE_DMA32 <<
38 select EXECMEM if DYNAMIC_FTRACE <<
39 <<
40 config FORCE_DYNAMIC_FTRACE <<
41 def_bool y <<
42 depends on X86_32 <<
43 depends on FUNCTION_TRACER <<
44 select DYNAMIC_FTRACE <<
45 help <<
46 We keep the static function tracing <<
47 in order to test the non static func <<
48 generic code, as other architectures <<
49 only need to keep it around for x86_ <<
50 for x86_32. For x86_32, force DYNAMI <<
51 # <<
52 # Arch settings <<
53 # <<
54 # ( Note that options that are marked 'if X86_ <<
55 # ported to 32-bit as well. ) <<
56 # <<
57 config X86 <<
58 def_bool y <<
59 # <<
60 # Note: keep this list sorted alphabet <<
61 # <<
62 select ACPI_LEGACY_TABLES_LOOKUP <<
63 select ACPI_SYSTEM_POWER_STATES_SUPPOR <<
64 select ACPI_HOTPLUG_CPU <<
65 select ARCH_32BIT_OFF_T <<
66 select ARCH_CLOCKSOURCE_INIT <<
67 select ARCH_CONFIGURES_CPU_MITIGATIONS <<
68 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
69 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
70 select ARCH_ENABLE_MEMORY_HOTPLUG if X <<
71 select ARCH_ENABLE_MEMORY_HOTREMOVE if <<
72 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
73 select ARCH_ENABLE_THP_MIGRATION if X8 <<
74 select ARCH_HAS_ACPI_TABLE_UPGRADE <<
75 select ARCH_HAS_CACHE_LINE_SIZE <<
76 select ARCH_HAS_CPU_CACHE_INVALIDATE_M <<
77 select ARCH_HAS_CPU_FINALIZE_INIT 8 select ARCH_HAS_CPU_FINALIZE_INIT
78 select ARCH_HAS_CPU_PASID !! 9 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
79 select ARCH_HAS_CURRENT_STACK_POINTER !! 10 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
80 select ARCH_HAS_DEBUG_VIRTUAL <<
81 select ARCH_HAS_DEBUG_VM_PGTABLE <<
82 select ARCH_HAS_DEVMEM_IS_ALLOWED <<
83 select ARCH_HAS_DMA_OPS <<
84 select ARCH_HAS_EARLY_DEBUG <<
85 select ARCH_HAS_ELF_RANDOMIZE <<
86 select ARCH_HAS_FAST_MULTIPLIER <<
87 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_FORTIFY_SOURCE
88 select ARCH_HAS_GCOV_PROFILE_ALL !! 12 select ARCH_HAS_KCOV
89 select ARCH_HAS_KCOV !! 13 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
90 select ARCH_HAS_KERNEL_FPU_SUPPORT !! 14 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
91 select ARCH_HAS_MEM_ENCRYPT !! 15 select ARCH_HAS_STRNCPY_FROM_USER
92 select ARCH_HAS_MEMBARRIER_SYNC_CORE !! 16 select ARCH_HAS_STRNLEN_USER
93 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS !! 17 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
94 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
95 select ARCH_HAS_PMEM_API <<
96 select ARCH_HAS_PTE_DEVMAP <<
97 select ARCH_HAS_PTE_SPECIAL <<
98 select ARCH_HAS_HW_PTE_YOUNG <<
99 select ARCH_HAS_NONLEAF_PMD_YOUNG <<
100 select ARCH_HAS_UACCESS_FLUSHCACHE <<
101 select ARCH_HAS_COPY_MC <<
102 select ARCH_HAS_SET_MEMORY <<
103 select ARCH_HAS_SET_DIRECT_MAP <<
104 select ARCH_HAS_STRICT_KERNEL_RWX <<
105 select ARCH_HAS_STRICT_MODULE_RWX <<
106 select ARCH_HAS_SYNC_CORE_BEFORE_USERM <<
107 select ARCH_HAS_SYSCALL_WRAPPER <<
108 select ARCH_HAS_UBSAN 18 select ARCH_HAS_UBSAN
109 select ARCH_HAS_DEBUG_WX !! 19 select ARCH_HAS_GCOV_PROFILE_ALL
110 select ARCH_HAS_ZONE_DMA_SET if EXPERT !! 20 select ARCH_KEEP_MEMBLOCK
111 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
112 select ARCH_HAVE_EXTRA_ELF_NOTES <<
113 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
114 select ARCH_MIGHT_HAVE_ACPI_PDC <<
115 select ARCH_MIGHT_HAVE_PC_PARPORT <<
116 select ARCH_MIGHT_HAVE_PC_SERIO <<
117 select ARCH_STACKWALK <<
118 select ARCH_SUPPORTS_ACPI <<
119 select ARCH_SUPPORTS_ATOMIC_RMW <<
120 select ARCH_SUPPORTS_DEBUG_PAGEALLOC <<
121 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
122 select ARCH_SUPPORTS_NUMA_BALANCING <<
123 select ARCH_SUPPORTS_KMAP_LOCAL_FORCE_ <<
124 select ARCH_SUPPORTS_CFI_CLANG <<
125 select ARCH_USES_CFI_TRAPS <<
126 select ARCH_SUPPORTS_LTO_CLANG <<
127 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
128 select ARCH_SUPPORTS_RT <<
129 select ARCH_USE_BUILTIN_BSWAP 21 select ARCH_USE_BUILTIN_BSWAP
130 select ARCH_USE_CMPXCHG_LOCKREF !! 22 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
131 select ARCH_USE_MEMTEST 23 select ARCH_USE_MEMTEST
132 select ARCH_USE_QUEUED_RWLOCKS 24 select ARCH_USE_QUEUED_RWLOCKS
133 select ARCH_USE_QUEUED_SPINLOCKS 25 select ARCH_USE_QUEUED_SPINLOCKS
134 select ARCH_USE_SYM_ANNOTATIONS !! 26 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
135 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU !! 27 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
136 select ARCH_WANT_DEFAULT_BPF_JIT !! 28 select ARCH_WANT_IPC_PARSE_VERSION
137 select ARCH_WANTS_DYNAMIC_TASK_STRUCT <<
138 select ARCH_WANTS_NO_INSTR <<
139 select ARCH_WANT_GENERAL_HUGETLB <<
140 select ARCH_WANT_HUGE_PMD_SHARE <<
141 select ARCH_WANT_LD_ORPHAN_WARN 29 select ARCH_WANT_LD_ORPHAN_WARN
142 select ARCH_WANT_OPTIMIZE_DAX_VMEMMAP <<
143 select ARCH_WANT_OPTIMIZE_HUGETLB_VMEM <<
144 select ARCH_WANTS_THP_SWAP <<
145 select ARCH_HAS_PARANOID_L1D_FLUSH <<
146 select BUILDTIME_TABLE_SORT 30 select BUILDTIME_TABLE_SORT
147 select CLKEVT_I8253 !! 31 select CLONE_BACKWARDS
148 select CLOCKSOURCE_VALIDATE_LAST_CYCLE !! 32 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
149 select CLOCKSOURCE_WATCHDOG !! 33 select CPU_PM if CPU_IDLE || SUSPEND
150 # Word-size accesses may read uninitia !! 34 select GENERIC_ATOMIC64 if !64BIT
151 # in strings and cause false KMSAN rep <<
152 select DCACHE_WORD_ACCESS <<
153 select DYNAMIC_SIGFRAME <<
154 select EDAC_ATOMIC_SCRUB <<
155 select EDAC_SUPPORT <<
156 select GENERIC_CLOCKEVENTS_BROADCAST <<
157 select GENERIC_CLOCKEVENTS_BROADCAST_I <<
158 select GENERIC_CLOCKEVENTS_MIN_ADJUST <<
159 select GENERIC_CMOS_UPDATE 35 select GENERIC_CMOS_UPDATE
160 select GENERIC_CPU_AUTOPROBE 36 select GENERIC_CPU_AUTOPROBE
161 select GENERIC_CPU_DEVICES !! 37 select GENERIC_GETTIMEOFDAY
162 select GENERIC_CPU_VULNERABILITIES <<
163 select GENERIC_EARLY_IOREMAP <<
164 select GENERIC_ENTRY <<
165 select GENERIC_IOMAP 38 select GENERIC_IOMAP
166 select GENERIC_IRQ_EFFECTIVE_AFF_MASK <<
167 select GENERIC_IRQ_MATRIX_ALLOCATOR <<
168 select GENERIC_IRQ_MIGRATION <<
169 select GENERIC_IRQ_PROBE 39 select GENERIC_IRQ_PROBE
170 select GENERIC_IRQ_RESERVATION_MODE <<
171 select GENERIC_IRQ_SHOW 40 select GENERIC_IRQ_SHOW
172 select GENERIC_PENDING_IRQ !! 41 select GENERIC_ISA_DMA if EISA
173 select GENERIC_PTDUMP !! 42 select GENERIC_LIB_ASHLDI3
>> 43 select GENERIC_LIB_ASHRDI3
>> 44 select GENERIC_LIB_CMPDI2
>> 45 select GENERIC_LIB_LSHRDI3
>> 46 select GENERIC_LIB_UCMPDI2
>> 47 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
174 select GENERIC_SMP_IDLE_THREAD 48 select GENERIC_SMP_IDLE_THREAD
>> 49 select GENERIC_IDLE_POLL_SETUP
175 select GENERIC_TIME_VSYSCALL 50 select GENERIC_TIME_VSYSCALL
176 select GENERIC_GETTIMEOFDAY !! 51 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
177 select GENERIC_VDSO_TIME_NS !! 52 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
178 select GENERIC_VDSO_OVERFLOW_PROTECT !! 53 select HAVE_ARCH_COMPILER_H
179 select GUP_GET_PXX_LOW_HIGH <<
180 select HARDIRQS_SW_RESEND <<
181 select HARDLOCKUP_CHECK_TIMESTAMP <<
182 select HAS_IOPORT <<
183 select HAVE_ACPI_APEI <<
184 select HAVE_ACPI_APEI_NMI <<
185 select HAVE_ALIGNED_STRUCT_PAGE <<
186 select HAVE_ARCH_AUDITSYSCALL <<
187 select HAVE_ARCH_HUGE_VMAP <<
188 select HAVE_ARCH_HUGE_VMALLOC <<
189 select HAVE_ARCH_JUMP_LABEL 54 select HAVE_ARCH_JUMP_LABEL
190 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 55 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
191 select HAVE_ARCH_KASAN !! 56 select HAVE_ARCH_MMAP_RND_BITS if MMU
192 select HAVE_ARCH_KASAN_VMALLOC !! 57 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
193 select HAVE_ARCH_KFENCE <<
194 select HAVE_ARCH_KMSAN <<
195 select HAVE_ARCH_KGDB <<
196 select HAVE_ARCH_MMAP_RND_BITS <<
197 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
198 select HAVE_ARCH_COMPAT_MMAP_BASES <<
199 select HAVE_ARCH_PREL32_RELOCATIONS <<
200 select HAVE_ARCH_SECCOMP_FILTER 58 select HAVE_ARCH_SECCOMP_FILTER
201 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
202 select HAVE_ARCH_STACKLEAK <<
203 select HAVE_ARCH_TRACEHOOK 59 select HAVE_ARCH_TRACEHOOK
204 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 60 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
205 select HAVE_ARCH_TRANSPARENT_HUGEPAGE_ <<
206 select HAVE_ARCH_USERFAULTFD_WP <<
207 select HAVE_ARCH_USERFAULTFD_MINOR <<
208 select HAVE_ARCH_VMAP_STACK <<
209 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
210 select HAVE_ARCH_WITHIN_STACK_FRAMES <<
211 select HAVE_ASM_MODVERSIONS 61 select HAVE_ASM_MODVERSIONS
212 select HAVE_CMPXCHG_DOUBLE !! 62 select HAVE_CONTEXT_TRACKING_USER
213 select HAVE_CMPXCHG_LOCAL !! 63 select HAVE_TIF_NOHZ
214 select HAVE_CONTEXT_TRACKING_USER <<
215 select HAVE_CONTEXT_TRACKING_USER_OFFS <<
216 select HAVE_C_RECORDMCOUNT 64 select HAVE_C_RECORDMCOUNT
217 select HAVE_OBJTOOL_MCOUNT <<
218 select HAVE_OBJTOOL_NOP_MCOUNT <<
219 select HAVE_BUILDTIME_MCOUNT_SORT <<
220 select HAVE_DEBUG_KMEMLEAK 65 select HAVE_DEBUG_KMEMLEAK
>> 66 select HAVE_DEBUG_STACKOVERFLOW
221 select HAVE_DMA_CONTIGUOUS 67 select HAVE_DMA_CONTIGUOUS
222 select HAVE_DYNAMIC_FTRACE 68 select HAVE_DYNAMIC_FTRACE
223 select HAVE_DYNAMIC_FTRACE_WITH_REGS !! 69 select HAVE_EBPF_JIT if !CPU_MICROMIPS
224 select HAVE_DYNAMIC_FTRACE_WITH_ARGS <<
225 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT <<
226 select HAVE_SAMPLE_FTRACE_DIRECT <<
227 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
228 select HAVE_EBPF_JIT <<
229 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
230 select HAVE_EISA <<
231 select HAVE_EXIT_THREAD 70 select HAVE_EXIT_THREAD
232 select HAVE_GUP_FAST 71 select HAVE_GUP_FAST
233 select HAVE_FENTRY <<
234 select HAVE_FTRACE_MCOUNT_RECORD 72 select HAVE_FTRACE_MCOUNT_RECORD
235 select HAVE_FUNCTION_GRAPH_RETVAL !! 73 select HAVE_FUNCTION_GRAPH_TRACER
236 select HAVE_FUNCTION_GRAPH_TRACER <<
237 select HAVE_FUNCTION_TRACER 74 select HAVE_FUNCTION_TRACER
238 select HAVE_GCC_PLUGINS 75 select HAVE_GCC_PLUGINS
239 select HAVE_HW_BREAKPOINT !! 76 select HAVE_GENERIC_VDSO
240 select HAVE_IOREMAP_PROT 77 select HAVE_IOREMAP_PROT
241 select HAVE_IRQ_EXIT_ON_IRQ_STACK !! 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
242 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_IRQ_TIME_ACCOUNTING
243 select HAVE_JUMP_LABEL_HACK <<
244 select HAVE_KERNEL_BZIP2 <<
245 select HAVE_KERNEL_GZIP <<
246 select HAVE_KERNEL_LZ4 <<
247 select HAVE_KERNEL_LZMA <<
248 select HAVE_KERNEL_LZO <<
249 select HAVE_KERNEL_XZ <<
250 select HAVE_KERNEL_ZSTD <<
251 select HAVE_KPROBES 80 select HAVE_KPROBES
252 select HAVE_KPROBES_ON_FTRACE <<
253 select HAVE_FUNCTION_ERROR_INJECTION <<
254 select HAVE_KRETPROBES 81 select HAVE_KRETPROBES
255 select HAVE_RETHOOK !! 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
256 select HAVE_LIVEPATCH <<
257 select HAVE_MIXED_BREAKPOINTS_REGS <<
258 select HAVE_MOD_ARCH_SPECIFIC 83 select HAVE_MOD_ARCH_SPECIFIC
259 select HAVE_MOVE_PMD <<
260 select HAVE_MOVE_PUD <<
261 select HAVE_NOINSTR_HACK <<
262 select HAVE_NMI 84 select HAVE_NMI
263 select HAVE_NOINSTR_VALIDATION !! 85 select HAVE_PAGE_SIZE_4KB if !CPU_LOONGSON2EF && !CPU_LOONGSON64
264 select HAVE_OBJTOOL !! 86 select HAVE_PAGE_SIZE_16KB if !CPU_R3000
265 select HAVE_OPTPROBES !! 87 select HAVE_PAGE_SIZE_64KB if !CPU_R3000
266 select HAVE_PAGE_SIZE_4KB <<
267 select HAVE_PCSPKR_PLATFORM <<
268 select HAVE_PERF_EVENTS 88 select HAVE_PERF_EVENTS
269 select HAVE_PERF_EVENTS_NMI <<
270 select HAVE_HARDLOCKUP_DETECTOR_PERF <<
271 select HAVE_PCI <<
272 select HAVE_PERF_REGS 89 select HAVE_PERF_REGS
273 select HAVE_PERF_USER_STACK_DUMP 90 select HAVE_PERF_USER_STACK_DUMP
274 select MMU_GATHER_RCU_TABLE_FREE <<
275 select MMU_GATHER_MERGE_VMAS <<
276 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
277 select HAVE_REGS_AND_STACK_ACCESS_API 91 select HAVE_REGS_AND_STACK_ACCESS_API
278 select HAVE_RELIABLE_STACKTRACE <<
279 select HAVE_FUNCTION_ARG_ACCESS_API <<
280 select HAVE_SETUP_PER_CPU_AREA <<
281 select HAVE_SOFTIRQ_ON_OWN_STACK <<
282 select HAVE_STACKPROTECTOR <<
283 select HAVE_STACK_VALIDATION <<
284 select HAVE_STATIC_CALL <<
285 select HAVE_STATIC_CALL_INLINE <<
286 select HAVE_PREEMPT_DYNAMIC_CALL <<
287 select HAVE_RSEQ 92 select HAVE_RSEQ
288 select HAVE_RUST !! 93 select HAVE_SPARSE_SYSCALL_NR
>> 94 select HAVE_STACKPROTECTOR
289 select HAVE_SYSCALL_TRACEPOINTS 95 select HAVE_SYSCALL_TRACEPOINTS
290 select HAVE_UACCESS_VALIDATION !! 96 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
291 select HAVE_UNSTABLE_SCHED_CLOCK <<
292 select HAVE_USER_RETURN_NOTIFIER <<
293 select HAVE_GENERIC_VDSO <<
294 select VDSO_GETRANDOM <<
295 select HOTPLUG_PARALLEL <<
296 select HOTPLUG_SMT <<
297 select HOTPLUG_SPLIT_STARTUP <<
298 select IRQ_FORCED_THREADING 97 select IRQ_FORCED_THREADING
>> 98 select ISA if EISA
299 select LOCK_MM_AND_FIND_VMA 99 select LOCK_MM_AND_FIND_VMA
300 select NEED_PER_CPU_EMBED_FIRST_CHUNK !! 100 select MODULES_USE_ELF_REL if MODULES
301 select NEED_PER_CPU_PAGE_FIRST_CHUNK !! 101 select MODULES_USE_ELF_RELA if MODULES && 64BIT
302 select NEED_SG_DMA_LENGTH !! 102 select PERF_USE_VMALLOC
303 select NUMA_MEMBLKS !! 103 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
304 select PCI_DOMAINS <<
305 select PCI_LOCKLESS_CONFIG <<
306 select PERF_EVENTS <<
307 select RTC_LIB 104 select RTC_LIB
308 select RTC_MC146818_LIB <<
309 select SPARSE_IRQ <<
310 select SYSCTL_EXCEPTION_TRACE 105 select SYSCTL_EXCEPTION_TRACE
311 select THREAD_INFO_IN_TASK <<
312 select TRACE_IRQFLAGS_SUPPORT 106 select TRACE_IRQFLAGS_SUPPORT
313 select TRACE_IRQFLAGS_NMI_SUPPORT !! 107 select ARCH_HAS_ELFCORE_COMPAT
314 select USER_STACKTRACE_SUPPORT !! 108 select HAVE_ARCH_KCSAN if 64BIT
315 select HAVE_ARCH_KCSAN <<
316 select PROC_PID_ARCH_STATUS <<
317 select HAVE_ARCH_NODE_DEV_GROUP <<
318 select FUNCTION_ALIGNMENT_16B <<
319 select FUNCTION_ALIGNMENT_4B <<
320 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
321 select HAVE_DYNAMIC_FTRACE_NO_PATCHABL <<
322 109
323 config INSTRUCTION_DECODER !! 110 config MIPS_FIXUP_BIGPHYS_ADDR
324 def_bool y !! 111 bool
325 depends on KPROBES || PERF_EVENTS || U <<
326 112
327 config OUTPUT_FORMAT !! 113 config MIPS_GENERIC
328 string !! 114 bool
329 default "elf32-i386" if X86_32 <<
330 default "elf64-x86-64" if X86_64 <<
331 115
332 config LOCKDEP_SUPPORT !! 116 config MACH_GENERIC_CORE
333 def_bool y !! 117 bool
334 118
335 config STACKTRACE_SUPPORT !! 119 config MACH_INGENIC
336 def_bool y !! 120 bool
>> 121 select SYS_SUPPORTS_32BIT_KERNEL
>> 122 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 123 select SYS_SUPPORTS_ZBOOT
>> 124 select DMA_NONCOHERENT
>> 125 select IRQ_MIPS_CPU
>> 126 select PINCTRL
>> 127 select GPIOLIB
>> 128 select COMMON_CLK
>> 129 select GENERIC_IRQ_CHIP
>> 130 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 131 select USE_OF
>> 132 select CPU_SUPPORTS_CPUFREQ
>> 133 select MIPS_EXTERNAL_TIMER
337 134
338 config MMU !! 135 menu "Machine selection"
339 def_bool y <<
340 136
341 config ARCH_MMAP_RND_BITS_MIN !! 137 choice
342 default 28 if 64BIT !! 138 prompt "System type"
343 default 8 !! 139 default MIPS_GENERIC_KERNEL
344 140
345 config ARCH_MMAP_RND_BITS_MAX !! 141 config MIPS_GENERIC_KERNEL
346 default 32 if 64BIT !! 142 bool "Generic board-agnostic MIPS kernel"
347 default 16 !! 143 select MIPS_GENERIC
>> 144 select BOOT_RAW
>> 145 select BUILTIN_DTB
>> 146 select CEVT_R4K
>> 147 select CLKSRC_MIPS_GIC
>> 148 select COMMON_CLK
>> 149 select CPU_MIPSR2_IRQ_EI
>> 150 select CPU_MIPSR2_IRQ_VI
>> 151 select CSRC_R4K
>> 152 select DMA_NONCOHERENT
>> 153 select HAVE_PCI
>> 154 select IRQ_MIPS_CPU
>> 155 select MACH_GENERIC_CORE
>> 156 select MIPS_AUTO_PFN_OFFSET
>> 157 select MIPS_CPU_SCACHE
>> 158 select MIPS_GIC
>> 159 select MIPS_L1_CACHE_SHIFT_7
>> 160 select NO_EXCEPT_FILL
>> 161 select PCI_DRIVERS_GENERIC
>> 162 select SMP_UP if SMP
>> 163 select SWAP_IO_SPACE
>> 164 select SYS_HAS_CPU_MIPS32_R1
>> 165 select SYS_HAS_CPU_MIPS32_R2
>> 166 select SYS_HAS_CPU_MIPS32_R5
>> 167 select SYS_HAS_CPU_MIPS32_R6
>> 168 select SYS_HAS_CPU_MIPS64_R1
>> 169 select SYS_HAS_CPU_MIPS64_R2
>> 170 select SYS_HAS_CPU_MIPS64_R5
>> 171 select SYS_HAS_CPU_MIPS64_R6
>> 172 select SYS_SUPPORTS_32BIT_KERNEL
>> 173 select SYS_SUPPORTS_64BIT_KERNEL
>> 174 select SYS_SUPPORTS_BIG_ENDIAN
>> 175 select SYS_SUPPORTS_HIGHMEM
>> 176 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 177 select SYS_SUPPORTS_MICROMIPS
>> 178 select SYS_SUPPORTS_MIPS16
>> 179 select SYS_SUPPORTS_MIPS_CPS
>> 180 select SYS_SUPPORTS_MULTITHREADING
>> 181 select SYS_SUPPORTS_RELOCATABLE
>> 182 select SYS_SUPPORTS_SMARTMIPS
>> 183 select SYS_SUPPORTS_ZBOOT
>> 184 select UHI_BOOT
>> 185 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 186 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 187 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 188 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 189 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 190 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 191 select USE_OF
>> 192 help
>> 193 Select this to build a kernel which aims to support multiple boards,
>> 194 generally using a flattened device tree passed from the bootloader
>> 195 using the boot protocol defined in the UHI (Unified Hosting
>> 196 Interface) specification.
348 197
349 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 198 config MIPS_ALCHEMY
350 default 8 !! 199 bool "Alchemy processor based machines"
>> 200 select PHYS_ADDR_T_64BIT
>> 201 select CEVT_R4K
>> 202 select CSRC_R4K
>> 203 select IRQ_MIPS_CPU
>> 204 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 205 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 206 select SYS_HAS_CPU_MIPS32_R1
>> 207 select SYS_SUPPORTS_32BIT_KERNEL
>> 208 select SYS_SUPPORTS_APM_EMULATION
>> 209 select GPIOLIB
>> 210 select SYS_SUPPORTS_ZBOOT
>> 211 select COMMON_CLK
351 212
352 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 213 config ATH25
353 default 16 !! 214 bool "Atheros AR231x/AR531x SoC support"
>> 215 select CEVT_R4K
>> 216 select CSRC_R4K
>> 217 select DMA_NONCOHERENT
>> 218 select IRQ_MIPS_CPU
>> 219 select IRQ_DOMAIN
>> 220 select SYS_HAS_CPU_MIPS32_R1
>> 221 select SYS_SUPPORTS_BIG_ENDIAN
>> 222 select SYS_SUPPORTS_32BIT_KERNEL
>> 223 select SYS_HAS_EARLY_PRINTK
>> 224 help
>> 225 Support for Atheros AR231x and Atheros AR531x based boards
>> 226
>> 227 config ATH79
>> 228 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 229 select ARCH_HAS_RESET_CONTROLLER
>> 230 select BOOT_RAW
>> 231 select CEVT_R4K
>> 232 select CSRC_R4K
>> 233 select DMA_NONCOHERENT
>> 234 select GPIOLIB
>> 235 select PINCTRL
>> 236 select COMMON_CLK
>> 237 select IRQ_MIPS_CPU
>> 238 select SYS_HAS_CPU_MIPS32_R2
>> 239 select SYS_HAS_EARLY_PRINTK
>> 240 select SYS_SUPPORTS_32BIT_KERNEL
>> 241 select SYS_SUPPORTS_BIG_ENDIAN
>> 242 select SYS_SUPPORTS_MIPS16
>> 243 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 244 select USE_OF
>> 245 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 246 help
>> 247 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 248
>> 249 config BMIPS_GENERIC
>> 250 bool "Broadcom Generic BMIPS kernel"
>> 251 select ARCH_HAS_RESET_CONTROLLER
>> 252 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 253 select BOOT_RAW
>> 254 select NO_EXCEPT_FILL
>> 255 select USE_OF
>> 256 select CEVT_R4K
>> 257 select CSRC_R4K
>> 258 select SYNC_R4K
>> 259 select COMMON_CLK
>> 260 select BCM6345_L1_IRQ
>> 261 select BCM7038_L1_IRQ
>> 262 select BCM7120_L2_IRQ
>> 263 select BRCMSTB_L2_IRQ
>> 264 select IRQ_MIPS_CPU
>> 265 select DMA_NONCOHERENT
>> 266 select SYS_SUPPORTS_32BIT_KERNEL
>> 267 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 268 select SYS_SUPPORTS_BIG_ENDIAN
>> 269 select SYS_SUPPORTS_HIGHMEM
>> 270 select SYS_HAS_CPU_BMIPS32_3300
>> 271 select SYS_HAS_CPU_BMIPS4350
>> 272 select SYS_HAS_CPU_BMIPS4380
>> 273 select SYS_HAS_CPU_BMIPS5000
>> 274 select SWAP_IO_SPACE
>> 275 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 276 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 277 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 278 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 279 select HARDIRQS_SW_RESEND
>> 280 select HAVE_PCI
>> 281 select PCI_DRIVERS_GENERIC
>> 282 select FW_CFE
>> 283 help
>> 284 Build a generic DT-based kernel image that boots on select
>> 285 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 286 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 287 must be set appropriately for your board.
>> 288
>> 289 config BCM47XX
>> 290 bool "Broadcom BCM47XX based boards"
>> 291 select BOOT_RAW
>> 292 select CEVT_R4K
>> 293 select CSRC_R4K
>> 294 select DMA_NONCOHERENT
>> 295 select HAVE_PCI
>> 296 select IRQ_MIPS_CPU
>> 297 select SYS_HAS_CPU_MIPS32_R1
>> 298 select NO_EXCEPT_FILL
>> 299 select SYS_SUPPORTS_32BIT_KERNEL
>> 300 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 301 select SYS_SUPPORTS_MIPS16
>> 302 select SYS_SUPPORTS_ZBOOT
>> 303 select SYS_HAS_EARLY_PRINTK
>> 304 select USE_GENERIC_EARLY_PRINTK_8250
>> 305 select GPIOLIB
>> 306 select LEDS_GPIO_REGISTER
>> 307 select BCM47XX_NVRAM
>> 308 select BCM47XX_SPROM
>> 309 select BCM47XX_SSB if !BCM47XX_BCMA
>> 310 help
>> 311 Support for BCM47XX based boards
>> 312
>> 313 config BCM63XX
>> 314 bool "Broadcom BCM63XX based boards"
>> 315 select BOOT_RAW
>> 316 select CEVT_R4K
>> 317 select CSRC_R4K
>> 318 select SYNC_R4K
>> 319 select DMA_NONCOHERENT
>> 320 select IRQ_MIPS_CPU
>> 321 select SYS_SUPPORTS_32BIT_KERNEL
>> 322 select SYS_SUPPORTS_BIG_ENDIAN
>> 323 select SYS_HAS_EARLY_PRINTK
>> 324 select SYS_HAS_CPU_BMIPS32_3300
>> 325 select SYS_HAS_CPU_BMIPS4350
>> 326 select SYS_HAS_CPU_BMIPS4380
>> 327 select SWAP_IO_SPACE
>> 328 select GPIOLIB
>> 329 select MIPS_L1_CACHE_SHIFT_4
>> 330 select HAVE_LEGACY_CLK
>> 331 help
>> 332 Support for BCM63XX based boards
>> 333
>> 334 config MIPS_COBALT
>> 335 bool "Cobalt Server"
>> 336 select CEVT_R4K
>> 337 select CSRC_R4K
>> 338 select CEVT_GT641XX
>> 339 select DMA_NONCOHERENT
>> 340 select FORCE_PCI
>> 341 select I8253
>> 342 select I8259
>> 343 select IRQ_MIPS_CPU
>> 344 select IRQ_GT641XX
>> 345 select PCI_GT64XXX_PCI0
>> 346 select SYS_HAS_CPU_NEVADA
>> 347 select SYS_HAS_EARLY_PRINTK
>> 348 select SYS_SUPPORTS_32BIT_KERNEL
>> 349 select SYS_SUPPORTS_64BIT_KERNEL
>> 350 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 351 select USE_GENERIC_EARLY_PRINTK_8250
>> 352
>> 353 config MACH_DECSTATION
>> 354 bool "DECstations"
>> 355 select BOOT_ELF32
>> 356 select CEVT_DS1287
>> 357 select CEVT_R4K if CPU_R4X00
>> 358 select CSRC_IOASIC
>> 359 select CSRC_R4K if CPU_R4X00
>> 360 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 361 select CPU_R4000_WORKAROUNDS if 64BIT
>> 362 select CPU_R4400_WORKAROUNDS if 64BIT
>> 363 select DMA_NONCOHERENT
>> 364 select NO_IOPORT_MAP
>> 365 select IRQ_MIPS_CPU
>> 366 select SYS_HAS_CPU_R3000
>> 367 select SYS_HAS_CPU_R4X00
>> 368 select SYS_SUPPORTS_32BIT_KERNEL
>> 369 select SYS_SUPPORTS_64BIT_KERNEL
>> 370 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 371 select SYS_SUPPORTS_128HZ
>> 372 select SYS_SUPPORTS_256HZ
>> 373 select SYS_SUPPORTS_1024HZ
>> 374 select MIPS_L1_CACHE_SHIFT_4
>> 375 help
>> 376 This enables support for DEC's MIPS based workstations. For details
>> 377 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 378 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 379
>> 380 If you have one of the following DECstation Models you definitely
>> 381 want to choose R4xx0 for the CPU Type:
>> 382
>> 383 DECstation 5000/50
>> 384 DECstation 5000/150
>> 385 DECstation 5000/260
>> 386 DECsystem 5900/260
>> 387
>> 388 otherwise choose R3000.
>> 389
>> 390 config MACH_JAZZ
>> 391 bool "Jazz family of machines"
>> 392 select ARC_MEMORY
>> 393 select ARC_PROMLIB
>> 394 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 395 select ARCH_MIGHT_HAVE_PC_SERIO
>> 396 select DMA_OPS
>> 397 select FW_ARC
>> 398 select FW_ARC32
>> 399 select ARCH_MAY_HAVE_PC_FDC
>> 400 select CEVT_R4K
>> 401 select CSRC_R4K
>> 402 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 403 select GENERIC_ISA_DMA
>> 404 select HAVE_PCSPKR_PLATFORM
>> 405 select IRQ_MIPS_CPU
>> 406 select I8253
>> 407 select I8259
>> 408 select ISA
>> 409 select SYS_HAS_CPU_R4X00
>> 410 select SYS_SUPPORTS_32BIT_KERNEL
>> 411 select SYS_SUPPORTS_64BIT_KERNEL
>> 412 select SYS_SUPPORTS_100HZ
>> 413 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 414 help
>> 415 This a family of machines based on the MIPS R4030 chipset which was
>> 416 used by several vendors to build RISC/os and Windows NT workstations.
>> 417 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 418 Olivetti M700-10 workstations.
>> 419
>> 420 config MACH_INGENIC_SOC
>> 421 bool "Ingenic SoC based machines"
>> 422 select MIPS_GENERIC
>> 423 select MACH_INGENIC
>> 424 select MACH_GENERIC_CORE
>> 425 select SYS_SUPPORTS_ZBOOT_UART16550
>> 426 select CPU_SUPPORTS_CPUFREQ
>> 427 select MIPS_EXTERNAL_TIMER
>> 428
>> 429 config LANTIQ
>> 430 bool "Lantiq based platforms"
>> 431 select DMA_NONCOHERENT
>> 432 select IRQ_MIPS_CPU
>> 433 select CEVT_R4K
>> 434 select CSRC_R4K
>> 435 select NO_EXCEPT_FILL
>> 436 select SYS_HAS_CPU_MIPS32_R1
>> 437 select SYS_HAS_CPU_MIPS32_R2
>> 438 select SYS_SUPPORTS_BIG_ENDIAN
>> 439 select SYS_SUPPORTS_32BIT_KERNEL
>> 440 select SYS_SUPPORTS_MIPS16
>> 441 select SYS_SUPPORTS_MULTITHREADING
>> 442 select SYS_SUPPORTS_VPE_LOADER
>> 443 select SYS_HAS_EARLY_PRINTK
>> 444 select GPIOLIB
>> 445 select SWAP_IO_SPACE
>> 446 select BOOT_RAW
>> 447 select HAVE_LEGACY_CLK
>> 448 select USE_OF
>> 449 select PINCTRL
>> 450 select PINCTRL_LANTIQ
>> 451 select ARCH_HAS_RESET_CONTROLLER
>> 452 select RESET_CONTROLLER
>> 453
>> 454 config MACH_LOONGSON32
>> 455 bool "Loongson 32-bit family of machines"
>> 456 select SYS_SUPPORTS_ZBOOT
>> 457 help
>> 458 This enables support for the Loongson-1 family of machines.
>> 459
>> 460 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 461 the Institute of Computing Technology (ICT), Chinese Academy of
>> 462 Sciences (CAS).
>> 463
>> 464 config MACH_LOONGSON2EF
>> 465 bool "Loongson-2E/F family of machines"
>> 466 select SYS_SUPPORTS_ZBOOT
>> 467 help
>> 468 This enables the support of early Loongson-2E/F family of machines.
>> 469
>> 470 config MACH_LOONGSON64
>> 471 bool "Loongson 64-bit family of machines"
>> 472 select ARCH_DMA_DEFAULT_COHERENT
>> 473 select ARCH_SPARSEMEM_ENABLE
>> 474 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 475 select ARCH_MIGHT_HAVE_PC_SERIO
>> 476 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 477 select BOOT_ELF32
>> 478 select BOARD_SCACHE
>> 479 select CSRC_R4K
>> 480 select CEVT_R4K
>> 481 select SYNC_R4K
>> 482 select FORCE_PCI
>> 483 select ISA
>> 484 select I8259
>> 485 select IRQ_MIPS_CPU
>> 486 select NO_EXCEPT_FILL
>> 487 select NR_CPUS_DEFAULT_64
>> 488 select USE_GENERIC_EARLY_PRINTK_8250
>> 489 select PCI_DRIVERS_GENERIC
>> 490 select SYS_HAS_CPU_LOONGSON64
>> 491 select SYS_HAS_EARLY_PRINTK
>> 492 select SYS_SUPPORTS_SMP
>> 493 select SYS_SUPPORTS_HOTPLUG_CPU
>> 494 select SYS_SUPPORTS_NUMA
>> 495 select SYS_SUPPORTS_64BIT_KERNEL
>> 496 select SYS_SUPPORTS_HIGHMEM
>> 497 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 498 select SYS_SUPPORTS_ZBOOT
>> 499 select SYS_SUPPORTS_RELOCATABLE
>> 500 select ZONE_DMA32
>> 501 select COMMON_CLK
>> 502 select USE_OF
>> 503 select BUILTIN_DTB
>> 504 select PCI_HOST_GENERIC
>> 505 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 506 help
>> 507 This enables the support of Loongson-2/3 family of machines.
>> 508
>> 509 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 510 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 511 and Loongson-2F which will be removed), developed by the Institute
>> 512 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 513
>> 514 config MIPS_MALTA
>> 515 bool "MIPS Malta board"
>> 516 select ARCH_MAY_HAVE_PC_FDC
>> 517 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 518 select ARCH_MIGHT_HAVE_PC_SERIO
>> 519 select BOOT_ELF32
>> 520 select BOOT_RAW
>> 521 select BUILTIN_DTB
>> 522 select CEVT_R4K
>> 523 select CLKSRC_MIPS_GIC
>> 524 select COMMON_CLK
>> 525 select CSRC_R4K
>> 526 select DMA_NONCOHERENT
>> 527 select GENERIC_ISA_DMA
>> 528 select HAVE_PCSPKR_PLATFORM
>> 529 select HAVE_PCI
>> 530 select I8253
>> 531 select I8259
>> 532 select IRQ_MIPS_CPU
>> 533 select MIPS_BONITO64
>> 534 select MIPS_CPU_SCACHE
>> 535 select MIPS_GIC
>> 536 select MIPS_L1_CACHE_SHIFT_6
>> 537 select MIPS_MSC
>> 538 select PCI_GT64XXX_PCI0
>> 539 select SMP_UP if SMP
>> 540 select SWAP_IO_SPACE
>> 541 select SYS_HAS_CPU_MIPS32_R1
>> 542 select SYS_HAS_CPU_MIPS32_R2
>> 543 select SYS_HAS_CPU_MIPS32_R3_5
>> 544 select SYS_HAS_CPU_MIPS32_R5
>> 545 select SYS_HAS_CPU_MIPS32_R6
>> 546 select SYS_HAS_CPU_MIPS64_R1
>> 547 select SYS_HAS_CPU_MIPS64_R2
>> 548 select SYS_HAS_CPU_MIPS64_R6
>> 549 select SYS_HAS_CPU_NEVADA
>> 550 select SYS_HAS_CPU_RM7000
>> 551 select SYS_SUPPORTS_32BIT_KERNEL
>> 552 select SYS_SUPPORTS_64BIT_KERNEL
>> 553 select SYS_SUPPORTS_BIG_ENDIAN
>> 554 select SYS_SUPPORTS_HIGHMEM
>> 555 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 556 select SYS_SUPPORTS_MICROMIPS
>> 557 select SYS_SUPPORTS_MIPS16
>> 558 select SYS_SUPPORTS_MIPS_CPS
>> 559 select SYS_SUPPORTS_MULTITHREADING
>> 560 select SYS_SUPPORTS_RELOCATABLE
>> 561 select SYS_SUPPORTS_SMARTMIPS
>> 562 select SYS_SUPPORTS_VPE_LOADER
>> 563 select SYS_SUPPORTS_ZBOOT
>> 564 select USE_OF
>> 565 select WAR_ICACHE_REFILLS
>> 566 select ZONE_DMA32 if 64BIT
>> 567 help
>> 568 This enables support for the MIPS Technologies Malta evaluation
>> 569 board.
>> 570
>> 571 config MACH_PIC32
>> 572 bool "Microchip PIC32 Family"
>> 573 help
>> 574 This enables support for the Microchip PIC32 family of platforms.
>> 575
>> 576 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 577 microcontrollers.
>> 578
>> 579 config EYEQ
>> 580 bool "Mobileye EyeQ SoC"
>> 581 select MACH_GENERIC_CORE
>> 582 select ARM_AMBA
>> 583 select PHYSICAL_START_BOOL
>> 584 select ARCH_SPARSEMEM_DEFAULT if 64BIT
>> 585 select BOOT_RAW
>> 586 select BUILTIN_DTB
>> 587 select CEVT_R4K
>> 588 select CLKSRC_MIPS_GIC
>> 589 select COMMON_CLK
>> 590 select CPU_MIPSR2_IRQ_EI
>> 591 select CPU_MIPSR2_IRQ_VI
>> 592 select CSRC_R4K
>> 593 select DMA_NONCOHERENT
>> 594 select HAVE_PCI
>> 595 select IRQ_MIPS_CPU
>> 596 select MIPS_AUTO_PFN_OFFSET
>> 597 select MIPS_CPU_SCACHE
>> 598 select MIPS_GIC
>> 599 select MIPS_L1_CACHE_SHIFT_7
>> 600 select PCI_DRIVERS_GENERIC
>> 601 select SMP_UP if SMP
>> 602 select SWAP_IO_SPACE
>> 603 select SYS_HAS_CPU_MIPS64_R6
>> 604 select SYS_SUPPORTS_64BIT_KERNEL
>> 605 select SYS_SUPPORTS_HIGHMEM
>> 606 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 607 select SYS_SUPPORTS_MIPS_CPS
>> 608 select SYS_SUPPORTS_RELOCATABLE
>> 609 select SYS_SUPPORTS_ZBOOT
>> 610 select UHI_BOOT
>> 611 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 612 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 613 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 614 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 615 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 616 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 617 select USE_OF
>> 618 help
>> 619 Select this to build a kernel supporting EyeQ SoC from Mobileye.
354 620
355 config SBUS <<
356 bool 621 bool
357 622
358 config GENERIC_ISA_DMA !! 623 config MACH_NINTENDO64
359 def_bool y !! 624 bool "Nintendo 64 console"
360 depends on ISA_DMA_API !! 625 select CEVT_R4K
>> 626 select CSRC_R4K
>> 627 select SYS_HAS_CPU_R4300
>> 628 select SYS_SUPPORTS_BIG_ENDIAN
>> 629 select SYS_SUPPORTS_ZBOOT
>> 630 select SYS_SUPPORTS_32BIT_KERNEL
>> 631 select SYS_SUPPORTS_64BIT_KERNEL
>> 632 select DMA_NONCOHERENT
>> 633 select IRQ_MIPS_CPU
>> 634
>> 635 config RALINK
>> 636 bool "Ralink based machines"
>> 637 select CEVT_R4K
>> 638 select COMMON_CLK
>> 639 select CSRC_R4K
>> 640 select BOOT_RAW
>> 641 select DMA_NONCOHERENT
>> 642 select IRQ_MIPS_CPU
>> 643 select USE_OF
>> 644 select SYS_HAS_CPU_MIPS32_R2
>> 645 select SYS_SUPPORTS_32BIT_KERNEL
>> 646 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 647 select SYS_SUPPORTS_MIPS16
>> 648 select SYS_SUPPORTS_ZBOOT
>> 649 select SYS_HAS_EARLY_PRINTK
>> 650 select ARCH_HAS_RESET_CONTROLLER
>> 651 select RESET_CONTROLLER
>> 652
>> 653 config MACH_REALTEK_RTL
>> 654 bool "Realtek RTL838x/RTL839x based machines"
>> 655 select MIPS_GENERIC
>> 656 select MACH_GENERIC_CORE
>> 657 select DMA_NONCOHERENT
>> 658 select IRQ_MIPS_CPU
>> 659 select CSRC_R4K
>> 660 select CEVT_R4K
>> 661 select SYS_HAS_CPU_MIPS32_R1
>> 662 select SYS_HAS_CPU_MIPS32_R2
>> 663 select SYS_SUPPORTS_BIG_ENDIAN
>> 664 select SYS_SUPPORTS_32BIT_KERNEL
>> 665 select SYS_SUPPORTS_MIPS16
>> 666 select SYS_SUPPORTS_MULTITHREADING
>> 667 select SYS_SUPPORTS_VPE_LOADER
>> 668 select BOOT_RAW
>> 669 select PINCTRL
>> 670 select USE_OF
>> 671 select REALTEK_OTTO_TIMER
361 672
362 config GENERIC_CSUM !! 673 config SGI_IP22
363 bool !! 674 bool "SGI IP22 (Indy/Indigo2)"
364 default y if KMSAN || KASAN !! 675 select ARC_MEMORY
>> 676 select ARC_PROMLIB
>> 677 select FW_ARC
>> 678 select FW_ARC32
>> 679 select ARCH_MIGHT_HAVE_PC_SERIO
>> 680 select BOOT_ELF32
>> 681 select CEVT_R4K
>> 682 select CSRC_R4K
>> 683 select DEFAULT_SGI_PARTITION
>> 684 select DMA_NONCOHERENT
>> 685 select HAVE_EISA
>> 686 select I8253
>> 687 select I8259
>> 688 select IP22_CPU_SCACHE
>> 689 select IRQ_MIPS_CPU
>> 690 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 691 select SGI_HAS_I8042
>> 692 select SGI_HAS_INDYDOG
>> 693 select SGI_HAS_HAL2
>> 694 select SGI_HAS_SEEQ
>> 695 select SGI_HAS_WD93
>> 696 select SGI_HAS_ZILOG
>> 697 select SWAP_IO_SPACE
>> 698 select SYS_HAS_CPU_R4X00
>> 699 select SYS_HAS_CPU_R5000
>> 700 select SYS_HAS_EARLY_PRINTK
>> 701 select SYS_SUPPORTS_32BIT_KERNEL
>> 702 select SYS_SUPPORTS_64BIT_KERNEL
>> 703 select SYS_SUPPORTS_BIG_ENDIAN
>> 704 select WAR_R4600_V1_INDEX_ICACHEOP
>> 705 select WAR_R4600_V1_HIT_CACHEOP
>> 706 select WAR_R4600_V2_HIT_CACHEOP
>> 707 select MIPS_L1_CACHE_SHIFT_7
>> 708 help
>> 709 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 710 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 711 that runs on these, say Y here.
>> 712
>> 713 config SGI_IP27
>> 714 bool "SGI IP27 (Origin200/2000)"
>> 715 select ARCH_HAS_PHYS_TO_DMA
>> 716 select ARCH_SPARSEMEM_ENABLE
>> 717 select FW_ARC
>> 718 select FW_ARC64
>> 719 select ARC_CMDLINE_ONLY
>> 720 select BOOT_ELF64
>> 721 select DEFAULT_SGI_PARTITION
>> 722 select FORCE_PCI
>> 723 select SYS_HAS_EARLY_PRINTK
>> 724 select HAVE_PCI
>> 725 select IRQ_MIPS_CPU
>> 726 select IRQ_DOMAIN_HIERARCHY
>> 727 select NR_CPUS_DEFAULT_64
>> 728 select PCI_DRIVERS_GENERIC
>> 729 select PCI_XTALK_BRIDGE
>> 730 select SYS_HAS_CPU_R10000
>> 731 select SYS_SUPPORTS_64BIT_KERNEL
>> 732 select SYS_SUPPORTS_BIG_ENDIAN
>> 733 select SYS_SUPPORTS_NUMA
>> 734 select SYS_SUPPORTS_SMP
>> 735 select WAR_R10000_LLSC
>> 736 select MIPS_L1_CACHE_SHIFT_7
>> 737 select NUMA
>> 738 select HAVE_ARCH_NODEDATA_EXTENSION
>> 739 help
>> 740 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 741 workstations. To compile a Linux kernel that runs on these, say Y
>> 742 here.
>> 743
>> 744 config SGI_IP28
>> 745 bool "SGI IP28 (Indigo2 R10k)"
>> 746 select ARC_MEMORY
>> 747 select ARC_PROMLIB
>> 748 select FW_ARC
>> 749 select FW_ARC64
>> 750 select ARCH_MIGHT_HAVE_PC_SERIO
>> 751 select BOOT_ELF64
>> 752 select CEVT_R4K
>> 753 select CSRC_R4K
>> 754 select DEFAULT_SGI_PARTITION
>> 755 select DMA_NONCOHERENT
>> 756 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 757 select IRQ_MIPS_CPU
>> 758 select HAVE_EISA
>> 759 select I8253
>> 760 select I8259
>> 761 select SGI_HAS_I8042
>> 762 select SGI_HAS_INDYDOG
>> 763 select SGI_HAS_HAL2
>> 764 select SGI_HAS_SEEQ
>> 765 select SGI_HAS_WD93
>> 766 select SGI_HAS_ZILOG
>> 767 select SWAP_IO_SPACE
>> 768 select SYS_HAS_CPU_R10000
>> 769 select SYS_HAS_EARLY_PRINTK
>> 770 select SYS_SUPPORTS_64BIT_KERNEL
>> 771 select SYS_SUPPORTS_BIG_ENDIAN
>> 772 select WAR_R10000_LLSC
>> 773 select MIPS_L1_CACHE_SHIFT_7
>> 774 help
>> 775 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 776 kernel that runs on these, say Y here.
>> 777
>> 778 config SGI_IP30
>> 779 bool "SGI IP30 (Octane/Octane2)"
>> 780 select ARCH_HAS_PHYS_TO_DMA
>> 781 select FW_ARC
>> 782 select FW_ARC64
>> 783 select BOOT_ELF64
>> 784 select CEVT_R4K
>> 785 select CSRC_R4K
>> 786 select FORCE_PCI
>> 787 select SYNC_R4K if SMP
>> 788 select ZONE_DMA32
>> 789 select HAVE_PCI
>> 790 select IRQ_MIPS_CPU
>> 791 select IRQ_DOMAIN_HIERARCHY
>> 792 select PCI_DRIVERS_GENERIC
>> 793 select PCI_XTALK_BRIDGE
>> 794 select SYS_HAS_EARLY_PRINTK
>> 795 select SYS_HAS_CPU_R10000
>> 796 select SYS_SUPPORTS_64BIT_KERNEL
>> 797 select SYS_SUPPORTS_BIG_ENDIAN
>> 798 select SYS_SUPPORTS_SMP
>> 799 select WAR_R10000_LLSC
>> 800 select MIPS_L1_CACHE_SHIFT_7
>> 801 select ARC_MEMORY
>> 802 help
>> 803 These are the SGI Octane and Octane2 graphics workstations. To
>> 804 compile a Linux kernel that runs on these, say Y here.
>> 805
>> 806 config SGI_IP32
>> 807 bool "SGI IP32 (O2)"
>> 808 select ARC_MEMORY
>> 809 select ARC_PROMLIB
>> 810 select ARCH_HAS_PHYS_TO_DMA
>> 811 select FW_ARC
>> 812 select FW_ARC32
>> 813 select BOOT_ELF32
>> 814 select CEVT_R4K
>> 815 select CSRC_R4K
>> 816 select DMA_NONCOHERENT
>> 817 select HAVE_PCI
>> 818 select IRQ_MIPS_CPU
>> 819 select R5000_CPU_SCACHE
>> 820 select RM7000_CPU_SCACHE
>> 821 select SYS_HAS_CPU_R5000
>> 822 select SYS_HAS_CPU_R10000 if BROKEN
>> 823 select SYS_HAS_CPU_RM7000
>> 824 select SYS_HAS_CPU_NEVADA
>> 825 select SYS_SUPPORTS_64BIT_KERNEL
>> 826 select SYS_SUPPORTS_BIG_ENDIAN
>> 827 select WAR_ICACHE_REFILLS
>> 828 help
>> 829 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 830
>> 831 config SIBYTE_CRHONE
>> 832 bool "Sibyte BCM91125C-CRhone"
>> 833 select BOOT_ELF32
>> 834 select SIBYTE_BCM1125
>> 835 select SWAP_IO_SPACE
>> 836 select SYS_HAS_CPU_SB1
>> 837 select SYS_SUPPORTS_BIG_ENDIAN
>> 838 select SYS_SUPPORTS_HIGHMEM
>> 839 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 840
>> 841 config SIBYTE_RHONE
>> 842 bool "Sibyte BCM91125E-Rhone"
>> 843 select BOOT_ELF32
>> 844 select SIBYTE_SB1250
>> 845 select SWAP_IO_SPACE
>> 846 select SYS_HAS_CPU_SB1
>> 847 select SYS_SUPPORTS_BIG_ENDIAN
>> 848 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 849
>> 850 config SIBYTE_SWARM
>> 851 bool "Sibyte BCM91250A-SWARM"
>> 852 select BOOT_ELF32
>> 853 select HAVE_PATA_PLATFORM
>> 854 select SIBYTE_SB1250
>> 855 select SWAP_IO_SPACE
>> 856 select SYS_HAS_CPU_SB1
>> 857 select SYS_SUPPORTS_BIG_ENDIAN
>> 858 select SYS_SUPPORTS_HIGHMEM
>> 859 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 860 select ZONE_DMA32 if 64BIT
>> 861 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 862
>> 863 config SIBYTE_LITTLESUR
>> 864 bool "Sibyte BCM91250C2-LittleSur"
>> 865 select BOOT_ELF32
>> 866 select HAVE_PATA_PLATFORM
>> 867 select SIBYTE_SB1250
>> 868 select SWAP_IO_SPACE
>> 869 select SYS_HAS_CPU_SB1
>> 870 select SYS_SUPPORTS_BIG_ENDIAN
>> 871 select SYS_SUPPORTS_HIGHMEM
>> 872 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 873 select ZONE_DMA32 if 64BIT
>> 874
>> 875 config SIBYTE_SENTOSA
>> 876 bool "Sibyte BCM91250E-Sentosa"
>> 877 select BOOT_ELF32
>> 878 select SIBYTE_SB1250
>> 879 select SWAP_IO_SPACE
>> 880 select SYS_HAS_CPU_SB1
>> 881 select SYS_SUPPORTS_BIG_ENDIAN
>> 882 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 883 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 884
>> 885 config SIBYTE_BIGSUR
>> 886 bool "Sibyte BCM91480B-BigSur"
>> 887 select BOOT_ELF32
>> 888 select NR_CPUS_DEFAULT_4
>> 889 select SIBYTE_BCM1x80
>> 890 select SWAP_IO_SPACE
>> 891 select SYS_HAS_CPU_SB1
>> 892 select SYS_SUPPORTS_BIG_ENDIAN
>> 893 select SYS_SUPPORTS_HIGHMEM
>> 894 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 895 select ZONE_DMA32 if 64BIT
>> 896 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 897
>> 898 config SNI_RM
>> 899 bool "SNI RM200/300/400"
>> 900 select ARC_MEMORY
>> 901 select ARC_PROMLIB
>> 902 select FW_ARC if CPU_LITTLE_ENDIAN
>> 903 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 904 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 905 select ARCH_MAY_HAVE_PC_FDC
>> 906 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 907 select ARCH_MIGHT_HAVE_PC_SERIO
>> 908 select BOOT_ELF32
>> 909 select CEVT_R4K
>> 910 select CSRC_R4K
>> 911 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 912 select DMA_NONCOHERENT
>> 913 select GENERIC_ISA_DMA
>> 914 select HAVE_EISA
>> 915 select HAVE_PCSPKR_PLATFORM
>> 916 select HAVE_PCI
>> 917 select IRQ_MIPS_CPU
>> 918 select I8253
>> 919 select I8259
>> 920 select ISA
>> 921 select MIPS_L1_CACHE_SHIFT_6
>> 922 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 923 select SYS_HAS_CPU_R4X00
>> 924 select SYS_HAS_CPU_R5000
>> 925 select SYS_HAS_CPU_R10000
>> 926 select R5000_CPU_SCACHE
>> 927 select SYS_HAS_EARLY_PRINTK
>> 928 select SYS_SUPPORTS_32BIT_KERNEL
>> 929 select SYS_SUPPORTS_64BIT_KERNEL
>> 930 select SYS_SUPPORTS_BIG_ENDIAN
>> 931 select SYS_SUPPORTS_HIGHMEM
>> 932 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 933 select WAR_R4600_V2_HIT_CACHEOP
>> 934 help
>> 935 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 936 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 937 Technology and now in turn merged with Fujitsu. Say Y here to
>> 938 support this machine type.
>> 939
>> 940 config MACH_TX49XX
>> 941 bool "Toshiba TX49 series based machines"
>> 942 select WAR_TX49XX_ICACHE_INDEX_INV
>> 943
>> 944 config MIKROTIK_RB532
>> 945 bool "Mikrotik RB532 boards"
>> 946 select CEVT_R4K
>> 947 select CSRC_R4K
>> 948 select DMA_NONCOHERENT
>> 949 select HAVE_PCI
>> 950 select IRQ_MIPS_CPU
>> 951 select SYS_HAS_CPU_MIPS32_R1
>> 952 select SYS_SUPPORTS_32BIT_KERNEL
>> 953 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 954 select SWAP_IO_SPACE
>> 955 select BOOT_RAW
>> 956 select GPIOLIB
>> 957 select MIPS_L1_CACHE_SHIFT_4
>> 958 help
>> 959 Support the Mikrotik(tm) RouterBoard 532 series,
>> 960 based on the IDT RC32434 SoC.
365 961
366 config GENERIC_BUG !! 962 config CAVIUM_OCTEON_SOC
367 def_bool y !! 963 bool "Cavium Networks Octeon SoC based boards"
368 depends on BUG !! 964 select CEVT_R4K
369 select GENERIC_BUG_RELATIVE_POINTERS i !! 965 select ARCH_HAS_PHYS_TO_DMA
>> 966 select HAVE_RAPIDIO
>> 967 select PHYS_ADDR_T_64BIT
>> 968 select SYS_SUPPORTS_64BIT_KERNEL
>> 969 select SYS_SUPPORTS_BIG_ENDIAN
>> 970 select EDAC_SUPPORT
>> 971 select EDAC_ATOMIC_SCRUB
>> 972 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 973 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 974 select SYS_HAS_EARLY_PRINTK
>> 975 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 976 select HAVE_PCI
>> 977 select HAVE_PLAT_DELAY
>> 978 select HAVE_PLAT_FW_INIT_CMDLINE
>> 979 select HAVE_PLAT_MEMCPY
>> 980 select ZONE_DMA32
>> 981 select GPIOLIB
>> 982 select USE_OF
>> 983 select ARCH_SPARSEMEM_ENABLE
>> 984 select SYS_SUPPORTS_SMP
>> 985 select NR_CPUS_DEFAULT_64
>> 986 select MIPS_NR_CPU_NR_MAP_1024
>> 987 select BUILTIN_DTB
>> 988 select MTD
>> 989 select MTD_COMPLEX_MAPPINGS
>> 990 select SWIOTLB
>> 991 select SYS_SUPPORTS_RELOCATABLE
>> 992 help
>> 993 This option supports all of the Octeon reference boards from Cavium
>> 994 Networks. It builds a kernel that dynamically determines the Octeon
>> 995 CPU type and supports all known board reference implementations.
>> 996 Some of the supported boards are:
>> 997 EBT3000
>> 998 EBH3000
>> 999 EBH3100
>> 1000 Thunder
>> 1001 Kodama
>> 1002 Hikari
>> 1003 Say Y here for most Octeon reference boards.
370 1004
371 config GENERIC_BUG_RELATIVE_POINTERS !! 1005 endchoice
372 bool <<
373 1006
374 config ARCH_MAY_HAVE_PC_FDC !! 1007 config FIT_IMAGE_FDT_EPM5
375 def_bool y !! 1008 bool "Include FDT for Mobileye EyeQ5 development platforms"
376 depends on ISA_DMA_API !! 1009 depends on MACH_EYEQ5
>> 1010 default n
>> 1011 help
>> 1012 Enable this to include the FDT for the EyeQ5 development platforms
>> 1013 from Mobileye in the FIT kernel image.
>> 1014 This requires u-boot on the platform.
>> 1015
>> 1016 source "arch/mips/alchemy/Kconfig"
>> 1017 source "arch/mips/ath25/Kconfig"
>> 1018 source "arch/mips/ath79/Kconfig"
>> 1019 source "arch/mips/bcm47xx/Kconfig"
>> 1020 source "arch/mips/bcm63xx/Kconfig"
>> 1021 source "arch/mips/bmips/Kconfig"
>> 1022 source "arch/mips/generic/Kconfig"
>> 1023 source "arch/mips/ingenic/Kconfig"
>> 1024 source "arch/mips/jazz/Kconfig"
>> 1025 source "arch/mips/lantiq/Kconfig"
>> 1026 source "arch/mips/mobileye/Kconfig"
>> 1027 source "arch/mips/pic32/Kconfig"
>> 1028 source "arch/mips/ralink/Kconfig"
>> 1029 source "arch/mips/sgi-ip27/Kconfig"
>> 1030 source "arch/mips/sibyte/Kconfig"
>> 1031 source "arch/mips/txx9/Kconfig"
>> 1032 source "arch/mips/cavium-octeon/Kconfig"
>> 1033 source "arch/mips/loongson2ef/Kconfig"
>> 1034 source "arch/mips/loongson32/Kconfig"
>> 1035 source "arch/mips/loongson64/Kconfig"
>> 1036
>> 1037 endmenu
>> 1038
>> 1039 config GENERIC_HWEIGHT
>> 1040 bool
>> 1041 default y
377 1042
378 config GENERIC_CALIBRATE_DELAY 1043 config GENERIC_CALIBRATE_DELAY
379 def_bool y !! 1044 bool
>> 1045 default y
380 1046
381 config ARCH_HAS_CPU_RELAX !! 1047 config SCHED_OMIT_FRAME_POINTER
382 def_bool y !! 1048 bool
>> 1049 default y
383 1050
384 config ARCH_HIBERNATION_POSSIBLE !! 1051 #
385 def_bool y !! 1052 # Select some configuration options automatically based on user selections.
>> 1053 #
>> 1054 config FW_ARC
>> 1055 bool
386 1056
387 config ARCH_SUSPEND_POSSIBLE !! 1057 config ARCH_MAY_HAVE_PC_FDC
388 def_bool y !! 1058 bool
389 1059
390 config AUDIT_ARCH !! 1060 config BOOT_RAW
391 def_bool y if X86_64 !! 1061 bool
392 1062
393 config KASAN_SHADOW_OFFSET !! 1063 config CEVT_BCM1480
394 hex !! 1064 bool
395 depends on KASAN <<
396 default 0xdffffc0000000000 <<
397 1065
398 config HAVE_INTEL_TXT !! 1066 config CEVT_DS1287
399 def_bool y !! 1067 bool
400 depends on INTEL_IOMMU && ACPI <<
401 1068
402 config X86_64_SMP !! 1069 config CEVT_GT641XX
403 def_bool y !! 1070 bool
404 depends on X86_64 && SMP <<
405 1071
406 config ARCH_SUPPORTS_UPROBES !! 1072 config CEVT_R4K
407 def_bool y !! 1073 bool
408 1074
409 config FIX_EARLYCON_MEM !! 1075 config CEVT_SB1250
410 def_bool y !! 1076 bool
411 1077
412 config DYNAMIC_PHYSICAL_MASK !! 1078 config CEVT_TXX9
413 bool 1079 bool
414 1080
415 config PGTABLE_LEVELS !! 1081 config CSRC_BCM1480
416 int !! 1082 bool
417 default 5 if X86_5LEVEL <<
418 default 4 if X86_64 <<
419 default 3 if X86_PAE <<
420 default 2 <<
421 1083
422 config CC_HAS_SANE_STACKPROTECTOR !! 1084 config CSRC_IOASIC
423 bool 1085 bool
424 default $(success,$(srctree)/scripts/g <<
425 default $(success,$(srctree)/scripts/g <<
426 help <<
427 We have to make sure stack protector <<
428 the compiler produces broken code or <<
429 the segment on 32-bit kernels. <<
430 1086
431 menu "Processor type and features" !! 1087 config CSRC_R4K
>> 1088 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1089 select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT
>> 1090 bool
432 1091
433 config SMP !! 1092 config CSRC_SB1250
434 bool "Symmetric multi-processing suppo !! 1093 bool
435 help <<
436 This enables support for systems wit <<
437 a system with only one CPU, say N. I <<
438 than one CPU, say Y. <<
439 1094
440 If you say N here, the kernel will r !! 1095 config MIPS_CLOCK_VSYSCALL
441 machines, but will use only one CPU !! 1096 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
442 you say Y here, the kernel will run <<
443 uniprocessor machines. On a uniproce <<
444 will run faster if you say N here. <<
445 1097
446 Note that if you say Y here and choo !! 1098 config GPIO_TXX9
447 "Pentium" under "Processor family", !! 1099 select GPIOLIB
448 architectures. Similarly, multiproce !! 1100 bool
449 architecture may not work on all Pen <<
450 1101
451 People using multiprocessor machines !! 1102 config FW_CFE
452 Y to "Enhanced Real Time Clock Suppo !! 1103 bool
453 Management" code will be disabled if <<
454 1104
455 See also <file:Documentation/arch/x8 !! 1105 config ARCH_SUPPORTS_UPROBES
456 <file:Documentation/admin-guide/lock !! 1106 def_bool y
457 <http://www.tldp.org/docs.html#howto <<
458 1107
459 If you don't know what to do here, s !! 1108 config DMA_NONCOHERENT
>> 1109 bool
>> 1110 #
>> 1111 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1112 # Attribute bits. It is believed that the uncached access through
>> 1113 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1114 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1115 # significant advantages.
>> 1116 #
>> 1117 select ARCH_HAS_SETUP_DMA_OPS
>> 1118 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1119 select ARCH_HAS_DMA_PREP_COHERENT
>> 1120 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 1121 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1122 select ARCH_HAS_DMA_SET_UNCACHED
>> 1123 select DMA_NONCOHERENT_MMAP
>> 1124 select NEED_DMA_MAP_STATE
460 1125
461 config X86_X2APIC !! 1126 config SYS_HAS_EARLY_PRINTK
462 bool "Support x2apic" !! 1127 bool
463 depends on X86_LOCAL_APIC && X86_64 && <<
464 help <<
465 This enables x2apic support on CPUs <<
466 <<
467 This allows 32-bit apic IDs (so it c <<
468 and accesses the local apic via MSRs <<
469 <<
470 Some Intel systems circa 2022 and la <<
471 and can not fall back to the legacy <<
472 enabled in the BIOS. They will boot <<
473 without enabling this option. <<
474 1128
475 If you don't know what to do here, s !! 1129 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1130 bool
476 1131
477 config X86_POSTED_MSI !! 1132 config MIPS_BONITO64
478 bool "Enable MSI and MSI-x delivery by !! 1133 bool
479 depends on X86_64 && IRQ_REMAP <<
480 help <<
481 This enables MSIs that are under int <<
482 posted interrupts to the host kernel <<
483 potentially be improved by coalescin <<
484 frequency bursts. <<
485 1134
486 If you don't know what to do here, s !! 1135 config MIPS_MSC
>> 1136 bool
487 1137
488 config X86_MPPARSE !! 1138 config SYNC_R4K
489 bool "Enable MPS table" if ACPI !! 1139 bool
490 default y <<
491 depends on X86_LOCAL_APIC <<
492 help <<
493 For old smp systems that do not have <<
494 (esp with 64bit cpus) with acpi supp <<
495 1140
496 config X86_CPU_RESCTRL !! 1141 config NO_IOPORT_MAP
497 bool "x86 CPU resource control support !! 1142 def_bool n
498 depends on X86 && (CPU_SUP_INTEL || CP !! 1143
499 select KERNFS !! 1144 config GENERIC_CSUM
500 select PROC_CPU_RESCTRL if PRO !! 1145 def_bool CPU_NO_LOAD_STORE_LR
501 help !! 1146
502 Enable x86 CPU resource control supp !! 1147 config GENERIC_ISA_DMA
>> 1148 bool
>> 1149 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1150 select ISA_DMA_API
503 1151
504 Provide support for the allocation a !! 1152 config GENERIC_ISA_DMA_SUPPORT_BROKEN
505 usage by the CPU. !! 1153 bool
>> 1154 select GENERIC_ISA_DMA
506 1155
507 Intel calls this Intel Resource Dire !! 1156 config HAVE_PLAT_DELAY
508 (Intel(R) RDT). More information abo !! 1157 bool
509 Intel x86 Architecture Software Deve <<
510 1158
511 AMD calls this AMD Platform Quality !! 1159 config HAVE_PLAT_FW_INIT_CMDLINE
512 More information about AMD QoS can b !! 1160 bool
513 Platform Quality of Service Extensio <<
514 1161
515 Say N if unsure. !! 1162 config HAVE_PLAT_MEMCPY
>> 1163 bool
516 1164
517 config X86_FRED !! 1165 config ISA_DMA_API
518 bool "Flexible Return and Event Delive !! 1166 bool
519 depends on X86_64 <<
520 help <<
521 When enabled, try to use Flexible Re <<
522 instead of the legacy SYSCALL/SYSENT <<
523 ring transitions and exception/inter <<
524 system supports it. <<
525 1167
526 config X86_BIGSMP !! 1168 config SYS_SUPPORTS_RELOCATABLE
527 bool "Support for big SMP systems with !! 1169 bool
528 depends on SMP && X86_32 <<
529 help 1170 help
530 This option is needed for the system !! 1171 Selected if the platform supports relocating the kernel.
>> 1172 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1173 to allow access to command line and entropy sources.
531 1174
532 config X86_EXTENDED_PLATFORM !! 1175 #
533 bool "Support for extended (non-PC) x8 !! 1176 # Endianness selection. Sufficiently obscure so many users don't know what to
534 default y !! 1177 # answer,so we try hard to limit the available choices. Also the use of a
535 help !! 1178 # choice statement should be more obvious to the user.
536 If you disable this option then the !! 1179 #
537 standard PC platforms. (which covers !! 1180 choice
538 systems out there.) !! 1181 prompt "Endianness selection"
539 <<
540 If you enable this option then you'l <<
541 for the following non-PC x86 platfor <<
542 CONFIG_64BIT. <<
543 <<
544 32-bit platforms (CONFIG_64BIT=n): <<
545 Goldfish (Android emulator) <<
546 AMD Elan <<
547 RDC R-321x SoC <<
548 SGI 320/540 (Visual Workstatio <<
549 STA2X11-based (e.g. Northville <<
550 Moorestown MID devices <<
551 <<
552 64-bit platforms (CONFIG_64BIT=y): <<
553 Numascale NumaChip <<
554 ScaleMP vSMP <<
555 SGI Ultraviolet <<
556 <<
557 If you have one of these systems, or <<
558 generic distribution kernel, say Y h <<
559 <<
560 # This is an alphabetically sorted list of 64 <<
561 # Please maintain the alphabetic order if and <<
562 config X86_NUMACHIP <<
563 bool "Numascale NumaChip" <<
564 depends on X86_64 <<
565 depends on X86_EXTENDED_PLATFORM <<
566 depends on NUMA <<
567 depends on SMP <<
568 depends on X86_X2APIC <<
569 depends on PCI_MMCONFIG <<
570 help <<
571 Adds support for Numascale NumaChip <<
572 enable more than ~168 cores. <<
573 If you don't have one of these, you <<
574 <<
575 config X86_VSMP <<
576 bool "ScaleMP vSMP" <<
577 select HYPERVISOR_GUEST <<
578 select PARAVIRT <<
579 depends on X86_64 && PCI <<
580 depends on X86_EXTENDED_PLATFORM <<
581 depends on SMP <<
582 help <<
583 Support for ScaleMP vSMP systems. S <<
584 supposed to run on these EM64T-based <<
585 if you have one of these machines. <<
586 <<
587 config X86_UV <<
588 bool "SGI Ultraviolet" <<
589 depends on X86_64 <<
590 depends on X86_EXTENDED_PLATFORM <<
591 depends on NUMA <<
592 depends on EFI <<
593 depends on KEXEC_CORE <<
594 depends on X86_X2APIC <<
595 depends on PCI <<
596 help <<
597 This option is needed in order to su <<
598 If you don't have one of these, you <<
599 <<
600 # Following is an alphabetically sorted list o <<
601 # Please maintain the alphabetic order if and <<
602 <<
603 config X86_GOLDFISH <<
604 bool "Goldfish (Virtual Platform)" <<
605 depends on X86_EXTENDED_PLATFORM <<
606 help <<
607 Enable support for the Goldfish virt <<
608 for Android development. Unless you <<
609 Goldfish emulator say N here. <<
610 <<
611 config X86_INTEL_CE <<
612 bool "CE4100 TV platform" <<
613 depends on PCI <<
614 depends on PCI_GODIRECT <<
615 depends on X86_IO_APIC <<
616 depends on X86_32 <<
617 depends on X86_EXTENDED_PLATFORM <<
618 select X86_REBOOTFIXUPS <<
619 select OF <<
620 select OF_EARLY_FLATTREE <<
621 help <<
622 Select for the Intel CE media proces <<
623 This option compiles in support for <<
624 boxes and media devices. <<
625 <<
626 config X86_INTEL_MID <<
627 bool "Intel MID platform support" <<
628 depends on X86_EXTENDED_PLATFORM <<
629 depends on X86_PLATFORM_DEVICES <<
630 depends on PCI <<
631 depends on X86_64 || (PCI_GOANY && X86 <<
632 depends on X86_IO_APIC <<
633 select I2C <<
634 select DW_APB_TIMER <<
635 select INTEL_SCU_PCI <<
636 help <<
637 Select to build a kernel capable of <<
638 Internet Device) platform systems wh <<
639 interfaces. If you are building for <<
640 <<
641 Intel MID platforms are based on an <<
642 consume less power than most of the <<
643 <<
644 config X86_INTEL_QUARK <<
645 bool "Intel Quark platform support" <<
646 depends on X86_32 <<
647 depends on X86_EXTENDED_PLATFORM <<
648 depends on X86_PLATFORM_DEVICES <<
649 depends on X86_TSC <<
650 depends on PCI <<
651 depends on PCI_GOANY <<
652 depends on X86_IO_APIC <<
653 select IOSF_MBI <<
654 select INTEL_IMR <<
655 select COMMON_CLK <<
656 help <<
657 Select to include support for Quark <<
658 Say Y here if you have a Quark based <<
659 compatible Intel Galileo. <<
660 <<
661 config X86_INTEL_LPSS <<
662 bool "Intel Low Power Subsystem Suppor <<
663 depends on X86 && ACPI && PCI <<
664 select COMMON_CLK <<
665 select PINCTRL <<
666 select IOSF_MBI <<
667 help <<
668 Select to build support for Intel Lo <<
669 found on Intel Lynxpoint PCH. Select <<
670 things like clock tree (common clock <<
671 which are needed by the LPSS periphe <<
672 <<
673 config X86_AMD_PLATFORM_DEVICE <<
674 bool "AMD ACPI2Platform devices suppor <<
675 depends on ACPI <<
676 select COMMON_CLK <<
677 select PINCTRL <<
678 help 1182 help
679 Select to interpret AMD specific ACP !! 1183 Some MIPS machines can be configured for either little or big endian
680 such as I2C, UART, GPIO found on AMD !! 1184 byte order. These modes require different kernels and a different
681 I2C and UART depend on COMMON_CLK to !! 1185 Linux distribution. In general there is one preferred byteorder for a
682 implemented under PINCTRL subsystem. !! 1186 particular system but some systems are just as commonly used in the
683 !! 1187 one or the other endianness.
684 config IOSF_MBI !! 1188
685 tristate "Intel SoC IOSF Sideband supp !! 1189 config CPU_BIG_ENDIAN
686 depends on PCI !! 1190 bool "Big endian"
687 help !! 1191 depends on SYS_SUPPORTS_BIG_ENDIAN
688 This option enables sideband registe !! 1192
689 platforms. On these platforms the IO !! 1193 config CPU_LITTLE_ENDIAN
690 MSR's for some register accesses, mo !! 1194 bool "Little endian"
691 and power. Drivers may query the ava !! 1195 depends on SYS_SUPPORTS_LITTLE_ENDIAN
692 determine if they need the sideband <<
693 platforms. The sideband is available <<
694 This list is not meant to be exclusi <<
695 - BayTrail <<
696 - Braswell <<
697 - Quark <<
698 <<
699 You should say Y if you are running <<
700 <<
701 config IOSF_MBI_DEBUG <<
702 bool "Enable IOSF sideband access thro <<
703 depends on IOSF_MBI && DEBUG_FS <<
704 help <<
705 Select this option to expose the IOS <<
706 MDR, MCRX) through debugfs to write <<
707 different units on the SoC. This is <<
708 state information for debug and anal <<
709 mechanism, users of this option woul <<
710 device they want to access. <<
711 <<
712 If you don't require the option or a <<
713 <<
714 config X86_RDC321X <<
715 bool "RDC R-321x SoC" <<
716 depends on X86_32 <<
717 depends on X86_EXTENDED_PLATFORM <<
718 select M486 <<
719 select X86_REBOOTFIXUPS <<
720 help <<
721 This option is needed for RDC R-321x <<
722 as R-8610-(G). <<
723 If you don't have one of these chips <<
724 <<
725 config X86_32_NON_STANDARD <<
726 bool "Support non-standard 32-bit SMP <<
727 depends on X86_32 && SMP <<
728 depends on X86_EXTENDED_PLATFORM <<
729 help <<
730 This option compiles in the bigsmp a <<
731 subarchitectures. It is intended fo <<
732 kernel. If you select them all, kern <<
733 one and will fallback to default. <<
734 1196
735 # Alphabetically sorted list of Non standard 3 !! 1197 endchoice
736 1198
737 config X86_SUPPORTS_MEMORY_FAILURE !! 1199 config EXPORT_UASM
738 def_bool y !! 1200 bool
739 # MCE code calls memory_failure(): <<
740 depends on X86_MCE <<
741 # On 32-bit this adds too big of NODES <<
742 # On 32-bit SPARSEMEM adds too big of <<
743 depends on X86_64 || !SPARSEMEM <<
744 select ARCH_SUPPORTS_MEMORY_FAILURE <<
745 <<
746 config STA2X11 <<
747 bool "STA2X11 Companion Chip Support" <<
748 depends on X86_32_NON_STANDARD && PCI <<
749 select SWIOTLB <<
750 select MFD_STA2X11 <<
751 select GPIOLIB <<
752 help <<
753 This adds support for boards based o <<
754 a.k.a. "ConneXt". The chip is used i <<
755 PC chipset, so all "standard" periph <<
756 option is selected the kernel will s <<
757 standard PC machines. <<
758 <<
759 config X86_32_IRIS <<
760 tristate "Eurobraille/Iris poweroff mo <<
761 depends on X86_32 <<
762 help <<
763 The Iris machines from EuroBraille d <<
764 to shut themselves down properly. A <<
765 needed to do so, which is what this <<
766 kernel shutdown. <<
767 1201
768 This is only for Iris machines from !! 1202 config SYS_SUPPORTS_APM_EMULATION
>> 1203 bool
769 1204
770 If unused, say N. !! 1205 config SYS_SUPPORTS_BIG_ENDIAN
>> 1206 bool
771 1207
772 config SCHED_OMIT_FRAME_POINTER !! 1208 config SYS_SUPPORTS_LITTLE_ENDIAN
773 def_bool y !! 1209 bool
774 prompt "Single-depth WCHAN output" <<
775 depends on X86 <<
776 help <<
777 Calculate simpler /proc/<PID>/wchan <<
778 is disabled then wchan values will r <<
779 caller function. This provides more <<
780 at the expense of slightly more sche <<
781 1210
782 If in doubt, say "Y". !! 1211 config MIPS_HUGE_TLB_SUPPORT
>> 1212 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
783 1213
784 menuconfig HYPERVISOR_GUEST !! 1214 config IRQ_TXX9
785 bool "Linux guest support" !! 1215 bool
786 help <<
787 Say Y here to enable options for run <<
788 visors. This option enables basic hy <<
789 setup. <<
790 1216
791 If you say N, all options in this su !! 1217 config IRQ_GT641XX
792 disabled, and Linux guest support wo !! 1218 bool
793 1219
794 if HYPERVISOR_GUEST !! 1220 config PCI_GT64XXX_PCI0
>> 1221 bool
795 1222
796 config PARAVIRT !! 1223 config PCI_XTALK_BRIDGE
797 bool "Enable paravirtualization code" !! 1224 bool
798 depends on HAVE_STATIC_CALL <<
799 help <<
800 This changes the kernel so it can mo <<
801 under a hypervisor, potentially impr <<
802 over full virtualization. However, <<
803 the kernel is theoretically slower a <<
804 1225
805 config PARAVIRT_XXL !! 1226 config NO_EXCEPT_FILL
806 bool 1227 bool
807 1228
808 config PARAVIRT_DEBUG !! 1229 config MIPS_SPRAM
809 bool "paravirt-ops debugging" !! 1230 bool
810 depends on PARAVIRT && DEBUG_KERNEL <<
811 help <<
812 Enable to debug paravirt_ops interna <<
813 a paravirt_op is missing when it is <<
814 1231
815 config PARAVIRT_SPINLOCKS !! 1232 config SWAP_IO_SPACE
816 bool "Paravirtualization layer for spi !! 1233 bool
817 depends on PARAVIRT && SMP <<
818 help <<
819 Paravirtualized spinlocks allow a pv <<
820 spinlock implementation with somethi <<
821 (for example, block the virtual CPU <<
822 1234
823 It has a minimal impact on native ke !! 1235 config SGI_HAS_INDYDOG
824 benefit on paravirtualized KVM / Xen !! 1236 bool
825 1237
826 If you are unsure how to answer this !! 1238 config SGI_HAS_HAL2
>> 1239 bool
827 1240
828 config X86_HV_CALLBACK_VECTOR !! 1241 config SGI_HAS_SEEQ
829 def_bool n !! 1242 bool
830 1243
831 source "arch/x86/xen/Kconfig" !! 1244 config SGI_HAS_WD93
>> 1245 bool
832 1246
833 config KVM_GUEST !! 1247 config SGI_HAS_ZILOG
834 bool "KVM Guest support (including kvm !! 1248 bool
835 depends on PARAVIRT <<
836 select PARAVIRT_CLOCK <<
837 select ARCH_CPUIDLE_HALTPOLL <<
838 select X86_HV_CALLBACK_VECTOR <<
839 default y <<
840 help <<
841 This option enables various optimiza <<
842 hypervisor. It includes a paravirtua <<
843 of relying on a PIT (or probably oth <<
844 underlying device model, the host pr <<
845 timing infrastructure such as time o <<
846 1249
847 config ARCH_CPUIDLE_HALTPOLL !! 1250 config SGI_HAS_I8042
848 def_bool n !! 1251 bool
849 prompt "Disable host haltpoll when loa <<
850 help <<
851 If virtualized under KVM, disable ho <<
852 1252
853 config PVH !! 1253 config DEFAULT_SGI_PARTITION
854 bool "Support for running PVH guests" !! 1254 bool
855 help <<
856 This option enables the PVH entry po <<
857 as specified in the x86/HVM direct b <<
858 <<
859 config PARAVIRT_TIME_ACCOUNTING <<
860 bool "Paravirtual steal time accountin <<
861 depends on PARAVIRT <<
862 help <<
863 Select this option to enable fine gr <<
864 accounting. Time spent executing oth <<
865 the current vCPU is discounted from <<
866 that, there can be a small performan <<
867 <<
868 If in doubt, say N here. <<
869 <<
870 config PARAVIRT_CLOCK <<
871 bool <<
872 <<
873 config JAILHOUSE_GUEST <<
874 bool "Jailhouse non-root cell support" <<
875 depends on X86_64 && PCI <<
876 select X86_PM_TIMER <<
877 help <<
878 This option allows to run Linux as g <<
879 cell. You can leave this option disa <<
880 Jailhouse and run Linux afterwards i <<
881 <<
882 config ACRN_GUEST <<
883 bool "ACRN Guest support" <<
884 depends on X86_64 <<
885 select X86_HV_CALLBACK_VECTOR <<
886 help <<
887 This option allows to run Linux as g <<
888 a flexible, lightweight reference op <<
889 real-time and safety-criticality in <<
890 IOT with small footprint and real-ti <<
891 found in https://projectacrn.org/. <<
892 <<
893 config INTEL_TDX_GUEST <<
894 bool "Intel TDX (Trust Domain Extensio <<
895 depends on X86_64 && CPU_SUP_INTEL <<
896 depends on X86_X2APIC <<
897 depends on EFI_STUB <<
898 select ARCH_HAS_CC_PLATFORM <<
899 select X86_MEM_ENCRYPT <<
900 select X86_MCE <<
901 select UNACCEPTED_MEMORY <<
902 help <<
903 Support running as a guest under Int <<
904 the guest kernel can not boot or run <<
905 TDX includes memory encryption and i <<
906 which protect the confidentiality an <<
907 memory contents and CPU state. TDX g <<
908 some attacks from the VMM. <<
909 <<
910 endif # HYPERVISOR_GUEST <<
911 <<
912 source "arch/x86/Kconfig.cpu" <<
913 <<
914 config HPET_TIMER <<
915 def_bool X86_64 <<
916 prompt "HPET Timer Support" if X86_32 <<
917 help <<
918 Use the IA-PC HPET (High Precision E <<
919 time in preference to the PIT and RT <<
920 present. <<
921 HPET is the next generation timer re <<
922 The HPET provides a stable time base <<
923 systems, unlike the TSC, but it is m <<
924 as it is off-chip. The interface us <<
925 in the HPET spec, revision 1. <<
926 <<
927 You can safely choose Y here. Howev <<
928 activated if the platform and the BI <<
929 Otherwise the 8254 will be used for <<
930 1255
931 Choose N to continue using the legac !! 1256 config FW_ARC32
>> 1257 bool
932 1258
933 config HPET_EMULATE_RTC !! 1259 config FW_SNIPROM
934 def_bool y !! 1260 bool
935 depends on HPET_TIMER && (RTC_DRV_CMOS <<
936 1261
937 # Mark as expert because too many people got i !! 1262 config BOOT_ELF32
938 # The code disables itself when not needed. !! 1263 bool
939 config DMI <<
940 default y <<
941 select DMI_SCAN_MACHINE_NON_EFI_FALLBA <<
942 bool "Enable DMI scanning" if EXPERT <<
943 help <<
944 Enabled scanning of DMI to identify <<
945 here unless you have verified that y <<
946 affected by entries in the DMI black <<
947 BIOS code. <<
948 1264
949 config GART_IOMMU !! 1265 config MIPS_L1_CACHE_SHIFT_4
950 bool "Old AMD GART IOMMU support" !! 1266 bool
951 select IOMMU_HELPER <<
952 select SWIOTLB <<
953 depends on X86_64 && PCI && AMD_NB <<
954 help <<
955 Provides a driver for older AMD Athl <<
956 GART based hardware IOMMUs. <<
957 1267
958 The GART supports full DMA access fo !! 1268 config MIPS_L1_CACHE_SHIFT_5
959 limitations, on systems with more th !! 1269 bool
960 for USB, sound, many IDE/SATA chipse <<
961 1270
962 Newer systems typically have a moder !! 1271 config MIPS_L1_CACHE_SHIFT_6
963 the CONFIG_AMD_IOMMU=y config option !! 1272 bool
964 1273
965 In normal configurations this driver !! 1274 config MIPS_L1_CACHE_SHIFT_7
966 there's more than 3 GB of memory and !! 1275 bool
967 32-bit limited device. <<
968 1276
969 If unsure, say Y. !! 1277 config MIPS_L1_CACHE_SHIFT
>> 1278 int
>> 1279 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1280 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1281 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1282 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1283 default "5"
970 1284
971 config BOOT_VESA_SUPPORT !! 1285 config ARC_CMDLINE_ONLY
972 bool 1286 bool
973 help <<
974 If true, at least one selected frame <<
975 of VESA video modes set at an early <<
976 1287
977 config MAXSMP !! 1288 config ARC_CONSOLE
978 bool "Enable Maximum number of SMP Pro !! 1289 bool "ARC console support"
979 depends on X86_64 && SMP && DEBUG_KERN !! 1290 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
980 select CPUMASK_OFFSTACK <<
981 help <<
982 Enable maximum number of CPUS and NU <<
983 If unsure, say N. <<
984 1291
985 # !! 1292 config ARC_MEMORY
986 # The maximum number of CPUs supported: !! 1293 bool
987 # <<
988 # The main config value is NR_CPUS, which defa <<
989 # and which can be configured interactively in <<
990 # [NR_CPUS_RANGE_BEGIN ... NR_CPUS_RANGE_END] <<
991 # <<
992 # The ranges are different on 32-bit and 64-bi <<
993 # hardware capabilities and scalability featur <<
994 # <<
995 # ( If MAXSMP is enabled we just use the highe <<
996 # interactive configuration. ) <<
997 # <<
998 1294
999 config NR_CPUS_RANGE_BEGIN !! 1295 config ARC_PROMLIB
1000 int !! 1296 bool
1001 default NR_CPUS_RANGE_END if MAXSMP <<
1002 default 1 if !SMP <<
1003 default 2 <<
1004 1297
1005 config NR_CPUS_RANGE_END !! 1298 config FW_ARC64
1006 int !! 1299 bool
1007 depends on X86_32 <<
1008 default 64 if SMP && X86_BIGSMP <<
1009 default 8 if SMP && !X86_BIGSMP <<
1010 default 1 if !SMP <<
1011 1300
1012 config NR_CPUS_RANGE_END !! 1301 config BOOT_ELF64
1013 int !! 1302 bool
1014 depends on X86_64 <<
1015 default 8192 if SMP && CPUMASK_OFFST <<
1016 default 512 if SMP && !CPUMASK_OFFS <<
1017 default 1 if !SMP <<
1018 1303
1019 config NR_CPUS_DEFAULT !! 1304 menu "CPU selection"
1020 int <<
1021 depends on X86_32 <<
1022 default 32 if X86_BIGSMP <<
1023 default 8 if SMP <<
1024 default 1 if !SMP <<
1025 1305
1026 config NR_CPUS_DEFAULT !! 1306 choice
1027 int !! 1307 prompt "CPU type"
1028 depends on X86_64 !! 1308 default CPU_R4X00
1029 default 8192 if MAXSMP <<
1030 default 64 if SMP <<
1031 default 1 if !SMP <<
1032 1309
1033 config NR_CPUS !! 1310 config CPU_LOONGSON64
1034 int "Maximum number of CPUs" if SMP & !! 1311 bool "Loongson 64-bit CPU"
1035 range NR_CPUS_RANGE_BEGIN NR_CPUS_RAN !! 1312 depends on SYS_HAS_CPU_LOONGSON64
1036 default NR_CPUS_DEFAULT !! 1313 select ARCH_HAS_PHYS_TO_DMA
>> 1314 select CPU_MIPSR2
>> 1315 select CPU_HAS_PREFETCH
>> 1316 select CPU_SUPPORTS_64BIT_KERNEL
>> 1317 select CPU_SUPPORTS_HIGHMEM
>> 1318 select CPU_SUPPORTS_HUGEPAGES
>> 1319 select CPU_SUPPORTS_MSA
>> 1320 select CPU_SUPPORTS_VZ
>> 1321 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1322 select CPU_MIPSR2_IRQ_VI
>> 1323 select DMA_NONCOHERENT
>> 1324 select WEAK_ORDERING
>> 1325 select WEAK_REORDERING_BEYOND_LLSC
>> 1326 select MIPS_ASID_BITS_VARIABLE
>> 1327 select MIPS_PGD_C0_CONTEXT
>> 1328 select MIPS_L1_CACHE_SHIFT_6
>> 1329 select MIPS_FP_SUPPORT
>> 1330 select GPIOLIB
>> 1331 select SWIOTLB
1037 help 1332 help
1038 This allows you to specify the maxi !! 1333 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1039 kernel will support. If CPUMASK_OF !! 1334 cores implements the MIPS64R2 instruction set with many extensions,
1040 supported value is 8192, otherwise !! 1335 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1041 minimum value which makes sense is !! 1336 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1337 Loongson-2E/2F is not covered here and will be removed in future.
>> 1338
>> 1339 config CPU_LOONGSON2E
>> 1340 bool "Loongson 2E"
>> 1341 depends on SYS_HAS_CPU_LOONGSON2E
>> 1342 select CPU_LOONGSON2EF
>> 1343 help
>> 1344 The Loongson 2E processor implements the MIPS III instruction set
>> 1345 with many extensions.
>> 1346
>> 1347 It has an internal FPGA northbridge, which is compatible to
>> 1348 bonito64.
>> 1349
>> 1350 config CPU_LOONGSON2F
>> 1351 bool "Loongson 2F"
>> 1352 depends on SYS_HAS_CPU_LOONGSON2F
>> 1353 select CPU_LOONGSON2EF
>> 1354 help
>> 1355 The Loongson 2F processor implements the MIPS III instruction set
>> 1356 with many extensions.
>> 1357
>> 1358 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1359 have a similar programming interface with FPGA northbridge used in
>> 1360 Loongson2E.
>> 1361
>> 1362 config CPU_LOONGSON1B
>> 1363 bool "Loongson 1B"
>> 1364 depends on SYS_HAS_CPU_LOONGSON1B
>> 1365 select CPU_LOONGSON32
>> 1366 select LEDS_GPIO_REGISTER
>> 1367 help
>> 1368 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1369 Release 1 instruction set and part of the MIPS32 Release 2
>> 1370 instruction set.
>> 1371
>> 1372 config CPU_LOONGSON1C
>> 1373 bool "Loongson 1C"
>> 1374 depends on SYS_HAS_CPU_LOONGSON1C
>> 1375 select CPU_LOONGSON32
>> 1376 select LEDS_GPIO_REGISTER
>> 1377 help
>> 1378 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1379 Release 1 instruction set and part of the MIPS32 Release 2
>> 1380 instruction set.
>> 1381
>> 1382 config CPU_MIPS32_R1
>> 1383 bool "MIPS32 Release 1"
>> 1384 depends on SYS_HAS_CPU_MIPS32_R1
>> 1385 select CPU_HAS_PREFETCH
>> 1386 select CPU_SUPPORTS_32BIT_KERNEL
>> 1387 select CPU_SUPPORTS_HIGHMEM
>> 1388 help
>> 1389 Choose this option to build a kernel for release 1 or later of the
>> 1390 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1391 MIPS processor are based on a MIPS32 processor. If you know the
>> 1392 specific type of processor in your system, choose those that one
>> 1393 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1394 Release 2 of the MIPS32 architecture is available since several
>> 1395 years so chances are you even have a MIPS32 Release 2 processor
>> 1396 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1397 performance.
1042 1398
1043 This is purely to save memory: each !! 1399 config CPU_MIPS32_R2
1044 to the kernel image. !! 1400 bool "MIPS32 Release 2"
>> 1401 depends on SYS_HAS_CPU_MIPS32_R2
>> 1402 select CPU_HAS_PREFETCH
>> 1403 select CPU_SUPPORTS_32BIT_KERNEL
>> 1404 select CPU_SUPPORTS_HIGHMEM
>> 1405 select CPU_SUPPORTS_MSA
>> 1406 help
>> 1407 Choose this option to build a kernel for release 2 or later of the
>> 1408 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1409 MIPS processor are based on a MIPS32 processor. If you know the
>> 1410 specific type of processor in your system, choose those that one
>> 1411 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1412
>> 1413 config CPU_MIPS32_R5
>> 1414 bool "MIPS32 Release 5"
>> 1415 depends on SYS_HAS_CPU_MIPS32_R5
>> 1416 select CPU_HAS_PREFETCH
>> 1417 select CPU_SUPPORTS_32BIT_KERNEL
>> 1418 select CPU_SUPPORTS_HIGHMEM
>> 1419 select CPU_SUPPORTS_MSA
>> 1420 select CPU_SUPPORTS_VZ
>> 1421 select MIPS_O32_FP64_SUPPORT
>> 1422 help
>> 1423 Choose this option to build a kernel for release 5 or later of the
>> 1424 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1425 family, are based on a MIPS32r5 processor. If you own an older
>> 1426 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1427
>> 1428 config CPU_MIPS32_R6
>> 1429 bool "MIPS32 Release 6"
>> 1430 depends on SYS_HAS_CPU_MIPS32_R6
>> 1431 select CPU_HAS_PREFETCH
>> 1432 select CPU_NO_LOAD_STORE_LR
>> 1433 select CPU_SUPPORTS_32BIT_KERNEL
>> 1434 select CPU_SUPPORTS_HIGHMEM
>> 1435 select CPU_SUPPORTS_MSA
>> 1436 select CPU_SUPPORTS_VZ
>> 1437 select MIPS_O32_FP64_SUPPORT
>> 1438 help
>> 1439 Choose this option to build a kernel for release 6 or later of the
>> 1440 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1441 family, are based on a MIPS32r6 processor. If you own an older
>> 1442 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1443
>> 1444 config CPU_MIPS64_R1
>> 1445 bool "MIPS64 Release 1"
>> 1446 depends on SYS_HAS_CPU_MIPS64_R1
>> 1447 select CPU_HAS_PREFETCH
>> 1448 select CPU_SUPPORTS_32BIT_KERNEL
>> 1449 select CPU_SUPPORTS_64BIT_KERNEL
>> 1450 select CPU_SUPPORTS_HIGHMEM
>> 1451 select CPU_SUPPORTS_HUGEPAGES
>> 1452 help
>> 1453 Choose this option to build a kernel for release 1 or later of the
>> 1454 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1455 MIPS processor are based on a MIPS64 processor. If you know the
>> 1456 specific type of processor in your system, choose those that one
>> 1457 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1458 Release 2 of the MIPS64 architecture is available since several
>> 1459 years so chances are you even have a MIPS64 Release 2 processor
>> 1460 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1461 performance.
1045 1462
1046 config SCHED_CLUSTER !! 1463 config CPU_MIPS64_R2
1047 bool "Cluster scheduler support" !! 1464 bool "MIPS64 Release 2"
1048 depends on SMP !! 1465 depends on SYS_HAS_CPU_MIPS64_R2
1049 default y !! 1466 select CPU_HAS_PREFETCH
>> 1467 select CPU_SUPPORTS_32BIT_KERNEL
>> 1468 select CPU_SUPPORTS_64BIT_KERNEL
>> 1469 select CPU_SUPPORTS_HIGHMEM
>> 1470 select CPU_SUPPORTS_HUGEPAGES
>> 1471 select CPU_SUPPORTS_MSA
>> 1472 help
>> 1473 Choose this option to build a kernel for release 2 or later of the
>> 1474 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1475 MIPS processor are based on a MIPS64 processor. If you know the
>> 1476 specific type of processor in your system, choose those that one
>> 1477 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1478
>> 1479 config CPU_MIPS64_R5
>> 1480 bool "MIPS64 Release 5"
>> 1481 depends on SYS_HAS_CPU_MIPS64_R5
>> 1482 select CPU_HAS_PREFETCH
>> 1483 select CPU_SUPPORTS_32BIT_KERNEL
>> 1484 select CPU_SUPPORTS_64BIT_KERNEL
>> 1485 select CPU_SUPPORTS_HIGHMEM
>> 1486 select CPU_SUPPORTS_HUGEPAGES
>> 1487 select CPU_SUPPORTS_MSA
>> 1488 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1489 select CPU_SUPPORTS_VZ
>> 1490 help
>> 1491 Choose this option to build a kernel for release 5 or later of the
>> 1492 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1493 release partly implementing release 6 features. Though there is no
>> 1494 any hardware known to be based on this release.
>> 1495
>> 1496 config CPU_MIPS64_R6
>> 1497 bool "MIPS64 Release 6"
>> 1498 depends on SYS_HAS_CPU_MIPS64_R6
>> 1499 select CPU_HAS_PREFETCH
>> 1500 select CPU_NO_LOAD_STORE_LR
>> 1501 select CPU_SUPPORTS_32BIT_KERNEL
>> 1502 select CPU_SUPPORTS_64BIT_KERNEL
>> 1503 select CPU_SUPPORTS_HIGHMEM
>> 1504 select CPU_SUPPORTS_HUGEPAGES
>> 1505 select CPU_SUPPORTS_MSA
>> 1506 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1507 select CPU_SUPPORTS_VZ
>> 1508 help
>> 1509 Choose this option to build a kernel for release 6 or later of the
>> 1510 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1511 family, are based on a MIPS64r6 processor. If you own an older
>> 1512 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1513
>> 1514 config CPU_P5600
>> 1515 bool "MIPS Warrior P5600"
>> 1516 depends on SYS_HAS_CPU_P5600
>> 1517 select CPU_HAS_PREFETCH
>> 1518 select CPU_SUPPORTS_32BIT_KERNEL
>> 1519 select CPU_SUPPORTS_HIGHMEM
>> 1520 select CPU_SUPPORTS_MSA
>> 1521 select CPU_SUPPORTS_CPUFREQ
>> 1522 select CPU_SUPPORTS_VZ
>> 1523 select CPU_MIPSR2_IRQ_VI
>> 1524 select CPU_MIPSR2_IRQ_EI
>> 1525 select MIPS_O32_FP64_SUPPORT
>> 1526 help
>> 1527 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1528 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1529 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1530 level features like up to six P5600 calculation cores, CM2 with L2
>> 1531 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1532 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1533 eJTAG and PDtrace.
>> 1534
>> 1535 config CPU_R3000
>> 1536 bool "R3000"
>> 1537 depends on SYS_HAS_CPU_R3000
>> 1538 select CPU_HAS_WB
>> 1539 select CPU_R3K_TLB
>> 1540 select CPU_SUPPORTS_32BIT_KERNEL
>> 1541 select CPU_SUPPORTS_HIGHMEM
>> 1542 help
>> 1543 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1544 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1545 *not* work on R4000 machines and vice versa. However, since most
>> 1546 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1547 might be a safe bet. If the resulting kernel does not work,
>> 1548 try to recompile with R3000.
>> 1549
>> 1550 config CPU_R4300
>> 1551 bool "R4300"
>> 1552 depends on SYS_HAS_CPU_R4300
>> 1553 select CPU_SUPPORTS_32BIT_KERNEL
>> 1554 select CPU_SUPPORTS_64BIT_KERNEL
>> 1555 help
>> 1556 MIPS Technologies R4300-series processors.
>> 1557
>> 1558 config CPU_R4X00
>> 1559 bool "R4x00"
>> 1560 depends on SYS_HAS_CPU_R4X00
>> 1561 select CPU_SUPPORTS_32BIT_KERNEL
>> 1562 select CPU_SUPPORTS_64BIT_KERNEL
>> 1563 select CPU_SUPPORTS_HUGEPAGES
>> 1564 help
>> 1565 MIPS Technologies R4000-series processors other than 4300, including
>> 1566 the R4000, R4400, R4600, and 4700.
>> 1567
>> 1568 config CPU_TX49XX
>> 1569 bool "R49XX"
>> 1570 depends on SYS_HAS_CPU_TX49XX
>> 1571 select CPU_HAS_PREFETCH
>> 1572 select CPU_SUPPORTS_32BIT_KERNEL
>> 1573 select CPU_SUPPORTS_64BIT_KERNEL
>> 1574 select CPU_SUPPORTS_HUGEPAGES
>> 1575
>> 1576 config CPU_R5000
>> 1577 bool "R5000"
>> 1578 depends on SYS_HAS_CPU_R5000
>> 1579 select CPU_SUPPORTS_32BIT_KERNEL
>> 1580 select CPU_SUPPORTS_64BIT_KERNEL
>> 1581 select CPU_SUPPORTS_HUGEPAGES
>> 1582 help
>> 1583 MIPS Technologies R5000-series processors other than the Nevada.
>> 1584
>> 1585 config CPU_R5500
>> 1586 bool "R5500"
>> 1587 depends on SYS_HAS_CPU_R5500
>> 1588 select CPU_SUPPORTS_32BIT_KERNEL
>> 1589 select CPU_SUPPORTS_64BIT_KERNEL
>> 1590 select CPU_SUPPORTS_HUGEPAGES
>> 1591 help
>> 1592 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1593 instruction set.
>> 1594
>> 1595 config CPU_NEVADA
>> 1596 bool "RM52xx"
>> 1597 depends on SYS_HAS_CPU_NEVADA
>> 1598 select CPU_SUPPORTS_32BIT_KERNEL
>> 1599 select CPU_SUPPORTS_64BIT_KERNEL
>> 1600 select CPU_SUPPORTS_HUGEPAGES
>> 1601 help
>> 1602 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1603
>> 1604 config CPU_R10000
>> 1605 bool "R10000"
>> 1606 depends on SYS_HAS_CPU_R10000
>> 1607 select CPU_HAS_PREFETCH
>> 1608 select CPU_SUPPORTS_32BIT_KERNEL
>> 1609 select CPU_SUPPORTS_64BIT_KERNEL
>> 1610 select CPU_SUPPORTS_HIGHMEM
>> 1611 select CPU_SUPPORTS_HUGEPAGES
>> 1612 help
>> 1613 MIPS Technologies R10000-series processors.
>> 1614
>> 1615 config CPU_RM7000
>> 1616 bool "RM7000"
>> 1617 depends on SYS_HAS_CPU_RM7000
>> 1618 select CPU_HAS_PREFETCH
>> 1619 select CPU_SUPPORTS_32BIT_KERNEL
>> 1620 select CPU_SUPPORTS_64BIT_KERNEL
>> 1621 select CPU_SUPPORTS_HIGHMEM
>> 1622 select CPU_SUPPORTS_HUGEPAGES
>> 1623
>> 1624 config CPU_SB1
>> 1625 bool "SB1"
>> 1626 depends on SYS_HAS_CPU_SB1
>> 1627 select CPU_SUPPORTS_32BIT_KERNEL
>> 1628 select CPU_SUPPORTS_64BIT_KERNEL
>> 1629 select CPU_SUPPORTS_HIGHMEM
>> 1630 select CPU_SUPPORTS_HUGEPAGES
>> 1631 select WEAK_ORDERING
>> 1632
>> 1633 config CPU_CAVIUM_OCTEON
>> 1634 bool "Cavium Octeon processor"
>> 1635 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1636 select CPU_HAS_PREFETCH
>> 1637 select CPU_SUPPORTS_64BIT_KERNEL
>> 1638 select HAVE_PAGE_SIZE_8KB if !MIPS_VA_BITS_48
>> 1639 select HAVE_PAGE_SIZE_32KB if !MIPS_VA_BITS_48
>> 1640 select WEAK_ORDERING
>> 1641 select CPU_SUPPORTS_HIGHMEM
>> 1642 select CPU_SUPPORTS_HUGEPAGES
>> 1643 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1644 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1645 select MIPS_L1_CACHE_SHIFT_7
>> 1646 select CPU_SUPPORTS_VZ
>> 1647 help
>> 1648 The Cavium Octeon processor is a highly integrated chip containing
>> 1649 many ethernet hardware widgets for networking tasks. The processor
>> 1650 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1651 Full details can be found at http://www.caviumnetworks.com.
>> 1652
>> 1653 config CPU_BMIPS
>> 1654 bool "Broadcom BMIPS"
>> 1655 depends on SYS_HAS_CPU_BMIPS
>> 1656 select CPU_MIPS32
>> 1657 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1658 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1659 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1660 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1661 select CPU_SUPPORTS_32BIT_KERNEL
>> 1662 select DMA_NONCOHERENT
>> 1663 select IRQ_MIPS_CPU
>> 1664 select SWAP_IO_SPACE
>> 1665 select WEAK_ORDERING
>> 1666 select CPU_SUPPORTS_HIGHMEM
>> 1667 select CPU_HAS_PREFETCH
>> 1668 select CPU_SUPPORTS_CPUFREQ
>> 1669 select MIPS_EXTERNAL_TIMER
>> 1670 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
1050 help 1671 help
1051 Cluster scheduler support improves !! 1672 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
1052 making when dealing with machines t <<
1053 Cluster usually means a couple of C <<
1054 by sharing mid-level caches, last-l <<
1055 busses. <<
1056 1673
1057 config SCHED_SMT !! 1674 endchoice
1058 def_bool y if SMP <<
1059 1675
1060 config SCHED_MC !! 1676 config LOONGSON3_ENHANCEMENT
1061 def_bool y !! 1677 bool "New Loongson-3 CPU Enhancements"
1062 prompt "Multi-core scheduler support" !! 1678 default n
1063 depends on SMP !! 1679 depends on CPU_LOONGSON64
1064 help 1680 help
1065 Multi-core scheduler support improv !! 1681 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1066 making when dealing with multi-core !! 1682 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1067 increased overhead in some places. !! 1683 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1684 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1685 Fast TLB refill support, etc.
>> 1686
>> 1687 This option enable those enhancements which are not probed at run
>> 1688 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1689 please say 'N' here. If you want a high-performance kernel to run on
>> 1690 new Loongson-3 machines only, please say 'Y' here.
>> 1691
>> 1692 config CPU_LOONGSON3_WORKAROUNDS
>> 1693 bool "Loongson-3 LLSC Workarounds"
>> 1694 default y if SMP
>> 1695 depends on CPU_LOONGSON64
>> 1696 help
>> 1697 Loongson-3 processors have the llsc issues which require workarounds.
>> 1698 Without workarounds the system may hang unexpectedly.
>> 1699
>> 1700 Say Y, unless you know what you are doing.
>> 1701
>> 1702 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1703 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1704 default y
>> 1705 depends on CPU_LOONGSON64
>> 1706 help
>> 1707 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1708 userland to query CPU capabilities, much like CPUID on x86. This
>> 1709 option provides emulation of the instruction on older Loongson
>> 1710 cores, back to Loongson-3A1000.
>> 1711
>> 1712 If unsure, please say Y.
>> 1713
>> 1714 config CPU_MIPS32_3_5_FEATURES
>> 1715 bool "MIPS32 Release 3.5 Features"
>> 1716 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1717 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1718 CPU_P5600
>> 1719 help
>> 1720 Choose this option to build a kernel for release 2 or later of the
>> 1721 MIPS32 architecture including features from the 3.5 release such as
>> 1722 support for Enhanced Virtual Addressing (EVA).
>> 1723
>> 1724 config CPU_MIPS32_3_5_EVA
>> 1725 bool "Enhanced Virtual Addressing (EVA)"
>> 1726 depends on CPU_MIPS32_3_5_FEATURES
>> 1727 select EVA
>> 1728 default y
>> 1729 help
>> 1730 Choose this option if you want to enable the Enhanced Virtual
>> 1731 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1732 One of its primary benefits is an increase in the maximum size
>> 1733 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1734
>> 1735 config CPU_MIPS32_R5_FEATURES
>> 1736 bool "MIPS32 Release 5 Features"
>> 1737 depends on SYS_HAS_CPU_MIPS32_R5
>> 1738 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1739 help
>> 1740 Choose this option to build a kernel for release 2 or later of the
>> 1741 MIPS32 architecture including features from release 5 such as
>> 1742 support for Extended Physical Addressing (XPA).
>> 1743
>> 1744 config CPU_MIPS32_R5_XPA
>> 1745 bool "Extended Physical Addressing (XPA)"
>> 1746 depends on CPU_MIPS32_R5_FEATURES
>> 1747 depends on !EVA
>> 1748 depends on !PAGE_SIZE_4KB
>> 1749 depends on SYS_SUPPORTS_HIGHMEM
>> 1750 select XPA
>> 1751 select HIGHMEM
>> 1752 select PHYS_ADDR_T_64BIT
>> 1753 default n
>> 1754 help
>> 1755 Choose this option if you want to enable the Extended Physical
>> 1756 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1757 benefit is to increase physical addressing equal to or greater
>> 1758 than 40 bits. Note that this has the side effect of turning on
>> 1759 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1760 If unsure, say 'N' here.
>> 1761
>> 1762 if CPU_LOONGSON2F
>> 1763 config CPU_NOP_WORKAROUNDS
>> 1764 bool
1068 1765
1069 config SCHED_MC_PRIO !! 1766 config CPU_JUMP_WORKAROUNDS
1070 bool "CPU core priorities scheduler s !! 1767 bool
1071 depends on SCHED_MC !! 1768
1072 select X86_INTEL_PSTATE if CPU_SUP_IN !! 1769 config CPU_LOONGSON2F_WORKAROUNDS
1073 select X86_AMD_PSTATE if CPU_SUP_AMD !! 1770 bool "Loongson 2F Workarounds"
1074 select CPU_FREQ <<
1075 default y 1771 default y
>> 1772 select CPU_NOP_WORKAROUNDS
>> 1773 select CPU_JUMP_WORKAROUNDS
1076 help 1774 help
1077 Intel Turbo Boost Max Technology 3. !! 1775 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1078 core ordering determined at manufac !! 1776 require workarounds. Without workarounds the system may hang
1079 certain cores to reach higher turbo !! 1777 unexpectedly. For more information please refer to the gas
1080 single threaded workloads) than oth !! 1778 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1779
>> 1780 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1781 are needed. The workarounds have no significant side effect on them
>> 1782 but may decrease the performance of the system so this option should
>> 1783 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1784 systems.
1081 1785
1082 Enabling this kernel feature teache !! 1786 If unsure, please say Y.
1083 the TBM3 (aka ITMT) priority order !! 1787 endif # CPU_LOONGSON2F
1084 scheduler's CPU selection logic acc <<
1085 overall system performance can be a <<
1086 1788
1087 This feature will have no effect on !! 1789 config SYS_SUPPORTS_ZBOOT
>> 1790 bool
>> 1791 select HAVE_KERNEL_GZIP
>> 1792 select HAVE_KERNEL_BZIP2
>> 1793 select HAVE_KERNEL_LZ4
>> 1794 select HAVE_KERNEL_LZMA
>> 1795 select HAVE_KERNEL_LZO
>> 1796 select HAVE_KERNEL_XZ
>> 1797 select HAVE_KERNEL_ZSTD
1088 1798
1089 If unsure say Y here. !! 1799 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1800 bool
>> 1801 select SYS_SUPPORTS_ZBOOT
1090 1802
1091 config UP_LATE_INIT !! 1803 config SYS_SUPPORTS_ZBOOT_UART_PROM
1092 def_bool y !! 1804 bool
1093 depends on !SMP && X86_LOCAL_APIC !! 1805 select SYS_SUPPORTS_ZBOOT
1094 1806
1095 config X86_UP_APIC !! 1807 config CPU_LOONGSON2EF
1096 bool "Local APIC support on uniproces !! 1808 bool
1097 default PCI_MSI !! 1809 select CPU_SUPPORTS_32BIT_KERNEL
1098 depends on X86_32 && !SMP && !X86_32_ !! 1810 select CPU_SUPPORTS_64BIT_KERNEL
1099 help !! 1811 select CPU_SUPPORTS_HIGHMEM
1100 A local APIC (Advanced Programmable !! 1812 select CPU_SUPPORTS_HUGEPAGES
1101 integrated interrupt controller in <<
1102 system which has a processor with a <<
1103 enable and use it. If you say Y her <<
1104 have a local APIC, then the kernel <<
1105 all. The local APIC supports CPU-ge <<
1106 performance counters), and the NMI <<
1107 lockups. <<
1108 <<
1109 config X86_UP_IOAPIC <<
1110 bool "IO-APIC support on uniprocessor <<
1111 depends on X86_UP_APIC <<
1112 help <<
1113 An IO-APIC (I/O Advanced Programmab <<
1114 SMP-capable replacement for PC-styl <<
1115 SMP systems and many recent uniproc <<
1116 <<
1117 If you have a single-CPU system wit <<
1118 to use it. If you say Y here even t <<
1119 an IO-APIC, then the kernel will st <<
1120 1813
1121 config X86_LOCAL_APIC !! 1814 config CPU_LOONGSON32
1122 def_bool y !! 1815 bool
1123 depends on X86_64 || SMP || X86_32_NO !! 1816 select CPU_MIPS32
1124 select IRQ_DOMAIN_HIERARCHY !! 1817 select CPU_MIPSR2
>> 1818 select CPU_HAS_PREFETCH
>> 1819 select CPU_SUPPORTS_32BIT_KERNEL
>> 1820 select CPU_SUPPORTS_HIGHMEM
>> 1821 select CPU_SUPPORTS_CPUFREQ
1125 1822
1126 config ACPI_MADT_WAKEUP !! 1823 config CPU_BMIPS32_3300
1127 def_bool y !! 1824 select SMP_UP if SMP
1128 depends on X86_64 !! 1825 bool
1129 depends on ACPI <<
1130 depends on SMP <<
1131 depends on X86_LOCAL_APIC <<
1132 1826
1133 config X86_IO_APIC !! 1827 config CPU_BMIPS4350
1134 def_bool y !! 1828 bool
1135 depends on X86_LOCAL_APIC || X86_UP_I !! 1829 select SYS_SUPPORTS_SMP
>> 1830 select SYS_SUPPORTS_HOTPLUG_CPU
1136 1831
1137 config X86_REROUTE_FOR_BROKEN_BOOT_IRQS !! 1832 config CPU_BMIPS4380
1138 bool "Reroute for broken boot IRQs" !! 1833 bool
1139 depends on X86_IO_APIC !! 1834 select MIPS_L1_CACHE_SHIFT_6
1140 help !! 1835 select SYS_SUPPORTS_SMP
1141 This option enables a workaround th !! 1836 select SYS_SUPPORTS_HOTPLUG_CPU
1142 spurious interrupts. This is recomm !! 1837 select CPU_HAS_RIXI
1143 interrupt handling is used on syste <<
1144 superfluous "boot interrupts" canno <<
1145 <<
1146 Some chipsets generate a legacy INT <<
1147 entry in the chipset's IO-APIC is m <<
1148 kernel does during interrupt handli <<
1149 boot IRQ generation cannot be disab <<
1150 the original IRQ line masked so tha <<
1151 IRQ" is delivered to the CPUs. The <<
1152 kernel to set up the IRQ handler on <<
1153 way only one interrupt is delivered <<
1154 the spurious second interrupt may c <<
1155 down (vital) interrupt lines. <<
1156 <<
1157 Only affects "broken" chipsets. Int <<
1158 increased on these systems. <<
1159 <<
1160 config X86_MCE <<
1161 bool "Machine Check / overheating rep <<
1162 select GENERIC_ALLOCATOR <<
1163 default y <<
1164 help <<
1165 Machine Check support allows the pr <<
1166 kernel if it detects a problem (e.g <<
1167 The action the kernel takes depends <<
1168 ranging from warning messages to ha <<
1169 <<
1170 config X86_MCELOG_LEGACY <<
1171 bool "Support for deprecated /dev/mce <<
1172 depends on X86_MCE <<
1173 help <<
1174 Enable support for /dev/mcelog whic <<
1175 userspace logging daemon. Consider <<
1176 rasdaemon solution. <<
1177 1838
1178 config X86_MCE_INTEL !! 1839 config CPU_BMIPS5000
1179 def_bool y !! 1840 bool
1180 prompt "Intel MCE features" !! 1841 select MIPS_CPU_SCACHE
1181 depends on X86_MCE && X86_LOCAL_APIC !! 1842 select MIPS_L1_CACHE_SHIFT_7
1182 help !! 1843 select SYS_SUPPORTS_SMP
1183 Additional support for intel specif !! 1844 select SYS_SUPPORTS_HOTPLUG_CPU
1184 the thermal monitor. !! 1845 select CPU_HAS_RIXI
1185 1846
1186 config X86_MCE_AMD !! 1847 config SYS_HAS_CPU_LOONGSON64
1187 def_bool y !! 1848 bool
1188 prompt "AMD MCE features" !! 1849 select CPU_SUPPORTS_CPUFREQ
1189 depends on X86_MCE && X86_LOCAL_APIC !! 1850 select CPU_HAS_RIXI
1190 help <<
1191 Additional support for AMD specific <<
1192 the DRAM Error Threshold. <<
1193 1851
1194 config X86_ANCIENT_MCE !! 1852 config SYS_HAS_CPU_LOONGSON2E
1195 bool "Support for old Pentium 5 / Win !! 1853 bool
1196 depends on X86_32 && X86_MCE <<
1197 help <<
1198 Include support for machine check h <<
1199 systems. These typically need to be <<
1200 line. <<
1201 1854
1202 config X86_MCE_THRESHOLD !! 1855 config SYS_HAS_CPU_LOONGSON2F
1203 depends on X86_MCE_AMD || X86_MCE_INT !! 1856 bool
1204 def_bool y !! 1857 select CPU_SUPPORTS_CPUFREQ
>> 1858 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1205 1859
1206 config X86_MCE_INJECT !! 1860 config SYS_HAS_CPU_LOONGSON1B
1207 depends on X86_MCE && X86_LOCAL_APIC !! 1861 bool
1208 tristate "Machine check injector supp <<
1209 help <<
1210 Provide support for injecting machi <<
1211 If you don't know what a machine ch <<
1212 QA it is safe to say n. <<
1213 1862
1214 source "arch/x86/events/Kconfig" !! 1863 config SYS_HAS_CPU_LOONGSON1C
>> 1864 bool
1215 1865
1216 config X86_LEGACY_VM86 !! 1866 config SYS_HAS_CPU_MIPS32_R1
1217 bool "Legacy VM86 support" !! 1867 bool
1218 depends on X86_32 <<
1219 help <<
1220 This option allows user programs to <<
1221 mode, which is an 80286-era approxi <<
1222 1868
1223 Some very old versions of X and/or !! 1869 config SYS_HAS_CPU_MIPS32_R2
1224 for user mode setting. Similarly, !! 1870 bool
1225 available to accelerate real mode D <<
1226 recent version of DOSEMU, X, or vbe <<
1227 functional even without kernel VM86 <<
1228 fall back to software emulation. Ne <<
1229 a 16-bit DOS program where 16-bit p <<
1230 mode might be faster than emulation <<
1231 enable this option. <<
1232 1871
1233 Note that any app that works on a 6 !! 1872 config SYS_HAS_CPU_MIPS32_R3_5
1234 need this option, as 64-bit kernels !! 1873 bool
1235 V8086 mode. This option is also unr <<
1236 mode and is not needed to run most <<
1237 1874
1238 Enabling this option increases the !! 1875 config SYS_HAS_CPU_MIPS32_R5
1239 and slows down exception handling a !! 1876 bool
1240 1877
1241 If unsure, say N here. !! 1878 config SYS_HAS_CPU_MIPS32_R6
>> 1879 bool
1242 1880
1243 config VM86 !! 1881 config SYS_HAS_CPU_MIPS64_R1
1244 bool 1882 bool
1245 default X86_LEGACY_VM86 <<
1246 1883
1247 config X86_16BIT !! 1884 config SYS_HAS_CPU_MIPS64_R2
1248 bool "Enable support for 16-bit segme !! 1885 bool
1249 default y <<
1250 depends on MODIFY_LDT_SYSCALL <<
1251 help <<
1252 This option is required by programs <<
1253 protected mode legacy code on x86 p <<
1254 this option saves about 300 bytes o <<
1255 plus 16K runtime memory on x86-64, <<
1256 1886
1257 config X86_ESPFIX32 !! 1887 config SYS_HAS_CPU_MIPS64_R5
1258 def_bool y !! 1888 bool
1259 depends on X86_16BIT && X86_32 <<
1260 1889
1261 config X86_ESPFIX64 !! 1890 config SYS_HAS_CPU_MIPS64_R6
1262 def_bool y !! 1891 bool
1263 depends on X86_16BIT && X86_64 <<
1264 1892
1265 config X86_VSYSCALL_EMULATION !! 1893 config SYS_HAS_CPU_P5600
1266 bool "Enable vsyscall emulation" if E !! 1894 bool
1267 default y <<
1268 depends on X86_64 <<
1269 help <<
1270 This enables emulation of the legac <<
1271 it is roughly equivalent to booting <<
1272 that it will also disable the helpf <<
1273 tries to use a vsyscall. With this <<
1274 programs will just segfault, citing <<
1275 0xffffffffff600?00. <<
1276 1895
1277 This option is required by many pro !! 1896 config SYS_HAS_CPU_R3000
1278 care should be used even with newer !! 1897 bool
1279 1898
1280 Disabling this option saves about 7 !! 1899 config SYS_HAS_CPU_R4300
1281 possibly 4K of additional runtime p !! 1900 bool
1282 1901
1283 config X86_IOPL_IOPERM !! 1902 config SYS_HAS_CPU_R4X00
1284 bool "IOPERM and IOPL Emulation" !! 1903 bool
1285 default y <<
1286 help <<
1287 This enables the ioperm() and iopl( <<
1288 for legacy applications. <<
1289 1904
1290 Legacy IOPL support is an overbroad !! 1905 config SYS_HAS_CPU_TX49XX
1291 space aside of accessing all 65536 !! 1906 bool
1292 interrupts. To gain this access the <<
1293 capabilities and permission from po <<
1294 modules. <<
1295 <<
1296 The emulation restricts the functio <<
1297 only allowing the full range I/O po <<
1298 ability to disable interrupts from <<
1299 granted if the hardware IOPL mechan <<
1300 <<
1301 config TOSHIBA <<
1302 tristate "Toshiba Laptop support" <<
1303 depends on X86_32 <<
1304 help <<
1305 This adds a driver to safely access <<
1306 the CPU on Toshiba portables with a <<
1307 not work on models with a Phoenix B <<
1308 is used to set the BIOS and power s <<
1309 <<
1310 For information on utilities to mak <<
1311 Toshiba Linux utilities web site at <<
1312 <http://www.buzzard.org.uk/toshiba/ <<
1313 <<
1314 Say Y if you intend to run this ker <<
1315 Say N otherwise. <<
1316 <<
1317 config X86_REBOOTFIXUPS <<
1318 bool "Enable X86 board specific fixup <<
1319 depends on X86_32 <<
1320 help <<
1321 This enables chipset and/or board s <<
1322 in order to get reboot to work corr <<
1323 some combinations of hardware and B <<
1324 this config is intended, is when re <<
1325 system. <<
1326 <<
1327 Currently, the only fixup is for th <<
1328 CS5530A and CS5536 chipsets and the <<
1329 <<
1330 Say Y if you want to enable the fix <<
1331 enable this option even if you don' <<
1332 Say N otherwise. <<
1333 1907
1334 config MICROCODE !! 1908 config SYS_HAS_CPU_R5000
1335 def_bool y !! 1909 bool
1336 depends on CPU_SUP_AMD || CPU_SUP_INT <<
1337 1910
1338 config MICROCODE_INITRD32 !! 1911 config SYS_HAS_CPU_R5500
1339 def_bool y !! 1912 bool
1340 depends on MICROCODE && X86_32 && BLK <<
1341 1913
1342 config MICROCODE_LATE_LOADING !! 1914 config SYS_HAS_CPU_NEVADA
1343 bool "Late microcode loading (DANGERO !! 1915 bool
1344 default n <<
1345 depends on MICROCODE && SMP <<
1346 help <<
1347 Loading microcode late, when the sy <<
1348 is a tricky business and should be <<
1349 of synchronizing all cores and SMT <<
1350 not guarantee that cores might not <<
1351 use this at your own risk. Late loa <<
1352 microcode header indicates that it <<
1353 minimal revision check. This minima <<
1354 the kernel command line with "micro <<
1355 1916
1356 config MICROCODE_LATE_FORCE_MINREV !! 1917 config SYS_HAS_CPU_R10000
1357 bool "Enforce late microcode loading !! 1918 bool
1358 default n <<
1359 depends on MICROCODE_LATE_LOADING <<
1360 help <<
1361 To prevent that users load microcod <<
1362 in use features, newer microcode pa <<
1363 in the microcode header, which tell <<
1364 revision must be active in the CPU <<
1365 late into the running system. If di <<
1366 be enforced but the kernel will be <<
1367 revision check fails. <<
1368 <<
1369 This minimal revision check can als <<
1370 "microcode.minrev" parameter on the <<
1371 <<
1372 If unsure say Y. <<
1373 <<
1374 config X86_MSR <<
1375 tristate "/dev/cpu/*/msr - Model-spec <<
1376 help <<
1377 This device gives privileged proces <<
1378 Model-Specific Registers (MSRs). I <<
1379 major 202 and minors 0 to 31 for /d <<
1380 MSR accesses are directed to a spec <<
1381 systems. <<
1382 1919
1383 config X86_CPUID !! 1920 config SYS_HAS_CPU_RM7000
1384 tristate "/dev/cpu/*/cpuid - CPU info !! 1921 bool
1385 help <<
1386 This device gives processes access <<
1387 be executed on a specific processor <<
1388 with major 203 and minors 0 to 31 f <<
1389 /dev/cpu/31/cpuid. <<
1390 1922
1391 choice !! 1923 config SYS_HAS_CPU_SB1
1392 prompt "High Memory Support" !! 1924 bool
1393 default HIGHMEM4G <<
1394 depends on X86_32 <<
1395 <<
1396 config NOHIGHMEM <<
1397 bool "off" <<
1398 help <<
1399 Linux can use up to 64 Gigabytes of <<
1400 However, the address space of 32-bi <<
1401 Gigabytes large. That means that, i <<
1402 physical memory, not all of it can <<
1403 kernel. The physical memory that's <<
1404 "high memory". <<
1405 <<
1406 If you are compiling a kernel which <<
1407 more than 1 Gigabyte total physical <<
1408 choice and suitable for most users) <<
1409 split: 3GB are mapped so that each <<
1410 space and the remaining part of the <<
1411 by the kernel to permanently map as <<
1412 possible. <<
1413 <<
1414 If the machine has between 1 and 4 <<
1415 answer "4GB" here. <<
1416 <<
1417 If more than 4 Gigabytes is used th <<
1418 selection turns Intel PAE (Physical <<
1419 PAE implements 3-level paging on IA <<
1420 supported by Linux, PAE mode is imp <<
1421 processors (Pentium Pro and better) <<
1422 then the kernel will not boot on CP <<
1423 <<
1424 The actual amount of total physical <<
1425 auto detected or can be forced by u <<
1426 such as "mem=256M". (Try "man bootp <<
1427 your boot loader (lilo or loadlin) <<
1428 kernel at boot time.) <<
1429 <<
1430 If unsure, say "off". <<
1431 <<
1432 config HIGHMEM4G <<
1433 bool "4GB" <<
1434 help <<
1435 Select this if you have a 32-bit pr <<
1436 gigabytes of physical RAM. <<
1437 <<
1438 config HIGHMEM64G <<
1439 bool "64GB" <<
1440 depends on X86_HAVE_PAE <<
1441 select X86_PAE <<
1442 help <<
1443 Select this if you have a 32-bit pr <<
1444 gigabytes of physical RAM. <<
1445 1925
1446 endchoice !! 1926 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1927 bool
1447 1928
1448 choice !! 1929 config SYS_HAS_CPU_BMIPS
1449 prompt "Memory split" if EXPERT !! 1930 bool
1450 default VMSPLIT_3G <<
1451 depends on X86_32 <<
1452 help <<
1453 Select the desired split between ke <<
1454 <<
1455 If the address range available to t <<
1456 physical memory installed, the rema <<
1457 as "high memory". Accessing high me <<
1458 than low memory, as it needs to be <<
1459 Note that increasing the kernel add <<
1460 available to user programs, making <<
1461 tighter. Selecting anything other <<
1462 will also likely make your kernel i <<
1463 kernel modules. <<
1464 <<
1465 If you are not absolutely sure what <<
1466 option alone! <<
1467 <<
1468 config VMSPLIT_3G <<
1469 bool "3G/1G user/kernel split <<
1470 config VMSPLIT_3G_OPT <<
1471 depends on !X86_PAE <<
1472 bool "3G/1G user/kernel split <<
1473 config VMSPLIT_2G <<
1474 bool "2G/2G user/kernel split <<
1475 config VMSPLIT_2G_OPT <<
1476 depends on !X86_PAE <<
1477 bool "2G/2G user/kernel split <<
1478 config VMSPLIT_1G <<
1479 bool "1G/3G user/kernel split <<
1480 endchoice <<
1481 1931
1482 config PAGE_OFFSET !! 1932 config SYS_HAS_CPU_BMIPS32_3300
1483 hex !! 1933 bool
1484 default 0xB0000000 if VMSPLIT_3G_OPT !! 1934 select SYS_HAS_CPU_BMIPS
1485 default 0x80000000 if VMSPLIT_2G <<
1486 default 0x78000000 if VMSPLIT_2G_OPT <<
1487 default 0x40000000 if VMSPLIT_1G <<
1488 default 0xC0000000 <<
1489 depends on X86_32 <<
1490 1935
1491 config HIGHMEM !! 1936 config SYS_HAS_CPU_BMIPS4350
1492 def_bool y !! 1937 bool
1493 depends on X86_32 && (HIGHMEM64G || H !! 1938 select SYS_HAS_CPU_BMIPS
1494 1939
1495 config X86_PAE !! 1940 config SYS_HAS_CPU_BMIPS4380
1496 bool "PAE (Physical Address Extension !! 1941 bool
1497 depends on X86_32 && X86_HAVE_PAE !! 1942 select SYS_HAS_CPU_BMIPS
1498 select PHYS_ADDR_T_64BIT <<
1499 select SWIOTLB <<
1500 help <<
1501 PAE is required for NX support, and <<
1502 larger swapspace support for non-ov <<
1503 has the cost of more pagetable look <<
1504 consumes more pagetable space per p <<
1505 1943
1506 config X86_5LEVEL !! 1944 config SYS_HAS_CPU_BMIPS5000
1507 bool "Enable 5-level page tables supp !! 1945 bool
1508 default y !! 1946 select SYS_HAS_CPU_BMIPS
1509 select DYNAMIC_MEMORY_LAYOUT <<
1510 select SPARSEMEM_VMEMMAP <<
1511 depends on X86_64 <<
1512 help <<
1513 5-level paging enables access to la <<
1514 up to 128 PiB of virtual address sp <<
1515 physical address space. <<
1516 1947
1517 It will be supported by future Inte !! 1948 #
>> 1949 # CPU may reorder R->R, R->W, W->R, W->W
>> 1950 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1951 #
>> 1952 config WEAK_ORDERING
>> 1953 bool
1518 1954
1519 A kernel with the option enabled ca !! 1955 #
1520 support 4- or 5-level paging. !! 1956 # CPU may reorder reads and writes beyond LL/SC
>> 1957 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 1958 #
>> 1959 config WEAK_REORDERING_BEYOND_LLSC
>> 1960 bool
>> 1961 endmenu
1521 1962
1522 See Documentation/arch/x86/x86_64/5 !! 1963 #
1523 information. !! 1964 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1965 #
>> 1966 config CPU_MIPS32
>> 1967 bool
>> 1968 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1969 CPU_MIPS32_R6 || CPU_P5600
1524 1970
1525 Say N if unsure. !! 1971 config CPU_MIPS64
>> 1972 bool
>> 1973 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1974 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1526 1975
1527 config X86_DIRECT_GBPAGES !! 1976 #
1528 def_bool y !! 1977 # These indicate the revision of the architecture
1529 depends on X86_64 !! 1978 #
1530 help !! 1979 config CPU_MIPSR1
1531 Certain kernel features effectively !! 1980 bool
1532 linear 1 GB mappings (even if the C !! 1981 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1533 supports them), so don't confuse th <<
1534 that we have them enabled. <<
1535 <<
1536 config X86_CPA_STATISTICS <<
1537 bool "Enable statistic for Change Pag <<
1538 depends on DEBUG_FS <<
1539 help <<
1540 Expose statistics about the Change <<
1541 helps to determine the effectivenes <<
1542 page mappings when mapping protecti <<
1543 <<
1544 config X86_MEM_ENCRYPT <<
1545 select ARCH_HAS_FORCE_DMA_UNENCRYPTED <<
1546 select DYNAMIC_PHYSICAL_MASK <<
1547 def_bool n <<
1548 1982
1549 config AMD_MEM_ENCRYPT !! 1983 config CPU_MIPSR2
1550 bool "AMD Secure Memory Encryption (S !! 1984 bool
1551 depends on X86_64 && CPU_SUP_AMD !! 1985 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1552 depends on EFI_STUB !! 1986 select CPU_HAS_RIXI
1553 select DMA_COHERENT_POOL !! 1987 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1554 select ARCH_USE_MEMREMAP_PROT !! 1988 select MIPS_SPRAM
1555 select INSTRUCTION_DECODER <<
1556 select ARCH_HAS_CC_PLATFORM <<
1557 select X86_MEM_ENCRYPT <<
1558 select UNACCEPTED_MEMORY <<
1559 help <<
1560 Say yes to enable support for the e <<
1561 This requires an AMD processor that <<
1562 Encryption (SME). <<
1563 1989
1564 # Common NUMA Features !! 1990 config CPU_MIPSR5
1565 config NUMA !! 1991 bool
1566 bool "NUMA Memory Allocation and Sche !! 1992 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1567 depends on SMP !! 1993 select CPU_HAS_RIXI
1568 depends on X86_64 || (X86_32 && HIGHM !! 1994 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1569 default y if X86_BIGSMP !! 1995 select MIPS_SPRAM
1570 select USE_PERCPU_NUMA_NODE_ID !! 1996
1571 select OF_NUMA if OF !! 1997 config CPU_MIPSR6
>> 1998 bool
>> 1999 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2000 select CPU_HAS_RIXI
>> 2001 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2002 select HAVE_ARCH_BITREVERSE
>> 2003 select MIPS_ASID_BITS_VARIABLE
>> 2004 select MIPS_CRC_SUPPORT
>> 2005 select MIPS_SPRAM
>> 2006
>> 2007 config TARGET_ISA_REV
>> 2008 int
>> 2009 default 1 if CPU_MIPSR1
>> 2010 default 2 if CPU_MIPSR2
>> 2011 default 5 if CPU_MIPSR5
>> 2012 default 6 if CPU_MIPSR6
>> 2013 default 0
1572 help 2014 help
1573 Enable NUMA (Non-Uniform Memory Acc !! 2015 Reflects the ISA revision being targeted by the kernel build. This
>> 2016 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1574 2017
1575 The kernel will try to allocate mem !! 2018 config EVA
1576 local memory controller of the CPU !! 2019 bool
1577 NUMA awareness to the kernel. <<
1578 2020
1579 For 64-bit this is recommended if t !! 2021 config XPA
1580 (or later), AMD Opteron, or EM64T N !! 2022 bool
1581 2023
1582 For 32-bit this is only needed if y !! 2024 config SYS_SUPPORTS_32BIT_KERNEL
1583 kernel on a 64-bit NUMA platform. !! 2025 bool
>> 2026 config SYS_SUPPORTS_64BIT_KERNEL
>> 2027 bool
>> 2028 config CPU_SUPPORTS_32BIT_KERNEL
>> 2029 bool
>> 2030 config CPU_SUPPORTS_64BIT_KERNEL
>> 2031 bool
>> 2032 config CPU_SUPPORTS_CPUFREQ
>> 2033 bool
>> 2034 config CPU_SUPPORTS_ADDRWINCFG
>> 2035 bool
>> 2036 config CPU_SUPPORTS_HUGEPAGES
>> 2037 bool
>> 2038 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2039 config CPU_SUPPORTS_VZ
>> 2040 bool
>> 2041 config MIPS_PGD_C0_CONTEXT
>> 2042 bool
>> 2043 depends on 64BIT
>> 2044 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1584 2045
1585 Otherwise, you should say N. !! 2046 #
>> 2047 # Set to y for ptrace access to watch registers.
>> 2048 #
>> 2049 config HARDWARE_WATCHPOINTS
>> 2050 bool
>> 2051 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1586 2052
1587 config AMD_NUMA !! 2053 menu "Kernel type"
1588 def_bool y !! 2054
1589 prompt "Old style AMD Opteron NUMA de !! 2055 choice
1590 depends on X86_64 && NUMA && PCI !! 2056 prompt "Kernel code model"
>> 2057 help
>> 2058 You should only select this option if you have a workload that
>> 2059 actually benefits from 64-bit processing or if your machine has
>> 2060 large memory. You will only be presented a single option in this
>> 2061 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2062
>> 2063 config 32BIT
>> 2064 bool "32-bit kernel"
>> 2065 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2066 select TRAD_SIGNALS
1591 help 2067 help
1592 Enable AMD NUMA node topology detec !! 2068 Select this option if you want to build a 32-bit kernel.
1593 you have a multi processor AMD syst <<
1594 read the NUMA configuration directl <<
1595 of Opteron. It is recommended to us <<
1596 which also takes priority if both a <<
1597 2069
1598 config X86_64_ACPI_NUMA !! 2070 config 64BIT
1599 def_bool y !! 2071 bool "64-bit kernel"
1600 prompt "ACPI NUMA detection" !! 2072 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1601 depends on X86_64 && NUMA && ACPI && <<
1602 select ACPI_NUMA <<
1603 help 2073 help
1604 Enable ACPI SRAT based node topolog !! 2074 Select this option if you want to build a 64-bit kernel.
1605 2075
1606 config NODES_SHIFT !! 2076 endchoice
1607 int "Maximum NUMA Nodes (as a power o !! 2077
1608 range 1 10 !! 2078 config MIPS_VA_BITS_48
1609 default "10" if MAXSMP !! 2079 bool "48 bits virtual memory"
1610 default "6" if X86_64 !! 2080 depends on 64BIT
1611 default "3" <<
1612 depends on NUMA <<
1613 help 2081 help
1614 Specify the maximum number of NUMA !! 2082 Support a maximum at least 48 bits of application virtual
1615 system. Increases memory reserved !! 2083 memory. Default is 40 bits or less, depending on the CPU.
>> 2084 For page sizes 16k and above, this option results in a small
>> 2085 memory overhead for page tables. For 4k page size, a fourth
>> 2086 level of page tables is added which imposes both a memory
>> 2087 overhead as well as slower TLB fault handling.
1616 2088
1617 config ARCH_FLATMEM_ENABLE !! 2089 If unsure, say N.
1618 def_bool y <<
1619 depends on X86_32 && !NUMA <<
1620 2090
1621 config ARCH_SPARSEMEM_ENABLE !! 2091 config ZBOOT_LOAD_ADDRESS
1622 def_bool y !! 2092 hex "Compressed kernel load address"
1623 depends on X86_64 || NUMA || X86_32 | !! 2093 default 0xffffffff80400000 if BCM47XX
1624 select SPARSEMEM_STATIC if X86_32 !! 2094 default 0x0
1625 select SPARSEMEM_VMEMMAP_ENABLE if X8 !! 2095 depends on SYS_SUPPORTS_ZBOOT
>> 2096 help
>> 2097 The address to load compressed kernel, aka vmlinuz.
>> 2098
>> 2099 This is only used if non-zero.
>> 2100
>> 2101 config ARCH_FORCE_MAX_ORDER
>> 2102 int "Maximum zone order"
>> 2103 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2104 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2105 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2106 default "10"
>> 2107 help
>> 2108 The kernel memory allocator divides physically contiguous memory
>> 2109 blocks into "zones", where each zone is a power of two number of
>> 2110 pages. This option selects the largest power of two that the kernel
>> 2111 keeps in the memory allocator. If you need to allocate very large
>> 2112 blocks of physically contiguous memory, then you may need to
>> 2113 increase this value.
1626 2114
1627 config ARCH_SPARSEMEM_DEFAULT !! 2115 The page size is not necessarily 4KB. Keep this in mind
1628 def_bool X86_64 || (NUMA && X86_32) !! 2116 when choosing a value for this option.
1629 2117
1630 config ARCH_SELECT_MEMORY_MODEL !! 2118 config BOARD_SCACHE
1631 def_bool y !! 2119 bool
1632 depends on ARCH_SPARSEMEM_ENABLE && A <<
1633 2120
1634 config ARCH_MEMORY_PROBE !! 2121 config IP22_CPU_SCACHE
1635 bool "Enable sysfs memory/probe inter !! 2122 bool
1636 depends on MEMORY_HOTPLUG !! 2123 select BOARD_SCACHE
1637 help <<
1638 This option enables a sysfs memory/ <<
1639 See Documentation/admin-guide/mm/me <<
1640 If you are unsure how to answer thi <<
1641 2124
1642 config ARCH_PROC_KCORE_TEXT !! 2125 #
1643 def_bool y !! 2126 # Support for a MIPS32 / MIPS64 style S-caches
1644 depends on X86_64 && PROC_KCORE !! 2127 #
>> 2128 config MIPS_CPU_SCACHE
>> 2129 bool
>> 2130 select BOARD_SCACHE
1645 2131
1646 config ILLEGAL_POINTER_VALUE !! 2132 config R5000_CPU_SCACHE
1647 hex !! 2133 bool
1648 default 0 if X86_32 !! 2134 select BOARD_SCACHE
1649 default 0xdead000000000000 if X86_64 <<
1650 <<
1651 config X86_PMEM_LEGACY_DEVICE <<
1652 bool <<
1653 <<
1654 config X86_PMEM_LEGACY <<
1655 tristate "Support non-standard NVDIMM <<
1656 depends on PHYS_ADDR_T_64BIT <<
1657 depends on BLK_DEV <<
1658 select X86_PMEM_LEGACY_DEVICE <<
1659 select NUMA_KEEP_MEMINFO if NUMA <<
1660 select LIBNVDIMM <<
1661 help <<
1662 Treat memory marked using the non-s <<
1663 by the Intel Sandy Bridge-EP refere <<
1664 The kernel will offer these regions <<
1665 they can be used for persistent sto <<
1666 <<
1667 Say Y if unsure. <<
1668 <<
1669 config HIGHPTE <<
1670 bool "Allocate 3rd-level pagetables f <<
1671 depends on HIGHMEM <<
1672 help <<
1673 The VM uses one page table entry fo <<
1674 For systems with a lot of RAM, this <<
1675 low memory. Setting this option wi <<
1676 entries in high memory. <<
1677 <<
1678 config X86_CHECK_BIOS_CORRUPTION <<
1679 bool "Check for low memory corruption <<
1680 help <<
1681 Periodically check for memory corru <<
1682 is suspected to be caused by BIOS. <<
1683 configuration, it is disabled at ru <<
1684 setting "memory_corruption_check=1" <<
1685 line. By default it scans the low <<
1686 seconds; see the memory_corruption_ <<
1687 memory_corruption_check_period para <<
1688 Documentation/admin-guide/kernel-pa <<
1689 <<
1690 When enabled with the default param <<
1691 almost no overhead, as it reserves <<
1692 of memory and scans it infrequently <<
1693 and prevents it from affecting the <<
1694 <<
1695 It is, however, intended as a diagn <<
1696 BIOS-originated corruption always a <<
1697 you can use memmap= to prevent the <<
1698 memory. <<
1699 <<
1700 config X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK <<
1701 bool "Set the default setting of memo <<
1702 depends on X86_CHECK_BIOS_CORRUPTION <<
1703 default y <<
1704 help <<
1705 Set whether the default state of me <<
1706 on or off. <<
1707 2135
1708 config MATH_EMULATION !! 2136 config RM7000_CPU_SCACHE
1709 bool 2137 bool
1710 depends on MODIFY_LDT_SYSCALL !! 2138 select BOARD_SCACHE
1711 prompt "Math emulation" if X86_32 && !! 2139
>> 2140 config SIBYTE_DMA_PAGEOPS
>> 2141 bool "Use DMA to clear/copy pages"
>> 2142 depends on CPU_SB1
1712 help 2143 help
1713 Linux can emulate a math coprocesso !! 2144 Instead of using the CPU to zero and copy pages, use a Data Mover
1714 operations) if you don't have one. !! 2145 channel. These DMA channels are otherwise unused by the standard
1715 a math coprocessor built in, 486SX !! 2146 SiByte Linux port. Seems to give a small performance benefit.
1716 a 487DX or 387, respectively. (The <<
1717 give you some hints here ["man dmes <<
1718 coprocessor or this emulation. <<
1719 <<
1720 If you don't have a math coprocesso <<
1721 say Y here even though you have a c <<
1722 be used nevertheless. (This behavio <<
1723 command line option "no387", which <<
1724 is broken. Try "man bootparam" or s <<
1725 loader (lilo or loadlin) about how <<
1726 boot time.) This means that it is a <<
1727 intend to use this kernel on differ <<
1728 2147
1729 More information about the internal !! 2148 config CPU_HAS_PREFETCH
1730 emulation can be found in <file:arc !! 2149 bool
1731 2150
1732 If you are not sure, say Y; apart f !! 2151 config CPU_GENERIC_DUMP_TLB
1733 kernel, it won't hurt. !! 2152 bool
>> 2153 default y if !CPU_R3000
1734 2154
1735 config MTRR !! 2155 config MIPS_FP_SUPPORT
1736 def_bool y !! 2156 bool "Floating Point support" if EXPERT
1737 prompt "MTRR (Memory Type Range Regis !! 2157 default y
1738 help 2158 help
1739 On Intel P6 family processors (Pent !! 2159 Select y to include support for floating point in the kernel
1740 the Memory Type Range Registers (MT !! 2160 including initialization of FPU hardware, FP context save & restore
1741 processor access to memory ranges. !! 2161 and emulation of an FPU where necessary. Without this support any
1742 a video (VGA) card on a PCI or AGP !! 2162 userland program attempting to use floating point instructions will
1743 allows bus write transfers to be co !! 2163 receive a SIGILL.
1744 before bursting over the PCI/AGP bu <<
1745 of image write operations 2.5 times <<
1746 /proc/mtrr file which may be used t <<
1747 MTRRs. Typically the X server shoul <<
1748 <<
1749 This code has a reasonably generic <<
1750 control registers on other processo <<
1751 as well: <<
1752 <<
1753 The Cyrix 6x86, 6x86MX and M II pro <<
1754 Registers (ARRs) which provide a si <<
1755 these, the ARRs are used to emulate <<
1756 The AMD K6-2 (stepping 8 and above) <<
1757 MTRRs. The Centaur C6 (WinChip) has <<
1758 write-combining. All of these proce <<
1759 and it makes sense to say Y here if <<
1760 <<
1761 Saying Y here also fixes a problem <<
1762 set the MTRRs for the boot CPU and <<
1763 can lead to all sorts of problems, <<
1764 2164
1765 You can safely say Y even if your m !! 2165 If you know that your userland will not attempt to use floating point
1766 just add about 9 KB to your kernel. !! 2166 instructions then you can say n here to shrink the kernel a little.
1767 2167
1768 See <file:Documentation/arch/x86/mt !! 2168 If unsure, say y.
1769 2169
1770 config MTRR_SANITIZER !! 2170 config CPU_R2300_FPU
1771 def_bool y !! 2171 bool
1772 prompt "MTRR cleanup support" !! 2172 depends on MIPS_FP_SUPPORT
1773 depends on MTRR !! 2173 default y if CPU_R3000
1774 help !! 2174
1775 Convert MTRR layout from continuous !! 2175 config CPU_R3K_TLB
1776 add writeback entries. !! 2176 bool
1777 2177
1778 Can be disabled with disable_mtrr_c !! 2178 config CPU_R4K_FPU
1779 The largest mtrr entry size for a c !! 2179 bool
1780 mtrr_chunk_size. !! 2180 depends on MIPS_FP_SUPPORT
>> 2181 default y if !CPU_R2300_FPU
1781 2182
1782 If unsure, say Y. !! 2183 config CPU_R4K_CACHE_TLB
>> 2184 bool
>> 2185 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
1783 2186
1784 config MTRR_SANITIZER_ENABLE_DEFAULT !! 2187 config MIPS_MT_SMP
1785 int "MTRR cleanup enable value (0-1)" !! 2188 bool "MIPS MT SMP support (1 TC on each available VPE)"
1786 range 0 1 !! 2189 default y
1787 default "0" !! 2190 depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
1788 depends on MTRR_SANITIZER !! 2191 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
1789 help !! 2192 select CPU_MIPSR2_IRQ_VI
1790 Enable mtrr cleanup default value !! 2193 select CPU_MIPSR2_IRQ_EI
1791 !! 2194 select SYNC_R4K
1792 config MTRR_SANITIZER_SPARE_REG_NR_DEFAULT !! 2195 select MIPS_MT
1793 int "MTRR cleanup spare reg num (0-7) !! 2196 select SMP
1794 range 0 7 !! 2197 select SMP_UP
1795 default "1" !! 2198 select SYS_SUPPORTS_SMP
1796 depends on MTRR_SANITIZER !! 2199 select SYS_SUPPORTS_SCHED_SMT
1797 help !! 2200 select MIPS_PERF_SHARED_TC_COUNTERS
1798 mtrr cleanup spare entries default, !! 2201 help
1799 mtrr_spare_reg_nr=N on the kernel c !! 2202 This is a kernel model which is known as SMVP. This is supported
>> 2203 on cores with the MT ASE and uses the available VPEs to implement
>> 2204 virtual processors which supports SMP. This is equivalent to the
>> 2205 Intel Hyperthreading feature. For further information go to
>> 2206 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1800 2207
1801 config X86_PAT !! 2208 config MIPS_MT
1802 def_bool y !! 2209 bool
1803 prompt "x86 PAT support" if EXPERT !! 2210
1804 depends on MTRR !! 2211 config SCHED_SMT
1805 select ARCH_USES_PG_ARCH_2 !! 2212 bool "SMT (multithreading) scheduler support"
>> 2213 depends on SYS_SUPPORTS_SCHED_SMT
>> 2214 default n
1806 help 2215 help
1807 Use PAT attributes to setup page le !! 2216 SMT scheduler support improves the CPU scheduler's decision making
>> 2217 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2218 increased overhead in some places. If unsure say N here.
1808 2219
1809 PATs are the modern equivalents of !! 2220 config SYS_SUPPORTS_SCHED_SMT
1810 flexible than MTRRs. !! 2221 bool
1811 2222
1812 Say N here if you see bootup proble !! 2223 config SYS_SUPPORTS_MULTITHREADING
1813 spontaneous reboots) or a non-worki !! 2224 bool
1814 2225
1815 If unsure, say Y. !! 2226 config MIPS_MT_FPAFF
>> 2227 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2228 default y
>> 2229 depends on MIPS_MT_SMP
1816 2230
1817 config X86_UMIP !! 2231 config MIPSR2_TO_R6_EMULATOR
1818 def_bool y !! 2232 bool "MIPS R2-to-R6 emulator"
1819 prompt "User Mode Instruction Prevent !! 2233 depends on CPU_MIPSR6
>> 2234 depends on MIPS_FP_SUPPORT
>> 2235 default y
1820 help 2236 help
1821 User Mode Instruction Prevention (U !! 2237 Choose this option if you want to run non-R6 MIPS userland code.
1822 some x86 processors. If enabled, a !! 2238 Even if you say 'Y' here, the emulator will still be disabled by
1823 issued if the SGDT, SLDT, SIDT, SMS !! 2239 default. You can enable it using the 'mipsr2emu' kernel option.
1824 executed in user mode. These instru !! 2240 The only reason this is a build-time option is to save ~14K from the
1825 information about the hardware stat !! 2241 final kernel image.
1826 <<
1827 The vast majority of applications d <<
1828 For the very few that do, software <<
1829 specific cases in protected and vir <<
1830 results are dummy. <<
1831 <<
1832 config CC_HAS_IBT <<
1833 # GCC >= 9 and binutils >= 2.29 <<
1834 # Retpoline check to work around http <<
1835 # Clang/LLVM >= 14 <<
1836 # https://github.com/llvm/llvm-projec <<
1837 # https://github.com/llvm/llvm-projec <<
1838 def_bool ((CC_IS_GCC && $(cc-option, <<
1839 (CC_IS_CLANG && CLANG_VERSI <<
1840 $(as-instr,endbr64) <<
1841 2242
1842 config X86_CET !! 2243 config SYS_SUPPORTS_VPE_LOADER
1843 def_bool n !! 2244 bool
>> 2245 depends on SYS_SUPPORTS_MULTITHREADING
1844 help 2246 help
1845 CET features configured (Shadow sta !! 2247 Indicates that the platform supports the VPE loader, and provides
>> 2248 physical_memsize.
1846 2249
1847 config X86_KERNEL_IBT !! 2250 config MIPS_VPE_LOADER
1848 prompt "Indirect Branch Tracking" !! 2251 bool "VPE loader support."
1849 def_bool y !! 2252 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
1850 depends on X86_64 && CC_HAS_IBT && HA !! 2253 select CPU_MIPSR2_IRQ_VI
1851 # https://github.com/llvm/llvm-projec !! 2254 select CPU_MIPSR2_IRQ_EI
1852 depends on !LD_IS_LLD || LLD_VERSION !! 2255 select MIPS_MT
1853 select OBJTOOL !! 2256 help
1854 select X86_CET !! 2257 Includes a loader for loading an elf relocatable object
1855 help !! 2258 onto another VPE and running it.
1856 Build the kernel with support for I <<
1857 hardware support course-grain forwa <<
1858 protection. It enforces that all in <<
1859 an ENDBR instruction, as such, the <<
1860 code with them to make this happen. <<
1861 <<
1862 In addition to building the kernel <<
1863 are not indirect call targets, avoi <<
1864 <<
1865 This requires LTO like objtool runs <<
1866 does significantly reduce the numbe <<
1867 kernel image. <<
1868 2259
1869 config X86_INTEL_MEMORY_PROTECTION_KEYS !! 2260 config MIPS_VPE_LOADER_MT
1870 prompt "Memory Protection Keys" !! 2261 bool
1871 def_bool y !! 2262 default "y"
1872 # Note: only available in 64-bit mode !! 2263 depends on MIPS_VPE_LOADER
1873 depends on X86_64 && (CPU_SUP_INTEL | <<
1874 select ARCH_USES_HIGH_VMA_FLAGS <<
1875 select ARCH_HAS_PKEYS <<
1876 help <<
1877 Memory Protection Keys provides a m <<
1878 page-based protections, but without <<
1879 page tables when an application cha <<
1880 2264
1881 For details, see Documentation/core !! 2265 config MIPS_VPE_LOADER_TOM
>> 2266 bool "Load VPE program into memory hidden from linux"
>> 2267 depends on MIPS_VPE_LOADER
>> 2268 default y
>> 2269 help
>> 2270 The loader can use memory that is present but has been hidden from
>> 2271 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2272 you to ensure the amount you put in the option and the space your
>> 2273 program requires is less or equal to the amount physically present.
1882 2274
1883 If unsure, say y. !! 2275 config MIPS_VPE_APSP_API
>> 2276 bool "Enable support for AP/SP API (RTLX)"
>> 2277 depends on MIPS_VPE_LOADER
1884 2278
1885 config ARCH_PKEY_BITS !! 2279 config MIPS_VPE_APSP_API_MT
1886 int !! 2280 bool
1887 default 4 !! 2281 default "y"
>> 2282 depends on MIPS_VPE_APSP_API
1888 2283
1889 choice !! 2284 config MIPS_CPS
1890 prompt "TSX enable mode" !! 2285 bool "MIPS Coherent Processing System support"
1891 depends on CPU_SUP_INTEL !! 2286 depends on SYS_SUPPORTS_MIPS_CPS
1892 default X86_INTEL_TSX_MODE_OFF !! 2287 select MIPS_CM
1893 help !! 2288 select MIPS_CPS_PM if HOTPLUG_CPU
1894 Intel's TSX (Transactional Synchron !! 2289 select SMP
1895 allows to optimize locking protocol !! 2290 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
1896 can lead to a noticeable performanc !! 2291 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2292 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2293 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2294 select SYS_SUPPORTS_SMP
>> 2295 select WEAK_ORDERING
>> 2296 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2297 help
>> 2298 Select this if you wish to run an SMP kernel across multiple cores
>> 2299 within a MIPS Coherent Processing System. When this option is
>> 2300 enabled the kernel will probe for other cores and boot them with
>> 2301 no external assistance. It is safe to enable this when hardware
>> 2302 support is unavailable.
>> 2303
>> 2304 config MIPS_CPS_PM
>> 2305 depends on MIPS_CPS
>> 2306 bool
>> 2307
>> 2308 config MIPS_CM
>> 2309 bool
>> 2310 select MIPS_CPC
1897 2311
1898 On the other hand it has been shown !! 2312 config MIPS_CPC
1899 to form side channel attacks (e.g. !! 2313 bool
1900 will be more of those attacks disco <<
1901 2314
1902 Therefore TSX is not enabled by def !! 2315 config SB1_PASS_2_WORKAROUNDS
1903 might override this decision by tsx !! 2316 bool
1904 Even with TSX enabled, the kernel w !! 2317 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
1905 possible TAA mitigation setting dep !! 2318 default y
1906 for the particular machine. <<
1907 2319
1908 This option allows to set the defau !! 2320 config SB1_PASS_2_1_WORKAROUNDS
1909 and =auto. See Documentation/admin- !! 2321 bool
1910 details. !! 2322 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2323 default y
1911 2324
1912 Say off if not sure, auto if TSX is !! 2325 choice
1913 platforms or on if TSX is in use an !! 2326 prompt "SmartMIPS or microMIPS ASE support"
1914 relevant. <<
1915 2327
1916 config X86_INTEL_TSX_MODE_OFF !! 2328 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
1917 bool "off" !! 2329 bool "None"
1918 help 2330 help
1919 TSX is disabled if possible - equal !! 2331 Select this if you want neither microMIPS nor SmartMIPS support
1920 2332
1921 config X86_INTEL_TSX_MODE_ON !! 2333 config CPU_HAS_SMARTMIPS
1922 bool "on" !! 2334 depends on SYS_SUPPORTS_SMARTMIPS
>> 2335 bool "SmartMIPS"
>> 2336 help
>> 2337 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2338 increased security at both hardware and software level for
>> 2339 smartcards. Enabling this option will allow proper use of the
>> 2340 SmartMIPS instructions by Linux applications. However a kernel with
>> 2341 this option will not work on a MIPS core without SmartMIPS core. If
>> 2342 you don't know you probably don't have SmartMIPS and should say N
>> 2343 here.
>> 2344
>> 2345 config CPU_MICROMIPS
>> 2346 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2347 bool "microMIPS"
1923 help 2348 help
1924 TSX is always enabled on TSX capabl !! 2349 When this option is enabled the kernel will be built using the
1925 line parameter. !! 2350 microMIPS ISA
1926 2351
1927 config X86_INTEL_TSX_MODE_AUTO <<
1928 bool "auto" <<
1929 help <<
1930 TSX is enabled on TSX capable HW th <<
1931 side channel attacks- equals the ts <<
1932 endchoice 2352 endchoice
1933 2353
1934 config X86_SGX !! 2354 config CPU_HAS_MSA
1935 bool "Software Guard eXtensions (SGX) !! 2355 bool "Support for the MIPS SIMD Architecture"
1936 depends on X86_64 && CPU_SUP_INTEL && !! 2356 depends on CPU_SUPPORTS_MSA
1937 depends on CRYPTO=y !! 2357 depends on MIPS_FP_SUPPORT
1938 depends on CRYPTO_SHA256=y !! 2358 depends on 64BIT || MIPS_O32_FP64_SUPPORT
1939 select MMU_NOTIFIER !! 2359 help
1940 select NUMA_KEEP_MEMINFO if NUMA !! 2360 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
1941 select XARRAY_MULTI !! 2361 and a set of SIMD instructions to operate on them. When this option
1942 help !! 2362 is enabled the kernel will support allocating & switching MSA
1943 Intel(R) Software Guard eXtensions !! 2363 vector register contexts. If you know that your kernel will only be
1944 that can be used by applications to !! 2364 running on CPUs which do not support MSA or that your userland will
1945 and data, referred to as enclaves. !! 2365 not be making use of it then you may wish to say N here to reduce
1946 only be accessed by code running wi !! 2366 the size & complexity of your kernel.
1947 outside the enclave, including othe <<
1948 hardware. <<
1949 2367
1950 If unsure, say N. !! 2368 If unsure, say Y.
1951 <<
1952 config X86_USER_SHADOW_STACK <<
1953 bool "X86 userspace shadow stack" <<
1954 depends on AS_WRUSS <<
1955 depends on X86_64 <<
1956 select ARCH_USES_HIGH_VMA_FLAGS <<
1957 select X86_CET <<
1958 help <<
1959 Shadow stack protection is a hardwa <<
1960 return address corruption. This he <<
1961 Applications must be enabled to use <<
1962 get protection "for free". <<
1963 2369
1964 CPUs supporting shadow stacks were !! 2370 config CPU_HAS_WB
>> 2371 bool
1965 2372
1966 See Documentation/arch/x86/shstk.rs !! 2373 config XKS01
>> 2374 bool
1967 2375
1968 If unsure, say N. !! 2376 config CPU_HAS_DIEI
>> 2377 depends on !CPU_DIEI_BROKEN
>> 2378 bool
1969 2379
1970 config INTEL_TDX_HOST !! 2380 config CPU_DIEI_BROKEN
1971 bool "Intel Trust Domain Extensions ( !! 2381 bool
1972 depends on CPU_SUP_INTEL <<
1973 depends on X86_64 <<
1974 depends on KVM_INTEL <<
1975 depends on X86_X2APIC <<
1976 select ARCH_KEEP_MEMBLOCK <<
1977 depends on CONTIG_ALLOC <<
1978 depends on !KEXEC_CORE <<
1979 depends on X86_MCE <<
1980 help <<
1981 Intel Trust Domain Extensions (TDX) <<
1982 host and certain physical attacks. <<
1983 support in the host kernel to run c <<
1984 2382
1985 If unsure, say N. !! 2383 config CPU_HAS_RIXI
>> 2384 bool
1986 2385
1987 config EFI !! 2386 config CPU_NO_LOAD_STORE_LR
1988 bool "EFI runtime service support" !! 2387 bool
1989 depends on ACPI <<
1990 select UCS2_STRING <<
1991 select EFI_RUNTIME_WRAPPERS <<
1992 select ARCH_USE_MEMREMAP_PROT <<
1993 select EFI_RUNTIME_MAP if KEXEC_CORE <<
1994 help <<
1995 This enables the kernel to use EFI <<
1996 available (such as the EFI variable <<
1997 <<
1998 This option is only useful on syste <<
1999 In addition, you should use the lat <<
2000 at <http://elilo.sourceforge.net> i <<
2001 of EFI runtime services. However, e <<
2002 resultant kernel should continue to <<
2003 platforms. <<
2004 <<
2005 config EFI_STUB <<
2006 bool "EFI stub support" <<
2007 depends on EFI <<
2008 select RELOCATABLE <<
2009 help <<
2010 This kernel feature allows a bzImag <<
2011 by EFI firmware without the use of <<
2012 <<
2013 See Documentation/admin-guide/efi-s <<
2014 <<
2015 config EFI_HANDOVER_PROTOCOL <<
2016 bool "EFI handover protocol (DEPRECAT <<
2017 depends on EFI_STUB <<
2018 default y <<
2019 help 2388 help
2020 Select this in order to include sup !! 2389 CPU lacks support for unaligned load and store instructions:
2021 handover protocol, which defines al !! 2390 LWL, LWR, SWL, SWR (Load/store word left/right).
2022 EFI stub. This is a practice that !! 2391 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
2023 specification, and requires a prior !! 2392 systems).
2024 bootloader about Linux/x86 specific <<
2025 and initrd, and where in memory tho <<
2026 <<
2027 If in doubt, say Y. Even though the <<
2028 present in upstream GRUB or other b <<
2029 GRUB with numerous downstream patch <<
2030 handover protocol as as result. <<
2031 <<
2032 config EFI_MIXED <<
2033 bool "EFI mixed-mode support" <<
2034 depends on EFI_STUB && X86_64 <<
2035 help <<
2036 Enabling this feature allows a 64-b <<
2037 on a 32-bit firmware, provided that <<
2038 mode. <<
2039 <<
2040 Note that it is not possible to boo <<
2041 kernel via the EFI boot stub - a bo <<
2042 the EFI handover protocol must be u <<
2043 2393
2044 If unsure, say N. !! 2394 #
>> 2395 # Vectored interrupt mode is an R2 feature
>> 2396 #
>> 2397 config CPU_MIPSR2_IRQ_VI
>> 2398 bool
2045 2399
2046 config EFI_RUNTIME_MAP !! 2400 #
2047 bool "Export EFI runtime maps to sysf !! 2401 # Extended interrupt mode is an R2 feature
2048 depends on EFI !! 2402 #
2049 help !! 2403 config CPU_MIPSR2_IRQ_EI
2050 Export EFI runtime memory regions t !! 2404 bool
2051 That memory map is required by the <<
2052 mappings after kexec, but can also <<
2053 2405
2054 See also Documentation/ABI/testing/ !! 2406 config CPU_HAS_SYNC
>> 2407 bool
>> 2408 depends on !CPU_R3000
>> 2409 default y
2055 2410
2056 source "kernel/Kconfig.hz" !! 2411 #
>> 2412 # CPU non-features
>> 2413 #
2057 2414
2058 config ARCH_SUPPORTS_KEXEC !! 2415 # Work around the "daddi" and "daddiu" CPU errata:
2059 def_bool y !! 2416 #
>> 2417 # - The `daddi' instruction fails to trap on overflow.
>> 2418 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2419 # erratum #23
>> 2420 #
>> 2421 # - The `daddiu' instruction can produce an incorrect result.
>> 2422 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2423 # erratum #41
>> 2424 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2425 # #15
>> 2426 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2427 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2428 config CPU_DADDI_WORKAROUNDS
>> 2429 bool
2060 2430
2061 config ARCH_SUPPORTS_KEXEC_FILE !! 2431 # Work around certain R4000 CPU errata (as implemented by GCC):
2062 def_bool X86_64 !! 2432 #
>> 2433 # - A double-word or a variable shift may give an incorrect result
>> 2434 # if executed immediately after starting an integer division:
>> 2435 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2436 # erratum #28
>> 2437 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2438 # #19
>> 2439 #
>> 2440 # - A double-word or a variable shift may give an incorrect result
>> 2441 # if executed while an integer multiplication is in progress:
>> 2442 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2443 # errata #16 & #28
>> 2444 #
>> 2445 # - An integer division may give an incorrect result if started in
>> 2446 # a delay slot of a taken branch or a jump:
>> 2447 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2448 # erratum #52
>> 2449 config CPU_R4000_WORKAROUNDS
>> 2450 bool
>> 2451 select CPU_R4400_WORKAROUNDS
2063 2452
2064 config ARCH_SELECTS_KEXEC_FILE !! 2453 # Work around certain R4400 CPU errata (as implemented by GCC):
2065 def_bool y !! 2454 #
2066 depends on KEXEC_FILE !! 2455 # - A double-word or a variable shift may give an incorrect result
2067 select HAVE_IMA_KEXEC if IMA !! 2456 # if executed immediately after starting an integer division:
>> 2457 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
>> 2458 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
>> 2459 config CPU_R4400_WORKAROUNDS
>> 2460 bool
2068 2461
2069 config ARCH_SUPPORTS_KEXEC_PURGATORY !! 2462 config CPU_R4X00_BUGS64
2070 def_bool y !! 2463 bool
>> 2464 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
2071 2465
2072 config ARCH_SUPPORTS_KEXEC_SIG !! 2466 config MIPS_ASID_SHIFT
2073 def_bool y !! 2467 int
>> 2468 default 6 if CPU_R3000
>> 2469 default 0
2074 2470
2075 config ARCH_SUPPORTS_KEXEC_SIG_FORCE !! 2471 config MIPS_ASID_BITS
2076 def_bool y !! 2472 int
>> 2473 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2474 default 6 if CPU_R3000
>> 2475 default 8
2077 2476
2078 config ARCH_SUPPORTS_KEXEC_BZIMAGE_VERIFY_SIG !! 2477 config MIPS_ASID_BITS_VARIABLE
2079 def_bool y !! 2478 bool
2080 2479
2081 config ARCH_SUPPORTS_KEXEC_JUMP !! 2480 config MIPS_CRC_SUPPORT
2082 def_bool y !! 2481 bool
2083 2482
2084 config ARCH_SUPPORTS_CRASH_DUMP !! 2483 # R4600 erratum. Due to the lack of errata information the exact
2085 def_bool X86_64 || (X86_32 && HIGHMEM !! 2484 # technical details aren't known. I've experimentally found that disabling
>> 2485 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2486 # with the issue.
>> 2487 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2488 bool
2086 2489
2087 config ARCH_SUPPORTS_CRASH_HOTPLUG !! 2490 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
2088 def_bool y !! 2491 #
>> 2492 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2493 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2494 # executed if there is no other dcache activity. If the dcache is
>> 2495 # accessed for another instruction immediately preceding when these
>> 2496 # cache instructions are executing, it is possible that the dcache
>> 2497 # tag match outputs used by these cache instructions will be
>> 2498 # incorrect. These cache instructions should be preceded by at least
>> 2499 # four instructions that are not any kind of load or store
>> 2500 # instruction.
>> 2501 #
>> 2502 # This is not allowed: lw
>> 2503 # nop
>> 2504 # nop
>> 2505 # nop
>> 2506 # cache Hit_Writeback_Invalidate_D
>> 2507 #
>> 2508 # This is allowed: lw
>> 2509 # nop
>> 2510 # nop
>> 2511 # nop
>> 2512 # nop
>> 2513 # cache Hit_Writeback_Invalidate_D
>> 2514 config WAR_R4600_V1_HIT_CACHEOP
>> 2515 bool
2089 2516
2090 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2517 # Writeback and invalidate the primary cache dcache before DMA.
2091 def_bool CRASH_RESERVE !! 2518 #
>> 2519 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2520 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2521 # operate correctly if the internal data cache refill buffer is empty. These
>> 2522 # CACHE instructions should be separated from any potential data cache miss
>> 2523 # by a load instruction to an uncached address to empty the response buffer."
>> 2524 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2525 # in .pdf format.)
>> 2526 config WAR_R4600_V2_HIT_CACHEOP
>> 2527 bool
2092 2528
2093 config PHYSICAL_START !! 2529 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
2094 hex "Physical address where the kerne !! 2530 # the line which this instruction itself exists, the following
2095 default "0x1000000" !! 2531 # operation is not guaranteed."
2096 help !! 2532 #
2097 This gives the physical address whe !! 2533 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2534 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2535 bool
2098 2536
2099 If the kernel is not relocatable (C !! 2537 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2100 will decompress itself to above phy !! 2538 # opposes it being called that) where invalid instructions in the same
2101 Otherwise, bzImage will run from th !! 2539 # I-cache line worth of instructions being fetched may case spurious
2102 by the boot loader. The only except !! 2540 # exceptions.
2103 above physical address, in which ca !! 2541 config WAR_ICACHE_REFILLS
2104 !! 2542 bool
2105 In normal kdump cases one does not <<
2106 as now bzImage can be compiled as a <<
2107 (CONFIG_RELOCATABLE=y) and be used <<
2108 address. This option is mainly usef <<
2109 to use a bzImage for capturing the <<
2110 vmlinux instead. vmlinux is not rel <<
2111 to be specifically compiled to run <<
2112 (normally a reserved region) and th <<
2113 <<
2114 So if you are using bzImage for cap <<
2115 leave the value here unchanged to 0 <<
2116 CONFIG_RELOCATABLE=y. Otherwise if <<
2117 for capturing the crash dump change <<
2118 the reserved region. In other word <<
2119 the "X" value as specified in the " <<
2120 command line boot parameter passed <<
2121 kernel. Please take a look at Docum <<
2122 for more details about crash dumps. <<
2123 <<
2124 Usage of bzImage for capturing the <<
2125 one does not have to build two kern <<
2126 as production kernel and capture ke <<
2127 gone away after relocatable bzImage <<
2128 is present because there are users <<
2129 vmlinux for dump capture. This opti <<
2130 line. <<
2131 2543
2132 Don't change this unless you know w !! 2544 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
>> 2545 # may cause ll / sc and lld / scd sequences to execute non-atomically.
>> 2546 config WAR_R10000_LLSC
>> 2547 bool
2133 2548
2134 config RELOCATABLE !! 2549 # 34K core erratum: "Problems Executing the TLBR Instruction"
2135 bool "Build a relocatable kernel" !! 2550 config WAR_MIPS34K_MISSED_ITLB
2136 default y !! 2551 bool
2137 help <<
2138 This builds a kernel image that ret <<
2139 so it can be loaded someplace besid <<
2140 The relocations tend to make the ke <<
2141 but are discarded at runtime. <<
2142 2552
2143 One use is for the kexec on panic c !! 2553 #
2144 must live at a different physical a !! 2554 # - Highmem only makes sense for the 32-bit kernel.
2145 kernel. !! 2555 # - The current highmem code will only work properly on physically indexed
2146 !! 2556 # caches such as R3000, SB1, R7000 or those that look like they're virtually
2147 Note: If CONFIG_RELOCATABLE=y, then !! 2557 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
2148 it has been loaded at and the compi !! 2558 # moment we protect the user and offer the highmem option only on machines
2149 (CONFIG_PHYSICAL_START) is used as !! 2559 # where it's known to be safe. This will not offer highmem on a few systems
>> 2560 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2561 # indexed CPUs but we're playing safe.
>> 2562 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2563 # know they might have memory configurations that could make use of highmem
>> 2564 # support.
>> 2565 #
>> 2566 config HIGHMEM
>> 2567 bool "High Memory Support"
>> 2568 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2569 select KMAP_LOCAL
2150 2570
2151 config RANDOMIZE_BASE !! 2571 config CPU_SUPPORTS_HIGHMEM
2152 bool "Randomize the address of the ke !! 2572 bool
2153 depends on RELOCATABLE <<
2154 default y <<
2155 help <<
2156 In support of Kernel Address Space <<
2157 this randomizes the physical addres <<
2158 is decompressed and the virtual add <<
2159 image is mapped, as a security feat <<
2160 attempts relying on knowledge of th <<
2161 code internals. <<
2162 <<
2163 On 64-bit, the kernel physical and <<
2164 randomized separately. The physical <<
2165 between 16MB and the top of physica <<
2166 virtual address will be randomized <<
2167 of entropy). Note that this also re <<
2168 available to kernel modules from 1. <<
2169 <<
2170 On 32-bit, the kernel physical and <<
2171 randomized together. They will be r <<
2172 512MB (8 bits of entropy). <<
2173 <<
2174 Entropy is generated using the RDRA <<
2175 supported. If RDTSC is supported, i <<
2176 the entropy pool as well. If neithe <<
2177 supported, then entropy is read fro <<
2178 usable entropy is limited by the ke <<
2179 2GB addressing, and that PHYSICAL_A <<
2180 minimum of 2MB. As a result, only 1 <<
2181 theoretically possible, but the imp <<
2182 limited due to memory layouts. <<
2183 2573
2184 If unsure, say Y. !! 2574 config SYS_SUPPORTS_HIGHMEM
>> 2575 bool
2185 2576
2186 # Relocation on x86 needs some additional bui !! 2577 config SYS_SUPPORTS_SMARTMIPS
2187 config X86_NEED_RELOCS !! 2578 bool
2188 def_bool y <<
2189 depends on RANDOMIZE_BASE || (X86_32 <<
2190 2579
2191 config PHYSICAL_ALIGN !! 2580 config SYS_SUPPORTS_MICROMIPS
2192 hex "Alignment value to which kernel !! 2581 bool
2193 default "0x200000" !! 2582
2194 range 0x2000 0x1000000 if X86_32 !! 2583 config SYS_SUPPORTS_MIPS16
2195 range 0x200000 0x1000000 if X86_64 !! 2584 bool
2196 help 2585 help
2197 This value puts the alignment restr !! 2586 This option must be set if a kernel might be executed on a MIPS16-
2198 where kernel is loaded and run from !! 2587 enabled CPU even if MIPS16 is not actually being used. In other
2199 address which meets above alignment !! 2588 words, it makes the kernel MIPS16-tolerant.
2200 2589
2201 If bootloader loads the kernel at a !! 2590 config CPU_SUPPORTS_MSA
2202 CONFIG_RELOCATABLE is set, kernel w !! 2591 bool
2203 address aligned to above value and <<
2204 2592
2205 If bootloader loads the kernel at a !! 2593 config ARCH_FLATMEM_ENABLE
2206 CONFIG_RELOCATABLE is not set, kern !! 2594 def_bool y
2207 load address and decompress itself !! 2595 depends on !NUMA && !CPU_LOONGSON2EF
2208 compiled for and run from there. Th <<
2209 compiled already meets above alignm <<
2210 end result is that kernel runs from <<
2211 above alignment restrictions. <<
2212 2596
2213 On 32-bit this value must be a mult !! 2597 config ARCH_SPARSEMEM_ENABLE
2214 this value must be a multiple of 0x !! 2598 bool
>> 2599
>> 2600 config NUMA
>> 2601 bool "NUMA Support"
>> 2602 depends on SYS_SUPPORTS_NUMA
>> 2603 select SMP
>> 2604 select HAVE_SETUP_PER_CPU_AREA
>> 2605 select NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2606 help
>> 2607 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2608 Access). This option improves performance on systems with more
>> 2609 than two nodes; on two node systems it is generally better to
>> 2610 leave it disabled; on single node systems leave this option
>> 2611 disabled.
2215 2612
2216 Don't change this unless you know w !! 2613 config SYS_SUPPORTS_NUMA
>> 2614 bool
2217 2615
2218 config DYNAMIC_MEMORY_LAYOUT !! 2616 config HAVE_ARCH_NODEDATA_EXTENSION
2219 bool 2617 bool
>> 2618
>> 2619 config RELOCATABLE
>> 2620 bool "Relocatable kernel"
>> 2621 depends on SYS_SUPPORTS_RELOCATABLE
>> 2622 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2623 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2624 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2625 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2626 CPU_LOONGSON64
2220 help 2627 help
2221 This option makes base addresses of !! 2628 This builds a kernel image that retains relocation information
2222 __PAGE_OFFSET movable during boot. !! 2629 so it can be loaded someplace besides the default 1MB.
>> 2630 The relocations make the kernel binary about 15% larger,
>> 2631 but are discarded at runtime
2223 2632
2224 config RANDOMIZE_MEMORY !! 2633 config RELOCATION_TABLE_SIZE
2225 bool "Randomize the kernel memory sec !! 2634 hex "Relocation table size"
2226 depends on X86_64 !! 2635 depends on RELOCATABLE
2227 depends on RANDOMIZE_BASE !! 2636 range 0x0 0x01000000
2228 select DYNAMIC_MEMORY_LAYOUT !! 2637 default "0x00200000" if CPU_LOONGSON64
2229 default RANDOMIZE_BASE !! 2638 default "0x00100000"
2230 help 2639 help
2231 Randomizes the base virtual address !! 2640 A table of relocation data will be appended to the kernel binary
2232 (physical memory mapping, vmalloc & !! 2641 and parsed at boot to fix up the relocated kernel.
2233 makes exploits relying on predictab <<
2234 <<
2235 The order of allocations remains un <<
2236 the same way as RANDOMIZE_BASE. Cur <<
2237 configuration have in average 30,00 <<
2238 addresses for each memory section. <<
2239 2642
2240 If unsure, say Y. !! 2643 This option allows the amount of space reserved for the table to be
>> 2644 adjusted, although the default of 1Mb should be ok in most cases.
2241 2645
2242 config RANDOMIZE_MEMORY_PHYSICAL_PADDING !! 2646 The build will fail and a valid size suggested if this is too small.
2243 hex "Physical memory mapping padding" <<
2244 depends on RANDOMIZE_MEMORY <<
2245 default "0xa" if MEMORY_HOTPLUG <<
2246 default "0x0" <<
2247 range 0x1 0x40 if MEMORY_HOTPLUG <<
2248 range 0x0 0x40 <<
2249 help <<
2250 Define the padding in terabytes add <<
2251 memory size during kernel memory ra <<
2252 for memory hotplug support but redu <<
2253 address randomization. <<
2254 2647
2255 If unsure, leave at the default val 2648 If unsure, leave at the default value.
2256 2649
2257 config ADDRESS_MASKING !! 2650 config RANDOMIZE_BASE
2258 bool "Linear Address Masking support" !! 2651 bool "Randomize the address of the kernel image"
2259 depends on X86_64 !! 2652 depends on RELOCATABLE
2260 depends on COMPILE_TEST || !CPU_MITIG <<
2261 help <<
2262 Linear Address Masking (LAM) modifi <<
2263 to 64-bit linear addresses, allowin <<
2264 untranslated address bits for metad <<
2265 <<
2266 The capability can be used for effi <<
2267 implementation and for optimization <<
2268 <<
2269 config HOTPLUG_CPU <<
2270 def_bool y <<
2271 depends on SMP <<
2272 <<
2273 config COMPAT_VDSO <<
2274 def_bool n <<
2275 prompt "Disable the 32-bit vDSO (need <<
2276 depends on COMPAT_32 <<
2277 help 2653 help
2278 Certain buggy versions of glibc wil !! 2654 Randomizes the physical and virtual address at which the
2279 presented with a 32-bit vDSO that i !! 2655 kernel image is loaded, as a security feature that
2280 indicated in its segment table. !! 2656 deters exploit attempts relying on knowledge of the location
2281 !! 2657 of kernel internals.
2282 The bug was introduced by f866314b8 <<
2283 and fixed by 3b3ddb4f7db98ec9e912cc <<
2284 49ad572a70b8aeb91e57483a11dd1b77e31 <<
2285 the only released version with the <<
2286 contains a buggy "glibc 2.3.2". <<
2287 <<
2288 The symptom of the bug is that ever <<
2289 dl_main: Assertion `(void *) ph->p_ <<
2290 <<
2291 Saying Y here changes the default v <<
2292 option from 1 to 0, which turns off <<
2293 This works around the glibc bug but <<
2294 <<
2295 If unsure, say N: if you are compil <<
2296 are unlikely to be using a buggy ve <<
2297 2658
2298 choice !! 2659 Entropy is generated using any coprocessor 0 registers available.
2299 prompt "vsyscall table for legacy app <<
2300 depends on X86_64 <<
2301 default LEGACY_VSYSCALL_XONLY <<
2302 help <<
2303 Legacy user code that does not know <<
2304 to be able to issue three syscalls <<
2305 kernel space. Since this location i <<
2306 it can be used to assist security v <<
2307 <<
2308 This setting can be changed at boot <<
2309 line parameter vsyscall=[emulate|xo <<
2310 is deprecated and can only be enabl <<
2311 line. <<
2312 <<
2313 On a system with recent enough glib <<
2314 static binaries, you can say None w <<
2315 to improve security. <<
2316 <<
2317 If unsure, select "Emulate executio <<
2318 2660
2319 config LEGACY_VSYSCALL_XONLY !! 2661 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
2320 bool "Emulate execution only" <<
2321 help <<
2322 The kernel traps and emulat <<
2323 address mapping and does no <<
2324 configuration is recommende <<
2325 legacy vsyscall area but su <<
2326 instrumentation of legacy c <<
2327 certain uses of the vsyscal <<
2328 buffer. <<
2329 2662
2330 config LEGACY_VSYSCALL_NONE !! 2663 If unsure, say N.
2331 bool "None" <<
2332 help <<
2333 There will be no vsyscall m <<
2334 eliminate any risk of ASLR <<
2335 fixed address mapping. Atte <<
2336 will be reported to dmesg, <<
2337 malicious userspace program <<
2338 2664
2339 endchoice !! 2665 config RANDOMIZE_BASE_MAX_OFFSET
>> 2666 hex "Maximum kASLR offset" if EXPERT
>> 2667 depends on RANDOMIZE_BASE
>> 2668 range 0x0 0x40000000 if EVA || 64BIT
>> 2669 range 0x0 0x08000000
>> 2670 default "0x01000000"
>> 2671 help
>> 2672 When kASLR is active, this provides the maximum offset that will
>> 2673 be applied to the kernel image. It should be set according to the
>> 2674 amount of physical RAM available in the target system minus
>> 2675 PHYSICAL_START and must be a power of 2.
2340 2676
2341 config CMDLINE_BOOL !! 2677 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2342 bool "Built-in kernel command line" !! 2678 EVA or 64-bit. The default is 16Mb.
2343 help <<
2344 Allow for specifying boot arguments <<
2345 build time. On some systems (e.g. <<
2346 necessary or convenient to provide <<
2347 kernel boot arguments with the kern <<
2348 to not rely on the boot loader to p <<
2349 <<
2350 To compile command line arguments i <<
2351 set this option to 'Y', then fill i <<
2352 boot arguments in CONFIG_CMDLINE. <<
2353 <<
2354 Systems with fully functional boot <<
2355 should leave this option set to 'N' <<
2356 <<
2357 config CMDLINE <<
2358 string "Built-in kernel command strin <<
2359 depends on CMDLINE_BOOL <<
2360 default "" <<
2361 help <<
2362 Enter arguments here that should be <<
2363 image and used at boot time. If th <<
2364 command line at boot time, it is ap <<
2365 form the full kernel command line, <<
2366 <<
2367 However, you can use the CONFIG_CMD <<
2368 change this behavior. <<
2369 <<
2370 In most cases, the command line (wh <<
2371 by the boot loader) should specify <<
2372 file system. <<
2373 <<
2374 config CMDLINE_OVERRIDE <<
2375 bool "Built-in command line overrides <<
2376 depends on CMDLINE_BOOL && CMDLINE != <<
2377 help <<
2378 Set this option to 'Y' to have the <<
2379 command line, and use ONLY the buil <<
2380 2679
2381 This is used to work around broken !! 2680 config NODES_SHIFT
2382 be set to 'N' under normal conditio !! 2681 int
>> 2682 default "6"
>> 2683 depends on NUMA
2383 2684
2384 config MODIFY_LDT_SYSCALL !! 2685 config HW_PERF_EVENTS
2385 bool "Enable the LDT (local descripto !! 2686 bool "Enable hardware performance counter support for perf events"
>> 2687 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
2386 default y 2688 default y
2387 help 2689 help
2388 Linux can allow user programs to in !! 2690 Enable hardware performance counter support for perf events. If
2389 Local Descriptor Table (LDT) using !! 2691 disabled, perf events will use software events only.
2390 call. This is required to run 16-b !! 2692
2391 DOSEMU or some Wine programs. It i !! 2693 config DMI
2392 threading libraries. !! 2694 bool "Enable DMI scanning"
2393 !! 2695 depends on MACH_LOONGSON64
2394 Enabling this feature adds a small !! 2696 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
2395 context switches and increases the <<
2396 surface. Disabling it removes the <<
2397 <<
2398 Saying 'N' here may make sense for <<
2399 <<
2400 config STRICT_SIGALTSTACK_SIZE <<
2401 bool "Enforce strict size checking fo <<
2402 depends on DYNAMIC_SIGFRAME <<
2403 help <<
2404 For historical reasons MINSIGSTKSZ <<
2405 already too small with AVX512 suppo <<
2406 enforce strict checking of the siga <<
2407 real size of the FPU frame. This op <<
2408 by default. It can also be controll <<
2409 line option 'strict_sas_size' indep <<
2410 switch. Enabling it might break exi <<
2411 allocate a too small sigaltstack bu <<
2412 never get a signal delivered. <<
2413 <<
2414 Say 'N' unless you want to really e <<
2415 <<
2416 config CFI_AUTO_DEFAULT <<
2417 bool "Attempt to use FineIBT by defau <<
2418 depends on FINEIBT <<
2419 default y 2697 default y
2420 help 2698 help
2421 Attempt to use FineIBT by default a !! 2699 Enabled scanning of DMI to identify machine quirks. Say Y
2422 this is the same as booting with "c !! 2700 here unless you have verified that your setup is not
2423 this is the same as booting with "c !! 2701 affected by entries in the DMI blacklist. Required by PNP
>> 2702 BIOS code.
2424 2703
2425 source "kernel/livepatch/Kconfig" !! 2704 config SMP
>> 2705 bool "Multi-Processing support"
>> 2706 depends on SYS_SUPPORTS_SMP
>> 2707 help
>> 2708 This enables support for systems with more than one CPU. If you have
>> 2709 a system with only one CPU, say N. If you have a system with more
>> 2710 than one CPU, say Y.
2426 2711
2427 endmenu !! 2712 If you say N here, the kernel will run on uni- and multiprocessor
>> 2713 machines, but will use only one CPU of a multiprocessor machine. If
>> 2714 you say Y here, the kernel will run on many, but not all,
>> 2715 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2716 will run faster if you say N here.
2428 2717
2429 config CC_HAS_NAMED_AS !! 2718 People using multiprocessor machines who say Y here should also say
2430 def_bool $(success,echo 'int __seg_fs !! 2719 Y to "Enhanced Real Time Clock Support", below.
2431 depends on CC_IS_GCC <<
2432 2720
2433 config CC_HAS_NAMED_AS_FIXED_SANITIZERS !! 2721 See also the SMP-HOWTO available at
2434 def_bool CC_IS_GCC && GCC_VERSION >= !! 2722 <https://www.tldp.org/docs.html#howto>.
2435 2723
2436 config USE_X86_SEG_SUPPORT !! 2724 If you don't know what to do here, say N.
2437 def_bool y <<
2438 depends on CC_HAS_NAMED_AS <<
2439 # <<
2440 # -fsanitize=kernel-address (KASAN) a <<
2441 # (KCSAN) are incompatible with named <<
2442 # GCC < 13.3 - see GCC PR sanitizer/1 <<
2443 # <<
2444 depends on !(KASAN || KCSAN) || CC_HA <<
2445 2725
2446 config CC_HAS_SLS !! 2726 config HOTPLUG_CPU
2447 def_bool $(cc-option,-mharden-sls=all !! 2727 bool "Support for hot-pluggable CPUs"
>> 2728 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
>> 2729 help
>> 2730 Say Y here to allow turning CPUs off and on. CPUs can be
>> 2731 controlled through /sys/devices/system/cpu.
>> 2732 (Note: power management support will enable this option
>> 2733 automatically on SMP systems. )
>> 2734 Say N if you want to disable CPU hotplug.
2448 2735
2449 config CC_HAS_RETURN_THUNK !! 2736 config SMP_UP
2450 def_bool $(cc-option,-mfunction-retur !! 2737 bool
2451 2738
2452 config CC_HAS_ENTRY_PADDING !! 2739 config SYS_SUPPORTS_MIPS_CPS
2453 def_bool $(cc-option,-fpatchable-func !! 2740 bool
2454 2741
2455 config FUNCTION_PADDING_CFI !! 2742 config SYS_SUPPORTS_SMP
2456 int !! 2743 bool
2457 default 59 if FUNCTION_ALIGNMENT_64B <<
2458 default 27 if FUNCTION_ALIGNMENT_32B <<
2459 default 11 if FUNCTION_ALIGNMENT_16B <<
2460 default 3 if FUNCTION_ALIGNMENT_8B <<
2461 default 0 <<
2462 <<
2463 # Basically: FUNCTION_ALIGNMENT - 5*CFI_CLANG <<
2464 # except Kconfig can't do arithmetic :/ <<
2465 config FUNCTION_PADDING_BYTES <<
2466 int <<
2467 default FUNCTION_PADDING_CFI if CFI_C <<
2468 default FUNCTION_ALIGNMENT <<
2469 2744
2470 config CALL_PADDING !! 2745 config NR_CPUS_DEFAULT_4
2471 def_bool n !! 2746 bool
2472 depends on CC_HAS_ENTRY_PADDING && OB <<
2473 select FUNCTION_ALIGNMENT_16B <<
2474 2747
2475 config FINEIBT !! 2748 config NR_CPUS_DEFAULT_8
2476 def_bool y !! 2749 bool
2477 depends on X86_KERNEL_IBT && CFI_CLAN <<
2478 select CALL_PADDING <<
2479 2750
2480 config HAVE_CALL_THUNKS !! 2751 config NR_CPUS_DEFAULT_16
2481 def_bool y !! 2752 bool
2482 depends on CC_HAS_ENTRY_PADDING && MI <<
2483 2753
2484 config CALL_THUNKS !! 2754 config NR_CPUS_DEFAULT_32
2485 def_bool n !! 2755 bool
2486 select CALL_PADDING <<
2487 2756
2488 config PREFIX_SYMBOLS !! 2757 config NR_CPUS_DEFAULT_64
2489 def_bool y !! 2758 bool
2490 depends on CALL_PADDING && !CFI_CLANG <<
2491 2759
2492 menuconfig CPU_MITIGATIONS !! 2760 config NR_CPUS
2493 bool "Mitigations for CPU vulnerabili !! 2761 int "Maximum number of CPUs (2-256)"
2494 default y !! 2762 range 2 256
>> 2763 depends on SMP
>> 2764 default "4" if NR_CPUS_DEFAULT_4
>> 2765 default "8" if NR_CPUS_DEFAULT_8
>> 2766 default "16" if NR_CPUS_DEFAULT_16
>> 2767 default "32" if NR_CPUS_DEFAULT_32
>> 2768 default "64" if NR_CPUS_DEFAULT_64
2495 help 2769 help
2496 Say Y here to enable options which !! 2770 This allows you to specify the maximum number of CPUs which this
2497 vulnerabilities (usually related to !! 2771 kernel will support. The maximum supported value is 32 for 32-bit
2498 Mitigations can be disabled or rest !! 2772 kernel and 64 for 64-bit kernels; the minimum value which makes
2499 via the "mitigations" kernel parame !! 2773 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2774 and 2 for all others.
>> 2775
>> 2776 This is purely to save memory - each supported CPU adds
>> 2777 approximately eight kilobytes to the kernel image. For best
>> 2778 performance should round up your number of processors to the next
>> 2779 power of two.
2500 2780
2501 If you say N, all mitigations will !! 2781 config MIPS_PERF_SHARED_TC_COUNTERS
2502 overridden at runtime. !! 2782 bool
2503 2783
2504 Say 'Y', unless you really know wha !! 2784 config MIPS_NR_CPU_NR_MAP_1024
>> 2785 bool
2505 2786
2506 if CPU_MITIGATIONS !! 2787 config MIPS_NR_CPU_NR_MAP
>> 2788 int
>> 2789 depends on SMP
>> 2790 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2791 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2507 2792
2508 config MITIGATION_PAGE_TABLE_ISOLATION !! 2793 #
2509 bool "Remove the kernel mapping in us !! 2794 # Timer Interrupt Frequency Configuration
2510 default y !! 2795 #
2511 depends on (X86_64 || X86_PAE) !! 2796
>> 2797 choice
>> 2798 prompt "Timer frequency"
>> 2799 default HZ_250
2512 help 2800 help
2513 This feature reduces the number of !! 2801 Allows the configuration of the timer frequency.
2514 ensuring that the majority of kerne <<
2515 into userspace. <<
2516 2802
2517 See Documentation/arch/x86/pti.rst !! 2803 config HZ_24
>> 2804 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2518 2805
2519 config MITIGATION_RETPOLINE !! 2806 config HZ_48
2520 bool "Avoid speculative indirect bran !! 2807 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2521 select OBJTOOL if HAVE_OBJTOOL <<
2522 default y <<
2523 help <<
2524 Compile kernel with the retpoline c <<
2525 kernel-to-user data leaks by avoidi <<
2526 branches. Requires a compiler with <<
2527 support for full protection. The ke <<
2528 <<
2529 config MITIGATION_RETHUNK <<
2530 bool "Enable return-thunks" <<
2531 depends on MITIGATION_RETPOLINE && CC <<
2532 select OBJTOOL if HAVE_OBJTOOL <<
2533 default y if X86_64 <<
2534 help <<
2535 Compile the kernel with the return- <<
2536 against kernel-to-user data leaks b <<
2537 Requires a compiler with -mfunction <<
2538 support for full protection. The ke <<
2539 <<
2540 config MITIGATION_UNRET_ENTRY <<
2541 bool "Enable UNRET on kernel entry" <<
2542 depends on CPU_SUP_AMD && MITIGATION_ <<
2543 default y <<
2544 help <<
2545 Compile the kernel with support for <<
2546 2808
2547 config MITIGATION_CALL_DEPTH_TRACKING !! 2809 config HZ_100
2548 bool "Mitigate RSB underflow with cal !! 2810 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2549 depends on CPU_SUP_INTEL && HAVE_CALL <<
2550 select HAVE_DYNAMIC_FTRACE_NO_PATCHAB <<
2551 select CALL_THUNKS <<
2552 default y <<
2553 help <<
2554 Compile the kernel with call depth <<
2555 SKL Return-Speculation-Buffer (RSB) <<
2556 mitigation is off by default and ne <<
2557 kernel command line via the retblee <<
2558 non-affected systems the overhead o <<
2559 the call depth tracking is using ru <<
2560 in a compiler generated padding are <<
2561 increases text size by ~5%. For non <<
2562 is unused. On affected SKL systems <<
2563 performance gain over the IBRS miti <<
2564 <<
2565 config CALL_THUNKS_DEBUG <<
2566 bool "Enable call thunks and call dep <<
2567 depends on MITIGATION_CALL_DEPTH_TRAC <<
2568 select FUNCTION_ALIGNMENT_32B <<
2569 default n <<
2570 help <<
2571 Enable call/ret counters for imbala <<
2572 a noisy dmesg about callthunks gene <<
2573 trouble shooting. The debug prints <<
2574 kernel command line with 'debug-cal <<
2575 Only enable this when you are debug <<
2576 creates a noticeable runtime overhe <<
2577 <<
2578 config MITIGATION_IBPB_ENTRY <<
2579 bool "Enable IBPB on kernel entry" <<
2580 depends on CPU_SUP_AMD && X86_64 <<
2581 default y <<
2582 help <<
2583 Compile the kernel with support for <<
2584 2811
2585 config MITIGATION_IBRS_ENTRY !! 2812 config HZ_128
2586 bool "Enable IBRS on kernel entry" !! 2813 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2587 depends on CPU_SUP_INTEL && X86_64 <<
2588 default y <<
2589 help <<
2590 Compile the kernel with support for <<
2591 This mitigates both spectre_v2 and <<
2592 performance. <<
2593 2814
2594 config MITIGATION_SRSO !! 2815 config HZ_250
2595 bool "Mitigate speculative RAS overfl !! 2816 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2596 depends on CPU_SUP_AMD && X86_64 && M <<
2597 default y <<
2598 help <<
2599 Enable the SRSO mitigation needed o <<
2600 2817
2601 config MITIGATION_SLS !! 2818 config HZ_256
2602 bool "Mitigate Straight-Line-Speculat !! 2819 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2603 depends on CC_HAS_SLS && X86_64 <<
2604 select OBJTOOL if HAVE_OBJTOOL <<
2605 default n <<
2606 help <<
2607 Compile the kernel with straight-li <<
2608 against straight line speculation. <<
2609 larger. <<
2610 <<
2611 config MITIGATION_GDS <<
2612 bool "Mitigate Gather Data Sampling" <<
2613 depends on CPU_SUP_INTEL <<
2614 default y <<
2615 help <<
2616 Enable mitigation for Gather Data S <<
2617 vulnerability which allows unprivil <<
2618 which was previously stored in vect <<
2619 instructions to infer the stale vec <<
2620 <<
2621 config MITIGATION_RFDS <<
2622 bool "RFDS Mitigation" <<
2623 depends on CPU_SUP_INTEL <<
2624 default y <<
2625 help <<
2626 Enable mitigation for Register File <<
2627 RFDS is a hardware vulnerability wh <<
2628 allows unprivileged speculative acc <<
2629 stored in floating point, vector an <<
2630 See also <file:Documentation/admin- <<
2631 <<
2632 config MITIGATION_SPECTRE_BHI <<
2633 bool "Mitigate Spectre-BHB (Branch Hi <<
2634 depends on CPU_SUP_INTEL <<
2635 default y <<
2636 help <<
2637 Enable BHI mitigations. BHI attacks <<
2638 where the branch history buffer is <<
2639 indirect branches. <<
2640 See <file:Documentation/admin-guide <<
2641 <<
2642 config MITIGATION_MDS <<
2643 bool "Mitigate Microarchitectural Dat <<
2644 depends on CPU_SUP_INTEL <<
2645 default y <<
2646 help <<
2647 Enable mitigation for Microarchitec <<
2648 a hardware vulnerability which allo <<
2649 to data which is available in vario <<
2650 See also <file:Documentation/admin- <<
2651 <<
2652 config MITIGATION_TAA <<
2653 bool "Mitigate TSX Asynchronous Abort <<
2654 depends on CPU_SUP_INTEL <<
2655 default y <<
2656 help <<
2657 Enable mitigation for TSX Asynchron <<
2658 vulnerability that allows unprivile <<
2659 which is available in various CPU i <<
2660 asynchronous aborts within an Intel <<
2661 See also <file:Documentation/admin- <<
2662 <<
2663 config MITIGATION_MMIO_STALE_DATA <<
2664 bool "Mitigate MMIO Stale Data hardwa <<
2665 depends on CPU_SUP_INTEL <<
2666 default y <<
2667 help <<
2668 Enable mitigation for MMIO Stale Da <<
2669 Stale Data Vulnerabilities are a cl <<
2670 vulnerabilities that can expose dat <<
2671 attacker to have access to MMIO. <<
2672 See also <<
2673 <file:Documentation/admin-guide/hw- <<
2674 <<
2675 config MITIGATION_L1TF <<
2676 bool "Mitigate L1 Terminal Fault (L1T <<
2677 depends on CPU_SUP_INTEL <<
2678 default y <<
2679 help <<
2680 Mitigate L1 Terminal Fault (L1TF) h <<
2681 hardware vulnerability which allows <<
2682 available in the Level 1 Data Cache <<
2683 See <file:Documentation/admin-guide <<
2684 <<
2685 config MITIGATION_RETBLEED <<
2686 bool "Mitigate RETBleed hardware bug" <<
2687 depends on (CPU_SUP_INTEL && MITIGATI <<
2688 default y <<
2689 help <<
2690 Enable mitigation for RETBleed (Arb <<
2691 with Return Instructions) vulnerabi <<
2692 execution attack which takes advant <<
2693 in many modern microprocessors, sim <<
2694 unprivileged attacker can use these <<
2695 memory security restrictions to gai <<
2696 that would otherwise be inaccessibl <<
2697 2820
2698 config MITIGATION_SPECTRE_V1 !! 2821 config HZ_1000
2699 bool "Mitigate SPECTRE V1 hardware bu !! 2822 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
2700 default y <<
2701 help <<
2702 Enable mitigation for Spectre V1 (B <<
2703 class of side channel attacks that <<
2704 execution that bypasses conditional <<
2705 memory access bounds check. <<
2706 See also <file:Documentation/admin- <<
2707 2823
2708 config MITIGATION_SPECTRE_V2 !! 2824 config HZ_1024
2709 bool "Mitigate SPECTRE V2 hardware bu !! 2825 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2710 default y <<
2711 help <<
2712 Enable mitigation for Spectre V2 (B <<
2713 V2 is a class of side channel attac <<
2714 indirect branch predictors inside t <<
2715 attacks, the attacker can steer spe <<
2716 victim to gadget code by poisoning <<
2717 used for predicting indirect branch <<
2718 See also <file:Documentation/admin- <<
2719 <<
2720 config MITIGATION_SRBDS <<
2721 bool "Mitigate Special Register Buffe <<
2722 depends on CPU_SUP_INTEL <<
2723 default y <<
2724 help <<
2725 Enable mitigation for Special Regis <<
2726 SRBDS is a hardware vulnerability t <<
2727 Sampling (MDS) techniques to infer <<
2728 register accesses. An unprivileged <<
2729 from RDRAND and RDSEED executed on <<
2730 using MDS techniques. <<
2731 See also <<
2732 <file:Documentation/admin-guide/hw- <<
2733 2826
2734 config MITIGATION_SSB !! 2827 endchoice
2735 bool "Mitigate Speculative Store Bypa <<
2736 default y <<
2737 help <<
2738 Enable mitigation for Speculative S <<
2739 hardware security vulnerability and <<
2740 of speculative execution in a simil <<
2741 security vulnerabilities. <<
2742 2828
2743 endif !! 2829 config SYS_SUPPORTS_24HZ
>> 2830 bool
2744 2831
2745 config ARCH_HAS_ADD_PAGES !! 2832 config SYS_SUPPORTS_48HZ
2746 def_bool y !! 2833 bool
2747 depends on ARCH_ENABLE_MEMORY_HOTPLUG <<
2748 2834
2749 menu "Power management and ACPI options" !! 2835 config SYS_SUPPORTS_100HZ
>> 2836 bool
2750 2837
2751 config ARCH_HIBERNATION_HEADER !! 2838 config SYS_SUPPORTS_128HZ
2752 def_bool y !! 2839 bool
2753 depends on HIBERNATION <<
2754 2840
2755 source "kernel/power/Kconfig" !! 2841 config SYS_SUPPORTS_250HZ
>> 2842 bool
2756 2843
2757 source "drivers/acpi/Kconfig" !! 2844 config SYS_SUPPORTS_256HZ
>> 2845 bool
2758 2846
2759 config X86_APM_BOOT !! 2847 config SYS_SUPPORTS_1000HZ
2760 def_bool y !! 2848 bool
2761 depends on APM !! 2849
>> 2850 config SYS_SUPPORTS_1024HZ
>> 2851 bool
2762 2852
2763 menuconfig APM !! 2853 config SYS_SUPPORTS_ARBIT_HZ
2764 tristate "APM (Advanced Power Managem !! 2854 bool
2765 depends on X86_32 && PM_SLEEP !! 2855 default y if !SYS_SUPPORTS_24HZ && \
2766 help !! 2856 !SYS_SUPPORTS_48HZ && \
2767 APM is a BIOS specification for sav !! 2857 !SYS_SUPPORTS_100HZ && \
2768 techniques. This is mostly useful f !! 2858 !SYS_SUPPORTS_128HZ && \
2769 APM compliant BIOSes. If you say Y !! 2859 !SYS_SUPPORTS_250HZ && \
2770 reset after a RESUME operation, the !! 2860 !SYS_SUPPORTS_256HZ && \
2771 battery status information, and use !! 2861 !SYS_SUPPORTS_1000HZ && \
2772 notification of APM "events" (e.g. !! 2862 !SYS_SUPPORTS_1024HZ
2773 <<
2774 If you select "Y" here, you can dis <<
2775 BIOS by passing the "apm=off" optio <<
2776 <<
2777 Note that the APM support is almost <<
2778 machines with more than one CPU. <<
2779 <<
2780 In order to use APM, you will need <<
2781 and more information, read <file:Do <<
2782 and the Battery Powered Linux mini- <<
2783 <http://www.tldp.org/docs.html#howt <<
2784 <<
2785 This driver does not spin down disk <<
2786 manpage ("man 8 hdparm") for that), <<
2787 VESA-compliant "green" monitors. <<
2788 <<
2789 This driver does not support the TI <<
2790 486/DX4/75 because they don't have <<
2791 desktop machines also don't have co <<
2792 may cause those machines to panic d <<
2793 <<
2794 Generally, if you don't have a batt <<
2795 much point in using this driver and <<
2796 random kernel OOPSes or reboots tha <<
2797 anything, try disabling/enabling th <<
2798 APM in your BIOS). <<
2799 <<
2800 Some other things you should try wh <<
2801 "weird" problems: <<
2802 <<
2803 1) make sure that you have enough s <<
2804 enabled. <<
2805 2) pass the "idle=poll" option to t <<
2806 3) switch on floating point emulati <<
2807 the "no387" option to the kernel <<
2808 4) pass the "floppy=nodma" option t <<
2809 5) pass the "mem=4M" option to the <<
2810 all but the first 4 MB of RAM) <<
2811 6) make sure that the CPU is not ov <<
2812 7) read the sig11 FAQ at <http://ww <<
2813 8) disable the cache from your BIOS <<
2814 9) install a fan for the video card <<
2815 10) install a better fan for the CP <<
2816 11) exchange RAM chips <<
2817 12) exchange the motherboard. <<
2818 <<
2819 To compile this driver as a module, <<
2820 module will be called apm. <<
2821 <<
2822 if APM <<
2823 <<
2824 config APM_IGNORE_USER_SUSPEND <<
2825 bool "Ignore USER SUSPEND" <<
2826 help <<
2827 This option will ignore USER SUSPEN <<
2828 compliant APM BIOS, you want to say <<
2829 series notebooks, it is necessary t <<
2830 <<
2831 config APM_DO_ENABLE <<
2832 bool "Enable PM at boot time" <<
2833 help <<
2834 Enable APM features at boot time. F <<
2835 specification: "When disabled, the <<
2836 power manage devices, enter the Sta <<
2837 State, or take power saving steps i <<
2838 This driver will make CPU Idle call <<
2839 feature is turned off -- see "Do CP <<
2840 should always save battery power, b <<
2841 will be dependent on your BIOS impl <<
2842 this option off if your computer ha <<
2843 support, or if it beeps continuousl <<
2844 this off if you have a NEC UltraLit <<
2845 T400CDT. This is off by default sin <<
2846 this feature. <<
2847 <<
2848 config APM_CPU_IDLE <<
2849 depends on CPU_IDLE <<
2850 bool "Make CPU Idle calls when idle" <<
2851 help <<
2852 Enable calls to APM CPU Idle/CPU Bu <<
2853 On some machines, this can activate <<
2854 a slowed CPU clock rate, when the m <<
2855 are made after the idle loop has ru <<
2856 333 mS). On some machines, this wil <<
2857 whenever the CPU becomes idle. (On <<
2858 this option does nothing.) <<
2859 <<
2860 config APM_DISPLAY_BLANK <<
2861 bool "Enable console blanking using A <<
2862 help <<
2863 Enable console blanking using the A <<
2864 turn off the LCD backlight when the <<
2865 virtual console blanks the screen. <<
2866 the virtual console screen blanker, <<
2867 when using the X Window system. Thi <<
2868 do with your VESA-compliant power-s <<
2869 option doesn't work for all laptops <<
2870 backlight at all, or it might print <<
2871 especially if you are using gpm. <<
2872 <<
2873 config APM_ALLOW_INTS <<
2874 bool "Allow interrupts during APM BIO <<
2875 help <<
2876 Normally we disable external interr <<
2877 the APM BIOS as a measure to lessen <<
2878 BIOS implementation. The BIOS shou <<
2879 needs to. Unfortunately, some BIOS <<
2880 many of the newer IBM Thinkpads. I <<
2881 suspend, try setting this to Y. Ot <<
2882 2863
2883 endif # APM !! 2864 config HZ
>> 2865 int
>> 2866 default 24 if HZ_24
>> 2867 default 48 if HZ_48
>> 2868 default 100 if HZ_100
>> 2869 default 128 if HZ_128
>> 2870 default 250 if HZ_250
>> 2871 default 256 if HZ_256
>> 2872 default 1000 if HZ_1000
>> 2873 default 1024 if HZ_1024
2884 2874
2885 source "drivers/cpufreq/Kconfig" !! 2875 config SCHED_HRTICK
>> 2876 def_bool HIGH_RES_TIMERS
2886 2877
2887 source "drivers/cpuidle/Kconfig" !! 2878 config ARCH_SUPPORTS_KEXEC
>> 2879 def_bool y
2888 2880
2889 source "drivers/idle/Kconfig" !! 2881 config ARCH_SUPPORTS_CRASH_DUMP
>> 2882 def_bool y
2890 2883
2891 endmenu !! 2884 config PHYSICAL_START
>> 2885 hex "Physical address where the kernel is loaded"
>> 2886 default "0xffffffff84000000"
>> 2887 depends on CRASH_DUMP
>> 2888 help
>> 2889 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2890 If you plan to use kernel for capturing the crash dump change
>> 2891 this value to start of the reserved region (the "X" value as
>> 2892 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2893 passed to the panic-ed kernel).
>> 2894
>> 2895 config MIPS_O32_FP64_SUPPORT
>> 2896 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2897 depends on 32BIT || MIPS32_O32
>> 2898 help
>> 2899 When this is enabled, the kernel will support use of 64-bit floating
>> 2900 point registers with binaries using the O32 ABI along with the
>> 2901 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2902 32-bit MIPS systems this support is at the cost of increasing the
>> 2903 size and complexity of the compiled FPU emulator. Thus if you are
>> 2904 running a MIPS32 system and know that none of your userland binaries
>> 2905 will require 64-bit floating point, you may wish to reduce the size
>> 2906 of your kernel & potentially improve FP emulation performance by
>> 2907 saying N here.
>> 2908
>> 2909 Although binutils currently supports use of this flag the details
>> 2910 concerning its effect upon the O32 ABI in userland are still being
>> 2911 worked on. In order to avoid userland becoming dependent upon current
>> 2912 behaviour before the details have been finalised, this option should
>> 2913 be considered experimental and only enabled by those working upon
>> 2914 said details.
2892 2915
2893 menu "Bus options (PCI etc.)" !! 2916 If unsure, say N.
>> 2917
>> 2918 config USE_OF
>> 2919 bool
>> 2920 select OF
>> 2921 select OF_EARLY_FLATTREE
>> 2922 select IRQ_DOMAIN
>> 2923
>> 2924 config UHI_BOOT
>> 2925 bool
>> 2926
>> 2927 config BUILTIN_DTB
>> 2928 bool
2894 2929
2895 choice 2930 choice
2896 prompt "PCI access mode" !! 2931 prompt "Kernel appended dtb support"
2897 depends on X86_32 && PCI !! 2932 depends on USE_OF
2898 default PCI_GOANY !! 2933 default MIPS_NO_APPENDED_DTB
2899 help !! 2934
2900 On PCI systems, the BIOS can be use !! 2935 config MIPS_NO_APPENDED_DTB
2901 determine their configuration. Howe !! 2936 bool "None"
2902 have BIOS bugs and may crash if thi !! 2937 help
2903 PCI-based systems don't have any BI !! 2938 Do not enable appended dtb support.
2904 detect the PCI hardware directly wi <<
2905 <<
2906 With this option, you can specify h <<
2907 PCI devices. If you choose "BIOS", <<
2908 if you choose "Direct", the BIOS wo <<
2909 choose "MMConfig", then PCI Express <<
2910 If you choose "Any", the kernel wil <<
2911 direct access method and falls back <<
2912 work. If unsure, go with the defaul <<
2913 <<
2914 config PCI_GOBIOS <<
2915 bool "BIOS" <<
2916 <<
2917 config PCI_GOMMCONFIG <<
2918 bool "MMConfig" <<
2919 <<
2920 config PCI_GODIRECT <<
2921 bool "Direct" <<
2922 <<
2923 config PCI_GOOLPC <<
2924 bool "OLPC XO-1" <<
2925 depends on OLPC <<
2926 2939
2927 config PCI_GOANY !! 2940 config MIPS_ELF_APPENDED_DTB
2928 bool "Any" !! 2941 bool "vmlinux"
>> 2942 help
>> 2943 With this option, the boot code will look for a device tree binary
>> 2944 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2945 it is empty and the DTB can be appended using binutils command
>> 2946 objcopy:
>> 2947
>> 2948 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2949
>> 2950 This is meant as a backward compatibility convenience for those
>> 2951 systems with a bootloader that can't be upgraded to accommodate
>> 2952 the documented boot protocol using a device tree.
2929 2953
>> 2954 config MIPS_RAW_APPENDED_DTB
>> 2955 bool "vmlinux.bin or vmlinuz.bin"
>> 2956 help
>> 2957 With this option, the boot code will look for a device tree binary
>> 2958 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2959 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2960
>> 2961 This is meant as a backward compatibility convenience for those
>> 2962 systems with a bootloader that can't be upgraded to accommodate
>> 2963 the documented boot protocol using a device tree.
>> 2964
>> 2965 Beware that there is very little in terms of protection against
>> 2966 this option being confused by leftover garbage in memory that might
>> 2967 look like a DTB header after a reboot if no actual DTB is appended
>> 2968 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2969 if you don't intend to always append a DTB.
2930 endchoice 2970 endchoice
2931 2971
2932 config PCI_BIOS !! 2972 choice
2933 def_bool y !! 2973 prompt "Kernel command line type"
2934 depends on X86_32 && PCI && (PCI_GOBI !! 2974 depends on !CMDLINE_OVERRIDE
>> 2975 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 2976 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 2977 !CAVIUM_OCTEON_SOC
>> 2978 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2979
>> 2980 config MIPS_CMDLINE_FROM_DTB
>> 2981 depends on USE_OF
>> 2982 bool "Dtb kernel arguments if available"
>> 2983
>> 2984 config MIPS_CMDLINE_DTB_EXTEND
>> 2985 depends on USE_OF
>> 2986 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2987
>> 2988 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2989 bool "Bootloader kernel arguments if available"
>> 2990
>> 2991 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2992 depends on CMDLINE_BOOL
>> 2993 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2994 endchoice
2935 2995
2936 # x86-64 doesn't support PCI BIOS access from !! 2996 endmenu
2937 config PCI_DIRECT <<
2938 def_bool y <<
2939 depends on PCI && (X86_64 || (PCI_GOD <<
2940 2997
2941 config PCI_MMCONFIG !! 2998 config LOCKDEP_SUPPORT
2942 bool "Support mmconfig PCI config spa !! 2999 bool
2943 default y 3000 default y
2944 depends on PCI && (ACPI || JAILHOUSE_ <<
2945 depends on X86_64 || (PCI_GOANY || PC <<
2946 3001
2947 config PCI_OLPC !! 3002 config STACKTRACE_SUPPORT
2948 def_bool y !! 3003 bool
2949 depends on PCI && OLPC && (PCI_GOOLPC !! 3004 default y
2950 3005
2951 config PCI_XEN !! 3006 config PGTABLE_LEVELS
2952 def_bool y !! 3007 int
2953 depends on PCI && XEN !! 3008 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3009 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3010 default 2
2954 3011
2955 config MMCONF_FAM10H !! 3012 config MIPS_AUTO_PFN_OFFSET
2956 def_bool y !! 3013 bool
2957 depends on X86_64 && PCI_MMCONFIG && <<
2958 3014
2959 config PCI_CNB20LE_QUIRK !! 3015 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
2960 bool "Read CNB20LE Host Bridge Window <<
2961 depends on PCI <<
2962 help <<
2963 Read the PCI windows out of the CNB <<
2964 PCI hotplug to work on systems with <<
2965 not have ACPI. <<
2966 3016
2967 There's no public spec for this chi !! 3017 config PCI_DRIVERS_GENERIC
2968 is known to be incomplete. !! 3018 select PCI_DOMAINS_GENERIC if PCI
>> 3019 bool
2969 3020
2970 You should say N unless you know yo !! 3021 config PCI_DRIVERS_LEGACY
>> 3022 def_bool !PCI_DRIVERS_GENERIC
>> 3023 select NO_GENERIC_PCI_IOPORT_MAP
>> 3024 select PCI_DOMAINS if PCI
2971 3025
2972 config ISA_BUS !! 3026 #
2973 bool "ISA bus support on modern syste !! 3027 # ISA support is now enabled via select. Too many systems still have the one
2974 help !! 3028 # or other ISA chip on the board that users don't know about so don't expect
2975 Expose ISA bus device drivers and o !! 3029 # users to choose the right thing ...
2976 configuration. Enable this option i !! 3030 #
2977 bus. ISA is an older system, displa !! 3031 config ISA
2978 architectures -- if your target mac !! 3032 bool
2979 not have an ISA bus. <<
2980 3033
2981 If unsure, say N. !! 3034 config TC
>> 3035 bool "TURBOchannel support"
>> 3036 depends on MACH_DECSTATION
>> 3037 help
>> 3038 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3039 processors. TURBOchannel programming specifications are available
>> 3040 at:
>> 3041 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3042 and:
>> 3043 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3044 Linux driver support status is documented at:
>> 3045 <http://www.linux-mips.org/wiki/DECstation>
2982 3046
2983 # x86_64 have no ISA slots, but can have ISA- !! 3047 config MMU
2984 config ISA_DMA_API !! 3048 bool
2985 bool "ISA-style DMA support" if (X86_ <<
2986 default y 3049 default y
2987 help <<
2988 Enables ISA-style DMA support for d <<
2989 If unsure, say Y. <<
2990 3050
2991 if X86_32 !! 3051 config ARCH_MMAP_RND_BITS_MIN
>> 3052 default 12 if 64BIT
>> 3053 default 8
2992 3054
2993 config ISA !! 3055 config ARCH_MMAP_RND_BITS_MAX
2994 bool "ISA support" !! 3056 default 18 if 64BIT
2995 help !! 3057 default 15
2996 Find out whether you have ISA slots <<
2997 name of a bus system, i.e. the way <<
2998 inside your box. Other bus systems <<
2999 (MCA) or VESA. ISA is an older sys <<
3000 newer boards don't support it. If <<
3001 <<
3002 config SCx200 <<
3003 tristate "NatSemi SCx200 support" <<
3004 help <<
3005 This provides basic support for Nat <<
3006 (now AMD's) Geode processors. The <<
3007 PCI-IDs of several on-chip devices, <<
3008 for other scx200_* drivers. <<
3009 <<
3010 If compiled as a module, the driver <<
3011 <<
3012 config SCx200HR_TIMER <<
3013 tristate "NatSemi SCx200 27MHz High-R <<
3014 depends on SCx200 <<
3015 default y <<
3016 help <<
3017 This driver provides a clocksource <<
3018 27MHz high-resolution timer. Its a <<
3019 NSC Geode SC-1100's buggy TSC, whic <<
3020 processor goes idle (as is done by <<
3021 other workaround is idle=poll boot <<
3022 <<
3023 config OLPC <<
3024 bool "One Laptop Per Child support" <<
3025 depends on !X86_PAE <<
3026 select GPIOLIB <<
3027 select OF <<
3028 select OF_PROMTREE <<
3029 select IRQ_DOMAIN <<
3030 select OLPC_EC <<
3031 help <<
3032 Add support for detecting the uniqu <<
3033 XO hardware. <<
3034 3058
3035 config OLPC_XO1_PM !! 3059 config ARCH_MMAP_RND_COMPAT_BITS_MIN
3036 bool "OLPC XO-1 Power Management" !! 3060 default 8
3037 depends on OLPC && MFD_CS5535=y && PM <<
3038 help <<
3039 Add support for poweroff and suspen <<
3040 3061
3041 config OLPC_XO1_RTC !! 3062 config ARCH_MMAP_RND_COMPAT_BITS_MAX
3042 bool "OLPC XO-1 Real Time Clock" !! 3063 default 15
3043 depends on OLPC_XO1_PM && RTC_DRV_CMO <<
3044 help <<
3045 Add support for the XO-1 real time <<
3046 programmable wakeup source. <<
3047 3064
3048 config OLPC_XO1_SCI !! 3065 config I8253
3049 bool "OLPC XO-1 SCI extras" !! 3066 bool
3050 depends on OLPC && OLPC_XO1_PM && GPI !! 3067 select CLKSRC_I8253
3051 depends on INPUT=y !! 3068 select CLKEVT_I8253
3052 select POWER_SUPPLY !! 3069 select MIPS_EXTERNAL_TIMER
3053 help !! 3070 endmenu
3054 Add support for SCI-based features <<
3055 - EC-driven system wakeups <<
3056 - Power button <<
3057 - Ebook switch <<
3058 - Lid switch <<
3059 - AC adapter status updates <<
3060 - Battery status updates <<
3061 3071
3062 config OLPC_XO15_SCI !! 3072 config TRAD_SIGNALS
3063 bool "OLPC XO-1.5 SCI extras" !! 3073 bool
3064 depends on OLPC && ACPI <<
3065 select POWER_SUPPLY <<
3066 help <<
3067 Add support for SCI-based features <<
3068 - EC-driven system wakeups <<
3069 - AC adapter status updates <<
3070 - Battery status updates <<
3071 3074
3072 config GEODE_COMMON !! 3075 config MIPS32_COMPAT
3073 bool 3076 bool
3074 3077
3075 config ALIX !! 3078 config COMPAT
3076 bool "PCEngines ALIX System Support ( !! 3079 bool
3077 select GPIOLIB !! 3080
3078 select GEODE_COMMON !! 3081 config MIPS32_O32
>> 3082 bool "Kernel support for o32 binaries"
>> 3083 depends on 64BIT
>> 3084 select ARCH_WANT_OLD_COMPAT_IPC
>> 3085 select COMPAT
>> 3086 select MIPS32_COMPAT
3079 help 3087 help
3080 This option enables system support !! 3088 Select this option if you want to run o32 binaries. These are pure
3081 At present this just sets up LEDs f !! 3089 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3082 ALIX2/3/6 boards. However, other s !! 3090 existing binaries are in this format.
3083 get added here. <<
3084 3091
3085 Note: You must still enable the dri !! 3092 If unsure, say Y.
3086 (GPIO_CS5535 & LEDS_GPIO) to actual <<
3087 3093
3088 Note: You have to set alix.force=1 !! 3094 config MIPS32_N32
>> 3095 bool "Kernel support for n32 binaries"
>> 3096 depends on 64BIT
>> 3097 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3098 select COMPAT
>> 3099 select MIPS32_COMPAT
>> 3100 help
>> 3101 Select this option if you want to run n32 binaries. These are
>> 3102 64-bit binaries using 32-bit quantities for addressing and certain
>> 3103 data that would normally be 64-bit. They are used in special
>> 3104 cases.
3089 3105
3090 config NET5501 !! 3106 If unsure, say N.
3091 bool "Soekris Engineering net5501 Sys <<
3092 select GPIOLIB <<
3093 select GEODE_COMMON <<
3094 help <<
3095 This option enables system support <<
3096 3107
3097 config GEOS !! 3108 config CC_HAS_MNO_BRANCH_LIKELY
3098 bool "Traverse Technologies GEOS Syst !! 3109 def_bool y
3099 select GPIOLIB !! 3110 depends on $(cc-option,-mno-branch-likely)
3100 select GEODE_COMMON <<
3101 depends on DMI <<
3102 help <<
3103 This option enables system support <<
3104 3111
3105 config TS5500 !! 3112 # https://github.com/llvm/llvm-project/issues/61045
3106 bool "Technologic Systems TS-5500 pla !! 3113 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
3107 depends on MELAN !! 3114 def_bool y if CC_IS_CLANG
3108 select CHECK_SIGNATURE <<
3109 select NEW_LEDS <<
3110 select LEDS_CLASS <<
3111 help <<
3112 This option enables system support <<
3113 3115
3114 endif # X86_32 !! 3116 menu "Power management options"
3115 3117
3116 config AMD_NB !! 3118 config ARCH_HIBERNATION_POSSIBLE
3117 def_bool y 3119 def_bool y
3118 depends on CPU_SUP_AMD && PCI !! 3120 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3119 3121
3120 endmenu !! 3122 config ARCH_SUSPEND_POSSIBLE
>> 3123 def_bool y
>> 3124 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3121 3125
3122 menu "Binary Emulations" !! 3126 source "kernel/power/Kconfig"
3123 3127
3124 config IA32_EMULATION !! 3128 endmenu
3125 bool "IA32 Emulation" <<
3126 depends on X86_64 <<
3127 select ARCH_WANT_OLD_COMPAT_IPC <<
3128 select BINFMT_ELF <<
3129 select COMPAT_OLD_SIGACTION <<
3130 help <<
3131 Include code to run legacy 32-bit p <<
3132 64-bit kernel. You should likely tu <<
3133 100% sure that you don't have any 3 <<
3134 3129
3135 config IA32_EMULATION_DEFAULT_DISABLED !! 3130 config MIPS_EXTERNAL_TIMER
3136 bool "IA32 emulation disabled by defa !! 3131 bool
3137 default n <<
3138 depends on IA32_EMULATION <<
3139 help <<
3140 Make IA32 emulation disabled by def <<
3141 processes and access to 32-bit sysc <<
3142 default value. <<
3143 <<
3144 config X86_X32_ABI <<
3145 bool "x32 ABI for 64-bit mode" <<
3146 depends on X86_64 <<
3147 # llvm-objcopy does not convert x86_6 <<
3148 # compressed debug sections to x86_x3 <<
3149 # https://github.com/ClangBuiltLinux/ <<
3150 # https://github.com/ClangBuiltLinux/ <<
3151 depends on $(success,$(OBJCOPY) --ver <<
3152 help <<
3153 Include code to run binaries for th <<
3154 for 64-bit processors. An x32 proc <<
3155 full 64-bit register file and wide <<
3156 pointers at 32 bits for smaller mem <<
3157 3132
3158 config COMPAT_32 !! 3133 menu "CPU Power Management"
3159 def_bool y <<
3160 depends on IA32_EMULATION || X86_32 <<
3161 select HAVE_UID16 <<
3162 select OLD_SIGSUSPEND3 <<
3163 3134
3164 config COMPAT !! 3135 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3165 def_bool y !! 3136 source "drivers/cpufreq/Kconfig"
3166 depends on IA32_EMULATION || X86_X32_ !! 3137 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
3167 3138
3168 config COMPAT_FOR_U64_ALIGNMENT !! 3139 source "drivers/cpuidle/Kconfig"
3169 def_bool y <<
3170 depends on COMPAT <<
3171 3140
3172 endmenu 3141 endmenu
3173 3142
3174 config HAVE_ATOMIC_IOMAP !! 3143 source "arch/mips/kvm/Kconfig"
3175 def_bool y <<
3176 depends on X86_32 <<
3177 <<
3178 source "arch/x86/kvm/Kconfig" <<
3179 3144
3180 source "arch/x86/Kconfig.assembler" !! 3145 source "arch/mips/vdso/Kconfig"
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