1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 # Select 32 or 64 bit !! 2 config MIPS
3 config 64BIT !! 3 bool
4 bool "64-bit kernel" if "$(ARCH)" = "x !! 4 default y
5 default "$(ARCH)" != "i386" !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 help !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 Say yes to build a 64-bit kernel - f !! 7 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
8 Say no to build a 32-bit kernel - fo !! 8 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
9 <<
10 config X86_32 <<
11 def_bool y <<
12 depends on !64BIT <<
13 # Options that are inherently 32-bit k <<
14 select ARCH_WANT_IPC_PARSE_VERSION <<
15 select CLKSRC_I8253 <<
16 select CLONE_BACKWARDS <<
17 select GENERIC_VDSO_32 <<
18 select HAVE_DEBUG_STACKOVERFLOW <<
19 select KMAP_LOCAL <<
20 select MODULES_USE_ELF_REL <<
21 select OLD_SIGACTION <<
22 select ARCH_SPLIT_ARG64 <<
23 <<
24 config X86_64 <<
25 def_bool y <<
26 depends on 64BIT <<
27 # Options that are inherently 64-bit k <<
28 select ARCH_HAS_GIGANTIC_PAGE <<
29 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
30 select ARCH_SUPPORTS_PER_VMA_LOCK <<
31 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
32 select HAVE_ARCH_SOFT_DIRTY <<
33 select MODULES_USE_ELF_RELA <<
34 select NEED_DMA_MAP_STATE <<
35 select SWIOTLB <<
36 select ARCH_HAS_ELFCORE_COMPAT <<
37 select ZONE_DMA32 <<
38 select EXECMEM if DYNAMIC_FTRACE <<
39 <<
40 config FORCE_DYNAMIC_FTRACE <<
41 def_bool y <<
42 depends on X86_32 <<
43 depends on FUNCTION_TRACER <<
44 select DYNAMIC_FTRACE <<
45 help <<
46 We keep the static function tracing <<
47 in order to test the non static func <<
48 generic code, as other architectures <<
49 only need to keep it around for x86_ <<
50 for x86_32. For x86_32, force DYNAMI <<
51 # <<
52 # Arch settings <<
53 # <<
54 # ( Note that options that are marked 'if X86_ <<
55 # ported to 32-bit as well. ) <<
56 # <<
57 config X86 <<
58 def_bool y <<
59 # <<
60 # Note: keep this list sorted alphabet <<
61 # <<
62 select ACPI_LEGACY_TABLES_LOOKUP <<
63 select ACPI_SYSTEM_POWER_STATES_SUPPOR <<
64 select ACPI_HOTPLUG_CPU <<
65 select ARCH_32BIT_OFF_T <<
66 select ARCH_CLOCKSOURCE_INIT <<
67 select ARCH_CONFIGURES_CPU_MITIGATIONS <<
68 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
69 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
70 select ARCH_ENABLE_MEMORY_HOTPLUG if X <<
71 select ARCH_ENABLE_MEMORY_HOTREMOVE if <<
72 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
73 select ARCH_ENABLE_THP_MIGRATION if X8 <<
74 select ARCH_HAS_ACPI_TABLE_UPGRADE <<
75 select ARCH_HAS_CACHE_LINE_SIZE <<
76 select ARCH_HAS_CPU_CACHE_INVALIDATE_M <<
77 select ARCH_HAS_CPU_FINALIZE_INIT <<
78 select ARCH_HAS_CPU_PASID <<
79 select ARCH_HAS_CURRENT_STACK_POINTER <<
80 select ARCH_HAS_DEBUG_VIRTUAL <<
81 select ARCH_HAS_DEBUG_VM_PGTABLE <<
82 select ARCH_HAS_DEVMEM_IS_ALLOWED <<
83 select ARCH_HAS_DMA_OPS <<
84 select ARCH_HAS_EARLY_DEBUG <<
85 select ARCH_HAS_ELF_RANDOMIZE <<
86 select ARCH_HAS_FAST_MULTIPLIER <<
87 select ARCH_HAS_FORTIFY_SOURCE 9 select ARCH_HAS_FORTIFY_SOURCE
>> 10 select ARCH_HAS_KCOV
>> 11 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
>> 12 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
>> 13 select ARCH_HAS_STRNCPY_FROM_USER
>> 14 select ARCH_HAS_STRNLEN_USER
>> 15 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 16 select ARCH_HAS_UBSAN_SANITIZE_ALL
88 select ARCH_HAS_GCOV_PROFILE_ALL 17 select ARCH_HAS_GCOV_PROFILE_ALL
89 select ARCH_HAS_KCOV !! 18 select ARCH_KEEP_MEMBLOCK
90 select ARCH_HAS_KERNEL_FPU_SUPPORT !! 19 select ARCH_SUPPORTS_UPROBES
91 select ARCH_HAS_MEM_ENCRYPT <<
92 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
93 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
94 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
95 select ARCH_HAS_PMEM_API <<
96 select ARCH_HAS_PTE_DEVMAP <<
97 select ARCH_HAS_PTE_SPECIAL <<
98 select ARCH_HAS_HW_PTE_YOUNG <<
99 select ARCH_HAS_NONLEAF_PMD_YOUNG <<
100 select ARCH_HAS_UACCESS_FLUSHCACHE <<
101 select ARCH_HAS_COPY_MC <<
102 select ARCH_HAS_SET_MEMORY <<
103 select ARCH_HAS_SET_DIRECT_MAP <<
104 select ARCH_HAS_STRICT_KERNEL_RWX <<
105 select ARCH_HAS_STRICT_MODULE_RWX <<
106 select ARCH_HAS_SYNC_CORE_BEFORE_USERM <<
107 select ARCH_HAS_SYSCALL_WRAPPER <<
108 select ARCH_HAS_UBSAN <<
109 select ARCH_HAS_DEBUG_WX <<
110 select ARCH_HAS_ZONE_DMA_SET if EXPERT <<
111 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
112 select ARCH_HAVE_EXTRA_ELF_NOTES <<
113 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
114 select ARCH_MIGHT_HAVE_ACPI_PDC <<
115 select ARCH_MIGHT_HAVE_PC_PARPORT <<
116 select ARCH_MIGHT_HAVE_PC_SERIO <<
117 select ARCH_STACKWALK <<
118 select ARCH_SUPPORTS_ACPI <<
119 select ARCH_SUPPORTS_ATOMIC_RMW <<
120 select ARCH_SUPPORTS_DEBUG_PAGEALLOC <<
121 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
122 select ARCH_SUPPORTS_NUMA_BALANCING <<
123 select ARCH_SUPPORTS_KMAP_LOCAL_FORCE_ <<
124 select ARCH_SUPPORTS_CFI_CLANG <<
125 select ARCH_USES_CFI_TRAPS <<
126 select ARCH_SUPPORTS_LTO_CLANG <<
127 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
128 select ARCH_SUPPORTS_RT <<
129 select ARCH_USE_BUILTIN_BSWAP 20 select ARCH_USE_BUILTIN_BSWAP
130 select ARCH_USE_CMPXCHG_LOCKREF !! 21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
131 select ARCH_USE_MEMTEST 22 select ARCH_USE_MEMTEST
132 select ARCH_USE_QUEUED_RWLOCKS 23 select ARCH_USE_QUEUED_RWLOCKS
133 select ARCH_USE_QUEUED_SPINLOCKS 24 select ARCH_USE_QUEUED_SPINLOCKS
134 select ARCH_USE_SYM_ANNOTATIONS !! 25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
135 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU !! 26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
136 select ARCH_WANT_DEFAULT_BPF_JIT !! 27 select ARCH_WANT_IPC_PARSE_VERSION
137 select ARCH_WANTS_DYNAMIC_TASK_STRUCT <<
138 select ARCH_WANTS_NO_INSTR <<
139 select ARCH_WANT_GENERAL_HUGETLB <<
140 select ARCH_WANT_HUGE_PMD_SHARE <<
141 select ARCH_WANT_LD_ORPHAN_WARN 28 select ARCH_WANT_LD_ORPHAN_WARN
142 select ARCH_WANT_OPTIMIZE_DAX_VMEMMAP <<
143 select ARCH_WANT_OPTIMIZE_HUGETLB_VMEM <<
144 select ARCH_WANTS_THP_SWAP <<
145 select ARCH_HAS_PARANOID_L1D_FLUSH <<
146 select BUILDTIME_TABLE_SORT 29 select BUILDTIME_TABLE_SORT
147 select CLKEVT_I8253 !! 30 select CLONE_BACKWARDS
148 select CLOCKSOURCE_VALIDATE_LAST_CYCLE !! 31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
149 select CLOCKSOURCE_WATCHDOG !! 32 select CPU_PM if CPU_IDLE
150 # Word-size accesses may read uninitia !! 33 select GENERIC_ATOMIC64 if !64BIT
151 # in strings and cause false KMSAN rep <<
152 select DCACHE_WORD_ACCESS <<
153 select DYNAMIC_SIGFRAME <<
154 select EDAC_ATOMIC_SCRUB <<
155 select EDAC_SUPPORT <<
156 select GENERIC_CLOCKEVENTS_BROADCAST <<
157 select GENERIC_CLOCKEVENTS_BROADCAST_I <<
158 select GENERIC_CLOCKEVENTS_MIN_ADJUST <<
159 select GENERIC_CMOS_UPDATE 34 select GENERIC_CMOS_UPDATE
160 select GENERIC_CPU_AUTOPROBE 35 select GENERIC_CPU_AUTOPROBE
161 select GENERIC_CPU_DEVICES !! 36 select GENERIC_GETTIMEOFDAY
162 select GENERIC_CPU_VULNERABILITIES <<
163 select GENERIC_EARLY_IOREMAP <<
164 select GENERIC_ENTRY <<
165 select GENERIC_IOMAP 37 select GENERIC_IOMAP
166 select GENERIC_IRQ_EFFECTIVE_AFF_MASK <<
167 select GENERIC_IRQ_MATRIX_ALLOCATOR <<
168 select GENERIC_IRQ_MIGRATION <<
169 select GENERIC_IRQ_PROBE 38 select GENERIC_IRQ_PROBE
170 select GENERIC_IRQ_RESERVATION_MODE <<
171 select GENERIC_IRQ_SHOW 39 select GENERIC_IRQ_SHOW
172 select GENERIC_PENDING_IRQ !! 40 select GENERIC_ISA_DMA if EISA
173 select GENERIC_PTDUMP !! 41 select GENERIC_LIB_ASHLDI3
>> 42 select GENERIC_LIB_ASHRDI3
>> 43 select GENERIC_LIB_CMPDI2
>> 44 select GENERIC_LIB_LSHRDI3
>> 45 select GENERIC_LIB_UCMPDI2
>> 46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
174 select GENERIC_SMP_IDLE_THREAD 47 select GENERIC_SMP_IDLE_THREAD
175 select GENERIC_TIME_VSYSCALL 48 select GENERIC_TIME_VSYSCALL
176 select GENERIC_GETTIMEOFDAY !! 49 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
177 select GENERIC_VDSO_TIME_NS !! 50 select HAVE_ARCH_COMPILER_H
178 select GENERIC_VDSO_OVERFLOW_PROTECT <<
179 select GUP_GET_PXX_LOW_HIGH <<
180 select HARDIRQS_SW_RESEND <<
181 select HARDLOCKUP_CHECK_TIMESTAMP <<
182 select HAS_IOPORT <<
183 select HAVE_ACPI_APEI <<
184 select HAVE_ACPI_APEI_NMI <<
185 select HAVE_ALIGNED_STRUCT_PAGE <<
186 select HAVE_ARCH_AUDITSYSCALL <<
187 select HAVE_ARCH_HUGE_VMAP <<
188 select HAVE_ARCH_HUGE_VMALLOC <<
189 select HAVE_ARCH_JUMP_LABEL 51 select HAVE_ARCH_JUMP_LABEL
190 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 52 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
191 select HAVE_ARCH_KASAN !! 53 select HAVE_ARCH_MMAP_RND_BITS if MMU
192 select HAVE_ARCH_KASAN_VMALLOC !! 54 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
193 select HAVE_ARCH_KFENCE <<
194 select HAVE_ARCH_KMSAN <<
195 select HAVE_ARCH_KGDB <<
196 select HAVE_ARCH_MMAP_RND_BITS <<
197 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
198 select HAVE_ARCH_COMPAT_MMAP_BASES <<
199 select HAVE_ARCH_PREL32_RELOCATIONS <<
200 select HAVE_ARCH_SECCOMP_FILTER 55 select HAVE_ARCH_SECCOMP_FILTER
201 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
202 select HAVE_ARCH_STACKLEAK <<
203 select HAVE_ARCH_TRACEHOOK 56 select HAVE_ARCH_TRACEHOOK
204 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 57 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
205 select HAVE_ARCH_TRANSPARENT_HUGEPAGE_ <<
206 select HAVE_ARCH_USERFAULTFD_WP <<
207 select HAVE_ARCH_USERFAULTFD_MINOR <<
208 select HAVE_ARCH_VMAP_STACK <<
209 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
210 select HAVE_ARCH_WITHIN_STACK_FRAMES <<
211 select HAVE_ASM_MODVERSIONS 58 select HAVE_ASM_MODVERSIONS
212 select HAVE_CMPXCHG_DOUBLE !! 59 select HAVE_CONTEXT_TRACKING_USER
213 select HAVE_CMPXCHG_LOCAL !! 60 select HAVE_TIF_NOHZ
214 select HAVE_CONTEXT_TRACKING_USER <<
215 select HAVE_CONTEXT_TRACKING_USER_OFFS <<
216 select HAVE_C_RECORDMCOUNT 61 select HAVE_C_RECORDMCOUNT
217 select HAVE_OBJTOOL_MCOUNT <<
218 select HAVE_OBJTOOL_NOP_MCOUNT <<
219 select HAVE_BUILDTIME_MCOUNT_SORT <<
220 select HAVE_DEBUG_KMEMLEAK 62 select HAVE_DEBUG_KMEMLEAK
>> 63 select HAVE_DEBUG_STACKOVERFLOW
221 select HAVE_DMA_CONTIGUOUS 64 select HAVE_DMA_CONTIGUOUS
222 select HAVE_DYNAMIC_FTRACE 65 select HAVE_DYNAMIC_FTRACE
223 select HAVE_DYNAMIC_FTRACE_WITH_REGS !! 66 select HAVE_EBPF_JIT if !CPU_MICROMIPS && \
224 select HAVE_DYNAMIC_FTRACE_WITH_ARGS !! 67 !CPU_DADDI_WORKAROUNDS && \
225 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT !! 68 !CPU_R4000_WORKAROUNDS && \
226 select HAVE_SAMPLE_FTRACE_DIRECT !! 69 !CPU_R4400_WORKAROUNDS
227 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
228 select HAVE_EBPF_JIT <<
229 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
230 select HAVE_EISA <<
231 select HAVE_EXIT_THREAD 70 select HAVE_EXIT_THREAD
232 select HAVE_GUP_FAST !! 71 select HAVE_FAST_GUP
233 select HAVE_FENTRY <<
234 select HAVE_FTRACE_MCOUNT_RECORD 72 select HAVE_FTRACE_MCOUNT_RECORD
235 select HAVE_FUNCTION_GRAPH_RETVAL !! 73 select HAVE_FUNCTION_GRAPH_TRACER
236 select HAVE_FUNCTION_GRAPH_TRACER <<
237 select HAVE_FUNCTION_TRACER 74 select HAVE_FUNCTION_TRACER
238 select HAVE_GCC_PLUGINS 75 select HAVE_GCC_PLUGINS
239 select HAVE_HW_BREAKPOINT !! 76 select HAVE_GENERIC_VDSO
240 select HAVE_IOREMAP_PROT 77 select HAVE_IOREMAP_PROT
241 select HAVE_IRQ_EXIT_ON_IRQ_STACK !! 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
242 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_IRQ_TIME_ACCOUNTING
243 select HAVE_JUMP_LABEL_HACK <<
244 select HAVE_KERNEL_BZIP2 <<
245 select HAVE_KERNEL_GZIP <<
246 select HAVE_KERNEL_LZ4 <<
247 select HAVE_KERNEL_LZMA <<
248 select HAVE_KERNEL_LZO <<
249 select HAVE_KERNEL_XZ <<
250 select HAVE_KERNEL_ZSTD <<
251 select HAVE_KPROBES 80 select HAVE_KPROBES
252 select HAVE_KPROBES_ON_FTRACE <<
253 select HAVE_FUNCTION_ERROR_INJECTION <<
254 select HAVE_KRETPROBES 81 select HAVE_KRETPROBES
255 select HAVE_RETHOOK !! 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
256 select HAVE_LIVEPATCH <<
257 select HAVE_MIXED_BREAKPOINTS_REGS <<
258 select HAVE_MOD_ARCH_SPECIFIC 83 select HAVE_MOD_ARCH_SPECIFIC
259 select HAVE_MOVE_PMD <<
260 select HAVE_MOVE_PUD <<
261 select HAVE_NOINSTR_HACK <<
262 select HAVE_NMI 84 select HAVE_NMI
263 select HAVE_NOINSTR_VALIDATION <<
264 select HAVE_OBJTOOL <<
265 select HAVE_OPTPROBES <<
266 select HAVE_PAGE_SIZE_4KB <<
267 select HAVE_PCSPKR_PLATFORM <<
268 select HAVE_PERF_EVENTS 85 select HAVE_PERF_EVENTS
269 select HAVE_PERF_EVENTS_NMI <<
270 select HAVE_HARDLOCKUP_DETECTOR_PERF <<
271 select HAVE_PCI <<
272 select HAVE_PERF_REGS 86 select HAVE_PERF_REGS
273 select HAVE_PERF_USER_STACK_DUMP 87 select HAVE_PERF_USER_STACK_DUMP
274 select MMU_GATHER_RCU_TABLE_FREE <<
275 select MMU_GATHER_MERGE_VMAS <<
276 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
277 select HAVE_REGS_AND_STACK_ACCESS_API 88 select HAVE_REGS_AND_STACK_ACCESS_API
278 select HAVE_RELIABLE_STACKTRACE <<
279 select HAVE_FUNCTION_ARG_ACCESS_API <<
280 select HAVE_SETUP_PER_CPU_AREA <<
281 select HAVE_SOFTIRQ_ON_OWN_STACK <<
282 select HAVE_STACKPROTECTOR <<
283 select HAVE_STACK_VALIDATION <<
284 select HAVE_STATIC_CALL <<
285 select HAVE_STATIC_CALL_INLINE <<
286 select HAVE_PREEMPT_DYNAMIC_CALL <<
287 select HAVE_RSEQ 89 select HAVE_RSEQ
288 select HAVE_RUST !! 90 select HAVE_SPARSE_SYSCALL_NR
>> 91 select HAVE_STACKPROTECTOR
289 select HAVE_SYSCALL_TRACEPOINTS 92 select HAVE_SYSCALL_TRACEPOINTS
290 select HAVE_UACCESS_VALIDATION !! 93 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
291 select HAVE_UNSTABLE_SCHED_CLOCK <<
292 select HAVE_USER_RETURN_NOTIFIER <<
293 select HAVE_GENERIC_VDSO <<
294 select VDSO_GETRANDOM <<
295 select HOTPLUG_PARALLEL <<
296 select HOTPLUG_SMT <<
297 select HOTPLUG_SPLIT_STARTUP <<
298 select IRQ_FORCED_THREADING 94 select IRQ_FORCED_THREADING
299 select LOCK_MM_AND_FIND_VMA !! 95 select ISA if EISA
300 select NEED_PER_CPU_EMBED_FIRST_CHUNK !! 96 select MODULES_USE_ELF_REL if MODULES
301 select NEED_PER_CPU_PAGE_FIRST_CHUNK !! 97 select MODULES_USE_ELF_RELA if MODULES && 64BIT
302 select NEED_SG_DMA_LENGTH !! 98 select PERF_USE_VMALLOC
303 select NUMA_MEMBLKS !! 99 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
304 select PCI_DOMAINS <<
305 select PCI_LOCKLESS_CONFIG <<
306 select PERF_EVENTS <<
307 select RTC_LIB 100 select RTC_LIB
308 select RTC_MC146818_LIB <<
309 select SPARSE_IRQ <<
310 select SYSCTL_EXCEPTION_TRACE 101 select SYSCTL_EXCEPTION_TRACE
311 select THREAD_INFO_IN_TASK <<
312 select TRACE_IRQFLAGS_SUPPORT 102 select TRACE_IRQFLAGS_SUPPORT
313 select TRACE_IRQFLAGS_NMI_SUPPORT !! 103 select ARCH_HAS_ELFCORE_COMPAT
314 select USER_STACKTRACE_SUPPORT !! 104 select HAVE_ARCH_KCSAN if 64BIT
315 select HAVE_ARCH_KCSAN <<
316 select PROC_PID_ARCH_STATUS <<
317 select HAVE_ARCH_NODE_DEV_GROUP <<
318 select FUNCTION_ALIGNMENT_16B <<
319 select FUNCTION_ALIGNMENT_4B <<
320 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
321 select HAVE_DYNAMIC_FTRACE_NO_PATCHABL <<
322 105
323 config INSTRUCTION_DECODER !! 106 config MIPS_FIXUP_BIGPHYS_ADDR
324 def_bool y !! 107 bool
325 depends on KPROBES || PERF_EVENTS || U <<
326 108
327 config OUTPUT_FORMAT !! 109 config MIPS_GENERIC
328 string !! 110 bool
329 default "elf32-i386" if X86_32 <<
330 default "elf64-x86-64" if X86_64 <<
331 111
332 config LOCKDEP_SUPPORT !! 112 config MACH_INGENIC
333 def_bool y !! 113 bool
>> 114 select SYS_SUPPORTS_32BIT_KERNEL
>> 115 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 116 select SYS_SUPPORTS_ZBOOT
>> 117 select DMA_NONCOHERENT
>> 118 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 119 select IRQ_MIPS_CPU
>> 120 select PINCTRL
>> 121 select GPIOLIB
>> 122 select COMMON_CLK
>> 123 select GENERIC_IRQ_CHIP
>> 124 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 125 select USE_OF
>> 126 select CPU_SUPPORTS_CPUFREQ
>> 127 select MIPS_EXTERNAL_TIMER
334 128
335 config STACKTRACE_SUPPORT !! 129 menu "Machine selection"
336 def_bool y <<
337 130
338 config MMU !! 131 choice
339 def_bool y !! 132 prompt "System type"
>> 133 default MIPS_GENERIC_KERNEL
340 134
341 config ARCH_MMAP_RND_BITS_MIN !! 135 config MIPS_GENERIC_KERNEL
342 default 28 if 64BIT !! 136 bool "Generic board-agnostic MIPS kernel"
343 default 8 !! 137 select ARCH_HAS_SETUP_DMA_OPS
>> 138 select MIPS_GENERIC
>> 139 select BOOT_RAW
>> 140 select BUILTIN_DTB
>> 141 select CEVT_R4K
>> 142 select CLKSRC_MIPS_GIC
>> 143 select COMMON_CLK
>> 144 select CPU_MIPSR2_IRQ_EI
>> 145 select CPU_MIPSR2_IRQ_VI
>> 146 select CSRC_R4K
>> 147 select DMA_NONCOHERENT
>> 148 select HAVE_PCI
>> 149 select IRQ_MIPS_CPU
>> 150 select MIPS_AUTO_PFN_OFFSET
>> 151 select MIPS_CPU_SCACHE
>> 152 select MIPS_GIC
>> 153 select MIPS_L1_CACHE_SHIFT_7
>> 154 select NO_EXCEPT_FILL
>> 155 select PCI_DRIVERS_GENERIC
>> 156 select SMP_UP if SMP
>> 157 select SWAP_IO_SPACE
>> 158 select SYS_HAS_CPU_MIPS32_R1
>> 159 select SYS_HAS_CPU_MIPS32_R2
>> 160 select SYS_HAS_CPU_MIPS32_R6
>> 161 select SYS_HAS_CPU_MIPS64_R1
>> 162 select SYS_HAS_CPU_MIPS64_R2
>> 163 select SYS_HAS_CPU_MIPS64_R6
>> 164 select SYS_SUPPORTS_32BIT_KERNEL
>> 165 select SYS_SUPPORTS_64BIT_KERNEL
>> 166 select SYS_SUPPORTS_BIG_ENDIAN
>> 167 select SYS_SUPPORTS_HIGHMEM
>> 168 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 169 select SYS_SUPPORTS_MICROMIPS
>> 170 select SYS_SUPPORTS_MIPS16
>> 171 select SYS_SUPPORTS_MIPS_CPS
>> 172 select SYS_SUPPORTS_MULTITHREADING
>> 173 select SYS_SUPPORTS_RELOCATABLE
>> 174 select SYS_SUPPORTS_SMARTMIPS
>> 175 select SYS_SUPPORTS_ZBOOT
>> 176 select UHI_BOOT
>> 177 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 178 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 179 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 180 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 181 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 182 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 183 select USE_OF
>> 184 help
>> 185 Select this to build a kernel which aims to support multiple boards,
>> 186 generally using a flattened device tree passed from the bootloader
>> 187 using the boot protocol defined in the UHI (Unified Hosting
>> 188 Interface) specification.
344 189
345 config ARCH_MMAP_RND_BITS_MAX !! 190 config MIPS_ALCHEMY
346 default 32 if 64BIT !! 191 bool "Alchemy processor based machines"
347 default 16 !! 192 select PHYS_ADDR_T_64BIT
>> 193 select CEVT_R4K
>> 194 select CSRC_R4K
>> 195 select IRQ_MIPS_CPU
>> 196 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 197 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 198 select SYS_HAS_CPU_MIPS32_R1
>> 199 select SYS_SUPPORTS_32BIT_KERNEL
>> 200 select SYS_SUPPORTS_APM_EMULATION
>> 201 select GPIOLIB
>> 202 select SYS_SUPPORTS_ZBOOT
>> 203 select COMMON_CLK
348 204
349 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 205 config AR7
350 default 8 !! 206 bool "Texas Instruments AR7"
>> 207 select BOOT_ELF32
>> 208 select COMMON_CLK
>> 209 select DMA_NONCOHERENT
>> 210 select CEVT_R4K
>> 211 select CSRC_R4K
>> 212 select IRQ_MIPS_CPU
>> 213 select NO_EXCEPT_FILL
>> 214 select SWAP_IO_SPACE
>> 215 select SYS_HAS_CPU_MIPS32_R1
>> 216 select SYS_HAS_EARLY_PRINTK
>> 217 select SYS_SUPPORTS_32BIT_KERNEL
>> 218 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 219 select SYS_SUPPORTS_MIPS16
>> 220 select SYS_SUPPORTS_ZBOOT_UART16550
>> 221 select GPIOLIB
>> 222 select VLYNQ
>> 223 help
>> 224 Support for the Texas Instruments AR7 System-on-a-Chip
>> 225 family: TNETD7100, 7200 and 7300.
351 226
352 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 227 config ATH25
353 default 16 !! 228 bool "Atheros AR231x/AR531x SoC support"
>> 229 select CEVT_R4K
>> 230 select CSRC_R4K
>> 231 select DMA_NONCOHERENT
>> 232 select IRQ_MIPS_CPU
>> 233 select IRQ_DOMAIN
>> 234 select SYS_HAS_CPU_MIPS32_R1
>> 235 select SYS_SUPPORTS_BIG_ENDIAN
>> 236 select SYS_SUPPORTS_32BIT_KERNEL
>> 237 select SYS_HAS_EARLY_PRINTK
>> 238 help
>> 239 Support for Atheros AR231x and Atheros AR531x based boards
>> 240
>> 241 config ATH79
>> 242 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 243 select ARCH_HAS_RESET_CONTROLLER
>> 244 select BOOT_RAW
>> 245 select CEVT_R4K
>> 246 select CSRC_R4K
>> 247 select DMA_NONCOHERENT
>> 248 select GPIOLIB
>> 249 select PINCTRL
>> 250 select COMMON_CLK
>> 251 select IRQ_MIPS_CPU
>> 252 select SYS_HAS_CPU_MIPS32_R2
>> 253 select SYS_HAS_EARLY_PRINTK
>> 254 select SYS_SUPPORTS_32BIT_KERNEL
>> 255 select SYS_SUPPORTS_BIG_ENDIAN
>> 256 select SYS_SUPPORTS_MIPS16
>> 257 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 258 select USE_OF
>> 259 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 260 help
>> 261 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 262
>> 263 config BMIPS_GENERIC
>> 264 bool "Broadcom Generic BMIPS kernel"
>> 265 select ARCH_HAS_RESET_CONTROLLER
>> 266 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 267 select BOOT_RAW
>> 268 select NO_EXCEPT_FILL
>> 269 select USE_OF
>> 270 select CEVT_R4K
>> 271 select CSRC_R4K
>> 272 select SYNC_R4K
>> 273 select COMMON_CLK
>> 274 select BCM6345_L1_IRQ
>> 275 select BCM7038_L1_IRQ
>> 276 select BCM7120_L2_IRQ
>> 277 select BRCMSTB_L2_IRQ
>> 278 select IRQ_MIPS_CPU
>> 279 select DMA_NONCOHERENT
>> 280 select SYS_SUPPORTS_32BIT_KERNEL
>> 281 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 282 select SYS_SUPPORTS_BIG_ENDIAN
>> 283 select SYS_SUPPORTS_HIGHMEM
>> 284 select SYS_HAS_CPU_BMIPS32_3300
>> 285 select SYS_HAS_CPU_BMIPS4350
>> 286 select SYS_HAS_CPU_BMIPS4380
>> 287 select SYS_HAS_CPU_BMIPS5000
>> 288 select SWAP_IO_SPACE
>> 289 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 290 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 291 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 292 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 293 select HARDIRQS_SW_RESEND
>> 294 select HAVE_PCI
>> 295 select PCI_DRIVERS_GENERIC
>> 296 select FW_CFE
>> 297 help
>> 298 Build a generic DT-based kernel image that boots on select
>> 299 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 300 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 301 must be set appropriately for your board.
>> 302
>> 303 config BCM47XX
>> 304 bool "Broadcom BCM47XX based boards"
>> 305 select BOOT_RAW
>> 306 select CEVT_R4K
>> 307 select CSRC_R4K
>> 308 select DMA_NONCOHERENT
>> 309 select HAVE_PCI
>> 310 select IRQ_MIPS_CPU
>> 311 select SYS_HAS_CPU_MIPS32_R1
>> 312 select NO_EXCEPT_FILL
>> 313 select SYS_SUPPORTS_32BIT_KERNEL
>> 314 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 315 select SYS_SUPPORTS_MIPS16
>> 316 select SYS_SUPPORTS_ZBOOT
>> 317 select SYS_HAS_EARLY_PRINTK
>> 318 select USE_GENERIC_EARLY_PRINTK_8250
>> 319 select GPIOLIB
>> 320 select LEDS_GPIO_REGISTER
>> 321 select BCM47XX_NVRAM
>> 322 select BCM47XX_SPROM
>> 323 select BCM47XX_SSB if !BCM47XX_BCMA
>> 324 help
>> 325 Support for BCM47XX based boards
>> 326
>> 327 config BCM63XX
>> 328 bool "Broadcom BCM63XX based boards"
>> 329 select BOOT_RAW
>> 330 select CEVT_R4K
>> 331 select CSRC_R4K
>> 332 select SYNC_R4K
>> 333 select DMA_NONCOHERENT
>> 334 select IRQ_MIPS_CPU
>> 335 select SYS_SUPPORTS_32BIT_KERNEL
>> 336 select SYS_SUPPORTS_BIG_ENDIAN
>> 337 select SYS_HAS_EARLY_PRINTK
>> 338 select SYS_HAS_CPU_BMIPS32_3300
>> 339 select SYS_HAS_CPU_BMIPS4350
>> 340 select SYS_HAS_CPU_BMIPS4380
>> 341 select SWAP_IO_SPACE
>> 342 select GPIOLIB
>> 343 select MIPS_L1_CACHE_SHIFT_4
>> 344 select HAVE_LEGACY_CLK
>> 345 help
>> 346 Support for BCM63XX based boards
354 347
355 config SBUS !! 348 config MIPS_COBALT
356 bool !! 349 bool "Cobalt Server"
>> 350 select CEVT_R4K
>> 351 select CSRC_R4K
>> 352 select CEVT_GT641XX
>> 353 select DMA_NONCOHERENT
>> 354 select FORCE_PCI
>> 355 select I8253
>> 356 select I8259
>> 357 select IRQ_MIPS_CPU
>> 358 select IRQ_GT641XX
>> 359 select PCI_GT64XXX_PCI0
>> 360 select SYS_HAS_CPU_NEVADA
>> 361 select SYS_HAS_EARLY_PRINTK
>> 362 select SYS_SUPPORTS_32BIT_KERNEL
>> 363 select SYS_SUPPORTS_64BIT_KERNEL
>> 364 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 365 select USE_GENERIC_EARLY_PRINTK_8250
>> 366
>> 367 config MACH_DECSTATION
>> 368 bool "DECstations"
>> 369 select BOOT_ELF32
>> 370 select CEVT_DS1287
>> 371 select CEVT_R4K if CPU_R4X00
>> 372 select CSRC_IOASIC
>> 373 select CSRC_R4K if CPU_R4X00
>> 374 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 375 select CPU_R4000_WORKAROUNDS if 64BIT
>> 376 select CPU_R4400_WORKAROUNDS if 64BIT
>> 377 select DMA_NONCOHERENT
>> 378 select NO_IOPORT_MAP
>> 379 select IRQ_MIPS_CPU
>> 380 select SYS_HAS_CPU_R3000
>> 381 select SYS_HAS_CPU_R4X00
>> 382 select SYS_SUPPORTS_32BIT_KERNEL
>> 383 select SYS_SUPPORTS_64BIT_KERNEL
>> 384 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 385 select SYS_SUPPORTS_128HZ
>> 386 select SYS_SUPPORTS_256HZ
>> 387 select SYS_SUPPORTS_1024HZ
>> 388 select MIPS_L1_CACHE_SHIFT_4
>> 389 help
>> 390 This enables support for DEC's MIPS based workstations. For details
>> 391 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 392 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 393
>> 394 If you have one of the following DECstation Models you definitely
>> 395 want to choose R4xx0 for the CPU Type:
>> 396
>> 397 DECstation 5000/50
>> 398 DECstation 5000/150
>> 399 DECstation 5000/260
>> 400 DECsystem 5900/260
>> 401
>> 402 otherwise choose R3000.
>> 403
>> 404 config MACH_JAZZ
>> 405 bool "Jazz family of machines"
>> 406 select ARC_MEMORY
>> 407 select ARC_PROMLIB
>> 408 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 409 select ARCH_MIGHT_HAVE_PC_SERIO
>> 410 select DMA_OPS
>> 411 select FW_ARC
>> 412 select FW_ARC32
>> 413 select ARCH_MAY_HAVE_PC_FDC
>> 414 select CEVT_R4K
>> 415 select CSRC_R4K
>> 416 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 417 select GENERIC_ISA_DMA
>> 418 select HAVE_PCSPKR_PLATFORM
>> 419 select IRQ_MIPS_CPU
>> 420 select I8253
>> 421 select I8259
>> 422 select ISA
>> 423 select SYS_HAS_CPU_R4X00
>> 424 select SYS_SUPPORTS_32BIT_KERNEL
>> 425 select SYS_SUPPORTS_64BIT_KERNEL
>> 426 select SYS_SUPPORTS_100HZ
>> 427 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 428 help
>> 429 This a family of machines based on the MIPS R4030 chipset which was
>> 430 used by several vendors to build RISC/os and Windows NT workstations.
>> 431 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 432 Olivetti M700-10 workstations.
>> 433
>> 434 config MACH_INGENIC_SOC
>> 435 bool "Ingenic SoC based machines"
>> 436 select MIPS_GENERIC
>> 437 select MACH_INGENIC
>> 438 select SYS_SUPPORTS_ZBOOT_UART16550
>> 439 select CPU_SUPPORTS_CPUFREQ
>> 440 select MIPS_EXTERNAL_TIMER
>> 441
>> 442 config LANTIQ
>> 443 bool "Lantiq based platforms"
>> 444 select DMA_NONCOHERENT
>> 445 select IRQ_MIPS_CPU
>> 446 select CEVT_R4K
>> 447 select CSRC_R4K
>> 448 select SYS_HAS_CPU_MIPS32_R1
>> 449 select SYS_HAS_CPU_MIPS32_R2
>> 450 select SYS_SUPPORTS_BIG_ENDIAN
>> 451 select SYS_SUPPORTS_32BIT_KERNEL
>> 452 select SYS_SUPPORTS_MIPS16
>> 453 select SYS_SUPPORTS_MULTITHREADING
>> 454 select SYS_SUPPORTS_VPE_LOADER
>> 455 select SYS_HAS_EARLY_PRINTK
>> 456 select GPIOLIB
>> 457 select SWAP_IO_SPACE
>> 458 select BOOT_RAW
>> 459 select HAVE_LEGACY_CLK
>> 460 select USE_OF
>> 461 select PINCTRL
>> 462 select PINCTRL_LANTIQ
>> 463 select ARCH_HAS_RESET_CONTROLLER
>> 464 select RESET_CONTROLLER
357 465
358 config GENERIC_ISA_DMA !! 466 config MACH_LOONGSON32
359 def_bool y !! 467 bool "Loongson 32-bit family of machines"
360 depends on ISA_DMA_API !! 468 select SYS_SUPPORTS_ZBOOT
>> 469 help
>> 470 This enables support for the Loongson-1 family of machines.
361 471
362 config GENERIC_CSUM !! 472 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 473 the Institute of Computing Technology (ICT), Chinese Academy of
>> 474 Sciences (CAS).
>> 475
>> 476 config MACH_LOONGSON2EF
>> 477 bool "Loongson-2E/F family of machines"
>> 478 select SYS_SUPPORTS_ZBOOT
>> 479 help
>> 480 This enables the support of early Loongson-2E/F family of machines.
>> 481
>> 482 config MACH_LOONGSON64
>> 483 bool "Loongson 64-bit family of machines"
>> 484 select ARCH_SPARSEMEM_ENABLE
>> 485 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 486 select ARCH_MIGHT_HAVE_PC_SERIO
>> 487 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 488 select BOOT_ELF32
>> 489 select BOARD_SCACHE
>> 490 select CSRC_R4K
>> 491 select CEVT_R4K
>> 492 select CPU_HAS_WB
>> 493 select FORCE_PCI
>> 494 select ISA
>> 495 select I8259
>> 496 select IRQ_MIPS_CPU
>> 497 select NO_EXCEPT_FILL
>> 498 select NR_CPUS_DEFAULT_64
>> 499 select USE_GENERIC_EARLY_PRINTK_8250
>> 500 select PCI_DRIVERS_GENERIC
>> 501 select SYS_HAS_CPU_LOONGSON64
>> 502 select SYS_HAS_EARLY_PRINTK
>> 503 select SYS_SUPPORTS_SMP
>> 504 select SYS_SUPPORTS_HOTPLUG_CPU
>> 505 select SYS_SUPPORTS_NUMA
>> 506 select SYS_SUPPORTS_64BIT_KERNEL
>> 507 select SYS_SUPPORTS_HIGHMEM
>> 508 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 509 select SYS_SUPPORTS_ZBOOT
>> 510 select SYS_SUPPORTS_RELOCATABLE
>> 511 select ZONE_DMA32
>> 512 select COMMON_CLK
>> 513 select USE_OF
>> 514 select BUILTIN_DTB
>> 515 select PCI_HOST_GENERIC
>> 516 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 517 help
>> 518 This enables the support of Loongson-2/3 family of machines.
>> 519
>> 520 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 521 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 522 and Loongson-2F which will be removed), developed by the Institute
>> 523 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 524
>> 525 config MIPS_MALTA
>> 526 bool "MIPS Malta board"
>> 527 select ARCH_MAY_HAVE_PC_FDC
>> 528 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 529 select ARCH_MIGHT_HAVE_PC_SERIO
>> 530 select BOOT_ELF32
>> 531 select BOOT_RAW
>> 532 select BUILTIN_DTB
>> 533 select CEVT_R4K
>> 534 select CLKSRC_MIPS_GIC
>> 535 select COMMON_CLK
>> 536 select CSRC_R4K
>> 537 select DMA_NONCOHERENT
>> 538 select GENERIC_ISA_DMA
>> 539 select HAVE_PCSPKR_PLATFORM
>> 540 select HAVE_PCI
>> 541 select I8253
>> 542 select I8259
>> 543 select IRQ_MIPS_CPU
>> 544 select MIPS_BONITO64
>> 545 select MIPS_CPU_SCACHE
>> 546 select MIPS_GIC
>> 547 select MIPS_L1_CACHE_SHIFT_6
>> 548 select MIPS_MSC
>> 549 select PCI_GT64XXX_PCI0
>> 550 select SMP_UP if SMP
>> 551 select SWAP_IO_SPACE
>> 552 select SYS_HAS_CPU_MIPS32_R1
>> 553 select SYS_HAS_CPU_MIPS32_R2
>> 554 select SYS_HAS_CPU_MIPS32_R3_5
>> 555 select SYS_HAS_CPU_MIPS32_R5
>> 556 select SYS_HAS_CPU_MIPS32_R6
>> 557 select SYS_HAS_CPU_MIPS64_R1
>> 558 select SYS_HAS_CPU_MIPS64_R2
>> 559 select SYS_HAS_CPU_MIPS64_R6
>> 560 select SYS_HAS_CPU_NEVADA
>> 561 select SYS_HAS_CPU_RM7000
>> 562 select SYS_SUPPORTS_32BIT_KERNEL
>> 563 select SYS_SUPPORTS_64BIT_KERNEL
>> 564 select SYS_SUPPORTS_BIG_ENDIAN
>> 565 select SYS_SUPPORTS_HIGHMEM
>> 566 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 567 select SYS_SUPPORTS_MICROMIPS
>> 568 select SYS_SUPPORTS_MIPS16
>> 569 select SYS_SUPPORTS_MIPS_CMP
>> 570 select SYS_SUPPORTS_MIPS_CPS
>> 571 select SYS_SUPPORTS_MULTITHREADING
>> 572 select SYS_SUPPORTS_RELOCATABLE
>> 573 select SYS_SUPPORTS_SMARTMIPS
>> 574 select SYS_SUPPORTS_VPE_LOADER
>> 575 select SYS_SUPPORTS_ZBOOT
>> 576 select USE_OF
>> 577 select WAR_ICACHE_REFILLS
>> 578 select ZONE_DMA32 if 64BIT
>> 579 help
>> 580 This enables support for the MIPS Technologies Malta evaluation
>> 581 board.
>> 582
>> 583 config MACH_PIC32
>> 584 bool "Microchip PIC32 Family"
>> 585 help
>> 586 This enables support for the Microchip PIC32 family of platforms.
>> 587
>> 588 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 589 microcontrollers.
>> 590
>> 591 config MACH_NINTENDO64
>> 592 bool "Nintendo 64 console"
>> 593 select CEVT_R4K
>> 594 select CSRC_R4K
>> 595 select SYS_HAS_CPU_R4300
>> 596 select SYS_SUPPORTS_BIG_ENDIAN
>> 597 select SYS_SUPPORTS_ZBOOT
>> 598 select SYS_SUPPORTS_32BIT_KERNEL
>> 599 select SYS_SUPPORTS_64BIT_KERNEL
>> 600 select DMA_NONCOHERENT
>> 601 select IRQ_MIPS_CPU
>> 602
>> 603 config RALINK
>> 604 bool "Ralink based machines"
>> 605 select CEVT_R4K
>> 606 select COMMON_CLK
>> 607 select CSRC_R4K
>> 608 select BOOT_RAW
>> 609 select DMA_NONCOHERENT
>> 610 select IRQ_MIPS_CPU
>> 611 select USE_OF
>> 612 select SYS_HAS_CPU_MIPS32_R1
>> 613 select SYS_HAS_CPU_MIPS32_R2
>> 614 select SYS_SUPPORTS_32BIT_KERNEL
>> 615 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 616 select SYS_SUPPORTS_MIPS16
>> 617 select SYS_SUPPORTS_ZBOOT
>> 618 select SYS_HAS_EARLY_PRINTK
>> 619 select ARCH_HAS_RESET_CONTROLLER
>> 620 select RESET_CONTROLLER
>> 621
>> 622 config MACH_REALTEK_RTL
>> 623 bool "Realtek RTL838x/RTL839x based machines"
>> 624 select MIPS_GENERIC
>> 625 select DMA_NONCOHERENT
>> 626 select IRQ_MIPS_CPU
>> 627 select CSRC_R4K
>> 628 select CEVT_R4K
>> 629 select SYS_HAS_CPU_MIPS32_R1
>> 630 select SYS_HAS_CPU_MIPS32_R2
>> 631 select SYS_SUPPORTS_BIG_ENDIAN
>> 632 select SYS_SUPPORTS_32BIT_KERNEL
>> 633 select SYS_SUPPORTS_MIPS16
>> 634 select SYS_SUPPORTS_MULTITHREADING
>> 635 select SYS_SUPPORTS_VPE_LOADER
>> 636 select BOOT_RAW
>> 637 select PINCTRL
>> 638 select USE_OF
>> 639
>> 640 config SGI_IP22
>> 641 bool "SGI IP22 (Indy/Indigo2)"
>> 642 select ARC_MEMORY
>> 643 select ARC_PROMLIB
>> 644 select FW_ARC
>> 645 select FW_ARC32
>> 646 select ARCH_MIGHT_HAVE_PC_SERIO
>> 647 select BOOT_ELF32
>> 648 select CEVT_R4K
>> 649 select CSRC_R4K
>> 650 select DEFAULT_SGI_PARTITION
>> 651 select DMA_NONCOHERENT
>> 652 select HAVE_EISA
>> 653 select I8253
>> 654 select I8259
>> 655 select IP22_CPU_SCACHE
>> 656 select IRQ_MIPS_CPU
>> 657 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 658 select SGI_HAS_I8042
>> 659 select SGI_HAS_INDYDOG
>> 660 select SGI_HAS_HAL2
>> 661 select SGI_HAS_SEEQ
>> 662 select SGI_HAS_WD93
>> 663 select SGI_HAS_ZILOG
>> 664 select SWAP_IO_SPACE
>> 665 select SYS_HAS_CPU_R4X00
>> 666 select SYS_HAS_CPU_R5000
>> 667 select SYS_HAS_EARLY_PRINTK
>> 668 select SYS_SUPPORTS_32BIT_KERNEL
>> 669 select SYS_SUPPORTS_64BIT_KERNEL
>> 670 select SYS_SUPPORTS_BIG_ENDIAN
>> 671 select WAR_R4600_V1_INDEX_ICACHEOP
>> 672 select WAR_R4600_V1_HIT_CACHEOP
>> 673 select WAR_R4600_V2_HIT_CACHEOP
>> 674 select MIPS_L1_CACHE_SHIFT_7
>> 675 help
>> 676 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 677 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 678 that runs on these, say Y here.
>> 679
>> 680 config SGI_IP27
>> 681 bool "SGI IP27 (Origin200/2000)"
>> 682 select ARCH_HAS_PHYS_TO_DMA
>> 683 select ARCH_SPARSEMEM_ENABLE
>> 684 select FW_ARC
>> 685 select FW_ARC64
>> 686 select ARC_CMDLINE_ONLY
>> 687 select BOOT_ELF64
>> 688 select DEFAULT_SGI_PARTITION
>> 689 select FORCE_PCI
>> 690 select SYS_HAS_EARLY_PRINTK
>> 691 select HAVE_PCI
>> 692 select IRQ_MIPS_CPU
>> 693 select IRQ_DOMAIN_HIERARCHY
>> 694 select NR_CPUS_DEFAULT_64
>> 695 select PCI_DRIVERS_GENERIC
>> 696 select PCI_XTALK_BRIDGE
>> 697 select SYS_HAS_CPU_R10000
>> 698 select SYS_SUPPORTS_64BIT_KERNEL
>> 699 select SYS_SUPPORTS_BIG_ENDIAN
>> 700 select SYS_SUPPORTS_NUMA
>> 701 select SYS_SUPPORTS_SMP
>> 702 select WAR_R10000_LLSC
>> 703 select MIPS_L1_CACHE_SHIFT_7
>> 704 select NUMA
>> 705 select HAVE_ARCH_NODEDATA_EXTENSION
>> 706 help
>> 707 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 708 workstations. To compile a Linux kernel that runs on these, say Y
>> 709 here.
>> 710
>> 711 config SGI_IP28
>> 712 bool "SGI IP28 (Indigo2 R10k)"
>> 713 select ARC_MEMORY
>> 714 select ARC_PROMLIB
>> 715 select FW_ARC
>> 716 select FW_ARC64
>> 717 select ARCH_MIGHT_HAVE_PC_SERIO
>> 718 select BOOT_ELF64
>> 719 select CEVT_R4K
>> 720 select CSRC_R4K
>> 721 select DEFAULT_SGI_PARTITION
>> 722 select DMA_NONCOHERENT
>> 723 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 724 select IRQ_MIPS_CPU
>> 725 select HAVE_EISA
>> 726 select I8253
>> 727 select I8259
>> 728 select SGI_HAS_I8042
>> 729 select SGI_HAS_INDYDOG
>> 730 select SGI_HAS_HAL2
>> 731 select SGI_HAS_SEEQ
>> 732 select SGI_HAS_WD93
>> 733 select SGI_HAS_ZILOG
>> 734 select SWAP_IO_SPACE
>> 735 select SYS_HAS_CPU_R10000
>> 736 select SYS_HAS_EARLY_PRINTK
>> 737 select SYS_SUPPORTS_64BIT_KERNEL
>> 738 select SYS_SUPPORTS_BIG_ENDIAN
>> 739 select WAR_R10000_LLSC
>> 740 select MIPS_L1_CACHE_SHIFT_7
>> 741 help
>> 742 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 743 kernel that runs on these, say Y here.
>> 744
>> 745 config SGI_IP30
>> 746 bool "SGI IP30 (Octane/Octane2)"
>> 747 select ARCH_HAS_PHYS_TO_DMA
>> 748 select FW_ARC
>> 749 select FW_ARC64
>> 750 select BOOT_ELF64
>> 751 select CEVT_R4K
>> 752 select CSRC_R4K
>> 753 select FORCE_PCI
>> 754 select SYNC_R4K if SMP
>> 755 select ZONE_DMA32
>> 756 select HAVE_PCI
>> 757 select IRQ_MIPS_CPU
>> 758 select IRQ_DOMAIN_HIERARCHY
>> 759 select PCI_DRIVERS_GENERIC
>> 760 select PCI_XTALK_BRIDGE
>> 761 select SYS_HAS_EARLY_PRINTK
>> 762 select SYS_HAS_CPU_R10000
>> 763 select SYS_SUPPORTS_64BIT_KERNEL
>> 764 select SYS_SUPPORTS_BIG_ENDIAN
>> 765 select SYS_SUPPORTS_SMP
>> 766 select WAR_R10000_LLSC
>> 767 select MIPS_L1_CACHE_SHIFT_7
>> 768 select ARC_MEMORY
>> 769 help
>> 770 These are the SGI Octane and Octane2 graphics workstations. To
>> 771 compile a Linux kernel that runs on these, say Y here.
>> 772
>> 773 config SGI_IP32
>> 774 bool "SGI IP32 (O2)"
>> 775 select ARC_MEMORY
>> 776 select ARC_PROMLIB
>> 777 select ARCH_HAS_PHYS_TO_DMA
>> 778 select FW_ARC
>> 779 select FW_ARC32
>> 780 select BOOT_ELF32
>> 781 select CEVT_R4K
>> 782 select CSRC_R4K
>> 783 select DMA_NONCOHERENT
>> 784 select HAVE_PCI
>> 785 select IRQ_MIPS_CPU
>> 786 select R5000_CPU_SCACHE
>> 787 select RM7000_CPU_SCACHE
>> 788 select SYS_HAS_CPU_R5000
>> 789 select SYS_HAS_CPU_R10000 if BROKEN
>> 790 select SYS_HAS_CPU_RM7000
>> 791 select SYS_HAS_CPU_NEVADA
>> 792 select SYS_SUPPORTS_64BIT_KERNEL
>> 793 select SYS_SUPPORTS_BIG_ENDIAN
>> 794 select WAR_ICACHE_REFILLS
>> 795 help
>> 796 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 797
>> 798 config SIBYTE_CRHINE
>> 799 bool "Sibyte BCM91120C-CRhine"
>> 800 select BOOT_ELF32
>> 801 select SIBYTE_BCM1120
>> 802 select SWAP_IO_SPACE
>> 803 select SYS_HAS_CPU_SB1
>> 804 select SYS_SUPPORTS_BIG_ENDIAN
>> 805 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 806
>> 807 config SIBYTE_CARMEL
>> 808 bool "Sibyte BCM91120x-Carmel"
>> 809 select BOOT_ELF32
>> 810 select SIBYTE_BCM1120
>> 811 select SWAP_IO_SPACE
>> 812 select SYS_HAS_CPU_SB1
>> 813 select SYS_SUPPORTS_BIG_ENDIAN
>> 814 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 815
>> 816 config SIBYTE_CRHONE
>> 817 bool "Sibyte BCM91125C-CRhone"
>> 818 select BOOT_ELF32
>> 819 select SIBYTE_BCM1125
>> 820 select SWAP_IO_SPACE
>> 821 select SYS_HAS_CPU_SB1
>> 822 select SYS_SUPPORTS_BIG_ENDIAN
>> 823 select SYS_SUPPORTS_HIGHMEM
>> 824 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 825
>> 826 config SIBYTE_RHONE
>> 827 bool "Sibyte BCM91125E-Rhone"
>> 828 select BOOT_ELF32
>> 829 select SIBYTE_BCM1125H
>> 830 select SWAP_IO_SPACE
>> 831 select SYS_HAS_CPU_SB1
>> 832 select SYS_SUPPORTS_BIG_ENDIAN
>> 833 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 834
>> 835 config SIBYTE_SWARM
>> 836 bool "Sibyte BCM91250A-SWARM"
>> 837 select BOOT_ELF32
>> 838 select HAVE_PATA_PLATFORM
>> 839 select SIBYTE_SB1250
>> 840 select SWAP_IO_SPACE
>> 841 select SYS_HAS_CPU_SB1
>> 842 select SYS_SUPPORTS_BIG_ENDIAN
>> 843 select SYS_SUPPORTS_HIGHMEM
>> 844 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 845 select ZONE_DMA32 if 64BIT
>> 846 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 847
>> 848 config SIBYTE_LITTLESUR
>> 849 bool "Sibyte BCM91250C2-LittleSur"
>> 850 select BOOT_ELF32
>> 851 select HAVE_PATA_PLATFORM
>> 852 select SIBYTE_SB1250
>> 853 select SWAP_IO_SPACE
>> 854 select SYS_HAS_CPU_SB1
>> 855 select SYS_SUPPORTS_BIG_ENDIAN
>> 856 select SYS_SUPPORTS_HIGHMEM
>> 857 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 858 select ZONE_DMA32 if 64BIT
>> 859
>> 860 config SIBYTE_SENTOSA
>> 861 bool "Sibyte BCM91250E-Sentosa"
>> 862 select BOOT_ELF32
>> 863 select SIBYTE_SB1250
>> 864 select SWAP_IO_SPACE
>> 865 select SYS_HAS_CPU_SB1
>> 866 select SYS_SUPPORTS_BIG_ENDIAN
>> 867 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 868 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 869
>> 870 config SIBYTE_BIGSUR
>> 871 bool "Sibyte BCM91480B-BigSur"
>> 872 select BOOT_ELF32
>> 873 select NR_CPUS_DEFAULT_4
>> 874 select SIBYTE_BCM1x80
>> 875 select SWAP_IO_SPACE
>> 876 select SYS_HAS_CPU_SB1
>> 877 select SYS_SUPPORTS_BIG_ENDIAN
>> 878 select SYS_SUPPORTS_HIGHMEM
>> 879 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 880 select ZONE_DMA32 if 64BIT
>> 881 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 882
>> 883 config SNI_RM
>> 884 bool "SNI RM200/300/400"
>> 885 select ARC_MEMORY
>> 886 select ARC_PROMLIB
>> 887 select FW_ARC if CPU_LITTLE_ENDIAN
>> 888 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 889 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 890 select ARCH_MAY_HAVE_PC_FDC
>> 891 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 892 select ARCH_MIGHT_HAVE_PC_SERIO
>> 893 select BOOT_ELF32
>> 894 select CEVT_R4K
>> 895 select CSRC_R4K
>> 896 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 897 select DMA_NONCOHERENT
>> 898 select GENERIC_ISA_DMA
>> 899 select HAVE_EISA
>> 900 select HAVE_PCSPKR_PLATFORM
>> 901 select HAVE_PCI
>> 902 select IRQ_MIPS_CPU
>> 903 select I8253
>> 904 select I8259
>> 905 select ISA
>> 906 select MIPS_L1_CACHE_SHIFT_6
>> 907 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 908 select SYS_HAS_CPU_R4X00
>> 909 select SYS_HAS_CPU_R5000
>> 910 select SYS_HAS_CPU_R10000
>> 911 select R5000_CPU_SCACHE
>> 912 select SYS_HAS_EARLY_PRINTK
>> 913 select SYS_SUPPORTS_32BIT_KERNEL
>> 914 select SYS_SUPPORTS_64BIT_KERNEL
>> 915 select SYS_SUPPORTS_BIG_ENDIAN
>> 916 select SYS_SUPPORTS_HIGHMEM
>> 917 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 918 select WAR_R4600_V2_HIT_CACHEOP
>> 919 help
>> 920 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 921 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 922 Technology and now in turn merged with Fujitsu. Say Y here to
>> 923 support this machine type.
>> 924
>> 925 config MACH_TX49XX
>> 926 bool "Toshiba TX49 series based machines"
>> 927 select WAR_TX49XX_ICACHE_INDEX_INV
>> 928
>> 929 config MIKROTIK_RB532
>> 930 bool "Mikrotik RB532 boards"
>> 931 select CEVT_R4K
>> 932 select CSRC_R4K
>> 933 select DMA_NONCOHERENT
>> 934 select HAVE_PCI
>> 935 select IRQ_MIPS_CPU
>> 936 select SYS_HAS_CPU_MIPS32_R1
>> 937 select SYS_SUPPORTS_32BIT_KERNEL
>> 938 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 939 select SWAP_IO_SPACE
>> 940 select BOOT_RAW
>> 941 select GPIOLIB
>> 942 select MIPS_L1_CACHE_SHIFT_4
>> 943 help
>> 944 Support the Mikrotik(tm) RouterBoard 532 series,
>> 945 based on the IDT RC32434 SoC.
>> 946
>> 947 config CAVIUM_OCTEON_SOC
>> 948 bool "Cavium Networks Octeon SoC based boards"
>> 949 select CEVT_R4K
>> 950 select ARCH_HAS_PHYS_TO_DMA
>> 951 select HAVE_RAPIDIO
>> 952 select PHYS_ADDR_T_64BIT
>> 953 select SYS_SUPPORTS_64BIT_KERNEL
>> 954 select SYS_SUPPORTS_BIG_ENDIAN
>> 955 select EDAC_SUPPORT
>> 956 select EDAC_ATOMIC_SCRUB
>> 957 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 958 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 959 select SYS_HAS_EARLY_PRINTK
>> 960 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 961 select HAVE_PCI
>> 962 select HAVE_PLAT_DELAY
>> 963 select HAVE_PLAT_FW_INIT_CMDLINE
>> 964 select HAVE_PLAT_MEMCPY
>> 965 select ZONE_DMA32
>> 966 select GPIOLIB
>> 967 select USE_OF
>> 968 select ARCH_SPARSEMEM_ENABLE
>> 969 select SYS_SUPPORTS_SMP
>> 970 select NR_CPUS_DEFAULT_64
>> 971 select MIPS_NR_CPU_NR_MAP_1024
>> 972 select BUILTIN_DTB
>> 973 select MTD
>> 974 select MTD_COMPLEX_MAPPINGS
>> 975 select SWIOTLB
>> 976 select SYS_SUPPORTS_RELOCATABLE
>> 977 help
>> 978 This option supports all of the Octeon reference boards from Cavium
>> 979 Networks. It builds a kernel that dynamically determines the Octeon
>> 980 CPU type and supports all known board reference implementations.
>> 981 Some of the supported boards are:
>> 982 EBT3000
>> 983 EBH3000
>> 984 EBH3100
>> 985 Thunder
>> 986 Kodama
>> 987 Hikari
>> 988 Say Y here for most Octeon reference boards.
>> 989
>> 990 endchoice
>> 991
>> 992 source "arch/mips/alchemy/Kconfig"
>> 993 source "arch/mips/ath25/Kconfig"
>> 994 source "arch/mips/ath79/Kconfig"
>> 995 source "arch/mips/bcm47xx/Kconfig"
>> 996 source "arch/mips/bcm63xx/Kconfig"
>> 997 source "arch/mips/bmips/Kconfig"
>> 998 source "arch/mips/generic/Kconfig"
>> 999 source "arch/mips/ingenic/Kconfig"
>> 1000 source "arch/mips/jazz/Kconfig"
>> 1001 source "arch/mips/lantiq/Kconfig"
>> 1002 source "arch/mips/pic32/Kconfig"
>> 1003 source "arch/mips/ralink/Kconfig"
>> 1004 source "arch/mips/sgi-ip27/Kconfig"
>> 1005 source "arch/mips/sibyte/Kconfig"
>> 1006 source "arch/mips/txx9/Kconfig"
>> 1007 source "arch/mips/cavium-octeon/Kconfig"
>> 1008 source "arch/mips/loongson2ef/Kconfig"
>> 1009 source "arch/mips/loongson32/Kconfig"
>> 1010 source "arch/mips/loongson64/Kconfig"
>> 1011
>> 1012 endmenu
>> 1013
>> 1014 config GENERIC_HWEIGHT
363 bool 1015 bool
364 default y if KMSAN || KASAN !! 1016 default y
365 1017
366 config GENERIC_BUG !! 1018 config GENERIC_CALIBRATE_DELAY
367 def_bool y !! 1019 bool
368 depends on BUG !! 1020 default y
369 select GENERIC_BUG_RELATIVE_POINTERS i <<
370 1021
371 config GENERIC_BUG_RELATIVE_POINTERS !! 1022 config SCHED_OMIT_FRAME_POINTER
>> 1023 bool
>> 1024 default y
>> 1025
>> 1026 #
>> 1027 # Select some configuration options automatically based on user selections.
>> 1028 #
>> 1029 config FW_ARC
372 bool 1030 bool
373 1031
374 config ARCH_MAY_HAVE_PC_FDC 1032 config ARCH_MAY_HAVE_PC_FDC
375 def_bool y !! 1033 bool
376 depends on ISA_DMA_API <<
377 1034
378 config GENERIC_CALIBRATE_DELAY !! 1035 config BOOT_RAW
379 def_bool y !! 1036 bool
380 1037
381 config ARCH_HAS_CPU_RELAX !! 1038 config CEVT_BCM1480
382 def_bool y !! 1039 bool
383 1040
384 config ARCH_HIBERNATION_POSSIBLE !! 1041 config CEVT_DS1287
385 def_bool y !! 1042 bool
386 1043
387 config ARCH_SUSPEND_POSSIBLE !! 1044 config CEVT_GT641XX
388 def_bool y !! 1045 bool
389 1046
390 config AUDIT_ARCH !! 1047 config CEVT_R4K
391 def_bool y if X86_64 !! 1048 bool
392 1049
393 config KASAN_SHADOW_OFFSET !! 1050 config CEVT_SB1250
394 hex !! 1051 bool
395 depends on KASAN <<
396 default 0xdffffc0000000000 <<
397 1052
398 config HAVE_INTEL_TXT !! 1053 config CEVT_TXX9
399 def_bool y !! 1054 bool
400 depends on INTEL_IOMMU && ACPI <<
401 1055
402 config X86_64_SMP !! 1056 config CSRC_BCM1480
403 def_bool y !! 1057 bool
404 depends on X86_64 && SMP <<
405 1058
406 config ARCH_SUPPORTS_UPROBES !! 1059 config CSRC_IOASIC
407 def_bool y !! 1060 bool
408 1061
409 config FIX_EARLYCON_MEM !! 1062 config CSRC_R4K
410 def_bool y !! 1063 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1064 bool
411 1065
412 config DYNAMIC_PHYSICAL_MASK !! 1066 config CSRC_SB1250
413 bool 1067 bool
414 1068
415 config PGTABLE_LEVELS !! 1069 config MIPS_CLOCK_VSYSCALL
416 int !! 1070 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
417 default 5 if X86_5LEVEL <<
418 default 4 if X86_64 <<
419 default 3 if X86_PAE <<
420 default 2 <<
421 1071
422 config CC_HAS_SANE_STACKPROTECTOR !! 1072 config GPIO_TXX9
>> 1073 select GPIOLIB
423 bool 1074 bool
424 default $(success,$(srctree)/scripts/g <<
425 default $(success,$(srctree)/scripts/g <<
426 help <<
427 We have to make sure stack protector <<
428 the compiler produces broken code or <<
429 the segment on 32-bit kernels. <<
430 1075
431 menu "Processor type and features" !! 1076 config FW_CFE
>> 1077 bool
432 1078
433 config SMP !! 1079 config ARCH_SUPPORTS_UPROBES
434 bool "Symmetric multi-processing suppo !! 1080 bool
435 help <<
436 This enables support for systems wit <<
437 a system with only one CPU, say N. I <<
438 than one CPU, say Y. <<
439 1081
440 If you say N here, the kernel will r !! 1082 config DMA_PERDEV_COHERENT
441 machines, but will use only one CPU !! 1083 bool
442 you say Y here, the kernel will run !! 1084 select ARCH_HAS_SETUP_DMA_OPS
443 uniprocessor machines. On a uniproce !! 1085 select DMA_NONCOHERENT
444 will run faster if you say N here. <<
445 1086
446 Note that if you say Y here and choo !! 1087 config DMA_NONCOHERENT
447 "Pentium" under "Processor family", !! 1088 bool
448 architectures. Similarly, multiproce !! 1089 #
449 architecture may not work on all Pen !! 1090 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1091 # Attribute bits. It is believed that the uncached access through
>> 1092 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1093 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1094 # significant advantages.
>> 1095 #
>> 1096 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1097 select ARCH_HAS_DMA_PREP_COHERENT
>> 1098 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1099 select ARCH_HAS_DMA_SET_UNCACHED
>> 1100 select DMA_NONCOHERENT_MMAP
>> 1101 select NEED_DMA_MAP_STATE
450 1102
451 People using multiprocessor machines !! 1103 config SYS_HAS_EARLY_PRINTK
452 Y to "Enhanced Real Time Clock Suppo !! 1104 bool
453 Management" code will be disabled if <<
454 1105
455 See also <file:Documentation/arch/x8 !! 1106 config SYS_SUPPORTS_HOTPLUG_CPU
456 <file:Documentation/admin-guide/lock !! 1107 bool
457 <http://www.tldp.org/docs.html#howto <<
458 1108
459 If you don't know what to do here, s !! 1109 config MIPS_BONITO64
>> 1110 bool
460 1111
461 config X86_X2APIC !! 1112 config MIPS_MSC
462 bool "Support x2apic" !! 1113 bool
463 depends on X86_LOCAL_APIC && X86_64 && <<
464 help <<
465 This enables x2apic support on CPUs <<
466 <<
467 This allows 32-bit apic IDs (so it c <<
468 and accesses the local apic via MSRs <<
469 <<
470 Some Intel systems circa 2022 and la <<
471 and can not fall back to the legacy <<
472 enabled in the BIOS. They will boot <<
473 without enabling this option. <<
474 1114
475 If you don't know what to do here, s !! 1115 config SYNC_R4K
>> 1116 bool
476 1117
477 config X86_POSTED_MSI !! 1118 config NO_IOPORT_MAP
478 bool "Enable MSI and MSI-x delivery by !! 1119 def_bool n
479 depends on X86_64 && IRQ_REMAP <<
480 help <<
481 This enables MSIs that are under int <<
482 posted interrupts to the host kernel <<
483 potentially be improved by coalescin <<
484 frequency bursts. <<
485 1120
486 If you don't know what to do here, s !! 1121 config GENERIC_CSUM
>> 1122 def_bool CPU_NO_LOAD_STORE_LR
487 1123
488 config X86_MPPARSE !! 1124 config GENERIC_ISA_DMA
489 bool "Enable MPS table" if ACPI !! 1125 bool
490 default y !! 1126 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
491 depends on X86_LOCAL_APIC !! 1127 select ISA_DMA_API
492 help <<
493 For old smp systems that do not have <<
494 (esp with 64bit cpus) with acpi supp <<
495 1128
496 config X86_CPU_RESCTRL !! 1129 config GENERIC_ISA_DMA_SUPPORT_BROKEN
497 bool "x86 CPU resource control support !! 1130 bool
498 depends on X86 && (CPU_SUP_INTEL || CP !! 1131 select GENERIC_ISA_DMA
499 select KERNFS <<
500 select PROC_CPU_RESCTRL if PRO <<
501 help <<
502 Enable x86 CPU resource control supp <<
503 1132
504 Provide support for the allocation a !! 1133 config HAVE_PLAT_DELAY
505 usage by the CPU. !! 1134 bool
506 1135
507 Intel calls this Intel Resource Dire !! 1136 config HAVE_PLAT_FW_INIT_CMDLINE
508 (Intel(R) RDT). More information abo !! 1137 bool
509 Intel x86 Architecture Software Deve <<
510 1138
511 AMD calls this AMD Platform Quality !! 1139 config HAVE_PLAT_MEMCPY
512 More information about AMD QoS can b !! 1140 bool
513 Platform Quality of Service Extensio <<
514 1141
515 Say N if unsure. !! 1142 config ISA_DMA_API
>> 1143 bool
516 1144
517 config X86_FRED !! 1145 config SYS_SUPPORTS_RELOCATABLE
518 bool "Flexible Return and Event Delive !! 1146 bool
519 depends on X86_64 <<
520 help 1147 help
521 When enabled, try to use Flexible Re !! 1148 Selected if the platform supports relocating the kernel.
522 instead of the legacy SYSCALL/SYSENT !! 1149 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
523 ring transitions and exception/inter !! 1150 to allow access to command line and entropy sources.
524 system supports it. <<
525 1151
526 config X86_BIGSMP !! 1152 #
527 bool "Support for big SMP systems with !! 1153 # Endianness selection. Sufficiently obscure so many users don't know what to
528 depends on SMP && X86_32 !! 1154 # answer,so we try hard to limit the available choices. Also the use of a
>> 1155 # choice statement should be more obvious to the user.
>> 1156 #
>> 1157 choice
>> 1158 prompt "Endianness selection"
529 help 1159 help
530 This option is needed for the system !! 1160 Some MIPS machines can be configured for either little or big endian
>> 1161 byte order. These modes require different kernels and a different
>> 1162 Linux distribution. In general there is one preferred byteorder for a
>> 1163 particular system but some systems are just as commonly used in the
>> 1164 one or the other endianness.
>> 1165
>> 1166 config CPU_BIG_ENDIAN
>> 1167 bool "Big endian"
>> 1168 depends on SYS_SUPPORTS_BIG_ENDIAN
>> 1169
>> 1170 config CPU_LITTLE_ENDIAN
>> 1171 bool "Little endian"
>> 1172 depends on SYS_SUPPORTS_LITTLE_ENDIAN
531 1173
532 config X86_EXTENDED_PLATFORM !! 1174 endchoice
533 bool "Support for extended (non-PC) x8 <<
534 default y <<
535 help <<
536 If you disable this option then the <<
537 standard PC platforms. (which covers <<
538 systems out there.) <<
539 <<
540 If you enable this option then you'l <<
541 for the following non-PC x86 platfor <<
542 CONFIG_64BIT. <<
543 <<
544 32-bit platforms (CONFIG_64BIT=n): <<
545 Goldfish (Android emulator) <<
546 AMD Elan <<
547 RDC R-321x SoC <<
548 SGI 320/540 (Visual Workstatio <<
549 STA2X11-based (e.g. Northville <<
550 Moorestown MID devices <<
551 <<
552 64-bit platforms (CONFIG_64BIT=y): <<
553 Numascale NumaChip <<
554 ScaleMP vSMP <<
555 SGI Ultraviolet <<
556 <<
557 If you have one of these systems, or <<
558 generic distribution kernel, say Y h <<
559 <<
560 # This is an alphabetically sorted list of 64 <<
561 # Please maintain the alphabetic order if and <<
562 config X86_NUMACHIP <<
563 bool "Numascale NumaChip" <<
564 depends on X86_64 <<
565 depends on X86_EXTENDED_PLATFORM <<
566 depends on NUMA <<
567 depends on SMP <<
568 depends on X86_X2APIC <<
569 depends on PCI_MMCONFIG <<
570 help <<
571 Adds support for Numascale NumaChip <<
572 enable more than ~168 cores. <<
573 If you don't have one of these, you <<
574 <<
575 config X86_VSMP <<
576 bool "ScaleMP vSMP" <<
577 select HYPERVISOR_GUEST <<
578 select PARAVIRT <<
579 depends on X86_64 && PCI <<
580 depends on X86_EXTENDED_PLATFORM <<
581 depends on SMP <<
582 help <<
583 Support for ScaleMP vSMP systems. S <<
584 supposed to run on these EM64T-based <<
585 if you have one of these machines. <<
586 <<
587 config X86_UV <<
588 bool "SGI Ultraviolet" <<
589 depends on X86_64 <<
590 depends on X86_EXTENDED_PLATFORM <<
591 depends on NUMA <<
592 depends on EFI <<
593 depends on KEXEC_CORE <<
594 depends on X86_X2APIC <<
595 depends on PCI <<
596 help <<
597 This option is needed in order to su <<
598 If you don't have one of these, you <<
599 <<
600 # Following is an alphabetically sorted list o <<
601 # Please maintain the alphabetic order if and <<
602 <<
603 config X86_GOLDFISH <<
604 bool "Goldfish (Virtual Platform)" <<
605 depends on X86_EXTENDED_PLATFORM <<
606 help <<
607 Enable support for the Goldfish virt <<
608 for Android development. Unless you <<
609 Goldfish emulator say N here. <<
610 <<
611 config X86_INTEL_CE <<
612 bool "CE4100 TV platform" <<
613 depends on PCI <<
614 depends on PCI_GODIRECT <<
615 depends on X86_IO_APIC <<
616 depends on X86_32 <<
617 depends on X86_EXTENDED_PLATFORM <<
618 select X86_REBOOTFIXUPS <<
619 select OF <<
620 select OF_EARLY_FLATTREE <<
621 help <<
622 Select for the Intel CE media proces <<
623 This option compiles in support for <<
624 boxes and media devices. <<
625 <<
626 config X86_INTEL_MID <<
627 bool "Intel MID platform support" <<
628 depends on X86_EXTENDED_PLATFORM <<
629 depends on X86_PLATFORM_DEVICES <<
630 depends on PCI <<
631 depends on X86_64 || (PCI_GOANY && X86 <<
632 depends on X86_IO_APIC <<
633 select I2C <<
634 select DW_APB_TIMER <<
635 select INTEL_SCU_PCI <<
636 help <<
637 Select to build a kernel capable of <<
638 Internet Device) platform systems wh <<
639 interfaces. If you are building for <<
640 <<
641 Intel MID platforms are based on an <<
642 consume less power than most of the <<
643 <<
644 config X86_INTEL_QUARK <<
645 bool "Intel Quark platform support" <<
646 depends on X86_32 <<
647 depends on X86_EXTENDED_PLATFORM <<
648 depends on X86_PLATFORM_DEVICES <<
649 depends on X86_TSC <<
650 depends on PCI <<
651 depends on PCI_GOANY <<
652 depends on X86_IO_APIC <<
653 select IOSF_MBI <<
654 select INTEL_IMR <<
655 select COMMON_CLK <<
656 help <<
657 Select to include support for Quark <<
658 Say Y here if you have a Quark based <<
659 compatible Intel Galileo. <<
660 <<
661 config X86_INTEL_LPSS <<
662 bool "Intel Low Power Subsystem Suppor <<
663 depends on X86 && ACPI && PCI <<
664 select COMMON_CLK <<
665 select PINCTRL <<
666 select IOSF_MBI <<
667 help <<
668 Select to build support for Intel Lo <<
669 found on Intel Lynxpoint PCH. Select <<
670 things like clock tree (common clock <<
671 which are needed by the LPSS periphe <<
672 <<
673 config X86_AMD_PLATFORM_DEVICE <<
674 bool "AMD ACPI2Platform devices suppor <<
675 depends on ACPI <<
676 select COMMON_CLK <<
677 select PINCTRL <<
678 help <<
679 Select to interpret AMD specific ACP <<
680 such as I2C, UART, GPIO found on AMD <<
681 I2C and UART depend on COMMON_CLK to <<
682 implemented under PINCTRL subsystem. <<
683 <<
684 config IOSF_MBI <<
685 tristate "Intel SoC IOSF Sideband supp <<
686 depends on PCI <<
687 help <<
688 This option enables sideband registe <<
689 platforms. On these platforms the IO <<
690 MSR's for some register accesses, mo <<
691 and power. Drivers may query the ava <<
692 determine if they need the sideband <<
693 platforms. The sideband is available <<
694 This list is not meant to be exclusi <<
695 - BayTrail <<
696 - Braswell <<
697 - Quark <<
698 <<
699 You should say Y if you are running <<
700 <<
701 config IOSF_MBI_DEBUG <<
702 bool "Enable IOSF sideband access thro <<
703 depends on IOSF_MBI && DEBUG_FS <<
704 help <<
705 Select this option to expose the IOS <<
706 MDR, MCRX) through debugfs to write <<
707 different units on the SoC. This is <<
708 state information for debug and anal <<
709 mechanism, users of this option woul <<
710 device they want to access. <<
711 <<
712 If you don't require the option or a <<
713 <<
714 config X86_RDC321X <<
715 bool "RDC R-321x SoC" <<
716 depends on X86_32 <<
717 depends on X86_EXTENDED_PLATFORM <<
718 select M486 <<
719 select X86_REBOOTFIXUPS <<
720 help <<
721 This option is needed for RDC R-321x <<
722 as R-8610-(G). <<
723 If you don't have one of these chips <<
724 <<
725 config X86_32_NON_STANDARD <<
726 bool "Support non-standard 32-bit SMP <<
727 depends on X86_32 && SMP <<
728 depends on X86_EXTENDED_PLATFORM <<
729 help <<
730 This option compiles in the bigsmp a <<
731 subarchitectures. It is intended fo <<
732 kernel. If you select them all, kern <<
733 one and will fallback to default. <<
734 1175
735 # Alphabetically sorted list of Non standard 3 !! 1176 config EXPORT_UASM
>> 1177 bool
736 1178
737 config X86_SUPPORTS_MEMORY_FAILURE !! 1179 config SYS_SUPPORTS_APM_EMULATION
738 def_bool y !! 1180 bool
739 # MCE code calls memory_failure(): <<
740 depends on X86_MCE <<
741 # On 32-bit this adds too big of NODES <<
742 # On 32-bit SPARSEMEM adds too big of <<
743 depends on X86_64 || !SPARSEMEM <<
744 select ARCH_SUPPORTS_MEMORY_FAILURE <<
745 <<
746 config STA2X11 <<
747 bool "STA2X11 Companion Chip Support" <<
748 depends on X86_32_NON_STANDARD && PCI <<
749 select SWIOTLB <<
750 select MFD_STA2X11 <<
751 select GPIOLIB <<
752 help <<
753 This adds support for boards based o <<
754 a.k.a. "ConneXt". The chip is used i <<
755 PC chipset, so all "standard" periph <<
756 option is selected the kernel will s <<
757 standard PC machines. <<
758 <<
759 config X86_32_IRIS <<
760 tristate "Eurobraille/Iris poweroff mo <<
761 depends on X86_32 <<
762 help <<
763 The Iris machines from EuroBraille d <<
764 to shut themselves down properly. A <<
765 needed to do so, which is what this <<
766 kernel shutdown. <<
767 1181
768 This is only for Iris machines from !! 1182 config SYS_SUPPORTS_BIG_ENDIAN
>> 1183 bool
769 1184
770 If unused, say N. !! 1185 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1186 bool
771 1187
772 config SCHED_OMIT_FRAME_POINTER !! 1188 config MIPS_HUGE_TLB_SUPPORT
773 def_bool y !! 1189 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
774 prompt "Single-depth WCHAN output" <<
775 depends on X86 <<
776 help <<
777 Calculate simpler /proc/<PID>/wchan <<
778 is disabled then wchan values will r <<
779 caller function. This provides more <<
780 at the expense of slightly more sche <<
781 1190
782 If in doubt, say "Y". !! 1191 config IRQ_MSP_SLP
>> 1192 bool
783 1193
784 menuconfig HYPERVISOR_GUEST !! 1194 config IRQ_MSP_CIC
785 bool "Linux guest support" !! 1195 bool
786 help <<
787 Say Y here to enable options for run <<
788 visors. This option enables basic hy <<
789 setup. <<
790 1196
791 If you say N, all options in this su !! 1197 config IRQ_TXX9
792 disabled, and Linux guest support wo !! 1198 bool
793 1199
794 if HYPERVISOR_GUEST !! 1200 config IRQ_GT641XX
>> 1201 bool
795 1202
796 config PARAVIRT !! 1203 config PCI_GT64XXX_PCI0
797 bool "Enable paravirtualization code" !! 1204 bool
798 depends on HAVE_STATIC_CALL <<
799 help <<
800 This changes the kernel so it can mo <<
801 under a hypervisor, potentially impr <<
802 over full virtualization. However, <<
803 the kernel is theoretically slower a <<
804 1205
805 config PARAVIRT_XXL !! 1206 config PCI_XTALK_BRIDGE
806 bool 1207 bool
807 1208
808 config PARAVIRT_DEBUG !! 1209 config NO_EXCEPT_FILL
809 bool "paravirt-ops debugging" !! 1210 bool
810 depends on PARAVIRT && DEBUG_KERNEL <<
811 help <<
812 Enable to debug paravirt_ops interna <<
813 a paravirt_op is missing when it is <<
814 1211
815 config PARAVIRT_SPINLOCKS !! 1212 config MIPS_SPRAM
816 bool "Paravirtualization layer for spi !! 1213 bool
817 depends on PARAVIRT && SMP <<
818 help <<
819 Paravirtualized spinlocks allow a pv <<
820 spinlock implementation with somethi <<
821 (for example, block the virtual CPU <<
822 1214
823 It has a minimal impact on native ke !! 1215 config SWAP_IO_SPACE
824 benefit on paravirtualized KVM / Xen !! 1216 bool
825 1217
826 If you are unsure how to answer this !! 1218 config SGI_HAS_INDYDOG
>> 1219 bool
827 1220
828 config X86_HV_CALLBACK_VECTOR !! 1221 config SGI_HAS_HAL2
829 def_bool n !! 1222 bool
830 1223
831 source "arch/x86/xen/Kconfig" !! 1224 config SGI_HAS_SEEQ
>> 1225 bool
832 1226
833 config KVM_GUEST !! 1227 config SGI_HAS_WD93
834 bool "KVM Guest support (including kvm !! 1228 bool
835 depends on PARAVIRT <<
836 select PARAVIRT_CLOCK <<
837 select ARCH_CPUIDLE_HALTPOLL <<
838 select X86_HV_CALLBACK_VECTOR <<
839 default y <<
840 help <<
841 This option enables various optimiza <<
842 hypervisor. It includes a paravirtua <<
843 of relying on a PIT (or probably oth <<
844 underlying device model, the host pr <<
845 timing infrastructure such as time o <<
846 1229
847 config ARCH_CPUIDLE_HALTPOLL !! 1230 config SGI_HAS_ZILOG
848 def_bool n !! 1231 bool
849 prompt "Disable host haltpoll when loa <<
850 help <<
851 If virtualized under KVM, disable ho <<
852 1232
853 config PVH !! 1233 config SGI_HAS_I8042
854 bool "Support for running PVH guests" !! 1234 bool
855 help <<
856 This option enables the PVH entry po <<
857 as specified in the x86/HVM direct b <<
858 <<
859 config PARAVIRT_TIME_ACCOUNTING <<
860 bool "Paravirtual steal time accountin <<
861 depends on PARAVIRT <<
862 help <<
863 Select this option to enable fine gr <<
864 accounting. Time spent executing oth <<
865 the current vCPU is discounted from <<
866 that, there can be a small performan <<
867 <<
868 If in doubt, say N here. <<
869 <<
870 config PARAVIRT_CLOCK <<
871 bool <<
872 <<
873 config JAILHOUSE_GUEST <<
874 bool "Jailhouse non-root cell support" <<
875 depends on X86_64 && PCI <<
876 select X86_PM_TIMER <<
877 help <<
878 This option allows to run Linux as g <<
879 cell. You can leave this option disa <<
880 Jailhouse and run Linux afterwards i <<
881 <<
882 config ACRN_GUEST <<
883 bool "ACRN Guest support" <<
884 depends on X86_64 <<
885 select X86_HV_CALLBACK_VECTOR <<
886 help <<
887 This option allows to run Linux as g <<
888 a flexible, lightweight reference op <<
889 real-time and safety-criticality in <<
890 IOT with small footprint and real-ti <<
891 found in https://projectacrn.org/. <<
892 <<
893 config INTEL_TDX_GUEST <<
894 bool "Intel TDX (Trust Domain Extensio <<
895 depends on X86_64 && CPU_SUP_INTEL <<
896 depends on X86_X2APIC <<
897 depends on EFI_STUB <<
898 select ARCH_HAS_CC_PLATFORM <<
899 select X86_MEM_ENCRYPT <<
900 select X86_MCE <<
901 select UNACCEPTED_MEMORY <<
902 help <<
903 Support running as a guest under Int <<
904 the guest kernel can not boot or run <<
905 TDX includes memory encryption and i <<
906 which protect the confidentiality an <<
907 memory contents and CPU state. TDX g <<
908 some attacks from the VMM. <<
909 <<
910 endif # HYPERVISOR_GUEST <<
911 <<
912 source "arch/x86/Kconfig.cpu" <<
913 <<
914 config HPET_TIMER <<
915 def_bool X86_64 <<
916 prompt "HPET Timer Support" if X86_32 <<
917 help <<
918 Use the IA-PC HPET (High Precision E <<
919 time in preference to the PIT and RT <<
920 present. <<
921 HPET is the next generation timer re <<
922 The HPET provides a stable time base <<
923 systems, unlike the TSC, but it is m <<
924 as it is off-chip. The interface us <<
925 in the HPET spec, revision 1. <<
926 <<
927 You can safely choose Y here. Howev <<
928 activated if the platform and the BI <<
929 Otherwise the 8254 will be used for <<
930 1235
931 Choose N to continue using the legac !! 1236 config DEFAULT_SGI_PARTITION
>> 1237 bool
932 1238
933 config HPET_EMULATE_RTC !! 1239 config FW_ARC32
934 def_bool y !! 1240 bool
935 depends on HPET_TIMER && (RTC_DRV_CMOS <<
936 1241
937 # Mark as expert because too many people got i !! 1242 config FW_SNIPROM
938 # The code disables itself when not needed. !! 1243 bool
939 config DMI <<
940 default y <<
941 select DMI_SCAN_MACHINE_NON_EFI_FALLBA <<
942 bool "Enable DMI scanning" if EXPERT <<
943 help <<
944 Enabled scanning of DMI to identify <<
945 here unless you have verified that y <<
946 affected by entries in the DMI black <<
947 BIOS code. <<
948 1244
949 config GART_IOMMU !! 1245 config BOOT_ELF32
950 bool "Old AMD GART IOMMU support" !! 1246 bool
951 select IOMMU_HELPER <<
952 select SWIOTLB <<
953 depends on X86_64 && PCI && AMD_NB <<
954 help <<
955 Provides a driver for older AMD Athl <<
956 GART based hardware IOMMUs. <<
957 1247
958 The GART supports full DMA access fo !! 1248 config MIPS_L1_CACHE_SHIFT_4
959 limitations, on systems with more th !! 1249 bool
960 for USB, sound, many IDE/SATA chipse <<
961 1250
962 Newer systems typically have a moder !! 1251 config MIPS_L1_CACHE_SHIFT_5
963 the CONFIG_AMD_IOMMU=y config option !! 1252 bool
964 1253
965 In normal configurations this driver !! 1254 config MIPS_L1_CACHE_SHIFT_6
966 there's more than 3 GB of memory and !! 1255 bool
967 32-bit limited device. <<
968 1256
969 If unsure, say Y. !! 1257 config MIPS_L1_CACHE_SHIFT_7
>> 1258 bool
970 1259
971 config BOOT_VESA_SUPPORT !! 1260 config MIPS_L1_CACHE_SHIFT
>> 1261 int
>> 1262 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1263 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1264 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1265 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1266 default "5"
>> 1267
>> 1268 config ARC_CMDLINE_ONLY
972 bool 1269 bool
973 help <<
974 If true, at least one selected frame <<
975 of VESA video modes set at an early <<
976 1270
977 config MAXSMP !! 1271 config ARC_CONSOLE
978 bool "Enable Maximum number of SMP Pro !! 1272 bool "ARC console support"
979 depends on X86_64 && SMP && DEBUG_KERN !! 1273 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
980 select CPUMASK_OFFSTACK <<
981 help <<
982 Enable maximum number of CPUS and NU <<
983 If unsure, say N. <<
984 1274
985 # !! 1275 config ARC_MEMORY
986 # The maximum number of CPUs supported: !! 1276 bool
987 # <<
988 # The main config value is NR_CPUS, which defa <<
989 # and which can be configured interactively in <<
990 # [NR_CPUS_RANGE_BEGIN ... NR_CPUS_RANGE_END] <<
991 # <<
992 # The ranges are different on 32-bit and 64-bi <<
993 # hardware capabilities and scalability featur <<
994 # <<
995 # ( If MAXSMP is enabled we just use the highe <<
996 # interactive configuration. ) <<
997 # <<
998 1277
999 config NR_CPUS_RANGE_BEGIN !! 1278 config ARC_PROMLIB
1000 int !! 1279 bool
1001 default NR_CPUS_RANGE_END if MAXSMP <<
1002 default 1 if !SMP <<
1003 default 2 <<
1004 1280
1005 config NR_CPUS_RANGE_END !! 1281 config FW_ARC64
1006 int !! 1282 bool
1007 depends on X86_32 <<
1008 default 64 if SMP && X86_BIGSMP <<
1009 default 8 if SMP && !X86_BIGSMP <<
1010 default 1 if !SMP <<
1011 1283
1012 config NR_CPUS_RANGE_END !! 1284 config BOOT_ELF64
1013 int !! 1285 bool
1014 depends on X86_64 <<
1015 default 8192 if SMP && CPUMASK_OFFST <<
1016 default 512 if SMP && !CPUMASK_OFFS <<
1017 default 1 if !SMP <<
1018 1286
1019 config NR_CPUS_DEFAULT !! 1287 menu "CPU selection"
1020 int <<
1021 depends on X86_32 <<
1022 default 32 if X86_BIGSMP <<
1023 default 8 if SMP <<
1024 default 1 if !SMP <<
1025 1288
1026 config NR_CPUS_DEFAULT !! 1289 choice
1027 int !! 1290 prompt "CPU type"
1028 depends on X86_64 !! 1291 default CPU_R4X00
1029 default 8192 if MAXSMP <<
1030 default 64 if SMP <<
1031 default 1 if !SMP <<
1032 1292
1033 config NR_CPUS !! 1293 config CPU_LOONGSON64
1034 int "Maximum number of CPUs" if SMP & !! 1294 bool "Loongson 64-bit CPU"
1035 range NR_CPUS_RANGE_BEGIN NR_CPUS_RAN !! 1295 depends on SYS_HAS_CPU_LOONGSON64
1036 default NR_CPUS_DEFAULT !! 1296 select ARCH_HAS_PHYS_TO_DMA
>> 1297 select CPU_MIPSR2
>> 1298 select CPU_HAS_PREFETCH
>> 1299 select CPU_SUPPORTS_64BIT_KERNEL
>> 1300 select CPU_SUPPORTS_HIGHMEM
>> 1301 select CPU_SUPPORTS_HUGEPAGES
>> 1302 select CPU_SUPPORTS_MSA
>> 1303 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1304 select CPU_MIPSR2_IRQ_VI
>> 1305 select WEAK_ORDERING
>> 1306 select WEAK_REORDERING_BEYOND_LLSC
>> 1307 select MIPS_ASID_BITS_VARIABLE
>> 1308 select MIPS_PGD_C0_CONTEXT
>> 1309 select MIPS_L1_CACHE_SHIFT_6
>> 1310 select MIPS_FP_SUPPORT
>> 1311 select GPIOLIB
>> 1312 select SWIOTLB
>> 1313 select HAVE_KVM
1037 help 1314 help
1038 This allows you to specify the maxi !! 1315 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1039 kernel will support. If CPUMASK_OF !! 1316 cores implements the MIPS64R2 instruction set with many extensions,
1040 supported value is 8192, otherwise !! 1317 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1041 minimum value which makes sense is !! 1318 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
1042 !! 1319 Loongson-2E/2F is not covered here and will be removed in future.
1043 This is purely to save memory: each <<
1044 to the kernel image. <<
1045 1320
1046 config SCHED_CLUSTER !! 1321 config LOONGSON3_ENHANCEMENT
1047 bool "Cluster scheduler support" !! 1322 bool "New Loongson-3 CPU Enhancements"
1048 depends on SMP !! 1323 default n
1049 default y !! 1324 depends on CPU_LOONGSON64
1050 help 1325 help
1051 Cluster scheduler support improves !! 1326 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1052 making when dealing with machines t !! 1327 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1053 Cluster usually means a couple of C !! 1328 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1054 by sharing mid-level caches, last-l !! 1329 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1055 busses. !! 1330 Fast TLB refill support, etc.
1056 1331
1057 config SCHED_SMT !! 1332 This option enable those enhancements which are not probed at run
1058 def_bool y if SMP !! 1333 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1334 please say 'N' here. If you want a high-performance kernel to run on
>> 1335 new Loongson-3 machines only, please say 'Y' here.
1059 1336
1060 config SCHED_MC !! 1337 config CPU_LOONGSON3_WORKAROUNDS
1061 def_bool y !! 1338 bool "Loongson-3 LLSC Workarounds"
1062 prompt "Multi-core scheduler support" !! 1339 default y if SMP
1063 depends on SMP !! 1340 depends on CPU_LOONGSON64
1064 help 1341 help
1065 Multi-core scheduler support improv !! 1342 Loongson-3 processors have the llsc issues which require workarounds.
1066 making when dealing with multi-core !! 1343 Without workarounds the system may hang unexpectedly.
1067 increased overhead in some places. <<
1068 1344
1069 config SCHED_MC_PRIO !! 1345 Say Y, unless you know what you are doing.
1070 bool "CPU core priorities scheduler s !! 1346
1071 depends on SCHED_MC !! 1347 config CPU_LOONGSON3_CPUCFG_EMULATION
1072 select X86_INTEL_PSTATE if CPU_SUP_IN !! 1348 bool "Emulate the CPUCFG instruction on older Loongson cores"
1073 select X86_AMD_PSTATE if CPU_SUP_AMD <<
1074 select CPU_FREQ <<
1075 default y 1349 default y
>> 1350 depends on CPU_LOONGSON64
1076 help 1351 help
1077 Intel Turbo Boost Max Technology 3. !! 1352 Loongson-3A R4 and newer have the CPUCFG instruction available for
1078 core ordering determined at manufac !! 1353 userland to query CPU capabilities, much like CPUID on x86. This
1079 certain cores to reach higher turbo !! 1354 option provides emulation of the instruction on older Loongson
1080 single threaded workloads) than oth !! 1355 cores, back to Loongson-3A1000.
1081 <<
1082 Enabling this kernel feature teache <<
1083 the TBM3 (aka ITMT) priority order <<
1084 scheduler's CPU selection logic acc <<
1085 overall system performance can be a <<
1086 <<
1087 This feature will have no effect on <<
1088 1356
1089 If unsure say Y here. !! 1357 If unsure, please say Y.
1090 1358
1091 config UP_LATE_INIT !! 1359 config CPU_LOONGSON2E
1092 def_bool y !! 1360 bool "Loongson 2E"
1093 depends on !SMP && X86_LOCAL_APIC !! 1361 depends on SYS_HAS_CPU_LOONGSON2E
>> 1362 select CPU_LOONGSON2EF
>> 1363 help
>> 1364 The Loongson 2E processor implements the MIPS III instruction set
>> 1365 with many extensions.
1094 1366
1095 config X86_UP_APIC !! 1367 It has an internal FPGA northbridge, which is compatible to
1096 bool "Local APIC support on uniproces !! 1368 bonito64.
1097 default PCI_MSI <<
1098 depends on X86_32 && !SMP && !X86_32_ <<
1099 help <<
1100 A local APIC (Advanced Programmable <<
1101 integrated interrupt controller in <<
1102 system which has a processor with a <<
1103 enable and use it. If you say Y her <<
1104 have a local APIC, then the kernel <<
1105 all. The local APIC supports CPU-ge <<
1106 performance counters), and the NMI <<
1107 lockups. <<
1108 <<
1109 config X86_UP_IOAPIC <<
1110 bool "IO-APIC support on uniprocessor <<
1111 depends on X86_UP_APIC <<
1112 help <<
1113 An IO-APIC (I/O Advanced Programmab <<
1114 SMP-capable replacement for PC-styl <<
1115 SMP systems and many recent uniproc <<
1116 <<
1117 If you have a single-CPU system wit <<
1118 to use it. If you say Y here even t <<
1119 an IO-APIC, then the kernel will st <<
1120 1369
1121 config X86_LOCAL_APIC !! 1370 config CPU_LOONGSON2F
1122 def_bool y !! 1371 bool "Loongson 2F"
1123 depends on X86_64 || SMP || X86_32_NO !! 1372 depends on SYS_HAS_CPU_LOONGSON2F
1124 select IRQ_DOMAIN_HIERARCHY !! 1373 select CPU_LOONGSON2EF
>> 1374 select GPIOLIB
>> 1375 help
>> 1376 The Loongson 2F processor implements the MIPS III instruction set
>> 1377 with many extensions.
1125 1378
1126 config ACPI_MADT_WAKEUP !! 1379 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1127 def_bool y !! 1380 have a similar programming interface with FPGA northbridge used in
1128 depends on X86_64 !! 1381 Loongson2E.
1129 depends on ACPI !! 1382
1130 depends on SMP !! 1383 config CPU_LOONGSON1B
1131 depends on X86_LOCAL_APIC !! 1384 bool "Loongson 1B"
>> 1385 depends on SYS_HAS_CPU_LOONGSON1B
>> 1386 select CPU_LOONGSON32
>> 1387 select LEDS_GPIO_REGISTER
>> 1388 help
>> 1389 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1390 Release 1 instruction set and part of the MIPS32 Release 2
>> 1391 instruction set.
>> 1392
>> 1393 config CPU_LOONGSON1C
>> 1394 bool "Loongson 1C"
>> 1395 depends on SYS_HAS_CPU_LOONGSON1C
>> 1396 select CPU_LOONGSON32
>> 1397 select LEDS_GPIO_REGISTER
>> 1398 help
>> 1399 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1400 Release 1 instruction set and part of the MIPS32 Release 2
>> 1401 instruction set.
>> 1402
>> 1403 config CPU_MIPS32_R1
>> 1404 bool "MIPS32 Release 1"
>> 1405 depends on SYS_HAS_CPU_MIPS32_R1
>> 1406 select CPU_HAS_PREFETCH
>> 1407 select CPU_SUPPORTS_32BIT_KERNEL
>> 1408 select CPU_SUPPORTS_HIGHMEM
>> 1409 help
>> 1410 Choose this option to build a kernel for release 1 or later of the
>> 1411 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1412 MIPS processor are based on a MIPS32 processor. If you know the
>> 1413 specific type of processor in your system, choose those that one
>> 1414 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1415 Release 2 of the MIPS32 architecture is available since several
>> 1416 years so chances are you even have a MIPS32 Release 2 processor
>> 1417 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1418 performance.
1132 1419
1133 config X86_IO_APIC !! 1420 config CPU_MIPS32_R2
1134 def_bool y !! 1421 bool "MIPS32 Release 2"
1135 depends on X86_LOCAL_APIC || X86_UP_I !! 1422 depends on SYS_HAS_CPU_MIPS32_R2
>> 1423 select CPU_HAS_PREFETCH
>> 1424 select CPU_SUPPORTS_32BIT_KERNEL
>> 1425 select CPU_SUPPORTS_HIGHMEM
>> 1426 select CPU_SUPPORTS_MSA
>> 1427 select HAVE_KVM
>> 1428 help
>> 1429 Choose this option to build a kernel for release 2 or later of the
>> 1430 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1431 MIPS processor are based on a MIPS32 processor. If you know the
>> 1432 specific type of processor in your system, choose those that one
>> 1433 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1434
>> 1435 config CPU_MIPS32_R5
>> 1436 bool "MIPS32 Release 5"
>> 1437 depends on SYS_HAS_CPU_MIPS32_R5
>> 1438 select CPU_HAS_PREFETCH
>> 1439 select CPU_SUPPORTS_32BIT_KERNEL
>> 1440 select CPU_SUPPORTS_HIGHMEM
>> 1441 select CPU_SUPPORTS_MSA
>> 1442 select HAVE_KVM
>> 1443 select MIPS_O32_FP64_SUPPORT
>> 1444 help
>> 1445 Choose this option to build a kernel for release 5 or later of the
>> 1446 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1447 family, are based on a MIPS32r5 processor. If you own an older
>> 1448 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1449
>> 1450 config CPU_MIPS32_R6
>> 1451 bool "MIPS32 Release 6"
>> 1452 depends on SYS_HAS_CPU_MIPS32_R6
>> 1453 select CPU_HAS_PREFETCH
>> 1454 select CPU_NO_LOAD_STORE_LR
>> 1455 select CPU_SUPPORTS_32BIT_KERNEL
>> 1456 select CPU_SUPPORTS_HIGHMEM
>> 1457 select CPU_SUPPORTS_MSA
>> 1458 select HAVE_KVM
>> 1459 select MIPS_O32_FP64_SUPPORT
>> 1460 help
>> 1461 Choose this option to build a kernel for release 6 or later of the
>> 1462 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1463 family, are based on a MIPS32r6 processor. If you own an older
>> 1464 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1465
>> 1466 config CPU_MIPS64_R1
>> 1467 bool "MIPS64 Release 1"
>> 1468 depends on SYS_HAS_CPU_MIPS64_R1
>> 1469 select CPU_HAS_PREFETCH
>> 1470 select CPU_SUPPORTS_32BIT_KERNEL
>> 1471 select CPU_SUPPORTS_64BIT_KERNEL
>> 1472 select CPU_SUPPORTS_HIGHMEM
>> 1473 select CPU_SUPPORTS_HUGEPAGES
>> 1474 help
>> 1475 Choose this option to build a kernel for release 1 or later of the
>> 1476 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1477 MIPS processor are based on a MIPS64 processor. If you know the
>> 1478 specific type of processor in your system, choose those that one
>> 1479 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1480 Release 2 of the MIPS64 architecture is available since several
>> 1481 years so chances are you even have a MIPS64 Release 2 processor
>> 1482 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1483 performance.
1136 1484
1137 config X86_REROUTE_FOR_BROKEN_BOOT_IRQS !! 1485 config CPU_MIPS64_R2
1138 bool "Reroute for broken boot IRQs" !! 1486 bool "MIPS64 Release 2"
1139 depends on X86_IO_APIC !! 1487 depends on SYS_HAS_CPU_MIPS64_R2
1140 help !! 1488 select CPU_HAS_PREFETCH
1141 This option enables a workaround th !! 1489 select CPU_SUPPORTS_32BIT_KERNEL
1142 spurious interrupts. This is recomm !! 1490 select CPU_SUPPORTS_64BIT_KERNEL
1143 interrupt handling is used on syste !! 1491 select CPU_SUPPORTS_HIGHMEM
1144 superfluous "boot interrupts" canno !! 1492 select CPU_SUPPORTS_HUGEPAGES
1145 !! 1493 select CPU_SUPPORTS_MSA
1146 Some chipsets generate a legacy INT !! 1494 select HAVE_KVM
1147 entry in the chipset's IO-APIC is m !! 1495 help
1148 kernel does during interrupt handli !! 1496 Choose this option to build a kernel for release 2 or later of the
1149 boot IRQ generation cannot be disab !! 1497 MIPS64 architecture. Many modern embedded systems with a 64-bit
1150 the original IRQ line masked so tha !! 1498 MIPS processor are based on a MIPS64 processor. If you know the
1151 IRQ" is delivered to the CPUs. The !! 1499 specific type of processor in your system, choose those that one
1152 kernel to set up the IRQ handler on !! 1500 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1153 way only one interrupt is delivered !! 1501
1154 the spurious second interrupt may c !! 1502 config CPU_MIPS64_R5
1155 down (vital) interrupt lines. !! 1503 bool "MIPS64 Release 5"
1156 !! 1504 depends on SYS_HAS_CPU_MIPS64_R5
1157 Only affects "broken" chipsets. Int !! 1505 select CPU_HAS_PREFETCH
1158 increased on these systems. !! 1506 select CPU_SUPPORTS_32BIT_KERNEL
1159 !! 1507 select CPU_SUPPORTS_64BIT_KERNEL
1160 config X86_MCE !! 1508 select CPU_SUPPORTS_HIGHMEM
1161 bool "Machine Check / overheating rep !! 1509 select CPU_SUPPORTS_HUGEPAGES
1162 select GENERIC_ALLOCATOR !! 1510 select CPU_SUPPORTS_MSA
1163 default y !! 1511 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1512 select HAVE_KVM
>> 1513 help
>> 1514 Choose this option to build a kernel for release 5 or later of the
>> 1515 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1516 release partly implementing release 6 features. Though there is no
>> 1517 any hardware known to be based on this release.
>> 1518
>> 1519 config CPU_MIPS64_R6
>> 1520 bool "MIPS64 Release 6"
>> 1521 depends on SYS_HAS_CPU_MIPS64_R6
>> 1522 select CPU_HAS_PREFETCH
>> 1523 select CPU_NO_LOAD_STORE_LR
>> 1524 select CPU_SUPPORTS_32BIT_KERNEL
>> 1525 select CPU_SUPPORTS_64BIT_KERNEL
>> 1526 select CPU_SUPPORTS_HIGHMEM
>> 1527 select CPU_SUPPORTS_HUGEPAGES
>> 1528 select CPU_SUPPORTS_MSA
>> 1529 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1530 select HAVE_KVM
>> 1531 help
>> 1532 Choose this option to build a kernel for release 6 or later of the
>> 1533 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1534 family, are based on a MIPS64r6 processor. If you own an older
>> 1535 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1536
>> 1537 config CPU_P5600
>> 1538 bool "MIPS Warrior P5600"
>> 1539 depends on SYS_HAS_CPU_P5600
>> 1540 select CPU_HAS_PREFETCH
>> 1541 select CPU_SUPPORTS_32BIT_KERNEL
>> 1542 select CPU_SUPPORTS_HIGHMEM
>> 1543 select CPU_SUPPORTS_MSA
>> 1544 select CPU_SUPPORTS_CPUFREQ
>> 1545 select CPU_MIPSR2_IRQ_VI
>> 1546 select CPU_MIPSR2_IRQ_EI
>> 1547 select HAVE_KVM
>> 1548 select MIPS_O32_FP64_SUPPORT
>> 1549 help
>> 1550 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1551 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1552 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1553 level features like up to six P5600 calculation cores, CM2 with L2
>> 1554 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1555 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1556 eJTAG and PDtrace.
>> 1557
>> 1558 config CPU_R3000
>> 1559 bool "R3000"
>> 1560 depends on SYS_HAS_CPU_R3000
>> 1561 select CPU_HAS_WB
>> 1562 select CPU_R3K_TLB
>> 1563 select CPU_SUPPORTS_32BIT_KERNEL
>> 1564 select CPU_SUPPORTS_HIGHMEM
>> 1565 help
>> 1566 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1567 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1568 *not* work on R4000 machines and vice versa. However, since most
>> 1569 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1570 might be a safe bet. If the resulting kernel does not work,
>> 1571 try to recompile with R3000.
>> 1572
>> 1573 config CPU_R4300
>> 1574 bool "R4300"
>> 1575 depends on SYS_HAS_CPU_R4300
>> 1576 select CPU_SUPPORTS_32BIT_KERNEL
>> 1577 select CPU_SUPPORTS_64BIT_KERNEL
>> 1578 help
>> 1579 MIPS Technologies R4300-series processors.
>> 1580
>> 1581 config CPU_R4X00
>> 1582 bool "R4x00"
>> 1583 depends on SYS_HAS_CPU_R4X00
>> 1584 select CPU_SUPPORTS_32BIT_KERNEL
>> 1585 select CPU_SUPPORTS_64BIT_KERNEL
>> 1586 select CPU_SUPPORTS_HUGEPAGES
>> 1587 help
>> 1588 MIPS Technologies R4000-series processors other than 4300, including
>> 1589 the R4000, R4400, R4600, and 4700.
>> 1590
>> 1591 config CPU_TX49XX
>> 1592 bool "R49XX"
>> 1593 depends on SYS_HAS_CPU_TX49XX
>> 1594 select CPU_HAS_PREFETCH
>> 1595 select CPU_SUPPORTS_32BIT_KERNEL
>> 1596 select CPU_SUPPORTS_64BIT_KERNEL
>> 1597 select CPU_SUPPORTS_HUGEPAGES
>> 1598
>> 1599 config CPU_R5000
>> 1600 bool "R5000"
>> 1601 depends on SYS_HAS_CPU_R5000
>> 1602 select CPU_SUPPORTS_32BIT_KERNEL
>> 1603 select CPU_SUPPORTS_64BIT_KERNEL
>> 1604 select CPU_SUPPORTS_HUGEPAGES
>> 1605 help
>> 1606 MIPS Technologies R5000-series processors other than the Nevada.
>> 1607
>> 1608 config CPU_R5500
>> 1609 bool "R5500"
>> 1610 depends on SYS_HAS_CPU_R5500
>> 1611 select CPU_SUPPORTS_32BIT_KERNEL
>> 1612 select CPU_SUPPORTS_64BIT_KERNEL
>> 1613 select CPU_SUPPORTS_HUGEPAGES
>> 1614 help
>> 1615 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1616 instruction set.
>> 1617
>> 1618 config CPU_NEVADA
>> 1619 bool "RM52xx"
>> 1620 depends on SYS_HAS_CPU_NEVADA
>> 1621 select CPU_SUPPORTS_32BIT_KERNEL
>> 1622 select CPU_SUPPORTS_64BIT_KERNEL
>> 1623 select CPU_SUPPORTS_HUGEPAGES
>> 1624 help
>> 1625 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1626
>> 1627 config CPU_R10000
>> 1628 bool "R10000"
>> 1629 depends on SYS_HAS_CPU_R10000
>> 1630 select CPU_HAS_PREFETCH
>> 1631 select CPU_SUPPORTS_32BIT_KERNEL
>> 1632 select CPU_SUPPORTS_64BIT_KERNEL
>> 1633 select CPU_SUPPORTS_HIGHMEM
>> 1634 select CPU_SUPPORTS_HUGEPAGES
>> 1635 help
>> 1636 MIPS Technologies R10000-series processors.
>> 1637
>> 1638 config CPU_RM7000
>> 1639 bool "RM7000"
>> 1640 depends on SYS_HAS_CPU_RM7000
>> 1641 select CPU_HAS_PREFETCH
>> 1642 select CPU_SUPPORTS_32BIT_KERNEL
>> 1643 select CPU_SUPPORTS_64BIT_KERNEL
>> 1644 select CPU_SUPPORTS_HIGHMEM
>> 1645 select CPU_SUPPORTS_HUGEPAGES
>> 1646
>> 1647 config CPU_SB1
>> 1648 bool "SB1"
>> 1649 depends on SYS_HAS_CPU_SB1
>> 1650 select CPU_SUPPORTS_32BIT_KERNEL
>> 1651 select CPU_SUPPORTS_64BIT_KERNEL
>> 1652 select CPU_SUPPORTS_HIGHMEM
>> 1653 select CPU_SUPPORTS_HUGEPAGES
>> 1654 select WEAK_ORDERING
>> 1655
>> 1656 config CPU_CAVIUM_OCTEON
>> 1657 bool "Cavium Octeon processor"
>> 1658 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1659 select CPU_HAS_PREFETCH
>> 1660 select CPU_SUPPORTS_64BIT_KERNEL
>> 1661 select WEAK_ORDERING
>> 1662 select CPU_SUPPORTS_HIGHMEM
>> 1663 select CPU_SUPPORTS_HUGEPAGES
>> 1664 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1665 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1666 select MIPS_L1_CACHE_SHIFT_7
>> 1667 select HAVE_KVM
>> 1668 help
>> 1669 The Cavium Octeon processor is a highly integrated chip containing
>> 1670 many ethernet hardware widgets for networking tasks. The processor
>> 1671 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1672 Full details can be found at http://www.caviumnetworks.com.
>> 1673
>> 1674 config CPU_BMIPS
>> 1675 bool "Broadcom BMIPS"
>> 1676 depends on SYS_HAS_CPU_BMIPS
>> 1677 select CPU_MIPS32
>> 1678 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1679 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1680 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1681 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1682 select CPU_SUPPORTS_32BIT_KERNEL
>> 1683 select DMA_NONCOHERENT
>> 1684 select IRQ_MIPS_CPU
>> 1685 select SWAP_IO_SPACE
>> 1686 select WEAK_ORDERING
>> 1687 select CPU_SUPPORTS_HIGHMEM
>> 1688 select CPU_HAS_PREFETCH
>> 1689 select CPU_SUPPORTS_CPUFREQ
>> 1690 select MIPS_EXTERNAL_TIMER
>> 1691 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
1164 help 1692 help
1165 Machine Check support allows the pr !! 1693 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
1166 kernel if it detects a problem (e.g <<
1167 The action the kernel takes depends <<
1168 ranging from warning messages to ha <<
1169 <<
1170 config X86_MCELOG_LEGACY <<
1171 bool "Support for deprecated /dev/mce <<
1172 depends on X86_MCE <<
1173 help <<
1174 Enable support for /dev/mcelog whic <<
1175 userspace logging daemon. Consider <<
1176 rasdaemon solution. <<
1177 1694
1178 config X86_MCE_INTEL !! 1695 endchoice
1179 def_bool y <<
1180 prompt "Intel MCE features" <<
1181 depends on X86_MCE && X86_LOCAL_APIC <<
1182 help <<
1183 Additional support for intel specif <<
1184 the thermal monitor. <<
1185 1696
1186 config X86_MCE_AMD !! 1697 config CPU_MIPS32_3_5_FEATURES
1187 def_bool y !! 1698 bool "MIPS32 Release 3.5 Features"
1188 prompt "AMD MCE features" !! 1699 depends on SYS_HAS_CPU_MIPS32_R3_5
1189 depends on X86_MCE && X86_LOCAL_APIC !! 1700 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1701 CPU_P5600
>> 1702 help
>> 1703 Choose this option to build a kernel for release 2 or later of the
>> 1704 MIPS32 architecture including features from the 3.5 release such as
>> 1705 support for Enhanced Virtual Addressing (EVA).
>> 1706
>> 1707 config CPU_MIPS32_3_5_EVA
>> 1708 bool "Enhanced Virtual Addressing (EVA)"
>> 1709 depends on CPU_MIPS32_3_5_FEATURES
>> 1710 select EVA
>> 1711 default y
>> 1712 help
>> 1713 Choose this option if you want to enable the Enhanced Virtual
>> 1714 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1715 One of its primary benefits is an increase in the maximum size
>> 1716 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1717
>> 1718 config CPU_MIPS32_R5_FEATURES
>> 1719 bool "MIPS32 Release 5 Features"
>> 1720 depends on SYS_HAS_CPU_MIPS32_R5
>> 1721 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1722 help
>> 1723 Choose this option to build a kernel for release 2 or later of the
>> 1724 MIPS32 architecture including features from release 5 such as
>> 1725 support for Extended Physical Addressing (XPA).
>> 1726
>> 1727 config CPU_MIPS32_R5_XPA
>> 1728 bool "Extended Physical Addressing (XPA)"
>> 1729 depends on CPU_MIPS32_R5_FEATURES
>> 1730 depends on !EVA
>> 1731 depends on !PAGE_SIZE_4KB
>> 1732 depends on SYS_SUPPORTS_HIGHMEM
>> 1733 select XPA
>> 1734 select HIGHMEM
>> 1735 select PHYS_ADDR_T_64BIT
>> 1736 default n
1190 help 1737 help
1191 Additional support for AMD specific !! 1738 Choose this option if you want to enable the Extended Physical
1192 the DRAM Error Threshold. !! 1739 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1740 benefit is to increase physical addressing equal to or greater
>> 1741 than 40 bits. Note that this has the side effect of turning on
>> 1742 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1743 If unsure, say 'N' here.
1193 1744
1194 config X86_ANCIENT_MCE !! 1745 if CPU_LOONGSON2F
1195 bool "Support for old Pentium 5 / Win !! 1746 config CPU_NOP_WORKAROUNDS
1196 depends on X86_32 && X86_MCE !! 1747 bool
1197 help <<
1198 Include support for machine check h <<
1199 systems. These typically need to be <<
1200 line. <<
1201 1748
1202 config X86_MCE_THRESHOLD !! 1749 config CPU_JUMP_WORKAROUNDS
1203 depends on X86_MCE_AMD || X86_MCE_INT !! 1750 bool
1204 def_bool y <<
1205 1751
1206 config X86_MCE_INJECT !! 1752 config CPU_LOONGSON2F_WORKAROUNDS
1207 depends on X86_MCE && X86_LOCAL_APIC !! 1753 bool "Loongson 2F Workarounds"
1208 tristate "Machine check injector supp !! 1754 default y
>> 1755 select CPU_NOP_WORKAROUNDS
>> 1756 select CPU_JUMP_WORKAROUNDS
1209 help 1757 help
1210 Provide support for injecting machi !! 1758 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1211 If you don't know what a machine ch !! 1759 require workarounds. Without workarounds the system may hang
1212 QA it is safe to say n. !! 1760 unexpectedly. For more information please refer to the gas
>> 1761 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1762
>> 1763 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1764 are needed. The workarounds have no significant side effect on them
>> 1765 but may decrease the performance of the system so this option should
>> 1766 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1767 systems.
1213 1768
1214 source "arch/x86/events/Kconfig" !! 1769 If unsure, please say Y.
>> 1770 endif # CPU_LOONGSON2F
1215 1771
1216 config X86_LEGACY_VM86 !! 1772 config SYS_SUPPORTS_ZBOOT
1217 bool "Legacy VM86 support" !! 1773 bool
1218 depends on X86_32 !! 1774 select HAVE_KERNEL_GZIP
1219 help !! 1775 select HAVE_KERNEL_BZIP2
1220 This option allows user programs to !! 1776 select HAVE_KERNEL_LZ4
1221 mode, which is an 80286-era approxi !! 1777 select HAVE_KERNEL_LZMA
>> 1778 select HAVE_KERNEL_LZO
>> 1779 select HAVE_KERNEL_XZ
>> 1780 select HAVE_KERNEL_ZSTD
1222 1781
1223 Some very old versions of X and/or !! 1782 config SYS_SUPPORTS_ZBOOT_UART16550
1224 for user mode setting. Similarly, !! 1783 bool
1225 available to accelerate real mode D !! 1784 select SYS_SUPPORTS_ZBOOT
1226 recent version of DOSEMU, X, or vbe <<
1227 functional even without kernel VM86 <<
1228 fall back to software emulation. Ne <<
1229 a 16-bit DOS program where 16-bit p <<
1230 mode might be faster than emulation <<
1231 enable this option. <<
1232 1785
1233 Note that any app that works on a 6 !! 1786 config SYS_SUPPORTS_ZBOOT_UART_PROM
1234 need this option, as 64-bit kernels !! 1787 bool
1235 V8086 mode. This option is also unr !! 1788 select SYS_SUPPORTS_ZBOOT
1236 mode and is not needed to run most <<
1237 1789
1238 Enabling this option increases the !! 1790 config CPU_LOONGSON2EF
1239 and slows down exception handling a !! 1791 bool
>> 1792 select CPU_SUPPORTS_32BIT_KERNEL
>> 1793 select CPU_SUPPORTS_64BIT_KERNEL
>> 1794 select CPU_SUPPORTS_HIGHMEM
>> 1795 select CPU_SUPPORTS_HUGEPAGES
>> 1796 select ARCH_HAS_PHYS_TO_DMA
1240 1797
1241 If unsure, say N here. !! 1798 config CPU_LOONGSON32
>> 1799 bool
>> 1800 select CPU_MIPS32
>> 1801 select CPU_MIPSR2
>> 1802 select CPU_HAS_PREFETCH
>> 1803 select CPU_SUPPORTS_32BIT_KERNEL
>> 1804 select CPU_SUPPORTS_HIGHMEM
>> 1805 select CPU_SUPPORTS_CPUFREQ
1242 1806
1243 config VM86 !! 1807 config CPU_BMIPS32_3300
>> 1808 select SMP_UP if SMP
1244 bool 1809 bool
1245 default X86_LEGACY_VM86 <<
1246 1810
1247 config X86_16BIT !! 1811 config CPU_BMIPS4350
1248 bool "Enable support for 16-bit segme !! 1812 bool
1249 default y !! 1813 select SYS_SUPPORTS_SMP
1250 depends on MODIFY_LDT_SYSCALL !! 1814 select SYS_SUPPORTS_HOTPLUG_CPU
1251 help <<
1252 This option is required by programs <<
1253 protected mode legacy code on x86 p <<
1254 this option saves about 300 bytes o <<
1255 plus 16K runtime memory on x86-64, <<
1256 1815
1257 config X86_ESPFIX32 !! 1816 config CPU_BMIPS4380
1258 def_bool y !! 1817 bool
1259 depends on X86_16BIT && X86_32 !! 1818 select MIPS_L1_CACHE_SHIFT_6
>> 1819 select SYS_SUPPORTS_SMP
>> 1820 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1821 select CPU_HAS_RIXI
1260 1822
1261 config X86_ESPFIX64 !! 1823 config CPU_BMIPS5000
1262 def_bool y !! 1824 bool
1263 depends on X86_16BIT && X86_64 !! 1825 select MIPS_CPU_SCACHE
>> 1826 select MIPS_L1_CACHE_SHIFT_7
>> 1827 select SYS_SUPPORTS_SMP
>> 1828 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1829 select CPU_HAS_RIXI
1264 1830
1265 config X86_VSYSCALL_EMULATION !! 1831 config SYS_HAS_CPU_LOONGSON64
1266 bool "Enable vsyscall emulation" if E !! 1832 bool
1267 default y !! 1833 select CPU_SUPPORTS_CPUFREQ
1268 depends on X86_64 !! 1834 select CPU_HAS_RIXI
1269 help <<
1270 This enables emulation of the legac <<
1271 it is roughly equivalent to booting <<
1272 that it will also disable the helpf <<
1273 tries to use a vsyscall. With this <<
1274 programs will just segfault, citing <<
1275 0xffffffffff600?00. <<
1276 1835
1277 This option is required by many pro !! 1836 config SYS_HAS_CPU_LOONGSON2E
1278 care should be used even with newer !! 1837 bool
1279 1838
1280 Disabling this option saves about 7 !! 1839 config SYS_HAS_CPU_LOONGSON2F
1281 possibly 4K of additional runtime p !! 1840 bool
>> 1841 select CPU_SUPPORTS_CPUFREQ
>> 1842 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1282 1843
1283 config X86_IOPL_IOPERM !! 1844 config SYS_HAS_CPU_LOONGSON1B
1284 bool "IOPERM and IOPL Emulation" !! 1845 bool
1285 default y <<
1286 help <<
1287 This enables the ioperm() and iopl( <<
1288 for legacy applications. <<
1289 1846
1290 Legacy IOPL support is an overbroad !! 1847 config SYS_HAS_CPU_LOONGSON1C
1291 space aside of accessing all 65536 !! 1848 bool
1292 interrupts. To gain this access the <<
1293 capabilities and permission from po <<
1294 modules. <<
1295 <<
1296 The emulation restricts the functio <<
1297 only allowing the full range I/O po <<
1298 ability to disable interrupts from <<
1299 granted if the hardware IOPL mechan <<
1300 <<
1301 config TOSHIBA <<
1302 tristate "Toshiba Laptop support" <<
1303 depends on X86_32 <<
1304 help <<
1305 This adds a driver to safely access <<
1306 the CPU on Toshiba portables with a <<
1307 not work on models with a Phoenix B <<
1308 is used to set the BIOS and power s <<
1309 <<
1310 For information on utilities to mak <<
1311 Toshiba Linux utilities web site at <<
1312 <http://www.buzzard.org.uk/toshiba/ <<
1313 <<
1314 Say Y if you intend to run this ker <<
1315 Say N otherwise. <<
1316 <<
1317 config X86_REBOOTFIXUPS <<
1318 bool "Enable X86 board specific fixup <<
1319 depends on X86_32 <<
1320 help <<
1321 This enables chipset and/or board s <<
1322 in order to get reboot to work corr <<
1323 some combinations of hardware and B <<
1324 this config is intended, is when re <<
1325 system. <<
1326 <<
1327 Currently, the only fixup is for th <<
1328 CS5530A and CS5536 chipsets and the <<
1329 <<
1330 Say Y if you want to enable the fix <<
1331 enable this option even if you don' <<
1332 Say N otherwise. <<
1333 1849
1334 config MICROCODE !! 1850 config SYS_HAS_CPU_MIPS32_R1
1335 def_bool y !! 1851 bool
1336 depends on CPU_SUP_AMD || CPU_SUP_INT <<
1337 1852
1338 config MICROCODE_INITRD32 !! 1853 config SYS_HAS_CPU_MIPS32_R2
1339 def_bool y !! 1854 bool
1340 depends on MICROCODE && X86_32 && BLK <<
1341 1855
1342 config MICROCODE_LATE_LOADING !! 1856 config SYS_HAS_CPU_MIPS32_R3_5
1343 bool "Late microcode loading (DANGERO !! 1857 bool
1344 default n <<
1345 depends on MICROCODE && SMP <<
1346 help <<
1347 Loading microcode late, when the sy <<
1348 is a tricky business and should be <<
1349 of synchronizing all cores and SMT <<
1350 not guarantee that cores might not <<
1351 use this at your own risk. Late loa <<
1352 microcode header indicates that it <<
1353 minimal revision check. This minima <<
1354 the kernel command line with "micro <<
1355 1858
1356 config MICROCODE_LATE_FORCE_MINREV !! 1859 config SYS_HAS_CPU_MIPS32_R5
1357 bool "Enforce late microcode loading !! 1860 bool
1358 default n !! 1861 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1359 depends on MICROCODE_LATE_LOADING <<
1360 help <<
1361 To prevent that users load microcod <<
1362 in use features, newer microcode pa <<
1363 in the microcode header, which tell <<
1364 revision must be active in the CPU <<
1365 late into the running system. If di <<
1366 be enforced but the kernel will be <<
1367 revision check fails. <<
1368 <<
1369 This minimal revision check can als <<
1370 "microcode.minrev" parameter on the <<
1371 <<
1372 If unsure say Y. <<
1373 <<
1374 config X86_MSR <<
1375 tristate "/dev/cpu/*/msr - Model-spec <<
1376 help <<
1377 This device gives privileged proces <<
1378 Model-Specific Registers (MSRs). I <<
1379 major 202 and minors 0 to 31 for /d <<
1380 MSR accesses are directed to a spec <<
1381 systems. <<
1382 1862
1383 config X86_CPUID !! 1863 config SYS_HAS_CPU_MIPS32_R6
1384 tristate "/dev/cpu/*/cpuid - CPU info !! 1864 bool
1385 help !! 1865 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1386 This device gives processes access <<
1387 be executed on a specific processor <<
1388 with major 203 and minors 0 to 31 f <<
1389 /dev/cpu/31/cpuid. <<
1390 1866
1391 choice !! 1867 config SYS_HAS_CPU_MIPS64_R1
1392 prompt "High Memory Support" !! 1868 bool
1393 default HIGHMEM4G <<
1394 depends on X86_32 <<
1395 <<
1396 config NOHIGHMEM <<
1397 bool "off" <<
1398 help <<
1399 Linux can use up to 64 Gigabytes of <<
1400 However, the address space of 32-bi <<
1401 Gigabytes large. That means that, i <<
1402 physical memory, not all of it can <<
1403 kernel. The physical memory that's <<
1404 "high memory". <<
1405 <<
1406 If you are compiling a kernel which <<
1407 more than 1 Gigabyte total physical <<
1408 choice and suitable for most users) <<
1409 split: 3GB are mapped so that each <<
1410 space and the remaining part of the <<
1411 by the kernel to permanently map as <<
1412 possible. <<
1413 <<
1414 If the machine has between 1 and 4 <<
1415 answer "4GB" here. <<
1416 <<
1417 If more than 4 Gigabytes is used th <<
1418 selection turns Intel PAE (Physical <<
1419 PAE implements 3-level paging on IA <<
1420 supported by Linux, PAE mode is imp <<
1421 processors (Pentium Pro and better) <<
1422 then the kernel will not boot on CP <<
1423 <<
1424 The actual amount of total physical <<
1425 auto detected or can be forced by u <<
1426 such as "mem=256M". (Try "man bootp <<
1427 your boot loader (lilo or loadlin) <<
1428 kernel at boot time.) <<
1429 <<
1430 If unsure, say "off". <<
1431 <<
1432 config HIGHMEM4G <<
1433 bool "4GB" <<
1434 help <<
1435 Select this if you have a 32-bit pr <<
1436 gigabytes of physical RAM. <<
1437 <<
1438 config HIGHMEM64G <<
1439 bool "64GB" <<
1440 depends on X86_HAVE_PAE <<
1441 select X86_PAE <<
1442 help <<
1443 Select this if you have a 32-bit pr <<
1444 gigabytes of physical RAM. <<
1445 1869
1446 endchoice !! 1870 config SYS_HAS_CPU_MIPS64_R2
>> 1871 bool
1447 1872
1448 choice !! 1873 config SYS_HAS_CPU_MIPS64_R5
1449 prompt "Memory split" if EXPERT !! 1874 bool
1450 default VMSPLIT_3G !! 1875 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1451 depends on X86_32 <<
1452 help <<
1453 Select the desired split between ke <<
1454 <<
1455 If the address range available to t <<
1456 physical memory installed, the rema <<
1457 as "high memory". Accessing high me <<
1458 than low memory, as it needs to be <<
1459 Note that increasing the kernel add <<
1460 available to user programs, making <<
1461 tighter. Selecting anything other <<
1462 will also likely make your kernel i <<
1463 kernel modules. <<
1464 <<
1465 If you are not absolutely sure what <<
1466 option alone! <<
1467 <<
1468 config VMSPLIT_3G <<
1469 bool "3G/1G user/kernel split <<
1470 config VMSPLIT_3G_OPT <<
1471 depends on !X86_PAE <<
1472 bool "3G/1G user/kernel split <<
1473 config VMSPLIT_2G <<
1474 bool "2G/2G user/kernel split <<
1475 config VMSPLIT_2G_OPT <<
1476 depends on !X86_PAE <<
1477 bool "2G/2G user/kernel split <<
1478 config VMSPLIT_1G <<
1479 bool "1G/3G user/kernel split <<
1480 endchoice <<
1481 1876
1482 config PAGE_OFFSET !! 1877 config SYS_HAS_CPU_MIPS64_R6
1483 hex !! 1878 bool
1484 default 0xB0000000 if VMSPLIT_3G_OPT !! 1879 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1485 default 0x80000000 if VMSPLIT_2G <<
1486 default 0x78000000 if VMSPLIT_2G_OPT <<
1487 default 0x40000000 if VMSPLIT_1G <<
1488 default 0xC0000000 <<
1489 depends on X86_32 <<
1490 1880
1491 config HIGHMEM !! 1881 config SYS_HAS_CPU_P5600
1492 def_bool y !! 1882 bool
1493 depends on X86_32 && (HIGHMEM64G || H !! 1883 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1494 1884
1495 config X86_PAE !! 1885 config SYS_HAS_CPU_R3000
1496 bool "PAE (Physical Address Extension !! 1886 bool
1497 depends on X86_32 && X86_HAVE_PAE <<
1498 select PHYS_ADDR_T_64BIT <<
1499 select SWIOTLB <<
1500 help <<
1501 PAE is required for NX support, and <<
1502 larger swapspace support for non-ov <<
1503 has the cost of more pagetable look <<
1504 consumes more pagetable space per p <<
1505 1887
1506 config X86_5LEVEL !! 1888 config SYS_HAS_CPU_R4300
1507 bool "Enable 5-level page tables supp !! 1889 bool
1508 default y <<
1509 select DYNAMIC_MEMORY_LAYOUT <<
1510 select SPARSEMEM_VMEMMAP <<
1511 depends on X86_64 <<
1512 help <<
1513 5-level paging enables access to la <<
1514 up to 128 PiB of virtual address sp <<
1515 physical address space. <<
1516 1890
1517 It will be supported by future Inte !! 1891 config SYS_HAS_CPU_R4X00
>> 1892 bool
1518 1893
1519 A kernel with the option enabled ca !! 1894 config SYS_HAS_CPU_TX49XX
1520 support 4- or 5-level paging. !! 1895 bool
1521 1896
1522 See Documentation/arch/x86/x86_64/5 !! 1897 config SYS_HAS_CPU_R5000
1523 information. !! 1898 bool
1524 1899
1525 Say N if unsure. !! 1900 config SYS_HAS_CPU_R5500
>> 1901 bool
1526 1902
1527 config X86_DIRECT_GBPAGES !! 1903 config SYS_HAS_CPU_NEVADA
1528 def_bool y !! 1904 bool
1529 depends on X86_64 <<
1530 help <<
1531 Certain kernel features effectively <<
1532 linear 1 GB mappings (even if the C <<
1533 supports them), so don't confuse th <<
1534 that we have them enabled. <<
1535 <<
1536 config X86_CPA_STATISTICS <<
1537 bool "Enable statistic for Change Pag <<
1538 depends on DEBUG_FS <<
1539 help <<
1540 Expose statistics about the Change <<
1541 helps to determine the effectivenes <<
1542 page mappings when mapping protecti <<
1543 <<
1544 config X86_MEM_ENCRYPT <<
1545 select ARCH_HAS_FORCE_DMA_UNENCRYPTED <<
1546 select DYNAMIC_PHYSICAL_MASK <<
1547 def_bool n <<
1548 1905
1549 config AMD_MEM_ENCRYPT !! 1906 config SYS_HAS_CPU_R10000
1550 bool "AMD Secure Memory Encryption (S !! 1907 bool
1551 depends on X86_64 && CPU_SUP_AMD !! 1908 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1552 depends on EFI_STUB <<
1553 select DMA_COHERENT_POOL <<
1554 select ARCH_USE_MEMREMAP_PROT <<
1555 select INSTRUCTION_DECODER <<
1556 select ARCH_HAS_CC_PLATFORM <<
1557 select X86_MEM_ENCRYPT <<
1558 select UNACCEPTED_MEMORY <<
1559 help <<
1560 Say yes to enable support for the e <<
1561 This requires an AMD processor that <<
1562 Encryption (SME). <<
1563 1909
1564 # Common NUMA Features !! 1910 config SYS_HAS_CPU_RM7000
1565 config NUMA !! 1911 bool
1566 bool "NUMA Memory Allocation and Sche <<
1567 depends on SMP <<
1568 depends on X86_64 || (X86_32 && HIGHM <<
1569 default y if X86_BIGSMP <<
1570 select USE_PERCPU_NUMA_NODE_ID <<
1571 select OF_NUMA if OF <<
1572 help <<
1573 Enable NUMA (Non-Uniform Memory Acc <<
1574 1912
1575 The kernel will try to allocate mem !! 1913 config SYS_HAS_CPU_SB1
1576 local memory controller of the CPU !! 1914 bool
1577 NUMA awareness to the kernel. <<
1578 1915
1579 For 64-bit this is recommended if t !! 1916 config SYS_HAS_CPU_CAVIUM_OCTEON
1580 (or later), AMD Opteron, or EM64T N !! 1917 bool
1581 1918
1582 For 32-bit this is only needed if y !! 1919 config SYS_HAS_CPU_BMIPS
1583 kernel on a 64-bit NUMA platform. !! 1920 bool
1584 1921
1585 Otherwise, you should say N. !! 1922 config SYS_HAS_CPU_BMIPS32_3300
>> 1923 bool
>> 1924 select SYS_HAS_CPU_BMIPS
1586 1925
1587 config AMD_NUMA !! 1926 config SYS_HAS_CPU_BMIPS4350
1588 def_bool y !! 1927 bool
1589 prompt "Old style AMD Opteron NUMA de !! 1928 select SYS_HAS_CPU_BMIPS
1590 depends on X86_64 && NUMA && PCI <<
1591 help <<
1592 Enable AMD NUMA node topology detec <<
1593 you have a multi processor AMD syst <<
1594 read the NUMA configuration directl <<
1595 of Opteron. It is recommended to us <<
1596 which also takes priority if both a <<
1597 1929
1598 config X86_64_ACPI_NUMA !! 1930 config SYS_HAS_CPU_BMIPS4380
1599 def_bool y !! 1931 bool
1600 prompt "ACPI NUMA detection" !! 1932 select SYS_HAS_CPU_BMIPS
1601 depends on X86_64 && NUMA && ACPI && <<
1602 select ACPI_NUMA <<
1603 help <<
1604 Enable ACPI SRAT based node topolog <<
1605 1933
1606 config NODES_SHIFT !! 1934 config SYS_HAS_CPU_BMIPS5000
1607 int "Maximum NUMA Nodes (as a power o !! 1935 bool
1608 range 1 10 !! 1936 select SYS_HAS_CPU_BMIPS
1609 default "10" if MAXSMP !! 1937 select ARCH_HAS_SYNC_DMA_FOR_CPU
1610 default "6" if X86_64 <<
1611 default "3" <<
1612 depends on NUMA <<
1613 help <<
1614 Specify the maximum number of NUMA <<
1615 system. Increases memory reserved <<
1616 1938
1617 config ARCH_FLATMEM_ENABLE !! 1939 #
1618 def_bool y !! 1940 # CPU may reorder R->R, R->W, W->R, W->W
1619 depends on X86_32 && !NUMA !! 1941 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1942 #
>> 1943 config WEAK_ORDERING
>> 1944 bool
1620 1945
1621 config ARCH_SPARSEMEM_ENABLE !! 1946 #
1622 def_bool y !! 1947 # CPU may reorder reads and writes beyond LL/SC
1623 depends on X86_64 || NUMA || X86_32 | !! 1948 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1624 select SPARSEMEM_STATIC if X86_32 !! 1949 #
1625 select SPARSEMEM_VMEMMAP_ENABLE if X8 !! 1950 config WEAK_REORDERING_BEYOND_LLSC
>> 1951 bool
>> 1952 endmenu
1626 1953
1627 config ARCH_SPARSEMEM_DEFAULT !! 1954 #
1628 def_bool X86_64 || (NUMA && X86_32) !! 1955 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1956 #
>> 1957 config CPU_MIPS32
>> 1958 bool
>> 1959 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1960 CPU_MIPS32_R6 || CPU_P5600
1629 1961
1630 config ARCH_SELECT_MEMORY_MODEL !! 1962 config CPU_MIPS64
1631 def_bool y !! 1963 bool
1632 depends on ARCH_SPARSEMEM_ENABLE && A !! 1964 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1965 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1633 1966
1634 config ARCH_MEMORY_PROBE !! 1967 #
1635 bool "Enable sysfs memory/probe inter !! 1968 # These indicate the revision of the architecture
1636 depends on MEMORY_HOTPLUG !! 1969 #
1637 help !! 1970 config CPU_MIPSR1
1638 This option enables a sysfs memory/ !! 1971 bool
1639 See Documentation/admin-guide/mm/me !! 1972 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1640 If you are unsure how to answer thi <<
1641 1973
1642 config ARCH_PROC_KCORE_TEXT !! 1974 config CPU_MIPSR2
1643 def_bool y !! 1975 bool
1644 depends on X86_64 && PROC_KCORE !! 1976 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 1977 select CPU_HAS_RIXI
>> 1978 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1979 select MIPS_SPRAM
1645 1980
1646 config ILLEGAL_POINTER_VALUE !! 1981 config CPU_MIPSR5
1647 hex !! 1982 bool
1648 default 0 if X86_32 !! 1983 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
1649 default 0xdead000000000000 if X86_64 !! 1984 select CPU_HAS_RIXI
1650 !! 1985 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1651 config X86_PMEM_LEGACY_DEVICE !! 1986 select MIPS_SPRAM
1652 bool <<
1653 <<
1654 config X86_PMEM_LEGACY <<
1655 tristate "Support non-standard NVDIMM <<
1656 depends on PHYS_ADDR_T_64BIT <<
1657 depends on BLK_DEV <<
1658 select X86_PMEM_LEGACY_DEVICE <<
1659 select NUMA_KEEP_MEMINFO if NUMA <<
1660 select LIBNVDIMM <<
1661 help <<
1662 Treat memory marked using the non-s <<
1663 by the Intel Sandy Bridge-EP refere <<
1664 The kernel will offer these regions <<
1665 they can be used for persistent sto <<
1666 <<
1667 Say Y if unsure. <<
1668 <<
1669 config HIGHPTE <<
1670 bool "Allocate 3rd-level pagetables f <<
1671 depends on HIGHMEM <<
1672 help <<
1673 The VM uses one page table entry fo <<
1674 For systems with a lot of RAM, this <<
1675 low memory. Setting this option wi <<
1676 entries in high memory. <<
1677 <<
1678 config X86_CHECK_BIOS_CORRUPTION <<
1679 bool "Check for low memory corruption <<
1680 help <<
1681 Periodically check for memory corru <<
1682 is suspected to be caused by BIOS. <<
1683 configuration, it is disabled at ru <<
1684 setting "memory_corruption_check=1" <<
1685 line. By default it scans the low <<
1686 seconds; see the memory_corruption_ <<
1687 memory_corruption_check_period para <<
1688 Documentation/admin-guide/kernel-pa <<
1689 <<
1690 When enabled with the default param <<
1691 almost no overhead, as it reserves <<
1692 of memory and scans it infrequently <<
1693 and prevents it from affecting the <<
1694 <<
1695 It is, however, intended as a diagn <<
1696 BIOS-originated corruption always a <<
1697 you can use memmap= to prevent the <<
1698 memory. <<
1699 <<
1700 config X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK <<
1701 bool "Set the default setting of memo <<
1702 depends on X86_CHECK_BIOS_CORRUPTION <<
1703 default y <<
1704 help <<
1705 Set whether the default state of me <<
1706 on or off. <<
1707 1987
1708 config MATH_EMULATION !! 1988 config CPU_MIPSR6
1709 bool 1989 bool
1710 depends on MODIFY_LDT_SYSCALL !! 1990 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
1711 prompt "Math emulation" if X86_32 && !! 1991 select CPU_HAS_RIXI
>> 1992 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1993 select HAVE_ARCH_BITREVERSE
>> 1994 select MIPS_ASID_BITS_VARIABLE
>> 1995 select MIPS_CRC_SUPPORT
>> 1996 select MIPS_SPRAM
>> 1997
>> 1998 config TARGET_ISA_REV
>> 1999 int
>> 2000 default 1 if CPU_MIPSR1
>> 2001 default 2 if CPU_MIPSR2
>> 2002 default 5 if CPU_MIPSR5
>> 2003 default 6 if CPU_MIPSR6
>> 2004 default 0
1712 help 2005 help
1713 Linux can emulate a math coprocesso !! 2006 Reflects the ISA revision being targeted by the kernel build. This
1714 operations) if you don't have one. !! 2007 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1715 a math coprocessor built in, 486SX <<
1716 a 487DX or 387, respectively. (The <<
1717 give you some hints here ["man dmes <<
1718 coprocessor or this emulation. <<
1719 <<
1720 If you don't have a math coprocesso <<
1721 say Y here even though you have a c <<
1722 be used nevertheless. (This behavio <<
1723 command line option "no387", which <<
1724 is broken. Try "man bootparam" or s <<
1725 loader (lilo or loadlin) about how <<
1726 boot time.) This means that it is a <<
1727 intend to use this kernel on differ <<
1728 2008
1729 More information about the internal !! 2009 config EVA
1730 emulation can be found in <file:arc !! 2010 bool
1731 2011
1732 If you are not sure, say Y; apart f !! 2012 config XPA
1733 kernel, it won't hurt. !! 2013 bool
1734 2014
1735 config MTRR !! 2015 config SYS_SUPPORTS_32BIT_KERNEL
1736 def_bool y !! 2016 bool
1737 prompt "MTRR (Memory Type Range Regis !! 2017 config SYS_SUPPORTS_64BIT_KERNEL
1738 help !! 2018 bool
1739 On Intel P6 family processors (Pent !! 2019 config CPU_SUPPORTS_32BIT_KERNEL
1740 the Memory Type Range Registers (MT !! 2020 bool
1741 processor access to memory ranges. !! 2021 config CPU_SUPPORTS_64BIT_KERNEL
1742 a video (VGA) card on a PCI or AGP !! 2022 bool
1743 allows bus write transfers to be co !! 2023 config CPU_SUPPORTS_CPUFREQ
1744 before bursting over the PCI/AGP bu !! 2024 bool
1745 of image write operations 2.5 times !! 2025 config CPU_SUPPORTS_ADDRWINCFG
1746 /proc/mtrr file which may be used t !! 2026 bool
1747 MTRRs. Typically the X server shoul !! 2027 config CPU_SUPPORTS_HUGEPAGES
1748 !! 2028 bool
1749 This code has a reasonably generic !! 2029 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
1750 control registers on other processo !! 2030 config MIPS_PGD_C0_CONTEXT
1751 as well: !! 2031 bool
1752 !! 2032 depends on 64BIT
1753 The Cyrix 6x86, 6x86MX and M II pro !! 2033 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1754 Registers (ARRs) which provide a si <<
1755 these, the ARRs are used to emulate <<
1756 The AMD K6-2 (stepping 8 and above) <<
1757 MTRRs. The Centaur C6 (WinChip) has <<
1758 write-combining. All of these proce <<
1759 and it makes sense to say Y here if <<
1760 <<
1761 Saying Y here also fixes a problem <<
1762 set the MTRRs for the boot CPU and <<
1763 can lead to all sorts of problems, <<
1764 2034
1765 You can safely say Y even if your m !! 2035 #
1766 just add about 9 KB to your kernel. !! 2036 # Set to y for ptrace access to watch registers.
>> 2037 #
>> 2038 config HARDWARE_WATCHPOINTS
>> 2039 bool
>> 2040 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1767 2041
1768 See <file:Documentation/arch/x86/mt !! 2042 menu "Kernel type"
1769 2043
1770 config MTRR_SANITIZER !! 2044 choice
1771 def_bool y !! 2045 prompt "Kernel code model"
1772 prompt "MTRR cleanup support" !! 2046 help
1773 depends on MTRR !! 2047 You should only select this option if you have a workload that
>> 2048 actually benefits from 64-bit processing or if your machine has
>> 2049 large memory. You will only be presented a single option in this
>> 2050 menu if your system does not support both 32-bit and 64-bit kernels.
>> 2051
>> 2052 config 32BIT
>> 2053 bool "32-bit kernel"
>> 2054 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2055 select TRAD_SIGNALS
1774 help 2056 help
1775 Convert MTRR layout from continuous !! 2057 Select this option if you want to build a 32-bit kernel.
1776 add writeback entries. <<
1777 2058
1778 Can be disabled with disable_mtrr_c !! 2059 config 64BIT
1779 The largest mtrr entry size for a c !! 2060 bool "64-bit kernel"
1780 mtrr_chunk_size. !! 2061 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
>> 2062 help
>> 2063 Select this option if you want to build a 64-bit kernel.
1781 2064
1782 If unsure, say Y. !! 2065 endchoice
1783 2066
1784 config MTRR_SANITIZER_ENABLE_DEFAULT !! 2067 config MIPS_VA_BITS_48
1785 int "MTRR cleanup enable value (0-1)" !! 2068 bool "48 bits virtual memory"
1786 range 0 1 !! 2069 depends on 64BIT
1787 default "0" <<
1788 depends on MTRR_SANITIZER <<
1789 help <<
1790 Enable mtrr cleanup default value <<
1791 <<
1792 config MTRR_SANITIZER_SPARE_REG_NR_DEFAULT <<
1793 int "MTRR cleanup spare reg num (0-7) <<
1794 range 0 7 <<
1795 default "1" <<
1796 depends on MTRR_SANITIZER <<
1797 help 2070 help
1798 mtrr cleanup spare entries default, !! 2071 Support a maximum at least 48 bits of application virtual
1799 mtrr_spare_reg_nr=N on the kernel c !! 2072 memory. Default is 40 bits or less, depending on the CPU.
>> 2073 For page sizes 16k and above, this option results in a small
>> 2074 memory overhead for page tables. For 4k page size, a fourth
>> 2075 level of page tables is added which imposes both a memory
>> 2076 overhead as well as slower TLB fault handling.
1800 2077
1801 config X86_PAT !! 2078 If unsure, say N.
1802 def_bool y !! 2079
1803 prompt "x86 PAT support" if EXPERT !! 2080 config ZBOOT_LOAD_ADDRESS
1804 depends on MTRR !! 2081 hex "Compressed kernel load address"
1805 select ARCH_USES_PG_ARCH_2 !! 2082 default 0xffffffff80400000 if BCM47XX
>> 2083 default 0x0
>> 2084 depends on SYS_SUPPORTS_ZBOOT
1806 help 2085 help
1807 Use PAT attributes to setup page le !! 2086 The address to load compressed kernel, aka vmlinuz.
1808 2087
1809 PATs are the modern equivalents of !! 2088 This is only used if non-zero.
1810 flexible than MTRRs. <<
1811 2089
1812 Say N here if you see bootup proble !! 2090 choice
1813 spontaneous reboots) or a non-worki !! 2091 prompt "Kernel page size"
>> 2092 default PAGE_SIZE_4KB
1814 2093
1815 If unsure, say Y. !! 2094 config PAGE_SIZE_4KB
>> 2095 bool "4kB"
>> 2096 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2097 help
>> 2098 This option select the standard 4kB Linux page size. On some
>> 2099 R3000-family processors this is the only available page size. Using
>> 2100 4kB page size will minimize memory consumption and is therefore
>> 2101 recommended for low memory systems.
>> 2102
>> 2103 config PAGE_SIZE_8KB
>> 2104 bool "8kB"
>> 2105 depends on CPU_CAVIUM_OCTEON
>> 2106 depends on !MIPS_VA_BITS_48
>> 2107 help
>> 2108 Using 8kB page size will result in higher performance kernel at
>> 2109 the price of higher memory consumption. This option is available
>> 2110 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2111 distribution to support this.
>> 2112
>> 2113 config PAGE_SIZE_16KB
>> 2114 bool "16kB"
>> 2115 depends on !CPU_R3000
>> 2116 help
>> 2117 Using 16kB page size will result in higher performance kernel at
>> 2118 the price of higher memory consumption. This option is available on
>> 2119 all non-R3000 family processors. Note that you will need a suitable
>> 2120 Linux distribution to support this.
>> 2121
>> 2122 config PAGE_SIZE_32KB
>> 2123 bool "32kB"
>> 2124 depends on CPU_CAVIUM_OCTEON
>> 2125 depends on !MIPS_VA_BITS_48
>> 2126 help
>> 2127 Using 32kB page size will result in higher performance kernel at
>> 2128 the price of higher memory consumption. This option is available
>> 2129 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2130 distribution to support this.
>> 2131
>> 2132 config PAGE_SIZE_64KB
>> 2133 bool "64kB"
>> 2134 depends on !CPU_R3000
>> 2135 help
>> 2136 Using 64kB page size will result in higher performance kernel at
>> 2137 the price of higher memory consumption. This option is available on
>> 2138 all non-R3000 family processor. Not that at the time of this
>> 2139 writing this option is still high experimental.
1816 2140
1817 config X86_UMIP !! 2141 endchoice
1818 def_bool y <<
1819 prompt "User Mode Instruction Prevent <<
1820 help <<
1821 User Mode Instruction Prevention (U <<
1822 some x86 processors. If enabled, a <<
1823 issued if the SGDT, SLDT, SIDT, SMS <<
1824 executed in user mode. These instru <<
1825 information about the hardware stat <<
1826 <<
1827 The vast majority of applications d <<
1828 For the very few that do, software <<
1829 specific cases in protected and vir <<
1830 results are dummy. <<
1831 <<
1832 config CC_HAS_IBT <<
1833 # GCC >= 9 and binutils >= 2.29 <<
1834 # Retpoline check to work around http <<
1835 # Clang/LLVM >= 14 <<
1836 # https://github.com/llvm/llvm-projec <<
1837 # https://github.com/llvm/llvm-projec <<
1838 def_bool ((CC_IS_GCC && $(cc-option, <<
1839 (CC_IS_CLANG && CLANG_VERSI <<
1840 $(as-instr,endbr64) <<
1841 2142
1842 config X86_CET !! 2143 config ARCH_FORCE_MAX_ORDER
1843 def_bool n !! 2144 int "Maximum zone order"
1844 help !! 2145 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1845 CET features configured (Shadow sta !! 2146 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2147 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2148 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2149 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2150 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2151 range 0 64
>> 2152 default "11"
>> 2153 help
>> 2154 The kernel memory allocator divides physically contiguous memory
>> 2155 blocks into "zones", where each zone is a power of two number of
>> 2156 pages. This option selects the largest power of two that the kernel
>> 2157 keeps in the memory allocator. If you need to allocate very large
>> 2158 blocks of physically contiguous memory, then you may need to
>> 2159 increase this value.
1846 2160
1847 config X86_KERNEL_IBT !! 2161 This config option is actually maximum order plus one. For example,
1848 prompt "Indirect Branch Tracking" !! 2162 a value of 11 means that the largest free memory block is 2^10 pages.
1849 def_bool y <<
1850 depends on X86_64 && CC_HAS_IBT && HA <<
1851 # https://github.com/llvm/llvm-projec <<
1852 depends on !LD_IS_LLD || LLD_VERSION <<
1853 select OBJTOOL <<
1854 select X86_CET <<
1855 help <<
1856 Build the kernel with support for I <<
1857 hardware support course-grain forwa <<
1858 protection. It enforces that all in <<
1859 an ENDBR instruction, as such, the <<
1860 code with them to make this happen. <<
1861 <<
1862 In addition to building the kernel <<
1863 are not indirect call targets, avoi <<
1864 <<
1865 This requires LTO like objtool runs <<
1866 does significantly reduce the numbe <<
1867 kernel image. <<
1868 2163
1869 config X86_INTEL_MEMORY_PROTECTION_KEYS !! 2164 The page size is not necessarily 4KB. Keep this in mind
1870 prompt "Memory Protection Keys" !! 2165 when choosing a value for this option.
1871 def_bool y <<
1872 # Note: only available in 64-bit mode <<
1873 depends on X86_64 && (CPU_SUP_INTEL | <<
1874 select ARCH_USES_HIGH_VMA_FLAGS <<
1875 select ARCH_HAS_PKEYS <<
1876 help <<
1877 Memory Protection Keys provides a m <<
1878 page-based protections, but without <<
1879 page tables when an application cha <<
1880 2166
1881 For details, see Documentation/core !! 2167 config BOARD_SCACHE
>> 2168 bool
1882 2169
1883 If unsure, say y. !! 2170 config IP22_CPU_SCACHE
>> 2171 bool
>> 2172 select BOARD_SCACHE
1884 2173
1885 config ARCH_PKEY_BITS !! 2174 #
1886 int !! 2175 # Support for a MIPS32 / MIPS64 style S-caches
1887 default 4 !! 2176 #
>> 2177 config MIPS_CPU_SCACHE
>> 2178 bool
>> 2179 select BOARD_SCACHE
1888 2180
1889 choice !! 2181 config R5000_CPU_SCACHE
1890 prompt "TSX enable mode" !! 2182 bool
1891 depends on CPU_SUP_INTEL !! 2183 select BOARD_SCACHE
1892 default X86_INTEL_TSX_MODE_OFF <<
1893 help <<
1894 Intel's TSX (Transactional Synchron <<
1895 allows to optimize locking protocol <<
1896 can lead to a noticeable performanc <<
1897 2184
1898 On the other hand it has been shown !! 2185 config RM7000_CPU_SCACHE
1899 to form side channel attacks (e.g. !! 2186 bool
1900 will be more of those attacks disco !! 2187 select BOARD_SCACHE
1901 2188
1902 Therefore TSX is not enabled by def !! 2189 config SIBYTE_DMA_PAGEOPS
1903 might override this decision by tsx !! 2190 bool "Use DMA to clear/copy pages"
1904 Even with TSX enabled, the kernel w !! 2191 depends on CPU_SB1
1905 possible TAA mitigation setting dep !! 2192 help
1906 for the particular machine. !! 2193 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2194 channel. These DMA channels are otherwise unused by the standard
>> 2195 SiByte Linux port. Seems to give a small performance benefit.
1907 2196
1908 This option allows to set the defau !! 2197 config CPU_HAS_PREFETCH
1909 and =auto. See Documentation/admin- !! 2198 bool
1910 details. <<
1911 2199
1912 Say off if not sure, auto if TSX is !! 2200 config CPU_GENERIC_DUMP_TLB
1913 platforms or on if TSX is in use an !! 2201 bool
1914 relevant. !! 2202 default y if !CPU_R3000
1915 2203
1916 config X86_INTEL_TSX_MODE_OFF !! 2204 config MIPS_FP_SUPPORT
1917 bool "off" !! 2205 bool "Floating Point support" if EXPERT
>> 2206 default y
1918 help 2207 help
1919 TSX is disabled if possible - equal !! 2208 Select y to include support for floating point in the kernel
>> 2209 including initialization of FPU hardware, FP context save & restore
>> 2210 and emulation of an FPU where necessary. Without this support any
>> 2211 userland program attempting to use floating point instructions will
>> 2212 receive a SIGILL.
1920 2213
1921 config X86_INTEL_TSX_MODE_ON !! 2214 If you know that your userland will not attempt to use floating point
1922 bool "on" !! 2215 instructions then you can say n here to shrink the kernel a little.
1923 help <<
1924 TSX is always enabled on TSX capabl <<
1925 line parameter. <<
1926 2216
1927 config X86_INTEL_TSX_MODE_AUTO !! 2217 If unsure, say y.
1928 bool "auto" <<
1929 help <<
1930 TSX is enabled on TSX capable HW th <<
1931 side channel attacks- equals the ts <<
1932 endchoice <<
1933 2218
1934 config X86_SGX !! 2219 config CPU_R2300_FPU
1935 bool "Software Guard eXtensions (SGX) !! 2220 bool
1936 depends on X86_64 && CPU_SUP_INTEL && !! 2221 depends on MIPS_FP_SUPPORT
1937 depends on CRYPTO=y !! 2222 default y if CPU_R3000
1938 depends on CRYPTO_SHA256=y <<
1939 select MMU_NOTIFIER <<
1940 select NUMA_KEEP_MEMINFO if NUMA <<
1941 select XARRAY_MULTI <<
1942 help <<
1943 Intel(R) Software Guard eXtensions <<
1944 that can be used by applications to <<
1945 and data, referred to as enclaves. <<
1946 only be accessed by code running wi <<
1947 outside the enclave, including othe <<
1948 hardware. <<
1949 2223
1950 If unsure, say N. !! 2224 config CPU_R3K_TLB
>> 2225 bool
1951 2226
1952 config X86_USER_SHADOW_STACK !! 2227 config CPU_R4K_FPU
1953 bool "X86 userspace shadow stack" !! 2228 bool
1954 depends on AS_WRUSS !! 2229 depends on MIPS_FP_SUPPORT
1955 depends on X86_64 !! 2230 default y if !CPU_R2300_FPU
1956 select ARCH_USES_HIGH_VMA_FLAGS <<
1957 select X86_CET <<
1958 help <<
1959 Shadow stack protection is a hardwa <<
1960 return address corruption. This he <<
1961 Applications must be enabled to use <<
1962 get protection "for free". <<
1963 2231
1964 CPUs supporting shadow stacks were !! 2232 config CPU_R4K_CACHE_TLB
>> 2233 bool
>> 2234 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
1965 2235
1966 See Documentation/arch/x86/shstk.rs !! 2236 config MIPS_MT_SMP
>> 2237 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2238 default y
>> 2239 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2240 select CPU_MIPSR2_IRQ_VI
>> 2241 select CPU_MIPSR2_IRQ_EI
>> 2242 select SYNC_R4K
>> 2243 select MIPS_MT
>> 2244 select SMP
>> 2245 select SMP_UP
>> 2246 select SYS_SUPPORTS_SMP
>> 2247 select SYS_SUPPORTS_SCHED_SMT
>> 2248 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2249 help
>> 2250 This is a kernel model which is known as SMVP. This is supported
>> 2251 on cores with the MT ASE and uses the available VPEs to implement
>> 2252 virtual processors which supports SMP. This is equivalent to the
>> 2253 Intel Hyperthreading feature. For further information go to
>> 2254 <http://www.imgtec.com/mips/mips-multithreading.asp>.
1967 2255
1968 If unsure, say N. !! 2256 config MIPS_MT
>> 2257 bool
1969 2258
1970 config INTEL_TDX_HOST !! 2259 config SCHED_SMT
1971 bool "Intel Trust Domain Extensions ( !! 2260 bool "SMT (multithreading) scheduler support"
1972 depends on CPU_SUP_INTEL !! 2261 depends on SYS_SUPPORTS_SCHED_SMT
1973 depends on X86_64 !! 2262 default n
1974 depends on KVM_INTEL !! 2263 help
1975 depends on X86_X2APIC !! 2264 SMT scheduler support improves the CPU scheduler's decision making
1976 select ARCH_KEEP_MEMBLOCK !! 2265 when dealing with MIPS MT enabled cores at a cost of slightly
1977 depends on CONTIG_ALLOC !! 2266 increased overhead in some places. If unsure say N here.
1978 depends on !KEXEC_CORE <<
1979 depends on X86_MCE <<
1980 help <<
1981 Intel Trust Domain Extensions (TDX) <<
1982 host and certain physical attacks. <<
1983 support in the host kernel to run c <<
1984 2267
1985 If unsure, say N. !! 2268 config SYS_SUPPORTS_SCHED_SMT
>> 2269 bool
1986 2270
1987 config EFI !! 2271 config SYS_SUPPORTS_MULTITHREADING
1988 bool "EFI runtime service support" !! 2272 bool
1989 depends on ACPI !! 2273
1990 select UCS2_STRING !! 2274 config MIPS_MT_FPAFF
1991 select EFI_RUNTIME_WRAPPERS !! 2275 bool "Dynamic FPU affinity for FP-intensive threads"
1992 select ARCH_USE_MEMREMAP_PROT !! 2276 default y
1993 select EFI_RUNTIME_MAP if KEXEC_CORE !! 2277 depends on MIPS_MT_SMP
1994 help !! 2278
1995 This enables the kernel to use EFI !! 2279 config MIPSR2_TO_R6_EMULATOR
1996 available (such as the EFI variable !! 2280 bool "MIPS R2-to-R6 emulator"
1997 !! 2281 depends on CPU_MIPSR6
1998 This option is only useful on syste !! 2282 depends on MIPS_FP_SUPPORT
1999 In addition, you should use the lat <<
2000 at <http://elilo.sourceforge.net> i <<
2001 of EFI runtime services. However, e <<
2002 resultant kernel should continue to <<
2003 platforms. <<
2004 <<
2005 config EFI_STUB <<
2006 bool "EFI stub support" <<
2007 depends on EFI <<
2008 select RELOCATABLE <<
2009 help <<
2010 This kernel feature allows a bzImag <<
2011 by EFI firmware without the use of <<
2012 <<
2013 See Documentation/admin-guide/efi-s <<
2014 <<
2015 config EFI_HANDOVER_PROTOCOL <<
2016 bool "EFI handover protocol (DEPRECAT <<
2017 depends on EFI_STUB <<
2018 default y 2283 default y
2019 help 2284 help
2020 Select this in order to include sup !! 2285 Choose this option if you want to run non-R6 MIPS userland code.
2021 handover protocol, which defines al !! 2286 Even if you say 'Y' here, the emulator will still be disabled by
2022 EFI stub. This is a practice that !! 2287 default. You can enable it using the 'mipsr2emu' kernel option.
2023 specification, and requires a prior !! 2288 The only reason this is a build-time option is to save ~14K from the
2024 bootloader about Linux/x86 specific !! 2289 final kernel image.
2025 and initrd, and where in memory tho <<
2026 <<
2027 If in doubt, say Y. Even though the <<
2028 present in upstream GRUB or other b <<
2029 GRUB with numerous downstream patch <<
2030 handover protocol as as result. <<
2031 <<
2032 config EFI_MIXED <<
2033 bool "EFI mixed-mode support" <<
2034 depends on EFI_STUB && X86_64 <<
2035 help <<
2036 Enabling this feature allows a 64-b <<
2037 on a 32-bit firmware, provided that <<
2038 mode. <<
2039 <<
2040 Note that it is not possible to boo <<
2041 kernel via the EFI boot stub - a bo <<
2042 the EFI handover protocol must be u <<
2043 2290
2044 If unsure, say N. !! 2291 config SYS_SUPPORTS_VPE_LOADER
>> 2292 bool
>> 2293 depends on SYS_SUPPORTS_MULTITHREADING
>> 2294 help
>> 2295 Indicates that the platform supports the VPE loader, and provides
>> 2296 physical_memsize.
2045 2297
2046 config EFI_RUNTIME_MAP !! 2298 config MIPS_VPE_LOADER
2047 bool "Export EFI runtime maps to sysf !! 2299 bool "VPE loader support."
2048 depends on EFI !! 2300 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2301 select CPU_MIPSR2_IRQ_VI
>> 2302 select CPU_MIPSR2_IRQ_EI
>> 2303 select MIPS_MT
2049 help 2304 help
2050 Export EFI runtime memory regions t !! 2305 Includes a loader for loading an elf relocatable object
2051 That memory map is required by the !! 2306 onto another VPE and running it.
2052 mappings after kexec, but can also <<
2053 2307
2054 See also Documentation/ABI/testing/ !! 2308 config MIPS_VPE_LOADER_CMP
>> 2309 bool
>> 2310 default "y"
>> 2311 depends on MIPS_VPE_LOADER && MIPS_CMP
2055 2312
2056 source "kernel/Kconfig.hz" !! 2313 config MIPS_VPE_LOADER_MT
>> 2314 bool
>> 2315 default "y"
>> 2316 depends on MIPS_VPE_LOADER && !MIPS_CMP
2057 2317
2058 config ARCH_SUPPORTS_KEXEC !! 2318 config MIPS_VPE_LOADER_TOM
2059 def_bool y !! 2319 bool "Load VPE program into memory hidden from linux"
>> 2320 depends on MIPS_VPE_LOADER
>> 2321 default y
>> 2322 help
>> 2323 The loader can use memory that is present but has been hidden from
>> 2324 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2325 you to ensure the amount you put in the option and the space your
>> 2326 program requires is less or equal to the amount physically present.
2060 2327
2061 config ARCH_SUPPORTS_KEXEC_FILE !! 2328 config MIPS_VPE_APSP_API
2062 def_bool X86_64 !! 2329 bool "Enable support for AP/SP API (RTLX)"
>> 2330 depends on MIPS_VPE_LOADER
2063 2331
2064 config ARCH_SELECTS_KEXEC_FILE !! 2332 config MIPS_VPE_APSP_API_CMP
2065 def_bool y !! 2333 bool
2066 depends on KEXEC_FILE !! 2334 default "y"
2067 select HAVE_IMA_KEXEC if IMA !! 2335 depends on MIPS_VPE_APSP_API && MIPS_CMP
2068 2336
2069 config ARCH_SUPPORTS_KEXEC_PURGATORY !! 2337 config MIPS_VPE_APSP_API_MT
2070 def_bool y !! 2338 bool
>> 2339 default "y"
>> 2340 depends on MIPS_VPE_APSP_API && !MIPS_CMP
2071 2341
2072 config ARCH_SUPPORTS_KEXEC_SIG !! 2342 config MIPS_CMP
2073 def_bool y !! 2343 bool "MIPS CMP framework support (DEPRECATED)"
>> 2344 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2345 select SMP
>> 2346 select SYNC_R4K
>> 2347 select SYS_SUPPORTS_SMP
>> 2348 select WEAK_ORDERING
>> 2349 default n
>> 2350 help
>> 2351 Select this if you are using a bootloader which implements the "CMP
>> 2352 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2353 its ability to start secondary CPUs.
>> 2354
>> 2355 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2356 instead of this.
>> 2357
>> 2358 config MIPS_CPS
>> 2359 bool "MIPS Coherent Processing System support"
>> 2360 depends on SYS_SUPPORTS_MIPS_CPS
>> 2361 select MIPS_CM
>> 2362 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2363 select SMP
>> 2364 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2365 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2366 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2367 select SYS_SUPPORTS_SMP
>> 2368 select WEAK_ORDERING
>> 2369 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2370 help
>> 2371 Select this if you wish to run an SMP kernel across multiple cores
>> 2372 within a MIPS Coherent Processing System. When this option is
>> 2373 enabled the kernel will probe for other cores and boot them with
>> 2374 no external assistance. It is safe to enable this when hardware
>> 2375 support is unavailable.
2074 2376
2075 config ARCH_SUPPORTS_KEXEC_SIG_FORCE !! 2377 config MIPS_CPS_PM
2076 def_bool y !! 2378 depends on MIPS_CPS
>> 2379 bool
2077 2380
2078 config ARCH_SUPPORTS_KEXEC_BZIMAGE_VERIFY_SIG !! 2381 config MIPS_CM
2079 def_bool y !! 2382 bool
>> 2383 select MIPS_CPC
2080 2384
2081 config ARCH_SUPPORTS_KEXEC_JUMP !! 2385 config MIPS_CPC
2082 def_bool y !! 2386 bool
2083 2387
2084 config ARCH_SUPPORTS_CRASH_DUMP !! 2388 config SB1_PASS_2_WORKAROUNDS
2085 def_bool X86_64 || (X86_32 && HIGHMEM !! 2389 bool
>> 2390 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2391 default y
2086 2392
2087 config ARCH_SUPPORTS_CRASH_HOTPLUG !! 2393 config SB1_PASS_2_1_WORKAROUNDS
2088 def_bool y !! 2394 bool
>> 2395 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2396 default y
2089 2397
2090 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2398 choice
2091 def_bool CRASH_RESERVE !! 2399 prompt "SmartMIPS or microMIPS ASE support"
2092 2400
2093 config PHYSICAL_START !! 2401 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
2094 hex "Physical address where the kerne !! 2402 bool "None"
2095 default "0x1000000" <<
2096 help 2403 help
2097 This gives the physical address whe !! 2404 Select this if you want neither microMIPS nor SmartMIPS support
2098 <<
2099 If the kernel is not relocatable (C <<
2100 will decompress itself to above phy <<
2101 Otherwise, bzImage will run from th <<
2102 by the boot loader. The only except <<
2103 above physical address, in which ca <<
2104 <<
2105 In normal kdump cases one does not <<
2106 as now bzImage can be compiled as a <<
2107 (CONFIG_RELOCATABLE=y) and be used <<
2108 address. This option is mainly usef <<
2109 to use a bzImage for capturing the <<
2110 vmlinux instead. vmlinux is not rel <<
2111 to be specifically compiled to run <<
2112 (normally a reserved region) and th <<
2113 <<
2114 So if you are using bzImage for cap <<
2115 leave the value here unchanged to 0 <<
2116 CONFIG_RELOCATABLE=y. Otherwise if <<
2117 for capturing the crash dump change <<
2118 the reserved region. In other word <<
2119 the "X" value as specified in the " <<
2120 command line boot parameter passed <<
2121 kernel. Please take a look at Docum <<
2122 for more details about crash dumps. <<
2123 <<
2124 Usage of bzImage for capturing the <<
2125 one does not have to build two kern <<
2126 as production kernel and capture ke <<
2127 gone away after relocatable bzImage <<
2128 is present because there are users <<
2129 vmlinux for dump capture. This opti <<
2130 line. <<
2131 2405
2132 Don't change this unless you know w !! 2406 config CPU_HAS_SMARTMIPS
2133 !! 2407 depends on SYS_SUPPORTS_SMARTMIPS
2134 config RELOCATABLE !! 2408 bool "SmartMIPS"
2135 bool "Build a relocatable kernel" !! 2409 help
2136 default y !! 2410 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2411 increased security at both hardware and software level for
>> 2412 smartcards. Enabling this option will allow proper use of the
>> 2413 SmartMIPS instructions by Linux applications. However a kernel with
>> 2414 this option will not work on a MIPS core without SmartMIPS core. If
>> 2415 you don't know you probably don't have SmartMIPS and should say N
>> 2416 here.
>> 2417
>> 2418 config CPU_MICROMIPS
>> 2419 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2420 bool "microMIPS"
2137 help 2421 help
2138 This builds a kernel image that ret !! 2422 When this option is enabled the kernel will be built using the
2139 so it can be loaded someplace besid !! 2423 microMIPS ISA
2140 The relocations tend to make the ke <<
2141 but are discarded at runtime. <<
2142 2424
2143 One use is for the kexec on panic c !! 2425 endchoice
2144 must live at a different physical a <<
2145 kernel. <<
2146 <<
2147 Note: If CONFIG_RELOCATABLE=y, then <<
2148 it has been loaded at and the compi <<
2149 (CONFIG_PHYSICAL_START) is used as <<
2150 2426
2151 config RANDOMIZE_BASE !! 2427 config CPU_HAS_MSA
2152 bool "Randomize the address of the ke !! 2428 bool "Support for the MIPS SIMD Architecture"
2153 depends on RELOCATABLE !! 2429 depends on CPU_SUPPORTS_MSA
2154 default y !! 2430 depends on MIPS_FP_SUPPORT
2155 help !! 2431 depends on 64BIT || MIPS_O32_FP64_SUPPORT
2156 In support of Kernel Address Space !! 2432 help
2157 this randomizes the physical addres !! 2433 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
2158 is decompressed and the virtual add !! 2434 and a set of SIMD instructions to operate on them. When this option
2159 image is mapped, as a security feat !! 2435 is enabled the kernel will support allocating & switching MSA
2160 attempts relying on knowledge of th !! 2436 vector register contexts. If you know that your kernel will only be
2161 code internals. !! 2437 running on CPUs which do not support MSA or that your userland will
2162 !! 2438 not be making use of it then you may wish to say N here to reduce
2163 On 64-bit, the kernel physical and !! 2439 the size & complexity of your kernel.
2164 randomized separately. The physical <<
2165 between 16MB and the top of physica <<
2166 virtual address will be randomized <<
2167 of entropy). Note that this also re <<
2168 available to kernel modules from 1. <<
2169 <<
2170 On 32-bit, the kernel physical and <<
2171 randomized together. They will be r <<
2172 512MB (8 bits of entropy). <<
2173 <<
2174 Entropy is generated using the RDRA <<
2175 supported. If RDTSC is supported, i <<
2176 the entropy pool as well. If neithe <<
2177 supported, then entropy is read fro <<
2178 usable entropy is limited by the ke <<
2179 2GB addressing, and that PHYSICAL_A <<
2180 minimum of 2MB. As a result, only 1 <<
2181 theoretically possible, but the imp <<
2182 limited due to memory layouts. <<
2183 2440
2184 If unsure, say Y. 2441 If unsure, say Y.
2185 2442
2186 # Relocation on x86 needs some additional bui !! 2443 config CPU_HAS_WB
2187 config X86_NEED_RELOCS !! 2444 bool
2188 def_bool y !! 2445
2189 depends on RANDOMIZE_BASE || (X86_32 !! 2446 config XKS01
>> 2447 bool
>> 2448
>> 2449 config CPU_HAS_DIEI
>> 2450 depends on !CPU_DIEI_BROKEN
>> 2451 bool
>> 2452
>> 2453 config CPU_DIEI_BROKEN
>> 2454 bool
>> 2455
>> 2456 config CPU_HAS_RIXI
>> 2457 bool
2190 2458
2191 config PHYSICAL_ALIGN !! 2459 config CPU_NO_LOAD_STORE_LR
2192 hex "Alignment value to which kernel !! 2460 bool
2193 default "0x200000" <<
2194 range 0x2000 0x1000000 if X86_32 <<
2195 range 0x200000 0x1000000 if X86_64 <<
2196 help 2461 help
2197 This value puts the alignment restr !! 2462 CPU lacks support for unaligned load and store instructions:
2198 where kernel is loaded and run from !! 2463 LWL, LWR, SWL, SWR (Load/store word left/right).
2199 address which meets above alignment !! 2464 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2465 systems).
2200 2466
2201 If bootloader loads the kernel at a !! 2467 #
2202 CONFIG_RELOCATABLE is set, kernel w !! 2468 # Vectored interrupt mode is an R2 feature
2203 address aligned to above value and !! 2469 #
>> 2470 config CPU_MIPSR2_IRQ_VI
>> 2471 bool
2204 2472
2205 If bootloader loads the kernel at a !! 2473 #
2206 CONFIG_RELOCATABLE is not set, kern !! 2474 # Extended interrupt mode is an R2 feature
2207 load address and decompress itself !! 2475 #
2208 compiled for and run from there. Th !! 2476 config CPU_MIPSR2_IRQ_EI
2209 compiled already meets above alignm !! 2477 bool
2210 end result is that kernel runs from <<
2211 above alignment restrictions. <<
2212 2478
2213 On 32-bit this value must be a mult !! 2479 config CPU_HAS_SYNC
2214 this value must be a multiple of 0x !! 2480 bool
>> 2481 depends on !CPU_R3000
>> 2482 default y
2215 2483
2216 Don't change this unless you know w !! 2484 #
>> 2485 # CPU non-features
>> 2486 #
2217 2487
2218 config DYNAMIC_MEMORY_LAYOUT !! 2488 # Work around the "daddi" and "daddiu" CPU errata:
>> 2489 #
>> 2490 # - The `daddi' instruction fails to trap on overflow.
>> 2491 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2492 # erratum #23
>> 2493 #
>> 2494 # - The `daddiu' instruction can produce an incorrect result.
>> 2495 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2496 # erratum #41
>> 2497 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2498 # #15
>> 2499 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2500 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2501 config CPU_DADDI_WORKAROUNDS
2219 bool 2502 bool
2220 help <<
2221 This option makes base addresses of <<
2222 __PAGE_OFFSET movable during boot. <<
2223 2503
2224 config RANDOMIZE_MEMORY !! 2504 # Work around certain R4000 CPU errata (as implemented by GCC):
2225 bool "Randomize the kernel memory sec !! 2505 #
2226 depends on X86_64 !! 2506 # - A double-word or a variable shift may give an incorrect result
2227 depends on RANDOMIZE_BASE !! 2507 # if executed immediately after starting an integer division:
2228 select DYNAMIC_MEMORY_LAYOUT !! 2508 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2229 default RANDOMIZE_BASE !! 2509 # erratum #28
2230 help !! 2510 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2231 Randomizes the base virtual address !! 2511 # #19
2232 (physical memory mapping, vmalloc & !! 2512 #
2233 makes exploits relying on predictab !! 2513 # - A double-word or a variable shift may give an incorrect result
2234 !! 2514 # if executed while an integer multiplication is in progress:
2235 The order of allocations remains un !! 2515 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2236 the same way as RANDOMIZE_BASE. Cur !! 2516 # errata #16 & #28
2237 configuration have in average 30,00 !! 2517 #
2238 addresses for each memory section. !! 2518 # - An integer division may give an incorrect result if started in
>> 2519 # a delay slot of a taken branch or a jump:
>> 2520 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2521 # erratum #52
>> 2522 config CPU_R4000_WORKAROUNDS
>> 2523 bool
>> 2524 select CPU_R4400_WORKAROUNDS
2239 2525
2240 If unsure, say Y. !! 2526 # Work around certain R4400 CPU errata (as implemented by GCC):
>> 2527 #
>> 2528 # - A double-word or a variable shift may give an incorrect result
>> 2529 # if executed immediately after starting an integer division:
>> 2530 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
>> 2531 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
>> 2532 config CPU_R4400_WORKAROUNDS
>> 2533 bool
2241 2534
2242 config RANDOMIZE_MEMORY_PHYSICAL_PADDING !! 2535 config CPU_R4X00_BUGS64
2243 hex "Physical memory mapping padding" !! 2536 bool
2244 depends on RANDOMIZE_MEMORY !! 2537 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
2245 default "0xa" if MEMORY_HOTPLUG <<
2246 default "0x0" <<
2247 range 0x1 0x40 if MEMORY_HOTPLUG <<
2248 range 0x0 0x40 <<
2249 help <<
2250 Define the padding in terabytes add <<
2251 memory size during kernel memory ra <<
2252 for memory hotplug support but redu <<
2253 address randomization. <<
2254 2538
2255 If unsure, leave at the default val !! 2539 config MIPS_ASID_SHIFT
>> 2540 int
>> 2541 default 6 if CPU_R3000
>> 2542 default 0
2256 2543
2257 config ADDRESS_MASKING !! 2544 config MIPS_ASID_BITS
2258 bool "Linear Address Masking support" !! 2545 int
2259 depends on X86_64 !! 2546 default 0 if MIPS_ASID_BITS_VARIABLE
2260 depends on COMPILE_TEST || !CPU_MITIG !! 2547 default 6 if CPU_R3000
2261 help !! 2548 default 8
2262 Linear Address Masking (LAM) modifi <<
2263 to 64-bit linear addresses, allowin <<
2264 untranslated address bits for metad <<
2265 2549
2266 The capability can be used for effi !! 2550 config MIPS_ASID_BITS_VARIABLE
2267 implementation and for optimization !! 2551 bool
2268 2552
2269 config HOTPLUG_CPU !! 2553 config MIPS_CRC_SUPPORT
2270 def_bool y !! 2554 bool
2271 depends on SMP <<
2272 2555
2273 config COMPAT_VDSO !! 2556 # R4600 erratum. Due to the lack of errata information the exact
2274 def_bool n !! 2557 # technical details aren't known. I've experimentally found that disabling
2275 prompt "Disable the 32-bit vDSO (need !! 2558 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2276 depends on COMPAT_32 !! 2559 # with the issue.
2277 help !! 2560 config WAR_R4600_V1_INDEX_ICACHEOP
2278 Certain buggy versions of glibc wil !! 2561 bool
2279 presented with a 32-bit vDSO that i <<
2280 indicated in its segment table. <<
2281 <<
2282 The bug was introduced by f866314b8 <<
2283 and fixed by 3b3ddb4f7db98ec9e912cc <<
2284 49ad572a70b8aeb91e57483a11dd1b77e31 <<
2285 the only released version with the <<
2286 contains a buggy "glibc 2.3.2". <<
2287 <<
2288 The symptom of the bug is that ever <<
2289 dl_main: Assertion `(void *) ph->p_ <<
2290 <<
2291 Saying Y here changes the default v <<
2292 option from 1 to 0, which turns off <<
2293 This works around the glibc bug but <<
2294 2562
2295 If unsure, say N: if you are compil !! 2563 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
2296 are unlikely to be using a buggy ve !! 2564 #
>> 2565 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
>> 2566 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
>> 2567 # executed if there is no other dcache activity. If the dcache is
>> 2568 # accessed for another instruction immediately preceding when these
>> 2569 # cache instructions are executing, it is possible that the dcache
>> 2570 # tag match outputs used by these cache instructions will be
>> 2571 # incorrect. These cache instructions should be preceded by at least
>> 2572 # four instructions that are not any kind of load or store
>> 2573 # instruction.
>> 2574 #
>> 2575 # This is not allowed: lw
>> 2576 # nop
>> 2577 # nop
>> 2578 # nop
>> 2579 # cache Hit_Writeback_Invalidate_D
>> 2580 #
>> 2581 # This is allowed: lw
>> 2582 # nop
>> 2583 # nop
>> 2584 # nop
>> 2585 # nop
>> 2586 # cache Hit_Writeback_Invalidate_D
>> 2587 config WAR_R4600_V1_HIT_CACHEOP
>> 2588 bool
2297 2589
2298 choice !! 2590 # Writeback and invalidate the primary cache dcache before DMA.
2299 prompt "vsyscall table for legacy app !! 2591 #
2300 depends on X86_64 !! 2592 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
2301 default LEGACY_VSYSCALL_XONLY !! 2593 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
2302 help !! 2594 # operate correctly if the internal data cache refill buffer is empty. These
2303 Legacy user code that does not know !! 2595 # CACHE instructions should be separated from any potential data cache miss
2304 to be able to issue three syscalls !! 2596 # by a load instruction to an uncached address to empty the response buffer."
2305 kernel space. Since this location i !! 2597 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
2306 it can be used to assist security v !! 2598 # in .pdf format.)
2307 !! 2599 config WAR_R4600_V2_HIT_CACHEOP
2308 This setting can be changed at boot !! 2600 bool
2309 line parameter vsyscall=[emulate|xo <<
2310 is deprecated and can only be enabl <<
2311 line. <<
2312 <<
2313 On a system with recent enough glib <<
2314 static binaries, you can say None w <<
2315 to improve security. <<
2316 2601
2317 If unsure, select "Emulate executio !! 2602 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
>> 2603 # the line which this instruction itself exists, the following
>> 2604 # operation is not guaranteed."
>> 2605 #
>> 2606 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2607 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2608 bool
2318 2609
2319 config LEGACY_VSYSCALL_XONLY !! 2610 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2320 bool "Emulate execution only" !! 2611 # opposes it being called that) where invalid instructions in the same
2321 help !! 2612 # I-cache line worth of instructions being fetched may case spurious
2322 The kernel traps and emulat !! 2613 # exceptions.
2323 address mapping and does no !! 2614 config WAR_ICACHE_REFILLS
2324 configuration is recommende !! 2615 bool
2325 legacy vsyscall area but su <<
2326 instrumentation of legacy c <<
2327 certain uses of the vsyscal <<
2328 buffer. <<
2329 2616
2330 config LEGACY_VSYSCALL_NONE !! 2617 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
2331 bool "None" !! 2618 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2332 help !! 2619 config WAR_R10000_LLSC
2333 There will be no vsyscall m !! 2620 bool
2334 eliminate any risk of ASLR <<
2335 fixed address mapping. Atte <<
2336 will be reported to dmesg, <<
2337 malicious userspace program <<
2338 2621
2339 endchoice !! 2622 # 34K core erratum: "Problems Executing the TLBR Instruction"
>> 2623 config WAR_MIPS34K_MISSED_ITLB
>> 2624 bool
2340 2625
2341 config CMDLINE_BOOL !! 2626 #
2342 bool "Built-in kernel command line" !! 2627 # - Highmem only makes sense for the 32-bit kernel.
2343 help !! 2628 # - The current highmem code will only work properly on physically indexed
2344 Allow for specifying boot arguments !! 2629 # caches such as R3000, SB1, R7000 or those that look like they're virtually
2345 build time. On some systems (e.g. !! 2630 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
2346 necessary or convenient to provide !! 2631 # moment we protect the user and offer the highmem option only on machines
2347 kernel boot arguments with the kern !! 2632 # where it's known to be safe. This will not offer highmem on a few systems
2348 to not rely on the boot loader to p !! 2633 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
2349 !! 2634 # indexed CPUs but we're playing safe.
2350 To compile command line arguments i !! 2635 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2351 set this option to 'Y', then fill i !! 2636 # know they might have memory configurations that could make use of highmem
2352 boot arguments in CONFIG_CMDLINE. !! 2637 # support.
2353 !! 2638 #
2354 Systems with fully functional boot !! 2639 config HIGHMEM
2355 should leave this option set to 'N' !! 2640 bool "High Memory Support"
2356 !! 2641 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
2357 config CMDLINE !! 2642 select KMAP_LOCAL
2358 string "Built-in kernel command strin <<
2359 depends on CMDLINE_BOOL <<
2360 default "" <<
2361 help <<
2362 Enter arguments here that should be <<
2363 image and used at boot time. If th <<
2364 command line at boot time, it is ap <<
2365 form the full kernel command line, <<
2366 <<
2367 However, you can use the CONFIG_CMD <<
2368 change this behavior. <<
2369 <<
2370 In most cases, the command line (wh <<
2371 by the boot loader) should specify <<
2372 file system. <<
2373 <<
2374 config CMDLINE_OVERRIDE <<
2375 bool "Built-in command line overrides <<
2376 depends on CMDLINE_BOOL && CMDLINE != <<
2377 help <<
2378 Set this option to 'Y' to have the <<
2379 command line, and use ONLY the buil <<
2380 2643
2381 This is used to work around broken !! 2644 config CPU_SUPPORTS_HIGHMEM
2382 be set to 'N' under normal conditio !! 2645 bool
2383 2646
2384 config MODIFY_LDT_SYSCALL !! 2647 config SYS_SUPPORTS_HIGHMEM
2385 bool "Enable the LDT (local descripto !! 2648 bool
2386 default y <<
2387 help <<
2388 Linux can allow user programs to in <<
2389 Local Descriptor Table (LDT) using <<
2390 call. This is required to run 16-b <<
2391 DOSEMU or some Wine programs. It i <<
2392 threading libraries. <<
2393 <<
2394 Enabling this feature adds a small <<
2395 context switches and increases the <<
2396 surface. Disabling it removes the <<
2397 <<
2398 Saying 'N' here may make sense for <<
2399 <<
2400 config STRICT_SIGALTSTACK_SIZE <<
2401 bool "Enforce strict size checking fo <<
2402 depends on DYNAMIC_SIGFRAME <<
2403 help <<
2404 For historical reasons MINSIGSTKSZ <<
2405 already too small with AVX512 suppo <<
2406 enforce strict checking of the siga <<
2407 real size of the FPU frame. This op <<
2408 by default. It can also be controll <<
2409 line option 'strict_sas_size' indep <<
2410 switch. Enabling it might break exi <<
2411 allocate a too small sigaltstack bu <<
2412 never get a signal delivered. <<
2413 <<
2414 Say 'N' unless you want to really e <<
2415 <<
2416 config CFI_AUTO_DEFAULT <<
2417 bool "Attempt to use FineIBT by defau <<
2418 depends on FINEIBT <<
2419 default y <<
2420 help <<
2421 Attempt to use FineIBT by default a <<
2422 this is the same as booting with "c <<
2423 this is the same as booting with "c <<
2424 2649
2425 source "kernel/livepatch/Kconfig" !! 2650 config SYS_SUPPORTS_SMARTMIPS
>> 2651 bool
2426 2652
2427 endmenu !! 2653 config SYS_SUPPORTS_MICROMIPS
>> 2654 bool
2428 2655
2429 config CC_HAS_NAMED_AS !! 2656 config SYS_SUPPORTS_MIPS16
2430 def_bool $(success,echo 'int __seg_fs !! 2657 bool
2431 depends on CC_IS_GCC !! 2658 help
>> 2659 This option must be set if a kernel might be executed on a MIPS16-
>> 2660 enabled CPU even if MIPS16 is not actually being used. In other
>> 2661 words, it makes the kernel MIPS16-tolerant.
2432 2662
2433 config CC_HAS_NAMED_AS_FIXED_SANITIZERS !! 2663 config CPU_SUPPORTS_MSA
2434 def_bool CC_IS_GCC && GCC_VERSION >= !! 2664 bool
2435 2665
2436 config USE_X86_SEG_SUPPORT !! 2666 config ARCH_FLATMEM_ENABLE
2437 def_bool y 2667 def_bool y
2438 depends on CC_HAS_NAMED_AS !! 2668 depends on !NUMA && !CPU_LOONGSON2EF
2439 # <<
2440 # -fsanitize=kernel-address (KASAN) a <<
2441 # (KCSAN) are incompatible with named <<
2442 # GCC < 13.3 - see GCC PR sanitizer/1 <<
2443 # <<
2444 depends on !(KASAN || KCSAN) || CC_HA <<
2445 2669
2446 config CC_HAS_SLS !! 2670 config ARCH_SPARSEMEM_ENABLE
2447 def_bool $(cc-option,-mharden-sls=all !! 2671 bool
2448 2672
2449 config CC_HAS_RETURN_THUNK !! 2673 config NUMA
2450 def_bool $(cc-option,-mfunction-retur !! 2674 bool "NUMA Support"
>> 2675 depends on SYS_SUPPORTS_NUMA
>> 2676 select SMP
>> 2677 select HAVE_SETUP_PER_CPU_AREA
>> 2678 select NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2679 help
>> 2680 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2681 Access). This option improves performance on systems with more
>> 2682 than two nodes; on two node systems it is generally better to
>> 2683 leave it disabled; on single node systems leave this option
>> 2684 disabled.
2451 2685
2452 config CC_HAS_ENTRY_PADDING !! 2686 config SYS_SUPPORTS_NUMA
2453 def_bool $(cc-option,-fpatchable-func !! 2687 bool
2454 2688
2455 config FUNCTION_PADDING_CFI !! 2689 config HAVE_ARCH_NODEDATA_EXTENSION
2456 int !! 2690 bool
2457 default 59 if FUNCTION_ALIGNMENT_64B <<
2458 default 27 if FUNCTION_ALIGNMENT_32B <<
2459 default 11 if FUNCTION_ALIGNMENT_16B <<
2460 default 3 if FUNCTION_ALIGNMENT_8B <<
2461 default 0 <<
2462 <<
2463 # Basically: FUNCTION_ALIGNMENT - 5*CFI_CLANG <<
2464 # except Kconfig can't do arithmetic :/ <<
2465 config FUNCTION_PADDING_BYTES <<
2466 int <<
2467 default FUNCTION_PADDING_CFI if CFI_C <<
2468 default FUNCTION_ALIGNMENT <<
2469 2691
2470 config CALL_PADDING !! 2692 config RELOCATABLE
2471 def_bool n !! 2693 bool "Relocatable kernel"
2472 depends on CC_HAS_ENTRY_PADDING && OB !! 2694 depends on SYS_SUPPORTS_RELOCATABLE
2473 select FUNCTION_ALIGNMENT_16B !! 2695 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2696 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2697 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2698 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2699 CPU_LOONGSON64
>> 2700 help
>> 2701 This builds a kernel image that retains relocation information
>> 2702 so it can be loaded someplace besides the default 1MB.
>> 2703 The relocations make the kernel binary about 15% larger,
>> 2704 but are discarded at runtime
2474 2705
2475 config FINEIBT !! 2706 config RELOCATION_TABLE_SIZE
2476 def_bool y !! 2707 hex "Relocation table size"
2477 depends on X86_KERNEL_IBT && CFI_CLAN !! 2708 depends on RELOCATABLE
2478 select CALL_PADDING !! 2709 range 0x0 0x01000000
>> 2710 default "0x00200000" if CPU_LOONGSON64
>> 2711 default "0x00100000"
>> 2712 help
>> 2713 A table of relocation data will be appended to the kernel binary
>> 2714 and parsed at boot to fix up the relocated kernel.
2479 2715
2480 config HAVE_CALL_THUNKS !! 2716 This option allows the amount of space reserved for the table to be
2481 def_bool y !! 2717 adjusted, although the default of 1Mb should be ok in most cases.
2482 depends on CC_HAS_ENTRY_PADDING && MI <<
2483 2718
2484 config CALL_THUNKS !! 2719 The build will fail and a valid size suggested if this is too small.
2485 def_bool n <<
2486 select CALL_PADDING <<
2487 2720
2488 config PREFIX_SYMBOLS !! 2721 If unsure, leave at the default value.
2489 def_bool y <<
2490 depends on CALL_PADDING && !CFI_CLANG <<
2491 2722
2492 menuconfig CPU_MITIGATIONS !! 2723 config RANDOMIZE_BASE
2493 bool "Mitigations for CPU vulnerabili !! 2724 bool "Randomize the address of the kernel image"
2494 default y !! 2725 depends on RELOCATABLE
2495 help 2726 help
2496 Say Y here to enable options which !! 2727 Randomizes the physical and virtual address at which the
2497 vulnerabilities (usually related to !! 2728 kernel image is loaded, as a security feature that
2498 Mitigations can be disabled or rest !! 2729 deters exploit attempts relying on knowledge of the location
2499 via the "mitigations" kernel parame !! 2730 of kernel internals.
2500 2731
2501 If you say N, all mitigations will !! 2732 Entropy is generated using any coprocessor 0 registers available.
2502 overridden at runtime. <<
2503 2733
2504 Say 'Y', unless you really know wha !! 2734 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
2505 2735
2506 if CPU_MITIGATIONS !! 2736 If unsure, say N.
2507 2737
2508 config MITIGATION_PAGE_TABLE_ISOLATION !! 2738 config RANDOMIZE_BASE_MAX_OFFSET
2509 bool "Remove the kernel mapping in us !! 2739 hex "Maximum kASLR offset" if EXPERT
2510 default y !! 2740 depends on RANDOMIZE_BASE
2511 depends on (X86_64 || X86_PAE) !! 2741 range 0x0 0x40000000 if EVA || 64BIT
2512 help !! 2742 range 0x0 0x08000000
2513 This feature reduces the number of !! 2743 default "0x01000000"
2514 ensuring that the majority of kerne !! 2744 help
2515 into userspace. !! 2745 When kASLR is active, this provides the maximum offset that will
>> 2746 be applied to the kernel image. It should be set according to the
>> 2747 amount of physical RAM available in the target system minus
>> 2748 PHYSICAL_START and must be a power of 2.
2516 2749
2517 See Documentation/arch/x86/pti.rst !! 2750 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2751 EVA or 64-bit. The default is 16Mb.
2518 2752
2519 config MITIGATION_RETPOLINE !! 2753 config NODES_SHIFT
2520 bool "Avoid speculative indirect bran !! 2754 int
2521 select OBJTOOL if HAVE_OBJTOOL !! 2755 default "6"
2522 default y !! 2756 depends on NUMA
2523 help <<
2524 Compile kernel with the retpoline c <<
2525 kernel-to-user data leaks by avoidi <<
2526 branches. Requires a compiler with <<
2527 support for full protection. The ke <<
2528 <<
2529 config MITIGATION_RETHUNK <<
2530 bool "Enable return-thunks" <<
2531 depends on MITIGATION_RETPOLINE && CC <<
2532 select OBJTOOL if HAVE_OBJTOOL <<
2533 default y if X86_64 <<
2534 help <<
2535 Compile the kernel with the return- <<
2536 against kernel-to-user data leaks b <<
2537 Requires a compiler with -mfunction <<
2538 support for full protection. The ke <<
2539 <<
2540 config MITIGATION_UNRET_ENTRY <<
2541 bool "Enable UNRET on kernel entry" <<
2542 depends on CPU_SUP_AMD && MITIGATION_ <<
2543 default y <<
2544 help <<
2545 Compile the kernel with support for <<
2546 2757
2547 config MITIGATION_CALL_DEPTH_TRACKING !! 2758 config HW_PERF_EVENTS
2548 bool "Mitigate RSB underflow with cal !! 2759 bool "Enable hardware performance counter support for perf events"
2549 depends on CPU_SUP_INTEL && HAVE_CALL !! 2760 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
2550 select HAVE_DYNAMIC_FTRACE_NO_PATCHAB <<
2551 select CALL_THUNKS <<
2552 default y <<
2553 help <<
2554 Compile the kernel with call depth <<
2555 SKL Return-Speculation-Buffer (RSB) <<
2556 mitigation is off by default and ne <<
2557 kernel command line via the retblee <<
2558 non-affected systems the overhead o <<
2559 the call depth tracking is using ru <<
2560 in a compiler generated padding are <<
2561 increases text size by ~5%. For non <<
2562 is unused. On affected SKL systems <<
2563 performance gain over the IBRS miti <<
2564 <<
2565 config CALL_THUNKS_DEBUG <<
2566 bool "Enable call thunks and call dep <<
2567 depends on MITIGATION_CALL_DEPTH_TRAC <<
2568 select FUNCTION_ALIGNMENT_32B <<
2569 default n <<
2570 help <<
2571 Enable call/ret counters for imbala <<
2572 a noisy dmesg about callthunks gene <<
2573 trouble shooting. The debug prints <<
2574 kernel command line with 'debug-cal <<
2575 Only enable this when you are debug <<
2576 creates a noticeable runtime overhe <<
2577 <<
2578 config MITIGATION_IBPB_ENTRY <<
2579 bool "Enable IBPB on kernel entry" <<
2580 depends on CPU_SUP_AMD && X86_64 <<
2581 default y 2761 default y
2582 help 2762 help
2583 Compile the kernel with support for !! 2763 Enable hardware performance counter support for perf events. If
>> 2764 disabled, perf events will use software events only.
2584 2765
2585 config MITIGATION_IBRS_ENTRY !! 2766 config DMI
2586 bool "Enable IBRS on kernel entry" !! 2767 bool "Enable DMI scanning"
2587 depends on CPU_SUP_INTEL && X86_64 !! 2768 depends on MACH_LOONGSON64
>> 2769 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
2588 default y 2770 default y
2589 help 2771 help
2590 Compile the kernel with support for !! 2772 Enabled scanning of DMI to identify machine quirks. Say Y
2591 This mitigates both spectre_v2 and !! 2773 here unless you have verified that your setup is not
2592 performance. !! 2774 affected by entries in the DMI blacklist. Required by PNP
>> 2775 BIOS code.
2593 2776
2594 config MITIGATION_SRSO !! 2777 config SMP
2595 bool "Mitigate speculative RAS overfl !! 2778 bool "Multi-Processing support"
2596 depends on CPU_SUP_AMD && X86_64 && M !! 2779 depends on SYS_SUPPORTS_SMP
2597 default y <<
2598 help 2780 help
2599 Enable the SRSO mitigation needed o !! 2781 This enables support for systems with more than one CPU. If you have
>> 2782 a system with only one CPU, say N. If you have a system with more
>> 2783 than one CPU, say Y.
2600 2784
2601 config MITIGATION_SLS !! 2785 If you say N here, the kernel will run on uni- and multiprocessor
2602 bool "Mitigate Straight-Line-Speculat !! 2786 machines, but will use only one CPU of a multiprocessor machine. If
2603 depends on CC_HAS_SLS && X86_64 !! 2787 you say Y here, the kernel will run on many, but not all,
2604 select OBJTOOL if HAVE_OBJTOOL !! 2788 uniprocessor machines. On a uniprocessor machine, the kernel
2605 default n !! 2789 will run faster if you say N here.
2606 help <<
2607 Compile the kernel with straight-li <<
2608 against straight line speculation. <<
2609 larger. <<
2610 <<
2611 config MITIGATION_GDS <<
2612 bool "Mitigate Gather Data Sampling" <<
2613 depends on CPU_SUP_INTEL <<
2614 default y <<
2615 help <<
2616 Enable mitigation for Gather Data S <<
2617 vulnerability which allows unprivil <<
2618 which was previously stored in vect <<
2619 instructions to infer the stale vec <<
2620 <<
2621 config MITIGATION_RFDS <<
2622 bool "RFDS Mitigation" <<
2623 depends on CPU_SUP_INTEL <<
2624 default y <<
2625 help <<
2626 Enable mitigation for Register File <<
2627 RFDS is a hardware vulnerability wh <<
2628 allows unprivileged speculative acc <<
2629 stored in floating point, vector an <<
2630 See also <file:Documentation/admin- <<
2631 <<
2632 config MITIGATION_SPECTRE_BHI <<
2633 bool "Mitigate Spectre-BHB (Branch Hi <<
2634 depends on CPU_SUP_INTEL <<
2635 default y <<
2636 help <<
2637 Enable BHI mitigations. BHI attacks <<
2638 where the branch history buffer is <<
2639 indirect branches. <<
2640 See <file:Documentation/admin-guide <<
2641 <<
2642 config MITIGATION_MDS <<
2643 bool "Mitigate Microarchitectural Dat <<
2644 depends on CPU_SUP_INTEL <<
2645 default y <<
2646 help <<
2647 Enable mitigation for Microarchitec <<
2648 a hardware vulnerability which allo <<
2649 to data which is available in vario <<
2650 See also <file:Documentation/admin- <<
2651 <<
2652 config MITIGATION_TAA <<
2653 bool "Mitigate TSX Asynchronous Abort <<
2654 depends on CPU_SUP_INTEL <<
2655 default y <<
2656 help <<
2657 Enable mitigation for TSX Asynchron <<
2658 vulnerability that allows unprivile <<
2659 which is available in various CPU i <<
2660 asynchronous aborts within an Intel <<
2661 See also <file:Documentation/admin- <<
2662 <<
2663 config MITIGATION_MMIO_STALE_DATA <<
2664 bool "Mitigate MMIO Stale Data hardwa <<
2665 depends on CPU_SUP_INTEL <<
2666 default y <<
2667 help <<
2668 Enable mitigation for MMIO Stale Da <<
2669 Stale Data Vulnerabilities are a cl <<
2670 vulnerabilities that can expose dat <<
2671 attacker to have access to MMIO. <<
2672 See also <<
2673 <file:Documentation/admin-guide/hw- <<
2674 <<
2675 config MITIGATION_L1TF <<
2676 bool "Mitigate L1 Terminal Fault (L1T <<
2677 depends on CPU_SUP_INTEL <<
2678 default y <<
2679 help <<
2680 Mitigate L1 Terminal Fault (L1TF) h <<
2681 hardware vulnerability which allows <<
2682 available in the Level 1 Data Cache <<
2683 See <file:Documentation/admin-guide <<
2684 <<
2685 config MITIGATION_RETBLEED <<
2686 bool "Mitigate RETBleed hardware bug" <<
2687 depends on (CPU_SUP_INTEL && MITIGATI <<
2688 default y <<
2689 help <<
2690 Enable mitigation for RETBleed (Arb <<
2691 with Return Instructions) vulnerabi <<
2692 execution attack which takes advant <<
2693 in many modern microprocessors, sim <<
2694 unprivileged attacker can use these <<
2695 memory security restrictions to gai <<
2696 that would otherwise be inaccessibl <<
2697 2790
2698 config MITIGATION_SPECTRE_V1 !! 2791 People using multiprocessor machines who say Y here should also say
2699 bool "Mitigate SPECTRE V1 hardware bu !! 2792 Y to "Enhanced Real Time Clock Support", below.
2700 default y <<
2701 help <<
2702 Enable mitigation for Spectre V1 (B <<
2703 class of side channel attacks that <<
2704 execution that bypasses conditional <<
2705 memory access bounds check. <<
2706 See also <file:Documentation/admin- <<
2707 2793
2708 config MITIGATION_SPECTRE_V2 !! 2794 See also the SMP-HOWTO available at
2709 bool "Mitigate SPECTRE V2 hardware bu !! 2795 <https://www.tldp.org/docs.html#howto>.
2710 default y <<
2711 help <<
2712 Enable mitigation for Spectre V2 (B <<
2713 V2 is a class of side channel attac <<
2714 indirect branch predictors inside t <<
2715 attacks, the attacker can steer spe <<
2716 victim to gadget code by poisoning <<
2717 used for predicting indirect branch <<
2718 See also <file:Documentation/admin- <<
2719 <<
2720 config MITIGATION_SRBDS <<
2721 bool "Mitigate Special Register Buffe <<
2722 depends on CPU_SUP_INTEL <<
2723 default y <<
2724 help <<
2725 Enable mitigation for Special Regis <<
2726 SRBDS is a hardware vulnerability t <<
2727 Sampling (MDS) techniques to infer <<
2728 register accesses. An unprivileged <<
2729 from RDRAND and RDSEED executed on <<
2730 using MDS techniques. <<
2731 See also <<
2732 <file:Documentation/admin-guide/hw- <<
2733 2796
2734 config MITIGATION_SSB !! 2797 If you don't know what to do here, say N.
2735 bool "Mitigate Speculative Store Bypa !! 2798
2736 default y !! 2799 config HOTPLUG_CPU
>> 2800 bool "Support for hot-pluggable CPUs"
>> 2801 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
2737 help 2802 help
2738 Enable mitigation for Speculative S !! 2803 Say Y here to allow turning CPUs off and on. CPUs can be
2739 hardware security vulnerability and !! 2804 controlled through /sys/devices/system/cpu.
2740 of speculative execution in a simil !! 2805 (Note: power management support will enable this option
2741 security vulnerabilities. !! 2806 automatically on SMP systems. )
>> 2807 Say N if you want to disable CPU hotplug.
2742 2808
2743 endif !! 2809 config SMP_UP
>> 2810 bool
2744 2811
2745 config ARCH_HAS_ADD_PAGES !! 2812 config SYS_SUPPORTS_MIPS_CMP
2746 def_bool y !! 2813 bool
2747 depends on ARCH_ENABLE_MEMORY_HOTPLUG <<
2748 2814
2749 menu "Power management and ACPI options" !! 2815 config SYS_SUPPORTS_MIPS_CPS
>> 2816 bool
2750 2817
2751 config ARCH_HIBERNATION_HEADER !! 2818 config SYS_SUPPORTS_SMP
2752 def_bool y !! 2819 bool
2753 depends on HIBERNATION <<
2754 2820
2755 source "kernel/power/Kconfig" !! 2821 config NR_CPUS_DEFAULT_4
>> 2822 bool
2756 2823
2757 source "drivers/acpi/Kconfig" !! 2824 config NR_CPUS_DEFAULT_8
>> 2825 bool
2758 2826
2759 config X86_APM_BOOT !! 2827 config NR_CPUS_DEFAULT_16
2760 def_bool y !! 2828 bool
2761 depends on APM <<
2762 2829
2763 menuconfig APM !! 2830 config NR_CPUS_DEFAULT_32
2764 tristate "APM (Advanced Power Managem !! 2831 bool
2765 depends on X86_32 && PM_SLEEP <<
2766 help <<
2767 APM is a BIOS specification for sav <<
2768 techniques. This is mostly useful f <<
2769 APM compliant BIOSes. If you say Y <<
2770 reset after a RESUME operation, the <<
2771 battery status information, and use <<
2772 notification of APM "events" (e.g. <<
2773 <<
2774 If you select "Y" here, you can dis <<
2775 BIOS by passing the "apm=off" optio <<
2776 <<
2777 Note that the APM support is almost <<
2778 machines with more than one CPU. <<
2779 <<
2780 In order to use APM, you will need <<
2781 and more information, read <file:Do <<
2782 and the Battery Powered Linux mini- <<
2783 <http://www.tldp.org/docs.html#howt <<
2784 <<
2785 This driver does not spin down disk <<
2786 manpage ("man 8 hdparm") for that), <<
2787 VESA-compliant "green" monitors. <<
2788 <<
2789 This driver does not support the TI <<
2790 486/DX4/75 because they don't have <<
2791 desktop machines also don't have co <<
2792 may cause those machines to panic d <<
2793 <<
2794 Generally, if you don't have a batt <<
2795 much point in using this driver and <<
2796 random kernel OOPSes or reboots tha <<
2797 anything, try disabling/enabling th <<
2798 APM in your BIOS). <<
2799 <<
2800 Some other things you should try wh <<
2801 "weird" problems: <<
2802 <<
2803 1) make sure that you have enough s <<
2804 enabled. <<
2805 2) pass the "idle=poll" option to t <<
2806 3) switch on floating point emulati <<
2807 the "no387" option to the kernel <<
2808 4) pass the "floppy=nodma" option t <<
2809 5) pass the "mem=4M" option to the <<
2810 all but the first 4 MB of RAM) <<
2811 6) make sure that the CPU is not ov <<
2812 7) read the sig11 FAQ at <http://ww <<
2813 8) disable the cache from your BIOS <<
2814 9) install a fan for the video card <<
2815 10) install a better fan for the CP <<
2816 11) exchange RAM chips <<
2817 12) exchange the motherboard. <<
2818 <<
2819 To compile this driver as a module, <<
2820 module will be called apm. <<
2821 <<
2822 if APM <<
2823 <<
2824 config APM_IGNORE_USER_SUSPEND <<
2825 bool "Ignore USER SUSPEND" <<
2826 help <<
2827 This option will ignore USER SUSPEN <<
2828 compliant APM BIOS, you want to say <<
2829 series notebooks, it is necessary t <<
2830 <<
2831 config APM_DO_ENABLE <<
2832 bool "Enable PM at boot time" <<
2833 help <<
2834 Enable APM features at boot time. F <<
2835 specification: "When disabled, the <<
2836 power manage devices, enter the Sta <<
2837 State, or take power saving steps i <<
2838 This driver will make CPU Idle call <<
2839 feature is turned off -- see "Do CP <<
2840 should always save battery power, b <<
2841 will be dependent on your BIOS impl <<
2842 this option off if your computer ha <<
2843 support, or if it beeps continuousl <<
2844 this off if you have a NEC UltraLit <<
2845 T400CDT. This is off by default sin <<
2846 this feature. <<
2847 <<
2848 config APM_CPU_IDLE <<
2849 depends on CPU_IDLE <<
2850 bool "Make CPU Idle calls when idle" <<
2851 help <<
2852 Enable calls to APM CPU Idle/CPU Bu <<
2853 On some machines, this can activate <<
2854 a slowed CPU clock rate, when the m <<
2855 are made after the idle loop has ru <<
2856 333 mS). On some machines, this wil <<
2857 whenever the CPU becomes idle. (On <<
2858 this option does nothing.) <<
2859 <<
2860 config APM_DISPLAY_BLANK <<
2861 bool "Enable console blanking using A <<
2862 help <<
2863 Enable console blanking using the A <<
2864 turn off the LCD backlight when the <<
2865 virtual console blanks the screen. <<
2866 the virtual console screen blanker, <<
2867 when using the X Window system. Thi <<
2868 do with your VESA-compliant power-s <<
2869 option doesn't work for all laptops <<
2870 backlight at all, or it might print <<
2871 especially if you are using gpm. <<
2872 <<
2873 config APM_ALLOW_INTS <<
2874 bool "Allow interrupts during APM BIO <<
2875 help <<
2876 Normally we disable external interr <<
2877 the APM BIOS as a measure to lessen <<
2878 BIOS implementation. The BIOS shou <<
2879 needs to. Unfortunately, some BIOS <<
2880 many of the newer IBM Thinkpads. I <<
2881 suspend, try setting this to Y. Ot <<
2882 2832
2883 endif # APM !! 2833 config NR_CPUS_DEFAULT_64
>> 2834 bool
2884 2835
2885 source "drivers/cpufreq/Kconfig" !! 2836 config NR_CPUS
>> 2837 int "Maximum number of CPUs (2-256)"
>> 2838 range 2 256
>> 2839 depends on SMP
>> 2840 default "4" if NR_CPUS_DEFAULT_4
>> 2841 default "8" if NR_CPUS_DEFAULT_8
>> 2842 default "16" if NR_CPUS_DEFAULT_16
>> 2843 default "32" if NR_CPUS_DEFAULT_32
>> 2844 default "64" if NR_CPUS_DEFAULT_64
>> 2845 help
>> 2846 This allows you to specify the maximum number of CPUs which this
>> 2847 kernel will support. The maximum supported value is 32 for 32-bit
>> 2848 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2849 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2850 and 2 for all others.
>> 2851
>> 2852 This is purely to save memory - each supported CPU adds
>> 2853 approximately eight kilobytes to the kernel image. For best
>> 2854 performance should round up your number of processors to the next
>> 2855 power of two.
2886 2856
2887 source "drivers/cpuidle/Kconfig" !! 2857 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2858 bool
2888 2859
2889 source "drivers/idle/Kconfig" !! 2860 config MIPS_NR_CPU_NR_MAP_1024
>> 2861 bool
2890 2862
2891 endmenu !! 2863 config MIPS_NR_CPU_NR_MAP
>> 2864 int
>> 2865 depends on SMP
>> 2866 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2867 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2892 2868
2893 menu "Bus options (PCI etc.)" !! 2869 #
>> 2870 # Timer Interrupt Frequency Configuration
>> 2871 #
2894 2872
2895 choice 2873 choice
2896 prompt "PCI access mode" !! 2874 prompt "Timer frequency"
2897 depends on X86_32 && PCI !! 2875 default HZ_250
2898 default PCI_GOANY !! 2876 help
2899 help !! 2877 Allows the configuration of the timer frequency.
2900 On PCI systems, the BIOS can be use !! 2878
2901 determine their configuration. Howe !! 2879 config HZ_24
2902 have BIOS bugs and may crash if thi !! 2880 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2903 PCI-based systems don't have any BI !! 2881
2904 detect the PCI hardware directly wi !! 2882 config HZ_48
2905 !! 2883 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2906 With this option, you can specify h !! 2884
2907 PCI devices. If you choose "BIOS", !! 2885 config HZ_100
2908 if you choose "Direct", the BIOS wo !! 2886 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2909 choose "MMConfig", then PCI Express !! 2887
2910 If you choose "Any", the kernel wil !! 2888 config HZ_128
2911 direct access method and falls back !! 2889 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2912 work. If unsure, go with the defaul !! 2890
2913 !! 2891 config HZ_250
2914 config PCI_GOBIOS !! 2892 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2915 bool "BIOS" <<
2916 <<
2917 config PCI_GOMMCONFIG <<
2918 bool "MMConfig" <<
2919 <<
2920 config PCI_GODIRECT <<
2921 bool "Direct" <<
2922 <<
2923 config PCI_GOOLPC <<
2924 bool "OLPC XO-1" <<
2925 depends on OLPC <<
2926 2893
2927 config PCI_GOANY !! 2894 config HZ_256
2928 bool "Any" !! 2895 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2896
>> 2897 config HZ_1000
>> 2898 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2899
>> 2900 config HZ_1024
>> 2901 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2929 2902
2930 endchoice 2903 endchoice
2931 2904
2932 config PCI_BIOS !! 2905 config SYS_SUPPORTS_24HZ
2933 def_bool y !! 2906 bool
2934 depends on X86_32 && PCI && (PCI_GOBI <<
2935 2907
2936 # x86-64 doesn't support PCI BIOS access from !! 2908 config SYS_SUPPORTS_48HZ
2937 config PCI_DIRECT !! 2909 bool
2938 def_bool y <<
2939 depends on PCI && (X86_64 || (PCI_GOD <<
2940 2910
2941 config PCI_MMCONFIG !! 2911 config SYS_SUPPORTS_100HZ
2942 bool "Support mmconfig PCI config spa !! 2912 bool
2943 default y <<
2944 depends on PCI && (ACPI || JAILHOUSE_ <<
2945 depends on X86_64 || (PCI_GOANY || PC <<
2946 2913
2947 config PCI_OLPC !! 2914 config SYS_SUPPORTS_128HZ
2948 def_bool y !! 2915 bool
2949 depends on PCI && OLPC && (PCI_GOOLPC <<
2950 2916
2951 config PCI_XEN !! 2917 config SYS_SUPPORTS_250HZ
2952 def_bool y !! 2918 bool
2953 depends on PCI && XEN <<
2954 2919
2955 config MMCONF_FAM10H !! 2920 config SYS_SUPPORTS_256HZ
2956 def_bool y !! 2921 bool
2957 depends on X86_64 && PCI_MMCONFIG && <<
2958 2922
2959 config PCI_CNB20LE_QUIRK !! 2923 config SYS_SUPPORTS_1000HZ
2960 bool "Read CNB20LE Host Bridge Window !! 2924 bool
2961 depends on PCI <<
2962 help <<
2963 Read the PCI windows out of the CNB <<
2964 PCI hotplug to work on systems with <<
2965 not have ACPI. <<
2966 2925
2967 There's no public spec for this chi !! 2926 config SYS_SUPPORTS_1024HZ
2968 is known to be incomplete. !! 2927 bool
2969 2928
2970 You should say N unless you know yo !! 2929 config SYS_SUPPORTS_ARBIT_HZ
>> 2930 bool
>> 2931 default y if !SYS_SUPPORTS_24HZ && \
>> 2932 !SYS_SUPPORTS_48HZ && \
>> 2933 !SYS_SUPPORTS_100HZ && \
>> 2934 !SYS_SUPPORTS_128HZ && \
>> 2935 !SYS_SUPPORTS_250HZ && \
>> 2936 !SYS_SUPPORTS_256HZ && \
>> 2937 !SYS_SUPPORTS_1000HZ && \
>> 2938 !SYS_SUPPORTS_1024HZ
2971 2939
2972 config ISA_BUS !! 2940 config HZ
2973 bool "ISA bus support on modern syste !! 2941 int
2974 help !! 2942 default 24 if HZ_24
2975 Expose ISA bus device drivers and o !! 2943 default 48 if HZ_48
2976 configuration. Enable this option i !! 2944 default 100 if HZ_100
2977 bus. ISA is an older system, displa !! 2945 default 128 if HZ_128
2978 architectures -- if your target mac !! 2946 default 250 if HZ_250
2979 not have an ISA bus. !! 2947 default 256 if HZ_256
>> 2948 default 1000 if HZ_1000
>> 2949 default 1024 if HZ_1024
>> 2950
>> 2951 config SCHED_HRTICK
>> 2952 def_bool HIGH_RES_TIMERS
>> 2953
>> 2954 config KEXEC
>> 2955 bool "Kexec system call"
>> 2956 select KEXEC_CORE
>> 2957 help
>> 2958 kexec is a system call that implements the ability to shutdown your
>> 2959 current kernel, and to start another kernel. It is like a reboot
>> 2960 but it is independent of the system firmware. And like a reboot
>> 2961 you can start any kernel with it, not just Linux.
>> 2962
>> 2963 The name comes from the similarity to the exec system call.
>> 2964
>> 2965 It is an ongoing process to be certain the hardware in a machine
>> 2966 is properly shutdown, so do not be surprised if this code does not
>> 2967 initially work for you. As of this writing the exact hardware
>> 2968 interface is strongly in flux, so no good recommendation can be
>> 2969 made.
>> 2970
>> 2971 config CRASH_DUMP
>> 2972 bool "Kernel crash dumps"
>> 2973 help
>> 2974 Generate crash dump after being started by kexec.
>> 2975 This should be normally only set in special crash dump kernels
>> 2976 which are loaded in the main kernel with kexec-tools into
>> 2977 a specially reserved region and then later executed after
>> 2978 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2979 to a memory address not used by the main kernel or firmware using
>> 2980 PHYSICAL_START.
>> 2981
>> 2982 config PHYSICAL_START
>> 2983 hex "Physical address where the kernel is loaded"
>> 2984 default "0xffffffff84000000"
>> 2985 depends on CRASH_DUMP
>> 2986 help
>> 2987 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2988 If you plan to use kernel for capturing the crash dump change
>> 2989 this value to start of the reserved region (the "X" value as
>> 2990 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2991 passed to the panic-ed kernel).
>> 2992
>> 2993 config MIPS_O32_FP64_SUPPORT
>> 2994 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2995 depends on 32BIT || MIPS32_O32
>> 2996 help
>> 2997 When this is enabled, the kernel will support use of 64-bit floating
>> 2998 point registers with binaries using the O32 ABI along with the
>> 2999 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3000 32-bit MIPS systems this support is at the cost of increasing the
>> 3001 size and complexity of the compiled FPU emulator. Thus if you are
>> 3002 running a MIPS32 system and know that none of your userland binaries
>> 3003 will require 64-bit floating point, you may wish to reduce the size
>> 3004 of your kernel & potentially improve FP emulation performance by
>> 3005 saying N here.
>> 3006
>> 3007 Although binutils currently supports use of this flag the details
>> 3008 concerning its effect upon the O32 ABI in userland are still being
>> 3009 worked on. In order to avoid userland becoming dependent upon current
>> 3010 behaviour before the details have been finalised, this option should
>> 3011 be considered experimental and only enabled by those working upon
>> 3012 said details.
2980 3013
2981 If unsure, say N. 3014 If unsure, say N.
2982 3015
2983 # x86_64 have no ISA slots, but can have ISA- !! 3016 config USE_OF
2984 config ISA_DMA_API !! 3017 bool
2985 bool "ISA-style DMA support" if (X86_ !! 3018 select OF
2986 default y !! 3019 select OF_EARLY_FLATTREE
2987 help !! 3020 select IRQ_DOMAIN
2988 Enables ISA-style DMA support for d <<
2989 If unsure, say Y. <<
2990 3021
2991 if X86_32 !! 3022 config UHI_BOOT
>> 3023 bool
2992 3024
2993 config ISA !! 3025 config BUILTIN_DTB
2994 bool "ISA support" !! 3026 bool
2995 help !! 3027
2996 Find out whether you have ISA slots !! 3028 choice
2997 name of a bus system, i.e. the way !! 3029 prompt "Kernel appended dtb support" if USE_OF
2998 inside your box. Other bus systems !! 3030 default MIPS_NO_APPENDED_DTB
2999 (MCA) or VESA. ISA is an older sys !! 3031
3000 newer boards don't support it. If !! 3032 config MIPS_NO_APPENDED_DTB
3001 !! 3033 bool "None"
3002 config SCx200 !! 3034 help
3003 tristate "NatSemi SCx200 support" !! 3035 Do not enable appended dtb support.
3004 help !! 3036
3005 This provides basic support for Nat !! 3037 config MIPS_ELF_APPENDED_DTB
3006 (now AMD's) Geode processors. The !! 3038 bool "vmlinux"
3007 PCI-IDs of several on-chip devices, !! 3039 help
3008 for other scx200_* drivers. !! 3040 With this option, the boot code will look for a device tree binary
3009 !! 3041 DTB) included in the vmlinux ELF section .appended_dtb. By default
3010 If compiled as a module, the driver !! 3042 it is empty and the DTB can be appended using binutils command
3011 !! 3043 objcopy:
3012 config SCx200HR_TIMER !! 3044
3013 tristate "NatSemi SCx200 27MHz High-R !! 3045 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
3014 depends on SCx200 !! 3046
>> 3047 This is meant as a backward compatibility convenience for those
>> 3048 systems with a bootloader that can't be upgraded to accommodate
>> 3049 the documented boot protocol using a device tree.
>> 3050
>> 3051 config MIPS_RAW_APPENDED_DTB
>> 3052 bool "vmlinux.bin or vmlinuz.bin"
>> 3053 help
>> 3054 With this option, the boot code will look for a device tree binary
>> 3055 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3056 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3057
>> 3058 This is meant as a backward compatibility convenience for those
>> 3059 systems with a bootloader that can't be upgraded to accommodate
>> 3060 the documented boot protocol using a device tree.
>> 3061
>> 3062 Beware that there is very little in terms of protection against
>> 3063 this option being confused by leftover garbage in memory that might
>> 3064 look like a DTB header after a reboot if no actual DTB is appended
>> 3065 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3066 if you don't intend to always append a DTB.
>> 3067 endchoice
>> 3068
>> 3069 choice
>> 3070 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 3071 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3072 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3073 !CAVIUM_OCTEON_SOC
>> 3074 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3075
>> 3076 config MIPS_CMDLINE_FROM_DTB
>> 3077 depends on USE_OF
>> 3078 bool "Dtb kernel arguments if available"
>> 3079
>> 3080 config MIPS_CMDLINE_DTB_EXTEND
>> 3081 depends on USE_OF
>> 3082 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3083
>> 3084 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3085 bool "Bootloader kernel arguments if available"
>> 3086
>> 3087 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3088 depends on CMDLINE_BOOL
>> 3089 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3090 endchoice
>> 3091
>> 3092 endmenu
>> 3093
>> 3094 config LOCKDEP_SUPPORT
>> 3095 bool
3015 default y 3096 default y
3016 help <<
3017 This driver provides a clocksource <<
3018 27MHz high-resolution timer. Its a <<
3019 NSC Geode SC-1100's buggy TSC, whic <<
3020 processor goes idle (as is done by <<
3021 other workaround is idle=poll boot <<
3022 <<
3023 config OLPC <<
3024 bool "One Laptop Per Child support" <<
3025 depends on !X86_PAE <<
3026 select GPIOLIB <<
3027 select OF <<
3028 select OF_PROMTREE <<
3029 select IRQ_DOMAIN <<
3030 select OLPC_EC <<
3031 help <<
3032 Add support for detecting the uniqu <<
3033 XO hardware. <<
3034 3097
3035 config OLPC_XO1_PM !! 3098 config STACKTRACE_SUPPORT
3036 bool "OLPC XO-1 Power Management" !! 3099 bool
3037 depends on OLPC && MFD_CS5535=y && PM !! 3100 default y
3038 help <<
3039 Add support for poweroff and suspen <<
3040 3101
3041 config OLPC_XO1_RTC !! 3102 config PGTABLE_LEVELS
3042 bool "OLPC XO-1 Real Time Clock" !! 3103 int
3043 depends on OLPC_XO1_PM && RTC_DRV_CMO !! 3104 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
3044 help !! 3105 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
3045 Add support for the XO-1 real time !! 3106 default 2
3046 programmable wakeup source. <<
3047 3107
3048 config OLPC_XO1_SCI !! 3108 config MIPS_AUTO_PFN_OFFSET
3049 bool "OLPC XO-1 SCI extras" !! 3109 bool
3050 depends on OLPC && OLPC_XO1_PM && GPI <<
3051 depends on INPUT=y <<
3052 select POWER_SUPPLY <<
3053 help <<
3054 Add support for SCI-based features <<
3055 - EC-driven system wakeups <<
3056 - Power button <<
3057 - Ebook switch <<
3058 - Lid switch <<
3059 - AC adapter status updates <<
3060 - Battery status updates <<
3061 3110
3062 config OLPC_XO15_SCI !! 3111 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
3063 bool "OLPC XO-1.5 SCI extras" <<
3064 depends on OLPC && ACPI <<
3065 select POWER_SUPPLY <<
3066 help <<
3067 Add support for SCI-based features <<
3068 - EC-driven system wakeups <<
3069 - AC adapter status updates <<
3070 - Battery status updates <<
3071 3112
3072 config GEODE_COMMON !! 3113 config PCI_DRIVERS_GENERIC
>> 3114 select PCI_DOMAINS_GENERIC if PCI
3073 bool 3115 bool
3074 3116
3075 config ALIX !! 3117 config PCI_DRIVERS_LEGACY
3076 bool "PCEngines ALIX System Support ( !! 3118 def_bool !PCI_DRIVERS_GENERIC
3077 select GPIOLIB !! 3119 select NO_GENERIC_PCI_IOPORT_MAP
3078 select GEODE_COMMON !! 3120 select PCI_DOMAINS if PCI
3079 help <<
3080 This option enables system support <<
3081 At present this just sets up LEDs f <<
3082 ALIX2/3/6 boards. However, other s <<
3083 get added here. <<
3084 3121
3085 Note: You must still enable the dri !! 3122 #
3086 (GPIO_CS5535 & LEDS_GPIO) to actual !! 3123 # ISA support is now enabled via select. Too many systems still have the one
>> 3124 # or other ISA chip on the board that users don't know about so don't expect
>> 3125 # users to choose the right thing ...
>> 3126 #
>> 3127 config ISA
>> 3128 bool
3087 3129
3088 Note: You have to set alix.force=1 !! 3130 config TC
>> 3131 bool "TURBOchannel support"
>> 3132 depends on MACH_DECSTATION
>> 3133 help
>> 3134 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3135 processors. TURBOchannel programming specifications are available
>> 3136 at:
>> 3137 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3138 and:
>> 3139 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3140 Linux driver support status is documented at:
>> 3141 <http://www.linux-mips.org/wiki/DECstation>
3089 3142
3090 config NET5501 !! 3143 config MMU
3091 bool "Soekris Engineering net5501 Sys !! 3144 bool
3092 select GPIOLIB !! 3145 default y
3093 select GEODE_COMMON <<
3094 help <<
3095 This option enables system support <<
3096 3146
3097 config GEOS !! 3147 config ARCH_MMAP_RND_BITS_MIN
3098 bool "Traverse Technologies GEOS Syst !! 3148 default 12 if 64BIT
3099 select GPIOLIB !! 3149 default 8
3100 select GEODE_COMMON <<
3101 depends on DMI <<
3102 help <<
3103 This option enables system support <<
3104 3150
3105 config TS5500 !! 3151 config ARCH_MMAP_RND_BITS_MAX
3106 bool "Technologic Systems TS-5500 pla !! 3152 default 18 if 64BIT
3107 depends on MELAN !! 3153 default 15
3108 select CHECK_SIGNATURE <<
3109 select NEW_LEDS <<
3110 select LEDS_CLASS <<
3111 help <<
3112 This option enables system support <<
3113 3154
3114 endif # X86_32 !! 3155 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3156 default 8
3115 3157
3116 config AMD_NB !! 3158 config ARCH_MMAP_RND_COMPAT_BITS_MAX
3117 def_bool y !! 3159 default 15
3118 depends on CPU_SUP_AMD && PCI <<
3119 3160
>> 3161 config I8253
>> 3162 bool
>> 3163 select CLKSRC_I8253
>> 3164 select CLKEVT_I8253
>> 3165 select MIPS_EXTERNAL_TIMER
3120 endmenu 3166 endmenu
3121 3167
3122 menu "Binary Emulations" !! 3168 config TRAD_SIGNALS
>> 3169 bool
3123 3170
3124 config IA32_EMULATION !! 3171 config MIPS32_COMPAT
3125 bool "IA32 Emulation" !! 3172 bool
3126 depends on X86_64 !! 3173
>> 3174 config COMPAT
>> 3175 bool
>> 3176
>> 3177 config MIPS32_O32
>> 3178 bool "Kernel support for o32 binaries"
>> 3179 depends on 64BIT
3127 select ARCH_WANT_OLD_COMPAT_IPC 3180 select ARCH_WANT_OLD_COMPAT_IPC
3128 select BINFMT_ELF !! 3181 select COMPAT
3129 select COMPAT_OLD_SIGACTION !! 3182 select MIPS32_COMPAT
3130 help 3183 help
3131 Include code to run legacy 32-bit p !! 3184 Select this option if you want to run o32 binaries. These are pure
3132 64-bit kernel. You should likely tu !! 3185 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3133 100% sure that you don't have any 3 !! 3186 existing binaries are in this format.
3134 3187
3135 config IA32_EMULATION_DEFAULT_DISABLED !! 3188 If unsure, say Y.
3136 bool "IA32 emulation disabled by defa !! 3189
3137 default n !! 3190 config MIPS32_N32
3138 depends on IA32_EMULATION !! 3191 bool "Kernel support for n32 binaries"
3139 help !! 3192 depends on 64BIT
3140 Make IA32 emulation disabled by def !! 3193 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
3141 processes and access to 32-bit sysc !! 3194 select COMPAT
3142 default value. !! 3195 select MIPS32_COMPAT
3143 !! 3196 help
3144 config X86_X32_ABI !! 3197 Select this option if you want to run n32 binaries. These are
3145 bool "x32 ABI for 64-bit mode" !! 3198 64-bit binaries using 32-bit quantities for addressing and certain
3146 depends on X86_64 !! 3199 data that would normally be 64-bit. They are used in special
3147 # llvm-objcopy does not convert x86_6 !! 3200 cases.
3148 # compressed debug sections to x86_x3 <<
3149 # https://github.com/ClangBuiltLinux/ <<
3150 # https://github.com/ClangBuiltLinux/ <<
3151 depends on $(success,$(OBJCOPY) --ver <<
3152 help <<
3153 Include code to run binaries for th <<
3154 for 64-bit processors. An x32 proc <<
3155 full 64-bit register file and wide <<
3156 pointers at 32 bits for smaller mem <<
3157 3201
3158 config COMPAT_32 !! 3202 If unsure, say N.
>> 3203
>> 3204 config CC_HAS_MNO_BRANCH_LIKELY
3159 def_bool y 3205 def_bool y
3160 depends on IA32_EMULATION || X86_32 !! 3206 depends on $(cc-option,-mno-branch-likely)
3161 select HAVE_UID16 <<
3162 select OLD_SIGSUSPEND3 <<
3163 3207
3164 config COMPAT !! 3208 menu "Power management options"
>> 3209
>> 3210 config ARCH_HIBERNATION_POSSIBLE
3165 def_bool y 3211 def_bool y
3166 depends on IA32_EMULATION || X86_X32_ !! 3212 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3167 3213
3168 config COMPAT_FOR_U64_ALIGNMENT !! 3214 config ARCH_SUSPEND_POSSIBLE
3169 def_bool y 3215 def_bool y
3170 depends on COMPAT !! 3216 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3217
>> 3218 source "kernel/power/Kconfig"
3171 3219
3172 endmenu 3220 endmenu
3173 3221
3174 config HAVE_ATOMIC_IOMAP !! 3222 config MIPS_EXTERNAL_TIMER
3175 def_bool y !! 3223 bool
3176 depends on X86_32 !! 3224
>> 3225 menu "CPU Power Management"
>> 3226
>> 3227 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3228 source "drivers/cpufreq/Kconfig"
>> 3229 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3230
>> 3231 source "drivers/cpuidle/Kconfig"
>> 3232
>> 3233 endmenu
3177 3234
3178 source "arch/x86/kvm/Kconfig" !! 3235 source "arch/mips/kvm/Kconfig"
3179 3236
3180 source "arch/x86/Kconfig.assembler" !! 3237 source "arch/mips/vdso/Kconfig"
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