1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 # Select 32 or 64 bit !! 2 config MIPS
3 config 64BIT !! 3 bool
4 bool "64-bit kernel" if "$(ARCH)" = "x !! 4 default y
5 default "$(ARCH)" != "i386" !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 help !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 Say yes to build a 64-bit kernel - f !! 7 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
8 Say no to build a 32-bit kernel - fo !! 8 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
9 <<
10 config X86_32 <<
11 def_bool y <<
12 depends on !64BIT <<
13 # Options that are inherently 32-bit k <<
14 select ARCH_WANT_IPC_PARSE_VERSION <<
15 select CLKSRC_I8253 <<
16 select CLONE_BACKWARDS <<
17 select GENERIC_VDSO_32 <<
18 select HAVE_DEBUG_STACKOVERFLOW <<
19 select KMAP_LOCAL <<
20 select MODULES_USE_ELF_REL <<
21 select OLD_SIGACTION <<
22 select ARCH_SPLIT_ARG64 <<
23 <<
24 config X86_64 <<
25 def_bool y <<
26 depends on 64BIT <<
27 # Options that are inherently 64-bit k <<
28 select ARCH_HAS_GIGANTIC_PAGE <<
29 select ARCH_SUPPORTS_INT128 if CC_HAS_ <<
30 select ARCH_SUPPORTS_PER_VMA_LOCK <<
31 select ARCH_SUPPORTS_HUGE_PFNMAP if TR <<
32 select HAVE_ARCH_SOFT_DIRTY <<
33 select MODULES_USE_ELF_RELA <<
34 select NEED_DMA_MAP_STATE <<
35 select SWIOTLB <<
36 select ARCH_HAS_ELFCORE_COMPAT <<
37 select ZONE_DMA32 <<
38 select EXECMEM if DYNAMIC_FTRACE <<
39 <<
40 config FORCE_DYNAMIC_FTRACE <<
41 def_bool y <<
42 depends on X86_32 <<
43 depends on FUNCTION_TRACER <<
44 select DYNAMIC_FTRACE <<
45 help <<
46 We keep the static function tracing <<
47 in order to test the non static func <<
48 generic code, as other architectures <<
49 only need to keep it around for x86_ <<
50 for x86_32. For x86_32, force DYNAMI <<
51 # <<
52 # Arch settings <<
53 # <<
54 # ( Note that options that are marked 'if X86_ <<
55 # ported to 32-bit as well. ) <<
56 # <<
57 config X86 <<
58 def_bool y <<
59 # <<
60 # Note: keep this list sorted alphabet <<
61 # <<
62 select ACPI_LEGACY_TABLES_LOOKUP <<
63 select ACPI_SYSTEM_POWER_STATES_SUPPOR <<
64 select ACPI_HOTPLUG_CPU <<
65 select ARCH_32BIT_OFF_T <<
66 select ARCH_CLOCKSOURCE_INIT <<
67 select ARCH_CONFIGURES_CPU_MITIGATIONS <<
68 select ARCH_CORRECT_STACKTRACE_ON_KRET <<
69 select ARCH_ENABLE_HUGEPAGE_MIGRATION <<
70 select ARCH_ENABLE_MEMORY_HOTPLUG if X <<
71 select ARCH_ENABLE_MEMORY_HOTREMOVE if <<
72 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if <<
73 select ARCH_ENABLE_THP_MIGRATION if X8 <<
74 select ARCH_HAS_ACPI_TABLE_UPGRADE <<
75 select ARCH_HAS_CACHE_LINE_SIZE <<
76 select ARCH_HAS_CPU_CACHE_INVALIDATE_M <<
77 select ARCH_HAS_CPU_FINALIZE_INIT <<
78 select ARCH_HAS_CPU_PASID <<
79 select ARCH_HAS_CURRENT_STACK_POINTER <<
80 select ARCH_HAS_DEBUG_VIRTUAL <<
81 select ARCH_HAS_DEBUG_VM_PGTABLE <<
82 select ARCH_HAS_DEVMEM_IS_ALLOWED <<
83 select ARCH_HAS_DMA_OPS <<
84 select ARCH_HAS_EARLY_DEBUG <<
85 select ARCH_HAS_ELF_RANDOMIZE <<
86 select ARCH_HAS_FAST_MULTIPLIER <<
87 select ARCH_HAS_FORTIFY_SOURCE 9 select ARCH_HAS_FORTIFY_SOURCE
>> 10 select ARCH_HAS_KCOV
>> 11 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
>> 12 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
>> 13 select ARCH_HAS_STRNCPY_FROM_USER
>> 14 select ARCH_HAS_STRNLEN_USER
>> 15 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 16 select ARCH_HAS_UBSAN_SANITIZE_ALL
88 select ARCH_HAS_GCOV_PROFILE_ALL 17 select ARCH_HAS_GCOV_PROFILE_ALL
89 select ARCH_HAS_KCOV !! 18 select ARCH_KEEP_MEMBLOCK
90 select ARCH_HAS_KERNEL_FPU_SUPPORT !! 19 select ARCH_SUPPORTS_UPROBES
91 select ARCH_HAS_MEM_ENCRYPT <<
92 select ARCH_HAS_MEMBARRIER_SYNC_CORE <<
93 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS <<
94 select ARCH_HAS_NON_OVERLAPPING_ADDRES <<
95 select ARCH_HAS_PMEM_API <<
96 select ARCH_HAS_PTE_DEVMAP <<
97 select ARCH_HAS_PTE_SPECIAL <<
98 select ARCH_HAS_HW_PTE_YOUNG <<
99 select ARCH_HAS_NONLEAF_PMD_YOUNG <<
100 select ARCH_HAS_UACCESS_FLUSHCACHE <<
101 select ARCH_HAS_COPY_MC <<
102 select ARCH_HAS_SET_MEMORY <<
103 select ARCH_HAS_SET_DIRECT_MAP <<
104 select ARCH_HAS_STRICT_KERNEL_RWX <<
105 select ARCH_HAS_STRICT_MODULE_RWX <<
106 select ARCH_HAS_SYNC_CORE_BEFORE_USERM <<
107 select ARCH_HAS_SYSCALL_WRAPPER <<
108 select ARCH_HAS_UBSAN <<
109 select ARCH_HAS_DEBUG_WX <<
110 select ARCH_HAS_ZONE_DMA_SET if EXPERT <<
111 select ARCH_HAVE_NMI_SAFE_CMPXCHG <<
112 select ARCH_HAVE_EXTRA_ELF_NOTES <<
113 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABL <<
114 select ARCH_MIGHT_HAVE_ACPI_PDC <<
115 select ARCH_MIGHT_HAVE_PC_PARPORT <<
116 select ARCH_MIGHT_HAVE_PC_SERIO <<
117 select ARCH_STACKWALK <<
118 select ARCH_SUPPORTS_ACPI <<
119 select ARCH_SUPPORTS_ATOMIC_RMW <<
120 select ARCH_SUPPORTS_DEBUG_PAGEALLOC <<
121 select ARCH_SUPPORTS_PAGE_TABLE_CHECK <<
122 select ARCH_SUPPORTS_NUMA_BALANCING <<
123 select ARCH_SUPPORTS_KMAP_LOCAL_FORCE_ <<
124 select ARCH_SUPPORTS_CFI_CLANG <<
125 select ARCH_USES_CFI_TRAPS <<
126 select ARCH_SUPPORTS_LTO_CLANG <<
127 select ARCH_SUPPORTS_LTO_CLANG_THIN <<
128 select ARCH_SUPPORTS_RT <<
129 select ARCH_USE_BUILTIN_BSWAP 20 select ARCH_USE_BUILTIN_BSWAP
130 select ARCH_USE_CMPXCHG_LOCKREF !! 21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
131 select ARCH_USE_MEMTEST 22 select ARCH_USE_MEMTEST
132 select ARCH_USE_QUEUED_RWLOCKS 23 select ARCH_USE_QUEUED_RWLOCKS
133 select ARCH_USE_QUEUED_SPINLOCKS 24 select ARCH_USE_QUEUED_SPINLOCKS
134 select ARCH_USE_SYM_ANNOTATIONS !! 25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
135 select ARCH_WANT_BATCHED_UNMAP_TLB_FLU !! 26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
136 select ARCH_WANT_DEFAULT_BPF_JIT !! 27 select ARCH_WANT_IPC_PARSE_VERSION
137 select ARCH_WANTS_DYNAMIC_TASK_STRUCT <<
138 select ARCH_WANTS_NO_INSTR <<
139 select ARCH_WANT_GENERAL_HUGETLB <<
140 select ARCH_WANT_HUGE_PMD_SHARE <<
141 select ARCH_WANT_LD_ORPHAN_WARN 28 select ARCH_WANT_LD_ORPHAN_WARN
142 select ARCH_WANT_OPTIMIZE_DAX_VMEMMAP <<
143 select ARCH_WANT_OPTIMIZE_HUGETLB_VMEM <<
144 select ARCH_WANTS_THP_SWAP <<
145 select ARCH_HAS_PARANOID_L1D_FLUSH <<
146 select BUILDTIME_TABLE_SORT 29 select BUILDTIME_TABLE_SORT
147 select CLKEVT_I8253 !! 30 select CLONE_BACKWARDS
148 select CLOCKSOURCE_VALIDATE_LAST_CYCLE !! 31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
149 select CLOCKSOURCE_WATCHDOG !! 32 select CPU_PM if CPU_IDLE
150 # Word-size accesses may read uninitia !! 33 select GENERIC_ATOMIC64 if !64BIT
151 # in strings and cause false KMSAN rep <<
152 select DCACHE_WORD_ACCESS <<
153 select DYNAMIC_SIGFRAME <<
154 select EDAC_ATOMIC_SCRUB <<
155 select EDAC_SUPPORT <<
156 select GENERIC_CLOCKEVENTS_BROADCAST <<
157 select GENERIC_CLOCKEVENTS_BROADCAST_I <<
158 select GENERIC_CLOCKEVENTS_MIN_ADJUST <<
159 select GENERIC_CMOS_UPDATE 34 select GENERIC_CMOS_UPDATE
160 select GENERIC_CPU_AUTOPROBE 35 select GENERIC_CPU_AUTOPROBE
161 select GENERIC_CPU_DEVICES !! 36 select GENERIC_GETTIMEOFDAY
162 select GENERIC_CPU_VULNERABILITIES <<
163 select GENERIC_EARLY_IOREMAP <<
164 select GENERIC_ENTRY <<
165 select GENERIC_IOMAP 37 select GENERIC_IOMAP
166 select GENERIC_IRQ_EFFECTIVE_AFF_MASK <<
167 select GENERIC_IRQ_MATRIX_ALLOCATOR <<
168 select GENERIC_IRQ_MIGRATION <<
169 select GENERIC_IRQ_PROBE 38 select GENERIC_IRQ_PROBE
170 select GENERIC_IRQ_RESERVATION_MODE <<
171 select GENERIC_IRQ_SHOW 39 select GENERIC_IRQ_SHOW
172 select GENERIC_PENDING_IRQ !! 40 select GENERIC_ISA_DMA if EISA
173 select GENERIC_PTDUMP !! 41 select GENERIC_LIB_ASHLDI3
>> 42 select GENERIC_LIB_ASHRDI3
>> 43 select GENERIC_LIB_CMPDI2
>> 44 select GENERIC_LIB_LSHRDI3
>> 45 select GENERIC_LIB_UCMPDI2
>> 46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
174 select GENERIC_SMP_IDLE_THREAD 47 select GENERIC_SMP_IDLE_THREAD
175 select GENERIC_TIME_VSYSCALL 48 select GENERIC_TIME_VSYSCALL
176 select GENERIC_GETTIMEOFDAY !! 49 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
177 select GENERIC_VDSO_TIME_NS !! 50 select HAVE_ARCH_COMPILER_H
178 select GENERIC_VDSO_OVERFLOW_PROTECT <<
179 select GUP_GET_PXX_LOW_HIGH <<
180 select HARDIRQS_SW_RESEND <<
181 select HARDLOCKUP_CHECK_TIMESTAMP <<
182 select HAS_IOPORT <<
183 select HAVE_ACPI_APEI <<
184 select HAVE_ACPI_APEI_NMI <<
185 select HAVE_ALIGNED_STRUCT_PAGE <<
186 select HAVE_ARCH_AUDITSYSCALL <<
187 select HAVE_ARCH_HUGE_VMAP <<
188 select HAVE_ARCH_HUGE_VMALLOC <<
189 select HAVE_ARCH_JUMP_LABEL 51 select HAVE_ARCH_JUMP_LABEL
190 select HAVE_ARCH_JUMP_LABEL_RELATIVE !! 52 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
191 select HAVE_ARCH_KASAN !! 53 select HAVE_ARCH_MMAP_RND_BITS if MMU
192 select HAVE_ARCH_KASAN_VMALLOC !! 54 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
193 select HAVE_ARCH_KFENCE <<
194 select HAVE_ARCH_KMSAN <<
195 select HAVE_ARCH_KGDB <<
196 select HAVE_ARCH_MMAP_RND_BITS <<
197 select HAVE_ARCH_MMAP_RND_COMPAT_BITS <<
198 select HAVE_ARCH_COMPAT_MMAP_BASES <<
199 select HAVE_ARCH_PREL32_RELOCATIONS <<
200 select HAVE_ARCH_SECCOMP_FILTER 55 select HAVE_ARCH_SECCOMP_FILTER
201 select HAVE_ARCH_THREAD_STRUCT_WHITELI <<
202 select HAVE_ARCH_STACKLEAK <<
203 select HAVE_ARCH_TRACEHOOK 56 select HAVE_ARCH_TRACEHOOK
204 select HAVE_ARCH_TRANSPARENT_HUGEPAGE !! 57 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
205 select HAVE_ARCH_TRANSPARENT_HUGEPAGE_ <<
206 select HAVE_ARCH_USERFAULTFD_WP <<
207 select HAVE_ARCH_USERFAULTFD_MINOR <<
208 select HAVE_ARCH_VMAP_STACK <<
209 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFS <<
210 select HAVE_ARCH_WITHIN_STACK_FRAMES <<
211 select HAVE_ASM_MODVERSIONS 58 select HAVE_ASM_MODVERSIONS
212 select HAVE_CMPXCHG_DOUBLE !! 59 select HAVE_CONTEXT_TRACKING_USER
213 select HAVE_CMPXCHG_LOCAL !! 60 select HAVE_TIF_NOHZ
214 select HAVE_CONTEXT_TRACKING_USER <<
215 select HAVE_CONTEXT_TRACKING_USER_OFFS <<
216 select HAVE_C_RECORDMCOUNT 61 select HAVE_C_RECORDMCOUNT
217 select HAVE_OBJTOOL_MCOUNT <<
218 select HAVE_OBJTOOL_NOP_MCOUNT <<
219 select HAVE_BUILDTIME_MCOUNT_SORT <<
220 select HAVE_DEBUG_KMEMLEAK 62 select HAVE_DEBUG_KMEMLEAK
>> 63 select HAVE_DEBUG_STACKOVERFLOW
221 select HAVE_DMA_CONTIGUOUS 64 select HAVE_DMA_CONTIGUOUS
222 select HAVE_DYNAMIC_FTRACE 65 select HAVE_DYNAMIC_FTRACE
223 select HAVE_DYNAMIC_FTRACE_WITH_REGS !! 66 select HAVE_EBPF_JIT if !CPU_MICROMIPS && \
224 select HAVE_DYNAMIC_FTRACE_WITH_ARGS !! 67 !CPU_DADDI_WORKAROUNDS && \
225 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT !! 68 !CPU_R4000_WORKAROUNDS && \
226 select HAVE_SAMPLE_FTRACE_DIRECT !! 69 !CPU_R4400_WORKAROUNDS
227 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI <<
228 select HAVE_EBPF_JIT <<
229 select HAVE_EFFICIENT_UNALIGNED_ACCESS <<
230 select HAVE_EISA <<
231 select HAVE_EXIT_THREAD 70 select HAVE_EXIT_THREAD
232 select HAVE_GUP_FAST !! 71 select HAVE_FAST_GUP
233 select HAVE_FENTRY <<
234 select HAVE_FTRACE_MCOUNT_RECORD 72 select HAVE_FTRACE_MCOUNT_RECORD
235 select HAVE_FUNCTION_GRAPH_RETVAL !! 73 select HAVE_FUNCTION_GRAPH_TRACER
236 select HAVE_FUNCTION_GRAPH_TRACER <<
237 select HAVE_FUNCTION_TRACER 74 select HAVE_FUNCTION_TRACER
238 select HAVE_GCC_PLUGINS 75 select HAVE_GCC_PLUGINS
239 select HAVE_HW_BREAKPOINT !! 76 select HAVE_GENERIC_VDSO
240 select HAVE_IOREMAP_PROT 77 select HAVE_IOREMAP_PROT
241 select HAVE_IRQ_EXIT_ON_IRQ_STACK !! 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
242 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_IRQ_TIME_ACCOUNTING
243 select HAVE_JUMP_LABEL_HACK <<
244 select HAVE_KERNEL_BZIP2 <<
245 select HAVE_KERNEL_GZIP <<
246 select HAVE_KERNEL_LZ4 <<
247 select HAVE_KERNEL_LZMA <<
248 select HAVE_KERNEL_LZO <<
249 select HAVE_KERNEL_XZ <<
250 select HAVE_KERNEL_ZSTD <<
251 select HAVE_KPROBES 80 select HAVE_KPROBES
252 select HAVE_KPROBES_ON_FTRACE <<
253 select HAVE_FUNCTION_ERROR_INJECTION <<
254 select HAVE_KRETPROBES 81 select HAVE_KRETPROBES
255 select HAVE_RETHOOK !! 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
256 select HAVE_LIVEPATCH <<
257 select HAVE_MIXED_BREAKPOINTS_REGS <<
258 select HAVE_MOD_ARCH_SPECIFIC 83 select HAVE_MOD_ARCH_SPECIFIC
259 select HAVE_MOVE_PMD <<
260 select HAVE_MOVE_PUD <<
261 select HAVE_NOINSTR_HACK <<
262 select HAVE_NMI 84 select HAVE_NMI
263 select HAVE_NOINSTR_VALIDATION !! 85 select HAVE_PATA_PLATFORM
264 select HAVE_OBJTOOL <<
265 select HAVE_OPTPROBES <<
266 select HAVE_PAGE_SIZE_4KB <<
267 select HAVE_PCSPKR_PLATFORM <<
268 select HAVE_PERF_EVENTS 86 select HAVE_PERF_EVENTS
269 select HAVE_PERF_EVENTS_NMI <<
270 select HAVE_HARDLOCKUP_DETECTOR_PERF <<
271 select HAVE_PCI <<
272 select HAVE_PERF_REGS 87 select HAVE_PERF_REGS
273 select HAVE_PERF_USER_STACK_DUMP 88 select HAVE_PERF_USER_STACK_DUMP
274 select MMU_GATHER_RCU_TABLE_FREE <<
275 select MMU_GATHER_MERGE_VMAS <<
276 select HAVE_POSIX_CPU_TIMERS_TASK_WORK <<
277 select HAVE_REGS_AND_STACK_ACCESS_API 89 select HAVE_REGS_AND_STACK_ACCESS_API
278 select HAVE_RELIABLE_STACKTRACE <<
279 select HAVE_FUNCTION_ARG_ACCESS_API <<
280 select HAVE_SETUP_PER_CPU_AREA <<
281 select HAVE_SOFTIRQ_ON_OWN_STACK <<
282 select HAVE_STACKPROTECTOR <<
283 select HAVE_STACK_VALIDATION <<
284 select HAVE_STATIC_CALL <<
285 select HAVE_STATIC_CALL_INLINE <<
286 select HAVE_PREEMPT_DYNAMIC_CALL <<
287 select HAVE_RSEQ 90 select HAVE_RSEQ
288 select HAVE_RUST !! 91 select HAVE_SPARSE_SYSCALL_NR
>> 92 select HAVE_STACKPROTECTOR
289 select HAVE_SYSCALL_TRACEPOINTS 93 select HAVE_SYSCALL_TRACEPOINTS
290 select HAVE_UACCESS_VALIDATION !! 94 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
291 select HAVE_UNSTABLE_SCHED_CLOCK <<
292 select HAVE_USER_RETURN_NOTIFIER <<
293 select HAVE_GENERIC_VDSO <<
294 select VDSO_GETRANDOM <<
295 select HOTPLUG_PARALLEL <<
296 select HOTPLUG_SMT <<
297 select HOTPLUG_SPLIT_STARTUP <<
298 select IRQ_FORCED_THREADING 95 select IRQ_FORCED_THREADING
>> 96 select ISA if EISA
299 select LOCK_MM_AND_FIND_VMA 97 select LOCK_MM_AND_FIND_VMA
300 select NEED_PER_CPU_EMBED_FIRST_CHUNK !! 98 select MODULES_USE_ELF_REL if MODULES
301 select NEED_PER_CPU_PAGE_FIRST_CHUNK !! 99 select MODULES_USE_ELF_RELA if MODULES && 64BIT
302 select NEED_SG_DMA_LENGTH !! 100 select PERF_USE_VMALLOC
303 select NUMA_MEMBLKS !! 101 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
304 select PCI_DOMAINS <<
305 select PCI_LOCKLESS_CONFIG <<
306 select PERF_EVENTS <<
307 select RTC_LIB 102 select RTC_LIB
308 select RTC_MC146818_LIB <<
309 select SPARSE_IRQ <<
310 select SYSCTL_EXCEPTION_TRACE 103 select SYSCTL_EXCEPTION_TRACE
311 select THREAD_INFO_IN_TASK <<
312 select TRACE_IRQFLAGS_SUPPORT 104 select TRACE_IRQFLAGS_SUPPORT
313 select TRACE_IRQFLAGS_NMI_SUPPORT !! 105 select ARCH_HAS_ELFCORE_COMPAT
314 select USER_STACKTRACE_SUPPORT !! 106 select HAVE_ARCH_KCSAN if 64BIT
315 select HAVE_ARCH_KCSAN <<
316 select PROC_PID_ARCH_STATUS <<
317 select HAVE_ARCH_NODE_DEV_GROUP <<
318 select FUNCTION_ALIGNMENT_16B <<
319 select FUNCTION_ALIGNMENT_4B <<
320 imply IMA_SECURE_AND_OR_TRUSTED_BOOT <<
321 select HAVE_DYNAMIC_FTRACE_NO_PATCHABL <<
322 107
323 config INSTRUCTION_DECODER !! 108 config MIPS_FIXUP_BIGPHYS_ADDR
324 def_bool y !! 109 bool
325 depends on KPROBES || PERF_EVENTS || U <<
326 110
327 config OUTPUT_FORMAT !! 111 config MIPS_GENERIC
328 string !! 112 bool
329 default "elf32-i386" if X86_32 <<
330 default "elf64-x86-64" if X86_64 <<
331 113
332 config LOCKDEP_SUPPORT !! 114 config MACH_INGENIC
333 def_bool y !! 115 bool
>> 116 select SYS_SUPPORTS_32BIT_KERNEL
>> 117 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 118 select SYS_SUPPORTS_ZBOOT
>> 119 select DMA_NONCOHERENT
>> 120 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 121 select IRQ_MIPS_CPU
>> 122 select PINCTRL
>> 123 select GPIOLIB
>> 124 select COMMON_CLK
>> 125 select GENERIC_IRQ_CHIP
>> 126 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 127 select USE_OF
>> 128 select CPU_SUPPORTS_CPUFREQ
>> 129 select MIPS_EXTERNAL_TIMER
334 130
335 config STACKTRACE_SUPPORT !! 131 menu "Machine selection"
336 def_bool y <<
337 132
338 config MMU !! 133 choice
339 def_bool y !! 134 prompt "System type"
>> 135 default MIPS_GENERIC_KERNEL
340 136
341 config ARCH_MMAP_RND_BITS_MIN !! 137 config MIPS_GENERIC_KERNEL
342 default 28 if 64BIT !! 138 bool "Generic board-agnostic MIPS kernel"
343 default 8 !! 139 select ARCH_HAS_SETUP_DMA_OPS
>> 140 select MIPS_GENERIC
>> 141 select BOOT_RAW
>> 142 select BUILTIN_DTB
>> 143 select CEVT_R4K
>> 144 select CLKSRC_MIPS_GIC
>> 145 select COMMON_CLK
>> 146 select CPU_MIPSR2_IRQ_EI
>> 147 select CPU_MIPSR2_IRQ_VI
>> 148 select CSRC_R4K
>> 149 select DMA_NONCOHERENT
>> 150 select HAVE_PCI
>> 151 select IRQ_MIPS_CPU
>> 152 select MIPS_AUTO_PFN_OFFSET
>> 153 select MIPS_CPU_SCACHE
>> 154 select MIPS_GIC
>> 155 select MIPS_L1_CACHE_SHIFT_7
>> 156 select NO_EXCEPT_FILL
>> 157 select PCI_DRIVERS_GENERIC
>> 158 select SMP_UP if SMP
>> 159 select SWAP_IO_SPACE
>> 160 select SYS_HAS_CPU_MIPS32_R1
>> 161 select SYS_HAS_CPU_MIPS32_R2
>> 162 select SYS_HAS_CPU_MIPS32_R6
>> 163 select SYS_HAS_CPU_MIPS64_R1
>> 164 select SYS_HAS_CPU_MIPS64_R2
>> 165 select SYS_HAS_CPU_MIPS64_R6
>> 166 select SYS_SUPPORTS_32BIT_KERNEL
>> 167 select SYS_SUPPORTS_64BIT_KERNEL
>> 168 select SYS_SUPPORTS_BIG_ENDIAN
>> 169 select SYS_SUPPORTS_HIGHMEM
>> 170 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 171 select SYS_SUPPORTS_MICROMIPS
>> 172 select SYS_SUPPORTS_MIPS16
>> 173 select SYS_SUPPORTS_MIPS_CPS
>> 174 select SYS_SUPPORTS_MULTITHREADING
>> 175 select SYS_SUPPORTS_RELOCATABLE
>> 176 select SYS_SUPPORTS_SMARTMIPS
>> 177 select SYS_SUPPORTS_ZBOOT
>> 178 select UHI_BOOT
>> 179 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 180 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 181 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 182 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 183 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 184 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 185 select USE_OF
>> 186 help
>> 187 Select this to build a kernel which aims to support multiple boards,
>> 188 generally using a flattened device tree passed from the bootloader
>> 189 using the boot protocol defined in the UHI (Unified Hosting
>> 190 Interface) specification.
344 191
345 config ARCH_MMAP_RND_BITS_MAX !! 192 config MIPS_ALCHEMY
346 default 32 if 64BIT !! 193 bool "Alchemy processor based machines"
347 default 16 !! 194 select PHYS_ADDR_T_64BIT
>> 195 select CEVT_R4K
>> 196 select CSRC_R4K
>> 197 select IRQ_MIPS_CPU
>> 198 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 199 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 200 select SYS_HAS_CPU_MIPS32_R1
>> 201 select SYS_SUPPORTS_32BIT_KERNEL
>> 202 select SYS_SUPPORTS_APM_EMULATION
>> 203 select GPIOLIB
>> 204 select SYS_SUPPORTS_ZBOOT
>> 205 select COMMON_CLK
348 206
349 config ARCH_MMAP_RND_COMPAT_BITS_MIN !! 207 config AR7
350 default 8 !! 208 bool "Texas Instruments AR7"
>> 209 select BOOT_ELF32
>> 210 select COMMON_CLK
>> 211 select DMA_NONCOHERENT
>> 212 select CEVT_R4K
>> 213 select CSRC_R4K
>> 214 select IRQ_MIPS_CPU
>> 215 select NO_EXCEPT_FILL
>> 216 select SWAP_IO_SPACE
>> 217 select SYS_HAS_CPU_MIPS32_R1
>> 218 select SYS_HAS_EARLY_PRINTK
>> 219 select SYS_SUPPORTS_32BIT_KERNEL
>> 220 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 221 select SYS_SUPPORTS_MIPS16
>> 222 select SYS_SUPPORTS_ZBOOT_UART16550
>> 223 select GPIOLIB
>> 224 select VLYNQ
>> 225 help
>> 226 Support for the Texas Instruments AR7 System-on-a-Chip
>> 227 family: TNETD7100, 7200 and 7300.
351 228
352 config ARCH_MMAP_RND_COMPAT_BITS_MAX !! 229 config ATH25
353 default 16 !! 230 bool "Atheros AR231x/AR531x SoC support"
>> 231 select CEVT_R4K
>> 232 select CSRC_R4K
>> 233 select DMA_NONCOHERENT
>> 234 select IRQ_MIPS_CPU
>> 235 select IRQ_DOMAIN
>> 236 select SYS_HAS_CPU_MIPS32_R1
>> 237 select SYS_SUPPORTS_BIG_ENDIAN
>> 238 select SYS_SUPPORTS_32BIT_KERNEL
>> 239 select SYS_HAS_EARLY_PRINTK
>> 240 help
>> 241 Support for Atheros AR231x and Atheros AR531x based boards
>> 242
>> 243 config ATH79
>> 244 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 245 select ARCH_HAS_RESET_CONTROLLER
>> 246 select BOOT_RAW
>> 247 select CEVT_R4K
>> 248 select CSRC_R4K
>> 249 select DMA_NONCOHERENT
>> 250 select GPIOLIB
>> 251 select PINCTRL
>> 252 select COMMON_CLK
>> 253 select IRQ_MIPS_CPU
>> 254 select SYS_HAS_CPU_MIPS32_R2
>> 255 select SYS_HAS_EARLY_PRINTK
>> 256 select SYS_SUPPORTS_32BIT_KERNEL
>> 257 select SYS_SUPPORTS_BIG_ENDIAN
>> 258 select SYS_SUPPORTS_MIPS16
>> 259 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 260 select USE_OF
>> 261 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 262 help
>> 263 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 264
>> 265 config BMIPS_GENERIC
>> 266 bool "Broadcom Generic BMIPS kernel"
>> 267 select ARCH_HAS_RESET_CONTROLLER
>> 268 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 269 select BOOT_RAW
>> 270 select NO_EXCEPT_FILL
>> 271 select USE_OF
>> 272 select CEVT_R4K
>> 273 select CSRC_R4K
>> 274 select SYNC_R4K
>> 275 select COMMON_CLK
>> 276 select BCM6345_L1_IRQ
>> 277 select BCM7038_L1_IRQ
>> 278 select BCM7120_L2_IRQ
>> 279 select BRCMSTB_L2_IRQ
>> 280 select IRQ_MIPS_CPU
>> 281 select DMA_NONCOHERENT
>> 282 select SYS_SUPPORTS_32BIT_KERNEL
>> 283 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 284 select SYS_SUPPORTS_BIG_ENDIAN
>> 285 select SYS_SUPPORTS_HIGHMEM
>> 286 select SYS_HAS_CPU_BMIPS32_3300
>> 287 select SYS_HAS_CPU_BMIPS4350
>> 288 select SYS_HAS_CPU_BMIPS4380
>> 289 select SYS_HAS_CPU_BMIPS5000
>> 290 select SWAP_IO_SPACE
>> 291 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 292 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 293 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 294 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 295 select HARDIRQS_SW_RESEND
>> 296 select HAVE_PCI
>> 297 select PCI_DRIVERS_GENERIC
>> 298 select FW_CFE
>> 299 help
>> 300 Build a generic DT-based kernel image that boots on select
>> 301 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 302 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 303 must be set appropriately for your board.
>> 304
>> 305 config BCM47XX
>> 306 bool "Broadcom BCM47XX based boards"
>> 307 select BOOT_RAW
>> 308 select CEVT_R4K
>> 309 select CSRC_R4K
>> 310 select DMA_NONCOHERENT
>> 311 select HAVE_PCI
>> 312 select IRQ_MIPS_CPU
>> 313 select SYS_HAS_CPU_MIPS32_R1
>> 314 select NO_EXCEPT_FILL
>> 315 select SYS_SUPPORTS_32BIT_KERNEL
>> 316 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 317 select SYS_SUPPORTS_MIPS16
>> 318 select SYS_SUPPORTS_ZBOOT
>> 319 select SYS_HAS_EARLY_PRINTK
>> 320 select USE_GENERIC_EARLY_PRINTK_8250
>> 321 select GPIOLIB
>> 322 select LEDS_GPIO_REGISTER
>> 323 select BCM47XX_NVRAM
>> 324 select BCM47XX_SPROM
>> 325 select BCM47XX_SSB if !BCM47XX_BCMA
>> 326 help
>> 327 Support for BCM47XX based boards
>> 328
>> 329 config BCM63XX
>> 330 bool "Broadcom BCM63XX based boards"
>> 331 select BOOT_RAW
>> 332 select CEVT_R4K
>> 333 select CSRC_R4K
>> 334 select SYNC_R4K
>> 335 select DMA_NONCOHERENT
>> 336 select IRQ_MIPS_CPU
>> 337 select SYS_SUPPORTS_32BIT_KERNEL
>> 338 select SYS_SUPPORTS_BIG_ENDIAN
>> 339 select SYS_HAS_EARLY_PRINTK
>> 340 select SYS_HAS_CPU_BMIPS32_3300
>> 341 select SYS_HAS_CPU_BMIPS4350
>> 342 select SYS_HAS_CPU_BMIPS4380
>> 343 select SWAP_IO_SPACE
>> 344 select GPIOLIB
>> 345 select MIPS_L1_CACHE_SHIFT_4
>> 346 select HAVE_LEGACY_CLK
>> 347 help
>> 348 Support for BCM63XX based boards
354 349
355 config SBUS !! 350 config MIPS_COBALT
356 bool !! 351 bool "Cobalt Server"
>> 352 select CEVT_R4K
>> 353 select CSRC_R4K
>> 354 select CEVT_GT641XX
>> 355 select DMA_NONCOHERENT
>> 356 select FORCE_PCI
>> 357 select I8253
>> 358 select I8259
>> 359 select IRQ_MIPS_CPU
>> 360 select IRQ_GT641XX
>> 361 select PCI_GT64XXX_PCI0
>> 362 select SYS_HAS_CPU_NEVADA
>> 363 select SYS_HAS_EARLY_PRINTK
>> 364 select SYS_SUPPORTS_32BIT_KERNEL
>> 365 select SYS_SUPPORTS_64BIT_KERNEL
>> 366 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 367 select USE_GENERIC_EARLY_PRINTK_8250
>> 368
>> 369 config MACH_DECSTATION
>> 370 bool "DECstations"
>> 371 select BOOT_ELF32
>> 372 select CEVT_DS1287
>> 373 select CEVT_R4K if CPU_R4X00
>> 374 select CSRC_IOASIC
>> 375 select CSRC_R4K if CPU_R4X00
>> 376 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 377 select CPU_R4000_WORKAROUNDS if 64BIT
>> 378 select CPU_R4400_WORKAROUNDS if 64BIT
>> 379 select DMA_NONCOHERENT
>> 380 select NO_IOPORT_MAP
>> 381 select IRQ_MIPS_CPU
>> 382 select SYS_HAS_CPU_R3000
>> 383 select SYS_HAS_CPU_R4X00
>> 384 select SYS_SUPPORTS_32BIT_KERNEL
>> 385 select SYS_SUPPORTS_64BIT_KERNEL
>> 386 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 387 select SYS_SUPPORTS_128HZ
>> 388 select SYS_SUPPORTS_256HZ
>> 389 select SYS_SUPPORTS_1024HZ
>> 390 select MIPS_L1_CACHE_SHIFT_4
>> 391 help
>> 392 This enables support for DEC's MIPS based workstations. For details
>> 393 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 394 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 395
>> 396 If you have one of the following DECstation Models you definitely
>> 397 want to choose R4xx0 for the CPU Type:
>> 398
>> 399 DECstation 5000/50
>> 400 DECstation 5000/150
>> 401 DECstation 5000/260
>> 402 DECsystem 5900/260
>> 403
>> 404 otherwise choose R3000.
>> 405
>> 406 config MACH_JAZZ
>> 407 bool "Jazz family of machines"
>> 408 select ARC_MEMORY
>> 409 select ARC_PROMLIB
>> 410 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 411 select ARCH_MIGHT_HAVE_PC_SERIO
>> 412 select DMA_OPS
>> 413 select FW_ARC
>> 414 select FW_ARC32
>> 415 select ARCH_MAY_HAVE_PC_FDC
>> 416 select CEVT_R4K
>> 417 select CSRC_R4K
>> 418 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 419 select GENERIC_ISA_DMA
>> 420 select HAVE_PCSPKR_PLATFORM
>> 421 select IRQ_MIPS_CPU
>> 422 select I8253
>> 423 select I8259
>> 424 select ISA
>> 425 select SYS_HAS_CPU_R4X00
>> 426 select SYS_SUPPORTS_32BIT_KERNEL
>> 427 select SYS_SUPPORTS_64BIT_KERNEL
>> 428 select SYS_SUPPORTS_100HZ
>> 429 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 430 help
>> 431 This a family of machines based on the MIPS R4030 chipset which was
>> 432 used by several vendors to build RISC/os and Windows NT workstations.
>> 433 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 434 Olivetti M700-10 workstations.
>> 435
>> 436 config MACH_INGENIC_SOC
>> 437 bool "Ingenic SoC based machines"
>> 438 select MIPS_GENERIC
>> 439 select MACH_INGENIC
>> 440 select SYS_SUPPORTS_ZBOOT_UART16550
>> 441 select CPU_SUPPORTS_CPUFREQ
>> 442 select MIPS_EXTERNAL_TIMER
>> 443
>> 444 config LANTIQ
>> 445 bool "Lantiq based platforms"
>> 446 select DMA_NONCOHERENT
>> 447 select IRQ_MIPS_CPU
>> 448 select CEVT_R4K
>> 449 select CSRC_R4K
>> 450 select NO_EXCEPT_FILL
>> 451 select SYS_HAS_CPU_MIPS32_R1
>> 452 select SYS_HAS_CPU_MIPS32_R2
>> 453 select SYS_SUPPORTS_BIG_ENDIAN
>> 454 select SYS_SUPPORTS_32BIT_KERNEL
>> 455 select SYS_SUPPORTS_MIPS16
>> 456 select SYS_SUPPORTS_MULTITHREADING
>> 457 select SYS_SUPPORTS_VPE_LOADER
>> 458 select SYS_HAS_EARLY_PRINTK
>> 459 select GPIOLIB
>> 460 select SWAP_IO_SPACE
>> 461 select BOOT_RAW
>> 462 select HAVE_LEGACY_CLK
>> 463 select USE_OF
>> 464 select PINCTRL
>> 465 select PINCTRL_LANTIQ
>> 466 select ARCH_HAS_RESET_CONTROLLER
>> 467 select RESET_CONTROLLER
357 468
358 config GENERIC_ISA_DMA !! 469 config MACH_LOONGSON32
359 def_bool y !! 470 bool "Loongson 32-bit family of machines"
360 depends on ISA_DMA_API !! 471 select SYS_SUPPORTS_ZBOOT
>> 472 help
>> 473 This enables support for the Loongson-1 family of machines.
361 474
362 config GENERIC_CSUM !! 475 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
363 bool !! 476 the Institute of Computing Technology (ICT), Chinese Academy of
364 default y if KMSAN || KASAN !! 477 Sciences (CAS).
365 478
366 config GENERIC_BUG !! 479 config MACH_LOONGSON2EF
367 def_bool y !! 480 bool "Loongson-2E/F family of machines"
368 depends on BUG !! 481 select SYS_SUPPORTS_ZBOOT
369 select GENERIC_BUG_RELATIVE_POINTERS i !! 482 help
>> 483 This enables the support of early Loongson-2E/F family of machines.
370 484
371 config GENERIC_BUG_RELATIVE_POINTERS !! 485 config MACH_LOONGSON64
372 bool !! 486 bool "Loongson 64-bit family of machines"
>> 487 select ARCH_SPARSEMEM_ENABLE
>> 488 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 489 select ARCH_MIGHT_HAVE_PC_SERIO
>> 490 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 491 select BOOT_ELF32
>> 492 select BOARD_SCACHE
>> 493 select CSRC_R4K
>> 494 select CEVT_R4K
>> 495 select CPU_HAS_WB
>> 496 select FORCE_PCI
>> 497 select ISA
>> 498 select I8259
>> 499 select IRQ_MIPS_CPU
>> 500 select NO_EXCEPT_FILL
>> 501 select NR_CPUS_DEFAULT_64
>> 502 select USE_GENERIC_EARLY_PRINTK_8250
>> 503 select PCI_DRIVERS_GENERIC
>> 504 select SYS_HAS_CPU_LOONGSON64
>> 505 select SYS_HAS_EARLY_PRINTK
>> 506 select SYS_SUPPORTS_SMP
>> 507 select SYS_SUPPORTS_HOTPLUG_CPU
>> 508 select SYS_SUPPORTS_NUMA
>> 509 select SYS_SUPPORTS_64BIT_KERNEL
>> 510 select SYS_SUPPORTS_HIGHMEM
>> 511 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 512 select SYS_SUPPORTS_ZBOOT
>> 513 select SYS_SUPPORTS_RELOCATABLE
>> 514 select ZONE_DMA32
>> 515 select COMMON_CLK
>> 516 select USE_OF
>> 517 select BUILTIN_DTB
>> 518 select PCI_HOST_GENERIC
>> 519 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 520 help
>> 521 This enables the support of Loongson-2/3 family of machines.
>> 522
>> 523 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 524 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 525 and Loongson-2F which will be removed), developed by the Institute
>> 526 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 527
>> 528 config MIPS_MALTA
>> 529 bool "MIPS Malta board"
>> 530 select ARCH_MAY_HAVE_PC_FDC
>> 531 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 532 select ARCH_MIGHT_HAVE_PC_SERIO
>> 533 select BOOT_ELF32
>> 534 select BOOT_RAW
>> 535 select BUILTIN_DTB
>> 536 select CEVT_R4K
>> 537 select CLKSRC_MIPS_GIC
>> 538 select COMMON_CLK
>> 539 select CSRC_R4K
>> 540 select DMA_NONCOHERENT
>> 541 select GENERIC_ISA_DMA
>> 542 select HAVE_PCSPKR_PLATFORM
>> 543 select HAVE_PCI
>> 544 select I8253
>> 545 select I8259
>> 546 select IRQ_MIPS_CPU
>> 547 select MIPS_BONITO64
>> 548 select MIPS_CPU_SCACHE
>> 549 select MIPS_GIC
>> 550 select MIPS_L1_CACHE_SHIFT_6
>> 551 select MIPS_MSC
>> 552 select PCI_GT64XXX_PCI0
>> 553 select SMP_UP if SMP
>> 554 select SWAP_IO_SPACE
>> 555 select SYS_HAS_CPU_MIPS32_R1
>> 556 select SYS_HAS_CPU_MIPS32_R2
>> 557 select SYS_HAS_CPU_MIPS32_R3_5
>> 558 select SYS_HAS_CPU_MIPS32_R5
>> 559 select SYS_HAS_CPU_MIPS32_R6
>> 560 select SYS_HAS_CPU_MIPS64_R1
>> 561 select SYS_HAS_CPU_MIPS64_R2
>> 562 select SYS_HAS_CPU_MIPS64_R6
>> 563 select SYS_HAS_CPU_NEVADA
>> 564 select SYS_HAS_CPU_RM7000
>> 565 select SYS_SUPPORTS_32BIT_KERNEL
>> 566 select SYS_SUPPORTS_64BIT_KERNEL
>> 567 select SYS_SUPPORTS_BIG_ENDIAN
>> 568 select SYS_SUPPORTS_HIGHMEM
>> 569 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 570 select SYS_SUPPORTS_MICROMIPS
>> 571 select SYS_SUPPORTS_MIPS16
>> 572 select SYS_SUPPORTS_MIPS_CMP
>> 573 select SYS_SUPPORTS_MIPS_CPS
>> 574 select SYS_SUPPORTS_MULTITHREADING
>> 575 select SYS_SUPPORTS_RELOCATABLE
>> 576 select SYS_SUPPORTS_SMARTMIPS
>> 577 select SYS_SUPPORTS_VPE_LOADER
>> 578 select SYS_SUPPORTS_ZBOOT
>> 579 select USE_OF
>> 580 select WAR_ICACHE_REFILLS
>> 581 select ZONE_DMA32 if 64BIT
>> 582 help
>> 583 This enables support for the MIPS Technologies Malta evaluation
>> 584 board.
>> 585
>> 586 config MACH_PIC32
>> 587 bool "Microchip PIC32 Family"
>> 588 help
>> 589 This enables support for the Microchip PIC32 family of platforms.
>> 590
>> 591 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 592 microcontrollers.
>> 593
>> 594 config MACH_NINTENDO64
>> 595 bool "Nintendo 64 console"
>> 596 select CEVT_R4K
>> 597 select CSRC_R4K
>> 598 select SYS_HAS_CPU_R4300
>> 599 select SYS_SUPPORTS_BIG_ENDIAN
>> 600 select SYS_SUPPORTS_ZBOOT
>> 601 select SYS_SUPPORTS_32BIT_KERNEL
>> 602 select SYS_SUPPORTS_64BIT_KERNEL
>> 603 select DMA_NONCOHERENT
>> 604 select IRQ_MIPS_CPU
>> 605
>> 606 config RALINK
>> 607 bool "Ralink based machines"
>> 608 select CEVT_R4K
>> 609 select COMMON_CLK
>> 610 select CSRC_R4K
>> 611 select BOOT_RAW
>> 612 select DMA_NONCOHERENT
>> 613 select IRQ_MIPS_CPU
>> 614 select USE_OF
>> 615 select SYS_HAS_CPU_MIPS32_R2
>> 616 select SYS_SUPPORTS_32BIT_KERNEL
>> 617 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 618 select SYS_SUPPORTS_MIPS16
>> 619 select SYS_SUPPORTS_ZBOOT
>> 620 select SYS_HAS_EARLY_PRINTK
>> 621 select ARCH_HAS_RESET_CONTROLLER
>> 622 select RESET_CONTROLLER
>> 623
>> 624 config MACH_REALTEK_RTL
>> 625 bool "Realtek RTL838x/RTL839x based machines"
>> 626 select MIPS_GENERIC
>> 627 select DMA_NONCOHERENT
>> 628 select IRQ_MIPS_CPU
>> 629 select CSRC_R4K
>> 630 select CEVT_R4K
>> 631 select SYS_HAS_CPU_MIPS32_R1
>> 632 select SYS_HAS_CPU_MIPS32_R2
>> 633 select SYS_SUPPORTS_BIG_ENDIAN
>> 634 select SYS_SUPPORTS_32BIT_KERNEL
>> 635 select SYS_SUPPORTS_MIPS16
>> 636 select SYS_SUPPORTS_MULTITHREADING
>> 637 select SYS_SUPPORTS_VPE_LOADER
>> 638 select BOOT_RAW
>> 639 select PINCTRL
>> 640 select USE_OF
373 641
374 config ARCH_MAY_HAVE_PC_FDC !! 642 config SGI_IP22
375 def_bool y !! 643 bool "SGI IP22 (Indy/Indigo2)"
376 depends on ISA_DMA_API !! 644 select ARC_MEMORY
>> 645 select ARC_PROMLIB
>> 646 select FW_ARC
>> 647 select FW_ARC32
>> 648 select ARCH_MIGHT_HAVE_PC_SERIO
>> 649 select BOOT_ELF32
>> 650 select CEVT_R4K
>> 651 select CSRC_R4K
>> 652 select DEFAULT_SGI_PARTITION
>> 653 select DMA_NONCOHERENT
>> 654 select HAVE_EISA
>> 655 select I8253
>> 656 select I8259
>> 657 select IP22_CPU_SCACHE
>> 658 select IRQ_MIPS_CPU
>> 659 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 660 select SGI_HAS_I8042
>> 661 select SGI_HAS_INDYDOG
>> 662 select SGI_HAS_HAL2
>> 663 select SGI_HAS_SEEQ
>> 664 select SGI_HAS_WD93
>> 665 select SGI_HAS_ZILOG
>> 666 select SWAP_IO_SPACE
>> 667 select SYS_HAS_CPU_R4X00
>> 668 select SYS_HAS_CPU_R5000
>> 669 select SYS_HAS_EARLY_PRINTK
>> 670 select SYS_SUPPORTS_32BIT_KERNEL
>> 671 select SYS_SUPPORTS_64BIT_KERNEL
>> 672 select SYS_SUPPORTS_BIG_ENDIAN
>> 673 select WAR_R4600_V1_INDEX_ICACHEOP
>> 674 select WAR_R4600_V1_HIT_CACHEOP
>> 675 select WAR_R4600_V2_HIT_CACHEOP
>> 676 select MIPS_L1_CACHE_SHIFT_7
>> 677 help
>> 678 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 679 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 680 that runs on these, say Y here.
>> 681
>> 682 config SGI_IP27
>> 683 bool "SGI IP27 (Origin200/2000)"
>> 684 select ARCH_HAS_PHYS_TO_DMA
>> 685 select ARCH_SPARSEMEM_ENABLE
>> 686 select FW_ARC
>> 687 select FW_ARC64
>> 688 select ARC_CMDLINE_ONLY
>> 689 select BOOT_ELF64
>> 690 select DEFAULT_SGI_PARTITION
>> 691 select FORCE_PCI
>> 692 select SYS_HAS_EARLY_PRINTK
>> 693 select HAVE_PCI
>> 694 select IRQ_MIPS_CPU
>> 695 select IRQ_DOMAIN_HIERARCHY
>> 696 select NR_CPUS_DEFAULT_64
>> 697 select PCI_DRIVERS_GENERIC
>> 698 select PCI_XTALK_BRIDGE
>> 699 select SYS_HAS_CPU_R10000
>> 700 select SYS_SUPPORTS_64BIT_KERNEL
>> 701 select SYS_SUPPORTS_BIG_ENDIAN
>> 702 select SYS_SUPPORTS_NUMA
>> 703 select SYS_SUPPORTS_SMP
>> 704 select WAR_R10000_LLSC
>> 705 select MIPS_L1_CACHE_SHIFT_7
>> 706 select NUMA
>> 707 select HAVE_ARCH_NODEDATA_EXTENSION
>> 708 help
>> 709 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 710 workstations. To compile a Linux kernel that runs on these, say Y
>> 711 here.
>> 712
>> 713 config SGI_IP28
>> 714 bool "SGI IP28 (Indigo2 R10k)"
>> 715 select ARC_MEMORY
>> 716 select ARC_PROMLIB
>> 717 select FW_ARC
>> 718 select FW_ARC64
>> 719 select ARCH_MIGHT_HAVE_PC_SERIO
>> 720 select BOOT_ELF64
>> 721 select CEVT_R4K
>> 722 select CSRC_R4K
>> 723 select DEFAULT_SGI_PARTITION
>> 724 select DMA_NONCOHERENT
>> 725 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 726 select IRQ_MIPS_CPU
>> 727 select HAVE_EISA
>> 728 select I8253
>> 729 select I8259
>> 730 select SGI_HAS_I8042
>> 731 select SGI_HAS_INDYDOG
>> 732 select SGI_HAS_HAL2
>> 733 select SGI_HAS_SEEQ
>> 734 select SGI_HAS_WD93
>> 735 select SGI_HAS_ZILOG
>> 736 select SWAP_IO_SPACE
>> 737 select SYS_HAS_CPU_R10000
>> 738 select SYS_HAS_EARLY_PRINTK
>> 739 select SYS_SUPPORTS_64BIT_KERNEL
>> 740 select SYS_SUPPORTS_BIG_ENDIAN
>> 741 select WAR_R10000_LLSC
>> 742 select MIPS_L1_CACHE_SHIFT_7
>> 743 help
>> 744 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 745 kernel that runs on these, say Y here.
>> 746
>> 747 config SGI_IP30
>> 748 bool "SGI IP30 (Octane/Octane2)"
>> 749 select ARCH_HAS_PHYS_TO_DMA
>> 750 select FW_ARC
>> 751 select FW_ARC64
>> 752 select BOOT_ELF64
>> 753 select CEVT_R4K
>> 754 select CSRC_R4K
>> 755 select FORCE_PCI
>> 756 select SYNC_R4K if SMP
>> 757 select ZONE_DMA32
>> 758 select HAVE_PCI
>> 759 select IRQ_MIPS_CPU
>> 760 select IRQ_DOMAIN_HIERARCHY
>> 761 select PCI_DRIVERS_GENERIC
>> 762 select PCI_XTALK_BRIDGE
>> 763 select SYS_HAS_EARLY_PRINTK
>> 764 select SYS_HAS_CPU_R10000
>> 765 select SYS_SUPPORTS_64BIT_KERNEL
>> 766 select SYS_SUPPORTS_BIG_ENDIAN
>> 767 select SYS_SUPPORTS_SMP
>> 768 select WAR_R10000_LLSC
>> 769 select MIPS_L1_CACHE_SHIFT_7
>> 770 select ARC_MEMORY
>> 771 help
>> 772 These are the SGI Octane and Octane2 graphics workstations. To
>> 773 compile a Linux kernel that runs on these, say Y here.
>> 774
>> 775 config SGI_IP32
>> 776 bool "SGI IP32 (O2)"
>> 777 select ARC_MEMORY
>> 778 select ARC_PROMLIB
>> 779 select ARCH_HAS_PHYS_TO_DMA
>> 780 select FW_ARC
>> 781 select FW_ARC32
>> 782 select BOOT_ELF32
>> 783 select CEVT_R4K
>> 784 select CSRC_R4K
>> 785 select DMA_NONCOHERENT
>> 786 select HAVE_PCI
>> 787 select IRQ_MIPS_CPU
>> 788 select R5000_CPU_SCACHE
>> 789 select RM7000_CPU_SCACHE
>> 790 select SYS_HAS_CPU_R5000
>> 791 select SYS_HAS_CPU_R10000 if BROKEN
>> 792 select SYS_HAS_CPU_RM7000
>> 793 select SYS_HAS_CPU_NEVADA
>> 794 select SYS_SUPPORTS_64BIT_KERNEL
>> 795 select SYS_SUPPORTS_BIG_ENDIAN
>> 796 select WAR_ICACHE_REFILLS
>> 797 help
>> 798 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 799
>> 800 config SIBYTE_CRHINE
>> 801 bool "Sibyte BCM91120C-CRhine"
>> 802 select BOOT_ELF32
>> 803 select SIBYTE_BCM1120
>> 804 select SWAP_IO_SPACE
>> 805 select SYS_HAS_CPU_SB1
>> 806 select SYS_SUPPORTS_BIG_ENDIAN
>> 807 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 808
>> 809 config SIBYTE_CARMEL
>> 810 bool "Sibyte BCM91120x-Carmel"
>> 811 select BOOT_ELF32
>> 812 select SIBYTE_BCM1120
>> 813 select SWAP_IO_SPACE
>> 814 select SYS_HAS_CPU_SB1
>> 815 select SYS_SUPPORTS_BIG_ENDIAN
>> 816 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 817
>> 818 config SIBYTE_CRHONE
>> 819 bool "Sibyte BCM91125C-CRhone"
>> 820 select BOOT_ELF32
>> 821 select SIBYTE_BCM1125
>> 822 select SWAP_IO_SPACE
>> 823 select SYS_HAS_CPU_SB1
>> 824 select SYS_SUPPORTS_BIG_ENDIAN
>> 825 select SYS_SUPPORTS_HIGHMEM
>> 826 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 827
>> 828 config SIBYTE_RHONE
>> 829 bool "Sibyte BCM91125E-Rhone"
>> 830 select BOOT_ELF32
>> 831 select SIBYTE_BCM1125H
>> 832 select SWAP_IO_SPACE
>> 833 select SYS_HAS_CPU_SB1
>> 834 select SYS_SUPPORTS_BIG_ENDIAN
>> 835 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 836
>> 837 config SIBYTE_SWARM
>> 838 bool "Sibyte BCM91250A-SWARM"
>> 839 select BOOT_ELF32
>> 840 select HAVE_PATA_PLATFORM
>> 841 select SIBYTE_SB1250
>> 842 select SWAP_IO_SPACE
>> 843 select SYS_HAS_CPU_SB1
>> 844 select SYS_SUPPORTS_BIG_ENDIAN
>> 845 select SYS_SUPPORTS_HIGHMEM
>> 846 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 847 select ZONE_DMA32 if 64BIT
>> 848 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 849
>> 850 config SIBYTE_LITTLESUR
>> 851 bool "Sibyte BCM91250C2-LittleSur"
>> 852 select BOOT_ELF32
>> 853 select HAVE_PATA_PLATFORM
>> 854 select SIBYTE_SB1250
>> 855 select SWAP_IO_SPACE
>> 856 select SYS_HAS_CPU_SB1
>> 857 select SYS_SUPPORTS_BIG_ENDIAN
>> 858 select SYS_SUPPORTS_HIGHMEM
>> 859 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 860 select ZONE_DMA32 if 64BIT
>> 861
>> 862 config SIBYTE_SENTOSA
>> 863 bool "Sibyte BCM91250E-Sentosa"
>> 864 select BOOT_ELF32
>> 865 select SIBYTE_SB1250
>> 866 select SWAP_IO_SPACE
>> 867 select SYS_HAS_CPU_SB1
>> 868 select SYS_SUPPORTS_BIG_ENDIAN
>> 869 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 870 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 871
>> 872 config SIBYTE_BIGSUR
>> 873 bool "Sibyte BCM91480B-BigSur"
>> 874 select BOOT_ELF32
>> 875 select NR_CPUS_DEFAULT_4
>> 876 select SIBYTE_BCM1x80
>> 877 select SWAP_IO_SPACE
>> 878 select SYS_HAS_CPU_SB1
>> 879 select SYS_SUPPORTS_BIG_ENDIAN
>> 880 select SYS_SUPPORTS_HIGHMEM
>> 881 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 882 select ZONE_DMA32 if 64BIT
>> 883 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 884
>> 885 config SNI_RM
>> 886 bool "SNI RM200/300/400"
>> 887 select ARC_MEMORY
>> 888 select ARC_PROMLIB
>> 889 select FW_ARC if CPU_LITTLE_ENDIAN
>> 890 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 891 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 892 select ARCH_MAY_HAVE_PC_FDC
>> 893 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 894 select ARCH_MIGHT_HAVE_PC_SERIO
>> 895 select BOOT_ELF32
>> 896 select CEVT_R4K
>> 897 select CSRC_R4K
>> 898 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 899 select DMA_NONCOHERENT
>> 900 select GENERIC_ISA_DMA
>> 901 select HAVE_EISA
>> 902 select HAVE_PCSPKR_PLATFORM
>> 903 select HAVE_PCI
>> 904 select IRQ_MIPS_CPU
>> 905 select I8253
>> 906 select I8259
>> 907 select ISA
>> 908 select MIPS_L1_CACHE_SHIFT_6
>> 909 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 910 select SYS_HAS_CPU_R4X00
>> 911 select SYS_HAS_CPU_R5000
>> 912 select SYS_HAS_CPU_R10000
>> 913 select R5000_CPU_SCACHE
>> 914 select SYS_HAS_EARLY_PRINTK
>> 915 select SYS_SUPPORTS_32BIT_KERNEL
>> 916 select SYS_SUPPORTS_64BIT_KERNEL
>> 917 select SYS_SUPPORTS_BIG_ENDIAN
>> 918 select SYS_SUPPORTS_HIGHMEM
>> 919 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 920 select WAR_R4600_V2_HIT_CACHEOP
>> 921 help
>> 922 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 923 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 924 Technology and now in turn merged with Fujitsu. Say Y here to
>> 925 support this machine type.
>> 926
>> 927 config MACH_TX49XX
>> 928 bool "Toshiba TX49 series based machines"
>> 929 select WAR_TX49XX_ICACHE_INDEX_INV
>> 930
>> 931 config MIKROTIK_RB532
>> 932 bool "Mikrotik RB532 boards"
>> 933 select CEVT_R4K
>> 934 select CSRC_R4K
>> 935 select DMA_NONCOHERENT
>> 936 select HAVE_PCI
>> 937 select IRQ_MIPS_CPU
>> 938 select SYS_HAS_CPU_MIPS32_R1
>> 939 select SYS_SUPPORTS_32BIT_KERNEL
>> 940 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 941 select SWAP_IO_SPACE
>> 942 select BOOT_RAW
>> 943 select GPIOLIB
>> 944 select MIPS_L1_CACHE_SHIFT_4
>> 945 help
>> 946 Support the Mikrotik(tm) RouterBoard 532 series,
>> 947 based on the IDT RC32434 SoC.
377 948
378 config GENERIC_CALIBRATE_DELAY !! 949 config CAVIUM_OCTEON_SOC
379 def_bool y !! 950 bool "Cavium Networks Octeon SoC based boards"
>> 951 select CEVT_R4K
>> 952 select ARCH_HAS_PHYS_TO_DMA
>> 953 select HAVE_RAPIDIO
>> 954 select PHYS_ADDR_T_64BIT
>> 955 select SYS_SUPPORTS_64BIT_KERNEL
>> 956 select SYS_SUPPORTS_BIG_ENDIAN
>> 957 select EDAC_SUPPORT
>> 958 select EDAC_ATOMIC_SCRUB
>> 959 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 960 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 961 select SYS_HAS_EARLY_PRINTK
>> 962 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 963 select HAVE_PCI
>> 964 select HAVE_PLAT_DELAY
>> 965 select HAVE_PLAT_FW_INIT_CMDLINE
>> 966 select HAVE_PLAT_MEMCPY
>> 967 select ZONE_DMA32
>> 968 select GPIOLIB
>> 969 select USE_OF
>> 970 select ARCH_SPARSEMEM_ENABLE
>> 971 select SYS_SUPPORTS_SMP
>> 972 select NR_CPUS_DEFAULT_64
>> 973 select MIPS_NR_CPU_NR_MAP_1024
>> 974 select BUILTIN_DTB
>> 975 select MTD
>> 976 select MTD_COMPLEX_MAPPINGS
>> 977 select SWIOTLB
>> 978 select SYS_SUPPORTS_RELOCATABLE
>> 979 help
>> 980 This option supports all of the Octeon reference boards from Cavium
>> 981 Networks. It builds a kernel that dynamically determines the Octeon
>> 982 CPU type and supports all known board reference implementations.
>> 983 Some of the supported boards are:
>> 984 EBT3000
>> 985 EBH3000
>> 986 EBH3100
>> 987 Thunder
>> 988 Kodama
>> 989 Hikari
>> 990 Say Y here for most Octeon reference boards.
380 991
381 config ARCH_HAS_CPU_RELAX !! 992 endchoice
382 def_bool y <<
383 993
384 config ARCH_HIBERNATION_POSSIBLE !! 994 source "arch/mips/alchemy/Kconfig"
385 def_bool y !! 995 source "arch/mips/ath25/Kconfig"
>> 996 source "arch/mips/ath79/Kconfig"
>> 997 source "arch/mips/bcm47xx/Kconfig"
>> 998 source "arch/mips/bcm63xx/Kconfig"
>> 999 source "arch/mips/bmips/Kconfig"
>> 1000 source "arch/mips/generic/Kconfig"
>> 1001 source "arch/mips/ingenic/Kconfig"
>> 1002 source "arch/mips/jazz/Kconfig"
>> 1003 source "arch/mips/lantiq/Kconfig"
>> 1004 source "arch/mips/pic32/Kconfig"
>> 1005 source "arch/mips/ralink/Kconfig"
>> 1006 source "arch/mips/sgi-ip27/Kconfig"
>> 1007 source "arch/mips/sibyte/Kconfig"
>> 1008 source "arch/mips/txx9/Kconfig"
>> 1009 source "arch/mips/cavium-octeon/Kconfig"
>> 1010 source "arch/mips/loongson2ef/Kconfig"
>> 1011 source "arch/mips/loongson32/Kconfig"
>> 1012 source "arch/mips/loongson64/Kconfig"
386 1013
387 config ARCH_SUSPEND_POSSIBLE !! 1014 endmenu
388 def_bool y <<
389 1015
390 config AUDIT_ARCH !! 1016 config GENERIC_HWEIGHT
391 def_bool y if X86_64 !! 1017 bool
>> 1018 default y
392 1019
393 config KASAN_SHADOW_OFFSET !! 1020 config GENERIC_CALIBRATE_DELAY
394 hex !! 1021 bool
395 depends on KASAN !! 1022 default y
396 default 0xdffffc0000000000 <<
397 1023
398 config HAVE_INTEL_TXT !! 1024 config SCHED_OMIT_FRAME_POINTER
399 def_bool y !! 1025 bool
400 depends on INTEL_IOMMU && ACPI !! 1026 default y
401 1027
402 config X86_64_SMP !! 1028 #
403 def_bool y !! 1029 # Select some configuration options automatically based on user selections.
404 depends on X86_64 && SMP !! 1030 #
>> 1031 config FW_ARC
>> 1032 bool
405 1033
406 config ARCH_SUPPORTS_UPROBES !! 1034 config ARCH_MAY_HAVE_PC_FDC
407 def_bool y !! 1035 bool
408 1036
409 config FIX_EARLYCON_MEM !! 1037 config BOOT_RAW
410 def_bool y !! 1038 bool
411 1039
412 config DYNAMIC_PHYSICAL_MASK !! 1040 config CEVT_BCM1480
413 bool 1041 bool
414 1042
415 config PGTABLE_LEVELS !! 1043 config CEVT_DS1287
416 int !! 1044 bool
417 default 5 if X86_5LEVEL <<
418 default 4 if X86_64 <<
419 default 3 if X86_PAE <<
420 default 2 <<
421 1045
422 config CC_HAS_SANE_STACKPROTECTOR !! 1046 config CEVT_GT641XX
423 bool 1047 bool
424 default $(success,$(srctree)/scripts/g <<
425 default $(success,$(srctree)/scripts/g <<
426 help <<
427 We have to make sure stack protector <<
428 the compiler produces broken code or <<
429 the segment on 32-bit kernels. <<
430 1048
431 menu "Processor type and features" !! 1049 config CEVT_R4K
>> 1050 bool
432 1051
433 config SMP !! 1052 config CEVT_SB1250
434 bool "Symmetric multi-processing suppo !! 1053 bool
435 help <<
436 This enables support for systems wit <<
437 a system with only one CPU, say N. I <<
438 than one CPU, say Y. <<
439 1054
440 If you say N here, the kernel will r !! 1055 config CEVT_TXX9
441 machines, but will use only one CPU !! 1056 bool
442 you say Y here, the kernel will run <<
443 uniprocessor machines. On a uniproce <<
444 will run faster if you say N here. <<
445 1057
446 Note that if you say Y here and choo !! 1058 config CSRC_BCM1480
447 "Pentium" under "Processor family", !! 1059 bool
448 architectures. Similarly, multiproce <<
449 architecture may not work on all Pen <<
450 1060
451 People using multiprocessor machines !! 1061 config CSRC_IOASIC
452 Y to "Enhanced Real Time Clock Suppo !! 1062 bool
453 Management" code will be disabled if <<
454 1063
455 See also <file:Documentation/arch/x8 !! 1064 config CSRC_R4K
456 <file:Documentation/admin-guide/lock !! 1065 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
457 <http://www.tldp.org/docs.html#howto !! 1066 bool
458 1067
459 If you don't know what to do here, s !! 1068 config CSRC_SB1250
>> 1069 bool
460 1070
461 config X86_X2APIC !! 1071 config MIPS_CLOCK_VSYSCALL
462 bool "Support x2apic" !! 1072 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
463 depends on X86_LOCAL_APIC && X86_64 && <<
464 help <<
465 This enables x2apic support on CPUs <<
466 <<
467 This allows 32-bit apic IDs (so it c <<
468 and accesses the local apic via MSRs <<
469 <<
470 Some Intel systems circa 2022 and la <<
471 and can not fall back to the legacy <<
472 enabled in the BIOS. They will boot <<
473 without enabling this option. <<
474 1073
475 If you don't know what to do here, s !! 1074 config GPIO_TXX9
>> 1075 select GPIOLIB
>> 1076 bool
476 1077
477 config X86_POSTED_MSI !! 1078 config FW_CFE
478 bool "Enable MSI and MSI-x delivery by !! 1079 bool
479 depends on X86_64 && IRQ_REMAP <<
480 help <<
481 This enables MSIs that are under int <<
482 posted interrupts to the host kernel <<
483 potentially be improved by coalescin <<
484 frequency bursts. <<
485 1080
486 If you don't know what to do here, s !! 1081 config ARCH_SUPPORTS_UPROBES
>> 1082 bool
487 1083
488 config X86_MPPARSE !! 1084 config DMA_NONCOHERENT
489 bool "Enable MPS table" if ACPI !! 1085 bool
490 default y !! 1086 #
491 depends on X86_LOCAL_APIC !! 1087 # MIPS allows mixing "slightly different" Cacheability and Coherency
492 help !! 1088 # Attribute bits. It is believed that the uncached access through
493 For old smp systems that do not have !! 1089 # KSEG1 and the implementation specific "uncached accelerated" used
494 (esp with 64bit cpus) with acpi supp !! 1090 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1091 # significant advantages.
>> 1092 #
>> 1093 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1094 select ARCH_HAS_DMA_PREP_COHERENT
>> 1095 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1096 select ARCH_HAS_DMA_SET_UNCACHED
>> 1097 select DMA_NONCOHERENT_MMAP
>> 1098 select NEED_DMA_MAP_STATE
495 1099
496 config X86_CPU_RESCTRL !! 1100 config SYS_HAS_EARLY_PRINTK
497 bool "x86 CPU resource control support !! 1101 bool
498 depends on X86 && (CPU_SUP_INTEL || CP <<
499 select KERNFS <<
500 select PROC_CPU_RESCTRL if PRO <<
501 help <<
502 Enable x86 CPU resource control supp <<
503 1102
504 Provide support for the allocation a !! 1103 config SYS_SUPPORTS_HOTPLUG_CPU
505 usage by the CPU. !! 1104 bool
506 1105
507 Intel calls this Intel Resource Dire !! 1106 config MIPS_BONITO64
508 (Intel(R) RDT). More information abo !! 1107 bool
509 Intel x86 Architecture Software Deve <<
510 1108
511 AMD calls this AMD Platform Quality !! 1109 config MIPS_MSC
512 More information about AMD QoS can b !! 1110 bool
513 Platform Quality of Service Extensio <<
514 1111
515 Say N if unsure. !! 1112 config SYNC_R4K
>> 1113 bool
516 1114
517 config X86_FRED !! 1115 config NO_IOPORT_MAP
518 bool "Flexible Return and Event Delive !! 1116 def_bool n
519 depends on X86_64 <<
520 help <<
521 When enabled, try to use Flexible Re <<
522 instead of the legacy SYSCALL/SYSENT <<
523 ring transitions and exception/inter <<
524 system supports it. <<
525 1117
526 config X86_BIGSMP !! 1118 config GENERIC_CSUM
527 bool "Support for big SMP systems with !! 1119 def_bool CPU_NO_LOAD_STORE_LR
528 depends on SMP && X86_32 <<
529 help <<
530 This option is needed for the system <<
531 1120
532 config X86_EXTENDED_PLATFORM !! 1121 config GENERIC_ISA_DMA
533 bool "Support for extended (non-PC) x8 !! 1122 bool
534 default y !! 1123 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
535 help !! 1124 select ISA_DMA_API
536 If you disable this option then the <<
537 standard PC platforms. (which covers <<
538 systems out there.) <<
539 <<
540 If you enable this option then you'l <<
541 for the following non-PC x86 platfor <<
542 CONFIG_64BIT. <<
543 <<
544 32-bit platforms (CONFIG_64BIT=n): <<
545 Goldfish (Android emulator) <<
546 AMD Elan <<
547 RDC R-321x SoC <<
548 SGI 320/540 (Visual Workstatio <<
549 STA2X11-based (e.g. Northville <<
550 Moorestown MID devices <<
551 <<
552 64-bit platforms (CONFIG_64BIT=y): <<
553 Numascale NumaChip <<
554 ScaleMP vSMP <<
555 SGI Ultraviolet <<
556 <<
557 If you have one of these systems, or <<
558 generic distribution kernel, say Y h <<
559 <<
560 # This is an alphabetically sorted list of 64 <<
561 # Please maintain the alphabetic order if and <<
562 config X86_NUMACHIP <<
563 bool "Numascale NumaChip" <<
564 depends on X86_64 <<
565 depends on X86_EXTENDED_PLATFORM <<
566 depends on NUMA <<
567 depends on SMP <<
568 depends on X86_X2APIC <<
569 depends on PCI_MMCONFIG <<
570 help <<
571 Adds support for Numascale NumaChip <<
572 enable more than ~168 cores. <<
573 If you don't have one of these, you <<
574 <<
575 config X86_VSMP <<
576 bool "ScaleMP vSMP" <<
577 select HYPERVISOR_GUEST <<
578 select PARAVIRT <<
579 depends on X86_64 && PCI <<
580 depends on X86_EXTENDED_PLATFORM <<
581 depends on SMP <<
582 help <<
583 Support for ScaleMP vSMP systems. S <<
584 supposed to run on these EM64T-based <<
585 if you have one of these machines. <<
586 <<
587 config X86_UV <<
588 bool "SGI Ultraviolet" <<
589 depends on X86_64 <<
590 depends on X86_EXTENDED_PLATFORM <<
591 depends on NUMA <<
592 depends on EFI <<
593 depends on KEXEC_CORE <<
594 depends on X86_X2APIC <<
595 depends on PCI <<
596 help <<
597 This option is needed in order to su <<
598 If you don't have one of these, you <<
599 <<
600 # Following is an alphabetically sorted list o <<
601 # Please maintain the alphabetic order if and <<
602 <<
603 config X86_GOLDFISH <<
604 bool "Goldfish (Virtual Platform)" <<
605 depends on X86_EXTENDED_PLATFORM <<
606 help <<
607 Enable support for the Goldfish virt <<
608 for Android development. Unless you <<
609 Goldfish emulator say N here. <<
610 <<
611 config X86_INTEL_CE <<
612 bool "CE4100 TV platform" <<
613 depends on PCI <<
614 depends on PCI_GODIRECT <<
615 depends on X86_IO_APIC <<
616 depends on X86_32 <<
617 depends on X86_EXTENDED_PLATFORM <<
618 select X86_REBOOTFIXUPS <<
619 select OF <<
620 select OF_EARLY_FLATTREE <<
621 help <<
622 Select for the Intel CE media proces <<
623 This option compiles in support for <<
624 boxes and media devices. <<
625 <<
626 config X86_INTEL_MID <<
627 bool "Intel MID platform support" <<
628 depends on X86_EXTENDED_PLATFORM <<
629 depends on X86_PLATFORM_DEVICES <<
630 depends on PCI <<
631 depends on X86_64 || (PCI_GOANY && X86 <<
632 depends on X86_IO_APIC <<
633 select I2C <<
634 select DW_APB_TIMER <<
635 select INTEL_SCU_PCI <<
636 help <<
637 Select to build a kernel capable of <<
638 Internet Device) platform systems wh <<
639 interfaces. If you are building for <<
640 <<
641 Intel MID platforms are based on an <<
642 consume less power than most of the <<
643 <<
644 config X86_INTEL_QUARK <<
645 bool "Intel Quark platform support" <<
646 depends on X86_32 <<
647 depends on X86_EXTENDED_PLATFORM <<
648 depends on X86_PLATFORM_DEVICES <<
649 depends on X86_TSC <<
650 depends on PCI <<
651 depends on PCI_GOANY <<
652 depends on X86_IO_APIC <<
653 select IOSF_MBI <<
654 select INTEL_IMR <<
655 select COMMON_CLK <<
656 help <<
657 Select to include support for Quark <<
658 Say Y here if you have a Quark based <<
659 compatible Intel Galileo. <<
660 <<
661 config X86_INTEL_LPSS <<
662 bool "Intel Low Power Subsystem Suppor <<
663 depends on X86 && ACPI && PCI <<
664 select COMMON_CLK <<
665 select PINCTRL <<
666 select IOSF_MBI <<
667 help <<
668 Select to build support for Intel Lo <<
669 found on Intel Lynxpoint PCH. Select <<
670 things like clock tree (common clock <<
671 which are needed by the LPSS periphe <<
672 <<
673 config X86_AMD_PLATFORM_DEVICE <<
674 bool "AMD ACPI2Platform devices suppor <<
675 depends on ACPI <<
676 select COMMON_CLK <<
677 select PINCTRL <<
678 help <<
679 Select to interpret AMD specific ACP <<
680 such as I2C, UART, GPIO found on AMD <<
681 I2C and UART depend on COMMON_CLK to <<
682 implemented under PINCTRL subsystem. <<
683 <<
684 config IOSF_MBI <<
685 tristate "Intel SoC IOSF Sideband supp <<
686 depends on PCI <<
687 help <<
688 This option enables sideband registe <<
689 platforms. On these platforms the IO <<
690 MSR's for some register accesses, mo <<
691 and power. Drivers may query the ava <<
692 determine if they need the sideband <<
693 platforms. The sideband is available <<
694 This list is not meant to be exclusi <<
695 - BayTrail <<
696 - Braswell <<
697 - Quark <<
698 <<
699 You should say Y if you are running <<
700 <<
701 config IOSF_MBI_DEBUG <<
702 bool "Enable IOSF sideband access thro <<
703 depends on IOSF_MBI && DEBUG_FS <<
704 help <<
705 Select this option to expose the IOS <<
706 MDR, MCRX) through debugfs to write <<
707 different units on the SoC. This is <<
708 state information for debug and anal <<
709 mechanism, users of this option woul <<
710 device they want to access. <<
711 <<
712 If you don't require the option or a <<
713 <<
714 config X86_RDC321X <<
715 bool "RDC R-321x SoC" <<
716 depends on X86_32 <<
717 depends on X86_EXTENDED_PLATFORM <<
718 select M486 <<
719 select X86_REBOOTFIXUPS <<
720 help <<
721 This option is needed for RDC R-321x <<
722 as R-8610-(G). <<
723 If you don't have one of these chips <<
724 <<
725 config X86_32_NON_STANDARD <<
726 bool "Support non-standard 32-bit SMP <<
727 depends on X86_32 && SMP <<
728 depends on X86_EXTENDED_PLATFORM <<
729 help <<
730 This option compiles in the bigsmp a <<
731 subarchitectures. It is intended fo <<
732 kernel. If you select them all, kern <<
733 one and will fallback to default. <<
734 1125
735 # Alphabetically sorted list of Non standard 3 !! 1126 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1127 bool
>> 1128 select GENERIC_ISA_DMA
736 1129
737 config X86_SUPPORTS_MEMORY_FAILURE !! 1130 config HAVE_PLAT_DELAY
738 def_bool y !! 1131 bool
739 # MCE code calls memory_failure(): <<
740 depends on X86_MCE <<
741 # On 32-bit this adds too big of NODES <<
742 # On 32-bit SPARSEMEM adds too big of <<
743 depends on X86_64 || !SPARSEMEM <<
744 select ARCH_SUPPORTS_MEMORY_FAILURE <<
745 <<
746 config STA2X11 <<
747 bool "STA2X11 Companion Chip Support" <<
748 depends on X86_32_NON_STANDARD && PCI <<
749 select SWIOTLB <<
750 select MFD_STA2X11 <<
751 select GPIOLIB <<
752 help <<
753 This adds support for boards based o <<
754 a.k.a. "ConneXt". The chip is used i <<
755 PC chipset, so all "standard" periph <<
756 option is selected the kernel will s <<
757 standard PC machines. <<
758 <<
759 config X86_32_IRIS <<
760 tristate "Eurobraille/Iris poweroff mo <<
761 depends on X86_32 <<
762 help <<
763 The Iris machines from EuroBraille d <<
764 to shut themselves down properly. A <<
765 needed to do so, which is what this <<
766 kernel shutdown. <<
767 1132
768 This is only for Iris machines from !! 1133 config HAVE_PLAT_FW_INIT_CMDLINE
>> 1134 bool
769 1135
770 If unused, say N. !! 1136 config HAVE_PLAT_MEMCPY
>> 1137 bool
771 1138
772 config SCHED_OMIT_FRAME_POINTER !! 1139 config ISA_DMA_API
773 def_bool y !! 1140 bool
774 prompt "Single-depth WCHAN output" <<
775 depends on X86 <<
776 help <<
777 Calculate simpler /proc/<PID>/wchan <<
778 is disabled then wchan values will r <<
779 caller function. This provides more <<
780 at the expense of slightly more sche <<
781 1141
782 If in doubt, say "Y". !! 1142 config SYS_SUPPORTS_RELOCATABLE
>> 1143 bool
>> 1144 help
>> 1145 Selected if the platform supports relocating the kernel.
>> 1146 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1147 to allow access to command line and entropy sources.
783 1148
784 menuconfig HYPERVISOR_GUEST !! 1149 #
785 bool "Linux guest support" !! 1150 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1151 # answer,so we try hard to limit the available choices. Also the use of a
>> 1152 # choice statement should be more obvious to the user.
>> 1153 #
>> 1154 choice
>> 1155 prompt "Endianness selection"
786 help 1156 help
787 Say Y here to enable options for run !! 1157 Some MIPS machines can be configured for either little or big endian
788 visors. This option enables basic hy !! 1158 byte order. These modes require different kernels and a different
789 setup. !! 1159 Linux distribution. In general there is one preferred byteorder for a
>> 1160 particular system but some systems are just as commonly used in the
>> 1161 one or the other endianness.
>> 1162
>> 1163 config CPU_BIG_ENDIAN
>> 1164 bool "Big endian"
>> 1165 depends on SYS_SUPPORTS_BIG_ENDIAN
>> 1166
>> 1167 config CPU_LITTLE_ENDIAN
>> 1168 bool "Little endian"
>> 1169 depends on SYS_SUPPORTS_LITTLE_ENDIAN
790 1170
791 If you say N, all options in this su !! 1171 endchoice
792 disabled, and Linux guest support wo <<
793 1172
794 if HYPERVISOR_GUEST !! 1173 config EXPORT_UASM
>> 1174 bool
795 1175
796 config PARAVIRT !! 1176 config SYS_SUPPORTS_APM_EMULATION
797 bool "Enable paravirtualization code" !! 1177 bool
798 depends on HAVE_STATIC_CALL <<
799 help <<
800 This changes the kernel so it can mo <<
801 under a hypervisor, potentially impr <<
802 over full virtualization. However, <<
803 the kernel is theoretically slower a <<
804 1178
805 config PARAVIRT_XXL !! 1179 config SYS_SUPPORTS_BIG_ENDIAN
806 bool 1180 bool
807 1181
808 config PARAVIRT_DEBUG !! 1182 config SYS_SUPPORTS_LITTLE_ENDIAN
809 bool "paravirt-ops debugging" !! 1183 bool
810 depends on PARAVIRT && DEBUG_KERNEL <<
811 help <<
812 Enable to debug paravirt_ops interna <<
813 a paravirt_op is missing when it is <<
814 1184
815 config PARAVIRT_SPINLOCKS !! 1185 config MIPS_HUGE_TLB_SUPPORT
816 bool "Paravirtualization layer for spi !! 1186 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
817 depends on PARAVIRT && SMP <<
818 help <<
819 Paravirtualized spinlocks allow a pv <<
820 spinlock implementation with somethi <<
821 (for example, block the virtual CPU <<
822 1187
823 It has a minimal impact on native ke !! 1188 config IRQ_MSP_SLP
824 benefit on paravirtualized KVM / Xen !! 1189 bool
825 1190
826 If you are unsure how to answer this !! 1191 config IRQ_MSP_CIC
>> 1192 bool
827 1193
828 config X86_HV_CALLBACK_VECTOR !! 1194 config IRQ_TXX9
829 def_bool n !! 1195 bool
830 1196
831 source "arch/x86/xen/Kconfig" !! 1197 config IRQ_GT641XX
>> 1198 bool
832 1199
833 config KVM_GUEST !! 1200 config PCI_GT64XXX_PCI0
834 bool "KVM Guest support (including kvm !! 1201 bool
835 depends on PARAVIRT <<
836 select PARAVIRT_CLOCK <<
837 select ARCH_CPUIDLE_HALTPOLL <<
838 select X86_HV_CALLBACK_VECTOR <<
839 default y <<
840 help <<
841 This option enables various optimiza <<
842 hypervisor. It includes a paravirtua <<
843 of relying on a PIT (or probably oth <<
844 underlying device model, the host pr <<
845 timing infrastructure such as time o <<
846 1202
847 config ARCH_CPUIDLE_HALTPOLL !! 1203 config PCI_XTALK_BRIDGE
848 def_bool n !! 1204 bool
849 prompt "Disable host haltpoll when loa <<
850 help <<
851 If virtualized under KVM, disable ho <<
852 1205
853 config PVH !! 1206 config NO_EXCEPT_FILL
854 bool "Support for running PVH guests" !! 1207 bool
855 help <<
856 This option enables the PVH entry po <<
857 as specified in the x86/HVM direct b <<
858 <<
859 config PARAVIRT_TIME_ACCOUNTING <<
860 bool "Paravirtual steal time accountin <<
861 depends on PARAVIRT <<
862 help <<
863 Select this option to enable fine gr <<
864 accounting. Time spent executing oth <<
865 the current vCPU is discounted from <<
866 that, there can be a small performan <<
867 <<
868 If in doubt, say N here. <<
869 <<
870 config PARAVIRT_CLOCK <<
871 bool <<
872 <<
873 config JAILHOUSE_GUEST <<
874 bool "Jailhouse non-root cell support" <<
875 depends on X86_64 && PCI <<
876 select X86_PM_TIMER <<
877 help <<
878 This option allows to run Linux as g <<
879 cell. You can leave this option disa <<
880 Jailhouse and run Linux afterwards i <<
881 <<
882 config ACRN_GUEST <<
883 bool "ACRN Guest support" <<
884 depends on X86_64 <<
885 select X86_HV_CALLBACK_VECTOR <<
886 help <<
887 This option allows to run Linux as g <<
888 a flexible, lightweight reference op <<
889 real-time and safety-criticality in <<
890 IOT with small footprint and real-ti <<
891 found in https://projectacrn.org/. <<
892 <<
893 config INTEL_TDX_GUEST <<
894 bool "Intel TDX (Trust Domain Extensio <<
895 depends on X86_64 && CPU_SUP_INTEL <<
896 depends on X86_X2APIC <<
897 depends on EFI_STUB <<
898 select ARCH_HAS_CC_PLATFORM <<
899 select X86_MEM_ENCRYPT <<
900 select X86_MCE <<
901 select UNACCEPTED_MEMORY <<
902 help <<
903 Support running as a guest under Int <<
904 the guest kernel can not boot or run <<
905 TDX includes memory encryption and i <<
906 which protect the confidentiality an <<
907 memory contents and CPU state. TDX g <<
908 some attacks from the VMM. <<
909 <<
910 endif # HYPERVISOR_GUEST <<
911 <<
912 source "arch/x86/Kconfig.cpu" <<
913 <<
914 config HPET_TIMER <<
915 def_bool X86_64 <<
916 prompt "HPET Timer Support" if X86_32 <<
917 help <<
918 Use the IA-PC HPET (High Precision E <<
919 time in preference to the PIT and RT <<
920 present. <<
921 HPET is the next generation timer re <<
922 The HPET provides a stable time base <<
923 systems, unlike the TSC, but it is m <<
924 as it is off-chip. The interface us <<
925 in the HPET spec, revision 1. <<
926 <<
927 You can safely choose Y here. Howev <<
928 activated if the platform and the BI <<
929 Otherwise the 8254 will be used for <<
930 1208
931 Choose N to continue using the legac !! 1209 config MIPS_SPRAM
>> 1210 bool
932 1211
933 config HPET_EMULATE_RTC !! 1212 config SWAP_IO_SPACE
934 def_bool y !! 1213 bool
935 depends on HPET_TIMER && (RTC_DRV_CMOS <<
936 1214
937 # Mark as expert because too many people got i !! 1215 config SGI_HAS_INDYDOG
938 # The code disables itself when not needed. !! 1216 bool
939 config DMI <<
940 default y <<
941 select DMI_SCAN_MACHINE_NON_EFI_FALLBA <<
942 bool "Enable DMI scanning" if EXPERT <<
943 help <<
944 Enabled scanning of DMI to identify <<
945 here unless you have verified that y <<
946 affected by entries in the DMI black <<
947 BIOS code. <<
948 1217
949 config GART_IOMMU !! 1218 config SGI_HAS_HAL2
950 bool "Old AMD GART IOMMU support" !! 1219 bool
951 select IOMMU_HELPER <<
952 select SWIOTLB <<
953 depends on X86_64 && PCI && AMD_NB <<
954 help <<
955 Provides a driver for older AMD Athl <<
956 GART based hardware IOMMUs. <<
957 1220
958 The GART supports full DMA access fo !! 1221 config SGI_HAS_SEEQ
959 limitations, on systems with more th !! 1222 bool
960 for USB, sound, many IDE/SATA chipse <<
961 1223
962 Newer systems typically have a moder !! 1224 config SGI_HAS_WD93
963 the CONFIG_AMD_IOMMU=y config option !! 1225 bool
964 1226
965 In normal configurations this driver !! 1227 config SGI_HAS_ZILOG
966 there's more than 3 GB of memory and !! 1228 bool
967 32-bit limited device. <<
968 1229
969 If unsure, say Y. !! 1230 config SGI_HAS_I8042
>> 1231 bool
970 1232
971 config BOOT_VESA_SUPPORT !! 1233 config DEFAULT_SGI_PARTITION
972 bool 1234 bool
973 help <<
974 If true, at least one selected frame <<
975 of VESA video modes set at an early <<
976 1235
977 config MAXSMP !! 1236 config FW_ARC32
978 bool "Enable Maximum number of SMP Pro !! 1237 bool
979 depends on X86_64 && SMP && DEBUG_KERN <<
980 select CPUMASK_OFFSTACK <<
981 help <<
982 Enable maximum number of CPUS and NU <<
983 If unsure, say N. <<
984 1238
985 # !! 1239 config FW_SNIPROM
986 # The maximum number of CPUs supported: !! 1240 bool
987 # <<
988 # The main config value is NR_CPUS, which defa <<
989 # and which can be configured interactively in <<
990 # [NR_CPUS_RANGE_BEGIN ... NR_CPUS_RANGE_END] <<
991 # <<
992 # The ranges are different on 32-bit and 64-bi <<
993 # hardware capabilities and scalability featur <<
994 # <<
995 # ( If MAXSMP is enabled we just use the highe <<
996 # interactive configuration. ) <<
997 # <<
998 1241
999 config NR_CPUS_RANGE_BEGIN !! 1242 config BOOT_ELF32
1000 int !! 1243 bool
1001 default NR_CPUS_RANGE_END if MAXSMP <<
1002 default 1 if !SMP <<
1003 default 2 <<
1004 1244
1005 config NR_CPUS_RANGE_END !! 1245 config MIPS_L1_CACHE_SHIFT_4
1006 int !! 1246 bool
1007 depends on X86_32 <<
1008 default 64 if SMP && X86_BIGSMP <<
1009 default 8 if SMP && !X86_BIGSMP <<
1010 default 1 if !SMP <<
1011 1247
1012 config NR_CPUS_RANGE_END !! 1248 config MIPS_L1_CACHE_SHIFT_5
1013 int !! 1249 bool
1014 depends on X86_64 <<
1015 default 8192 if SMP && CPUMASK_OFFST <<
1016 default 512 if SMP && !CPUMASK_OFFS <<
1017 default 1 if !SMP <<
1018 1250
1019 config NR_CPUS_DEFAULT !! 1251 config MIPS_L1_CACHE_SHIFT_6
1020 int !! 1252 bool
1021 depends on X86_32 <<
1022 default 32 if X86_BIGSMP <<
1023 default 8 if SMP <<
1024 default 1 if !SMP <<
1025 1253
1026 config NR_CPUS_DEFAULT !! 1254 config MIPS_L1_CACHE_SHIFT_7
1027 int !! 1255 bool
1028 depends on X86_64 <<
1029 default 8192 if MAXSMP <<
1030 default 64 if SMP <<
1031 default 1 if !SMP <<
1032 1256
1033 config NR_CPUS !! 1257 config MIPS_L1_CACHE_SHIFT
1034 int "Maximum number of CPUs" if SMP & !! 1258 int
1035 range NR_CPUS_RANGE_BEGIN NR_CPUS_RAN !! 1259 default "7" if MIPS_L1_CACHE_SHIFT_7
1036 default NR_CPUS_DEFAULT !! 1260 default "6" if MIPS_L1_CACHE_SHIFT_6
1037 help !! 1261 default "5" if MIPS_L1_CACHE_SHIFT_5
1038 This allows you to specify the maxi !! 1262 default "4" if MIPS_L1_CACHE_SHIFT_4
1039 kernel will support. If CPUMASK_OF !! 1263 default "5"
1040 supported value is 8192, otherwise <<
1041 minimum value which makes sense is <<
1042 1264
1043 This is purely to save memory: each !! 1265 config ARC_CMDLINE_ONLY
1044 to the kernel image. !! 1266 bool
1045 1267
1046 config SCHED_CLUSTER !! 1268 config ARC_CONSOLE
1047 bool "Cluster scheduler support" !! 1269 bool "ARC console support"
1048 depends on SMP !! 1270 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
1049 default y <<
1050 help <<
1051 Cluster scheduler support improves <<
1052 making when dealing with machines t <<
1053 Cluster usually means a couple of C <<
1054 by sharing mid-level caches, last-l <<
1055 busses. <<
1056 1271
1057 config SCHED_SMT !! 1272 config ARC_MEMORY
1058 def_bool y if SMP !! 1273 bool
1059 1274
1060 config SCHED_MC !! 1275 config ARC_PROMLIB
1061 def_bool y !! 1276 bool
1062 prompt "Multi-core scheduler support" <<
1063 depends on SMP <<
1064 help <<
1065 Multi-core scheduler support improv <<
1066 making when dealing with multi-core <<
1067 increased overhead in some places. <<
1068 1277
1069 config SCHED_MC_PRIO !! 1278 config FW_ARC64
1070 bool "CPU core priorities scheduler s !! 1279 bool
1071 depends on SCHED_MC <<
1072 select X86_INTEL_PSTATE if CPU_SUP_IN <<
1073 select X86_AMD_PSTATE if CPU_SUP_AMD <<
1074 select CPU_FREQ <<
1075 default y <<
1076 help <<
1077 Intel Turbo Boost Max Technology 3. <<
1078 core ordering determined at manufac <<
1079 certain cores to reach higher turbo <<
1080 single threaded workloads) than oth <<
1081 1280
1082 Enabling this kernel feature teache !! 1281 config BOOT_ELF64
1083 the TBM3 (aka ITMT) priority order !! 1282 bool
1084 scheduler's CPU selection logic acc <<
1085 overall system performance can be a <<
1086 1283
1087 This feature will have no effect on !! 1284 menu "CPU selection"
1088 1285
1089 If unsure say Y here. !! 1286 choice
>> 1287 prompt "CPU type"
>> 1288 default CPU_R4X00
1090 1289
1091 config UP_LATE_INIT !! 1290 config CPU_LOONGSON64
1092 def_bool y !! 1291 bool "Loongson 64-bit CPU"
1093 depends on !SMP && X86_LOCAL_APIC !! 1292 depends on SYS_HAS_CPU_LOONGSON64
>> 1293 select ARCH_HAS_PHYS_TO_DMA
>> 1294 select CPU_MIPSR2
>> 1295 select CPU_HAS_PREFETCH
>> 1296 select CPU_SUPPORTS_64BIT_KERNEL
>> 1297 select CPU_SUPPORTS_HIGHMEM
>> 1298 select CPU_SUPPORTS_HUGEPAGES
>> 1299 select CPU_SUPPORTS_MSA
>> 1300 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1301 select CPU_MIPSR2_IRQ_VI
>> 1302 select WEAK_ORDERING
>> 1303 select WEAK_REORDERING_BEYOND_LLSC
>> 1304 select MIPS_ASID_BITS_VARIABLE
>> 1305 select MIPS_PGD_C0_CONTEXT
>> 1306 select MIPS_L1_CACHE_SHIFT_6
>> 1307 select MIPS_FP_SUPPORT
>> 1308 select GPIOLIB
>> 1309 select SWIOTLB
>> 1310 select HAVE_KVM
>> 1311 help
>> 1312 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1313 cores implements the MIPS64R2 instruction set with many extensions,
>> 1314 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1315 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1316 Loongson-2E/2F is not covered here and will be removed in future.
1094 1317
1095 config X86_UP_APIC !! 1318 config LOONGSON3_ENHANCEMENT
1096 bool "Local APIC support on uniproces !! 1319 bool "New Loongson-3 CPU Enhancements"
1097 default PCI_MSI !! 1320 default n
1098 depends on X86_32 && !SMP && !X86_32_ !! 1321 depends on CPU_LOONGSON64
1099 help !! 1322 help
1100 A local APIC (Advanced Programmable !! 1323 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1101 integrated interrupt controller in !! 1324 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1102 system which has a processor with a !! 1325 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1103 enable and use it. If you say Y her !! 1326 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1104 have a local APIC, then the kernel !! 1327 Fast TLB refill support, etc.
1105 all. The local APIC supports CPU-ge <<
1106 performance counters), and the NMI <<
1107 lockups. <<
1108 <<
1109 config X86_UP_IOAPIC <<
1110 bool "IO-APIC support on uniprocessor <<
1111 depends on X86_UP_APIC <<
1112 help <<
1113 An IO-APIC (I/O Advanced Programmab <<
1114 SMP-capable replacement for PC-styl <<
1115 SMP systems and many recent uniproc <<
1116 <<
1117 If you have a single-CPU system wit <<
1118 to use it. If you say Y here even t <<
1119 an IO-APIC, then the kernel will st <<
1120 1328
1121 config X86_LOCAL_APIC !! 1329 This option enable those enhancements which are not probed at run
1122 def_bool y !! 1330 time. If you want a generic kernel to run on all Loongson 3 machines,
1123 depends on X86_64 || SMP || X86_32_NO !! 1331 please say 'N' here. If you want a high-performance kernel to run on
1124 select IRQ_DOMAIN_HIERARCHY !! 1332 new Loongson-3 machines only, please say 'Y' here.
1125 1333
1126 config ACPI_MADT_WAKEUP !! 1334 config CPU_LOONGSON3_WORKAROUNDS
1127 def_bool y !! 1335 bool "Loongson-3 LLSC Workarounds"
1128 depends on X86_64 !! 1336 default y if SMP
1129 depends on ACPI !! 1337 depends on CPU_LOONGSON64
1130 depends on SMP !! 1338 help
1131 depends on X86_LOCAL_APIC !! 1339 Loongson-3 processors have the llsc issues which require workarounds.
>> 1340 Without workarounds the system may hang unexpectedly.
1132 1341
1133 config X86_IO_APIC !! 1342 Say Y, unless you know what you are doing.
1134 def_bool y <<
1135 depends on X86_LOCAL_APIC || X86_UP_I <<
1136 1343
1137 config X86_REROUTE_FOR_BROKEN_BOOT_IRQS !! 1344 config CPU_LOONGSON3_CPUCFG_EMULATION
1138 bool "Reroute for broken boot IRQs" !! 1345 bool "Emulate the CPUCFG instruction on older Loongson cores"
1139 depends on X86_IO_APIC <<
1140 help <<
1141 This option enables a workaround th <<
1142 spurious interrupts. This is recomm <<
1143 interrupt handling is used on syste <<
1144 superfluous "boot interrupts" canno <<
1145 <<
1146 Some chipsets generate a legacy INT <<
1147 entry in the chipset's IO-APIC is m <<
1148 kernel does during interrupt handli <<
1149 boot IRQ generation cannot be disab <<
1150 the original IRQ line masked so tha <<
1151 IRQ" is delivered to the CPUs. The <<
1152 kernel to set up the IRQ handler on <<
1153 way only one interrupt is delivered <<
1154 the spurious second interrupt may c <<
1155 down (vital) interrupt lines. <<
1156 <<
1157 Only affects "broken" chipsets. Int <<
1158 increased on these systems. <<
1159 <<
1160 config X86_MCE <<
1161 bool "Machine Check / overheating rep <<
1162 select GENERIC_ALLOCATOR <<
1163 default y 1346 default y
>> 1347 depends on CPU_LOONGSON64
1164 help 1348 help
1165 Machine Check support allows the pr !! 1349 Loongson-3A R4 and newer have the CPUCFG instruction available for
1166 kernel if it detects a problem (e.g !! 1350 userland to query CPU capabilities, much like CPUID on x86. This
1167 The action the kernel takes depends !! 1351 option provides emulation of the instruction on older Loongson
1168 ranging from warning messages to ha !! 1352 cores, back to Loongson-3A1000.
1169 <<
1170 config X86_MCELOG_LEGACY <<
1171 bool "Support for deprecated /dev/mce <<
1172 depends on X86_MCE <<
1173 help <<
1174 Enable support for /dev/mcelog whic <<
1175 userspace logging daemon. Consider <<
1176 rasdaemon solution. <<
1177 1353
1178 config X86_MCE_INTEL !! 1354 If unsure, please say Y.
1179 def_bool y <<
1180 prompt "Intel MCE features" <<
1181 depends on X86_MCE && X86_LOCAL_APIC <<
1182 help <<
1183 Additional support for intel specif <<
1184 the thermal monitor. <<
1185 1355
1186 config X86_MCE_AMD !! 1356 config CPU_LOONGSON2E
1187 def_bool y !! 1357 bool "Loongson 2E"
1188 prompt "AMD MCE features" !! 1358 depends on SYS_HAS_CPU_LOONGSON2E
1189 depends on X86_MCE && X86_LOCAL_APIC !! 1359 select CPU_LOONGSON2EF
1190 help 1360 help
1191 Additional support for AMD specific !! 1361 The Loongson 2E processor implements the MIPS III instruction set
1192 the DRAM Error Threshold. !! 1362 with many extensions.
1193 1363
1194 config X86_ANCIENT_MCE !! 1364 It has an internal FPGA northbridge, which is compatible to
1195 bool "Support for old Pentium 5 / Win !! 1365 bonito64.
1196 depends on X86_32 && X86_MCE <<
1197 help <<
1198 Include support for machine check h <<
1199 systems. These typically need to be <<
1200 line. <<
1201 <<
1202 config X86_MCE_THRESHOLD <<
1203 depends on X86_MCE_AMD || X86_MCE_INT <<
1204 def_bool y <<
1205 1366
1206 config X86_MCE_INJECT !! 1367 config CPU_LOONGSON2F
1207 depends on X86_MCE && X86_LOCAL_APIC !! 1368 bool "Loongson 2F"
1208 tristate "Machine check injector supp !! 1369 depends on SYS_HAS_CPU_LOONGSON2F
>> 1370 select CPU_LOONGSON2EF
>> 1371 select GPIOLIB
1209 help 1372 help
1210 Provide support for injecting machi !! 1373 The Loongson 2F processor implements the MIPS III instruction set
1211 If you don't know what a machine ch !! 1374 with many extensions.
1212 QA it is safe to say n. <<
1213 1375
1214 source "arch/x86/events/Kconfig" !! 1376 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1377 have a similar programming interface with FPGA northbridge used in
>> 1378 Loongson2E.
>> 1379
>> 1380 config CPU_LOONGSON1B
>> 1381 bool "Loongson 1B"
>> 1382 depends on SYS_HAS_CPU_LOONGSON1B
>> 1383 select CPU_LOONGSON32
>> 1384 select LEDS_GPIO_REGISTER
>> 1385 help
>> 1386 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1387 Release 1 instruction set and part of the MIPS32 Release 2
>> 1388 instruction set.
>> 1389
>> 1390 config CPU_LOONGSON1C
>> 1391 bool "Loongson 1C"
>> 1392 depends on SYS_HAS_CPU_LOONGSON1C
>> 1393 select CPU_LOONGSON32
>> 1394 select LEDS_GPIO_REGISTER
>> 1395 help
>> 1396 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1397 Release 1 instruction set and part of the MIPS32 Release 2
>> 1398 instruction set.
>> 1399
>> 1400 config CPU_MIPS32_R1
>> 1401 bool "MIPS32 Release 1"
>> 1402 depends on SYS_HAS_CPU_MIPS32_R1
>> 1403 select CPU_HAS_PREFETCH
>> 1404 select CPU_SUPPORTS_32BIT_KERNEL
>> 1405 select CPU_SUPPORTS_HIGHMEM
>> 1406 help
>> 1407 Choose this option to build a kernel for release 1 or later of the
>> 1408 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1409 MIPS processor are based on a MIPS32 processor. If you know the
>> 1410 specific type of processor in your system, choose those that one
>> 1411 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1412 Release 2 of the MIPS32 architecture is available since several
>> 1413 years so chances are you even have a MIPS32 Release 2 processor
>> 1414 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1415 performance.
1215 1416
1216 config X86_LEGACY_VM86 !! 1417 config CPU_MIPS32_R2
1217 bool "Legacy VM86 support" !! 1418 bool "MIPS32 Release 2"
1218 depends on X86_32 !! 1419 depends on SYS_HAS_CPU_MIPS32_R2
1219 help !! 1420 select CPU_HAS_PREFETCH
1220 This option allows user programs to !! 1421 select CPU_SUPPORTS_32BIT_KERNEL
1221 mode, which is an 80286-era approxi !! 1422 select CPU_SUPPORTS_HIGHMEM
>> 1423 select CPU_SUPPORTS_MSA
>> 1424 select HAVE_KVM
>> 1425 help
>> 1426 Choose this option to build a kernel for release 2 or later of the
>> 1427 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1428 MIPS processor are based on a MIPS32 processor. If you know the
>> 1429 specific type of processor in your system, choose those that one
>> 1430 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1431
>> 1432 config CPU_MIPS32_R5
>> 1433 bool "MIPS32 Release 5"
>> 1434 depends on SYS_HAS_CPU_MIPS32_R5
>> 1435 select CPU_HAS_PREFETCH
>> 1436 select CPU_SUPPORTS_32BIT_KERNEL
>> 1437 select CPU_SUPPORTS_HIGHMEM
>> 1438 select CPU_SUPPORTS_MSA
>> 1439 select HAVE_KVM
>> 1440 select MIPS_O32_FP64_SUPPORT
>> 1441 help
>> 1442 Choose this option to build a kernel for release 5 or later of the
>> 1443 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1444 family, are based on a MIPS32r5 processor. If you own an older
>> 1445 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1446
>> 1447 config CPU_MIPS32_R6
>> 1448 bool "MIPS32 Release 6"
>> 1449 depends on SYS_HAS_CPU_MIPS32_R6
>> 1450 select CPU_HAS_PREFETCH
>> 1451 select CPU_NO_LOAD_STORE_LR
>> 1452 select CPU_SUPPORTS_32BIT_KERNEL
>> 1453 select CPU_SUPPORTS_HIGHMEM
>> 1454 select CPU_SUPPORTS_MSA
>> 1455 select HAVE_KVM
>> 1456 select MIPS_O32_FP64_SUPPORT
>> 1457 help
>> 1458 Choose this option to build a kernel for release 6 or later of the
>> 1459 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1460 family, are based on a MIPS32r6 processor. If you own an older
>> 1461 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1462
>> 1463 config CPU_MIPS64_R1
>> 1464 bool "MIPS64 Release 1"
>> 1465 depends on SYS_HAS_CPU_MIPS64_R1
>> 1466 select CPU_HAS_PREFETCH
>> 1467 select CPU_SUPPORTS_32BIT_KERNEL
>> 1468 select CPU_SUPPORTS_64BIT_KERNEL
>> 1469 select CPU_SUPPORTS_HIGHMEM
>> 1470 select CPU_SUPPORTS_HUGEPAGES
>> 1471 help
>> 1472 Choose this option to build a kernel for release 1 or later of the
>> 1473 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1474 MIPS processor are based on a MIPS64 processor. If you know the
>> 1475 specific type of processor in your system, choose those that one
>> 1476 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1477 Release 2 of the MIPS64 architecture is available since several
>> 1478 years so chances are you even have a MIPS64 Release 2 processor
>> 1479 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1480 performance.
1222 1481
1223 Some very old versions of X and/or !! 1482 config CPU_MIPS64_R2
1224 for user mode setting. Similarly, !! 1483 bool "MIPS64 Release 2"
1225 available to accelerate real mode D !! 1484 depends on SYS_HAS_CPU_MIPS64_R2
1226 recent version of DOSEMU, X, or vbe !! 1485 select CPU_HAS_PREFETCH
1227 functional even without kernel VM86 !! 1486 select CPU_SUPPORTS_32BIT_KERNEL
1228 fall back to software emulation. Ne !! 1487 select CPU_SUPPORTS_64BIT_KERNEL
1229 a 16-bit DOS program where 16-bit p !! 1488 select CPU_SUPPORTS_HIGHMEM
1230 mode might be faster than emulation !! 1489 select CPU_SUPPORTS_HUGEPAGES
1231 enable this option. !! 1490 select CPU_SUPPORTS_MSA
>> 1491 select HAVE_KVM
>> 1492 help
>> 1493 Choose this option to build a kernel for release 2 or later of the
>> 1494 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1495 MIPS processor are based on a MIPS64 processor. If you know the
>> 1496 specific type of processor in your system, choose those that one
>> 1497 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1498
>> 1499 config CPU_MIPS64_R5
>> 1500 bool "MIPS64 Release 5"
>> 1501 depends on SYS_HAS_CPU_MIPS64_R5
>> 1502 select CPU_HAS_PREFETCH
>> 1503 select CPU_SUPPORTS_32BIT_KERNEL
>> 1504 select CPU_SUPPORTS_64BIT_KERNEL
>> 1505 select CPU_SUPPORTS_HIGHMEM
>> 1506 select CPU_SUPPORTS_HUGEPAGES
>> 1507 select CPU_SUPPORTS_MSA
>> 1508 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1509 select HAVE_KVM
>> 1510 help
>> 1511 Choose this option to build a kernel for release 5 or later of the
>> 1512 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1513 release partly implementing release 6 features. Though there is no
>> 1514 any hardware known to be based on this release.
>> 1515
>> 1516 config CPU_MIPS64_R6
>> 1517 bool "MIPS64 Release 6"
>> 1518 depends on SYS_HAS_CPU_MIPS64_R6
>> 1519 select CPU_HAS_PREFETCH
>> 1520 select CPU_NO_LOAD_STORE_LR
>> 1521 select CPU_SUPPORTS_32BIT_KERNEL
>> 1522 select CPU_SUPPORTS_64BIT_KERNEL
>> 1523 select CPU_SUPPORTS_HIGHMEM
>> 1524 select CPU_SUPPORTS_HUGEPAGES
>> 1525 select CPU_SUPPORTS_MSA
>> 1526 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1527 select HAVE_KVM
>> 1528 help
>> 1529 Choose this option to build a kernel for release 6 or later of the
>> 1530 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1531 family, are based on a MIPS64r6 processor. If you own an older
>> 1532 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1533
>> 1534 config CPU_P5600
>> 1535 bool "MIPS Warrior P5600"
>> 1536 depends on SYS_HAS_CPU_P5600
>> 1537 select CPU_HAS_PREFETCH
>> 1538 select CPU_SUPPORTS_32BIT_KERNEL
>> 1539 select CPU_SUPPORTS_HIGHMEM
>> 1540 select CPU_SUPPORTS_MSA
>> 1541 select CPU_SUPPORTS_CPUFREQ
>> 1542 select CPU_MIPSR2_IRQ_VI
>> 1543 select CPU_MIPSR2_IRQ_EI
>> 1544 select HAVE_KVM
>> 1545 select MIPS_O32_FP64_SUPPORT
>> 1546 help
>> 1547 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1548 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1549 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1550 level features like up to six P5600 calculation cores, CM2 with L2
>> 1551 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1552 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1553 eJTAG and PDtrace.
>> 1554
>> 1555 config CPU_R3000
>> 1556 bool "R3000"
>> 1557 depends on SYS_HAS_CPU_R3000
>> 1558 select CPU_HAS_WB
>> 1559 select CPU_R3K_TLB
>> 1560 select CPU_SUPPORTS_32BIT_KERNEL
>> 1561 select CPU_SUPPORTS_HIGHMEM
>> 1562 help
>> 1563 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1564 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1565 *not* work on R4000 machines and vice versa. However, since most
>> 1566 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1567 might be a safe bet. If the resulting kernel does not work,
>> 1568 try to recompile with R3000.
>> 1569
>> 1570 config CPU_R4300
>> 1571 bool "R4300"
>> 1572 depends on SYS_HAS_CPU_R4300
>> 1573 select CPU_SUPPORTS_32BIT_KERNEL
>> 1574 select CPU_SUPPORTS_64BIT_KERNEL
>> 1575 help
>> 1576 MIPS Technologies R4300-series processors.
>> 1577
>> 1578 config CPU_R4X00
>> 1579 bool "R4x00"
>> 1580 depends on SYS_HAS_CPU_R4X00
>> 1581 select CPU_SUPPORTS_32BIT_KERNEL
>> 1582 select CPU_SUPPORTS_64BIT_KERNEL
>> 1583 select CPU_SUPPORTS_HUGEPAGES
>> 1584 help
>> 1585 MIPS Technologies R4000-series processors other than 4300, including
>> 1586 the R4000, R4400, R4600, and 4700.
>> 1587
>> 1588 config CPU_TX49XX
>> 1589 bool "R49XX"
>> 1590 depends on SYS_HAS_CPU_TX49XX
>> 1591 select CPU_HAS_PREFETCH
>> 1592 select CPU_SUPPORTS_32BIT_KERNEL
>> 1593 select CPU_SUPPORTS_64BIT_KERNEL
>> 1594 select CPU_SUPPORTS_HUGEPAGES
>> 1595
>> 1596 config CPU_R5000
>> 1597 bool "R5000"
>> 1598 depends on SYS_HAS_CPU_R5000
>> 1599 select CPU_SUPPORTS_32BIT_KERNEL
>> 1600 select CPU_SUPPORTS_64BIT_KERNEL
>> 1601 select CPU_SUPPORTS_HUGEPAGES
>> 1602 help
>> 1603 MIPS Technologies R5000-series processors other than the Nevada.
>> 1604
>> 1605 config CPU_R5500
>> 1606 bool "R5500"
>> 1607 depends on SYS_HAS_CPU_R5500
>> 1608 select CPU_SUPPORTS_32BIT_KERNEL
>> 1609 select CPU_SUPPORTS_64BIT_KERNEL
>> 1610 select CPU_SUPPORTS_HUGEPAGES
>> 1611 help
>> 1612 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1613 instruction set.
>> 1614
>> 1615 config CPU_NEVADA
>> 1616 bool "RM52xx"
>> 1617 depends on SYS_HAS_CPU_NEVADA
>> 1618 select CPU_SUPPORTS_32BIT_KERNEL
>> 1619 select CPU_SUPPORTS_64BIT_KERNEL
>> 1620 select CPU_SUPPORTS_HUGEPAGES
>> 1621 help
>> 1622 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1623
>> 1624 config CPU_R10000
>> 1625 bool "R10000"
>> 1626 depends on SYS_HAS_CPU_R10000
>> 1627 select CPU_HAS_PREFETCH
>> 1628 select CPU_SUPPORTS_32BIT_KERNEL
>> 1629 select CPU_SUPPORTS_64BIT_KERNEL
>> 1630 select CPU_SUPPORTS_HIGHMEM
>> 1631 select CPU_SUPPORTS_HUGEPAGES
>> 1632 help
>> 1633 MIPS Technologies R10000-series processors.
>> 1634
>> 1635 config CPU_RM7000
>> 1636 bool "RM7000"
>> 1637 depends on SYS_HAS_CPU_RM7000
>> 1638 select CPU_HAS_PREFETCH
>> 1639 select CPU_SUPPORTS_32BIT_KERNEL
>> 1640 select CPU_SUPPORTS_64BIT_KERNEL
>> 1641 select CPU_SUPPORTS_HIGHMEM
>> 1642 select CPU_SUPPORTS_HUGEPAGES
>> 1643
>> 1644 config CPU_SB1
>> 1645 bool "SB1"
>> 1646 depends on SYS_HAS_CPU_SB1
>> 1647 select CPU_SUPPORTS_32BIT_KERNEL
>> 1648 select CPU_SUPPORTS_64BIT_KERNEL
>> 1649 select CPU_SUPPORTS_HIGHMEM
>> 1650 select CPU_SUPPORTS_HUGEPAGES
>> 1651 select WEAK_ORDERING
>> 1652
>> 1653 config CPU_CAVIUM_OCTEON
>> 1654 bool "Cavium Octeon processor"
>> 1655 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1656 select CPU_HAS_PREFETCH
>> 1657 select CPU_SUPPORTS_64BIT_KERNEL
>> 1658 select WEAK_ORDERING
>> 1659 select CPU_SUPPORTS_HIGHMEM
>> 1660 select CPU_SUPPORTS_HUGEPAGES
>> 1661 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1662 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1663 select MIPS_L1_CACHE_SHIFT_7
>> 1664 select HAVE_KVM
>> 1665 help
>> 1666 The Cavium Octeon processor is a highly integrated chip containing
>> 1667 many ethernet hardware widgets for networking tasks. The processor
>> 1668 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1669 Full details can be found at http://www.caviumnetworks.com.
>> 1670
>> 1671 config CPU_BMIPS
>> 1672 bool "Broadcom BMIPS"
>> 1673 depends on SYS_HAS_CPU_BMIPS
>> 1674 select CPU_MIPS32
>> 1675 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1676 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1677 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1678 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1679 select CPU_SUPPORTS_32BIT_KERNEL
>> 1680 select DMA_NONCOHERENT
>> 1681 select IRQ_MIPS_CPU
>> 1682 select SWAP_IO_SPACE
>> 1683 select WEAK_ORDERING
>> 1684 select CPU_SUPPORTS_HIGHMEM
>> 1685 select CPU_HAS_PREFETCH
>> 1686 select CPU_SUPPORTS_CPUFREQ
>> 1687 select MIPS_EXTERNAL_TIMER
>> 1688 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 1689 help
>> 1690 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
1232 1691
1233 Note that any app that works on a 6 !! 1692 endchoice
1234 need this option, as 64-bit kernels <<
1235 V8086 mode. This option is also unr <<
1236 mode and is not needed to run most <<
1237 1693
1238 Enabling this option increases the !! 1694 config CPU_MIPS32_3_5_FEATURES
1239 and slows down exception handling a !! 1695 bool "MIPS32 Release 3.5 Features"
>> 1696 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1697 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1698 CPU_P5600
>> 1699 help
>> 1700 Choose this option to build a kernel for release 2 or later of the
>> 1701 MIPS32 architecture including features from the 3.5 release such as
>> 1702 support for Enhanced Virtual Addressing (EVA).
>> 1703
>> 1704 config CPU_MIPS32_3_5_EVA
>> 1705 bool "Enhanced Virtual Addressing (EVA)"
>> 1706 depends on CPU_MIPS32_3_5_FEATURES
>> 1707 select EVA
>> 1708 default y
>> 1709 help
>> 1710 Choose this option if you want to enable the Enhanced Virtual
>> 1711 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1712 One of its primary benefits is an increase in the maximum size
>> 1713 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1714
>> 1715 config CPU_MIPS32_R5_FEATURES
>> 1716 bool "MIPS32 Release 5 Features"
>> 1717 depends on SYS_HAS_CPU_MIPS32_R5
>> 1718 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1719 help
>> 1720 Choose this option to build a kernel for release 2 or later of the
>> 1721 MIPS32 architecture including features from release 5 such as
>> 1722 support for Extended Physical Addressing (XPA).
>> 1723
>> 1724 config CPU_MIPS32_R5_XPA
>> 1725 bool "Extended Physical Addressing (XPA)"
>> 1726 depends on CPU_MIPS32_R5_FEATURES
>> 1727 depends on !EVA
>> 1728 depends on !PAGE_SIZE_4KB
>> 1729 depends on SYS_SUPPORTS_HIGHMEM
>> 1730 select XPA
>> 1731 select HIGHMEM
>> 1732 select PHYS_ADDR_T_64BIT
>> 1733 default n
>> 1734 help
>> 1735 Choose this option if you want to enable the Extended Physical
>> 1736 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1737 benefit is to increase physical addressing equal to or greater
>> 1738 than 40 bits. Note that this has the side effect of turning on
>> 1739 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1740 If unsure, say 'N' here.
1240 1741
1241 If unsure, say N here. !! 1742 if CPU_LOONGSON2F
>> 1743 config CPU_NOP_WORKAROUNDS
>> 1744 bool
1242 1745
1243 config VM86 !! 1746 config CPU_JUMP_WORKAROUNDS
1244 bool 1747 bool
1245 default X86_LEGACY_VM86 <<
1246 1748
1247 config X86_16BIT !! 1749 config CPU_LOONGSON2F_WORKAROUNDS
1248 bool "Enable support for 16-bit segme !! 1750 bool "Loongson 2F Workarounds"
1249 default y 1751 default y
1250 depends on MODIFY_LDT_SYSCALL !! 1752 select CPU_NOP_WORKAROUNDS
>> 1753 select CPU_JUMP_WORKAROUNDS
1251 help 1754 help
1252 This option is required by programs !! 1755 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1253 protected mode legacy code on x86 p !! 1756 require workarounds. Without workarounds the system may hang
1254 this option saves about 300 bytes o !! 1757 unexpectedly. For more information please refer to the gas
1255 plus 16K runtime memory on x86-64, !! 1758 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1759
>> 1760 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1761 are needed. The workarounds have no significant side effect on them
>> 1762 but may decrease the performance of the system so this option should
>> 1763 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1764 systems.
1256 1765
1257 config X86_ESPFIX32 !! 1766 If unsure, please say Y.
1258 def_bool y !! 1767 endif # CPU_LOONGSON2F
1259 depends on X86_16BIT && X86_32 <<
1260 1768
1261 config X86_ESPFIX64 !! 1769 config SYS_SUPPORTS_ZBOOT
1262 def_bool y !! 1770 bool
1263 depends on X86_16BIT && X86_64 !! 1771 select HAVE_KERNEL_GZIP
>> 1772 select HAVE_KERNEL_BZIP2
>> 1773 select HAVE_KERNEL_LZ4
>> 1774 select HAVE_KERNEL_LZMA
>> 1775 select HAVE_KERNEL_LZO
>> 1776 select HAVE_KERNEL_XZ
>> 1777 select HAVE_KERNEL_ZSTD
1264 1778
1265 config X86_VSYSCALL_EMULATION !! 1779 config SYS_SUPPORTS_ZBOOT_UART16550
1266 bool "Enable vsyscall emulation" if E !! 1780 bool
1267 default y !! 1781 select SYS_SUPPORTS_ZBOOT
1268 depends on X86_64 <<
1269 help <<
1270 This enables emulation of the legac <<
1271 it is roughly equivalent to booting <<
1272 that it will also disable the helpf <<
1273 tries to use a vsyscall. With this <<
1274 programs will just segfault, citing <<
1275 0xffffffffff600?00. <<
1276 1782
1277 This option is required by many pro !! 1783 config SYS_SUPPORTS_ZBOOT_UART_PROM
1278 care should be used even with newer !! 1784 bool
>> 1785 select SYS_SUPPORTS_ZBOOT
1279 1786
1280 Disabling this option saves about 7 !! 1787 config CPU_LOONGSON2EF
1281 possibly 4K of additional runtime p !! 1788 bool
>> 1789 select CPU_SUPPORTS_32BIT_KERNEL
>> 1790 select CPU_SUPPORTS_64BIT_KERNEL
>> 1791 select CPU_SUPPORTS_HIGHMEM
>> 1792 select CPU_SUPPORTS_HUGEPAGES
>> 1793 select ARCH_HAS_PHYS_TO_DMA
1282 1794
1283 config X86_IOPL_IOPERM !! 1795 config CPU_LOONGSON32
1284 bool "IOPERM and IOPL Emulation" !! 1796 bool
1285 default y !! 1797 select CPU_MIPS32
1286 help !! 1798 select CPU_MIPSR2
1287 This enables the ioperm() and iopl( !! 1799 select CPU_HAS_PREFETCH
1288 for legacy applications. !! 1800 select CPU_SUPPORTS_32BIT_KERNEL
>> 1801 select CPU_SUPPORTS_HIGHMEM
>> 1802 select CPU_SUPPORTS_CPUFREQ
1289 1803
1290 Legacy IOPL support is an overbroad !! 1804 config CPU_BMIPS32_3300
1291 space aside of accessing all 65536 !! 1805 select SMP_UP if SMP
1292 interrupts. To gain this access the !! 1806 bool
1293 capabilities and permission from po <<
1294 modules. <<
1295 <<
1296 The emulation restricts the functio <<
1297 only allowing the full range I/O po <<
1298 ability to disable interrupts from <<
1299 granted if the hardware IOPL mechan <<
1300 <<
1301 config TOSHIBA <<
1302 tristate "Toshiba Laptop support" <<
1303 depends on X86_32 <<
1304 help <<
1305 This adds a driver to safely access <<
1306 the CPU on Toshiba portables with a <<
1307 not work on models with a Phoenix B <<
1308 is used to set the BIOS and power s <<
1309 <<
1310 For information on utilities to mak <<
1311 Toshiba Linux utilities web site at <<
1312 <http://www.buzzard.org.uk/toshiba/ <<
1313 <<
1314 Say Y if you intend to run this ker <<
1315 Say N otherwise. <<
1316 <<
1317 config X86_REBOOTFIXUPS <<
1318 bool "Enable X86 board specific fixup <<
1319 depends on X86_32 <<
1320 help <<
1321 This enables chipset and/or board s <<
1322 in order to get reboot to work corr <<
1323 some combinations of hardware and B <<
1324 this config is intended, is when re <<
1325 system. <<
1326 <<
1327 Currently, the only fixup is for th <<
1328 CS5530A and CS5536 chipsets and the <<
1329 <<
1330 Say Y if you want to enable the fix <<
1331 enable this option even if you don' <<
1332 Say N otherwise. <<
1333 1807
1334 config MICROCODE !! 1808 config CPU_BMIPS4350
1335 def_bool y !! 1809 bool
1336 depends on CPU_SUP_AMD || CPU_SUP_INT !! 1810 select SYS_SUPPORTS_SMP
>> 1811 select SYS_SUPPORTS_HOTPLUG_CPU
1337 1812
1338 config MICROCODE_INITRD32 !! 1813 config CPU_BMIPS4380
1339 def_bool y !! 1814 bool
1340 depends on MICROCODE && X86_32 && BLK !! 1815 select MIPS_L1_CACHE_SHIFT_6
>> 1816 select SYS_SUPPORTS_SMP
>> 1817 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1818 select CPU_HAS_RIXI
1341 1819
1342 config MICROCODE_LATE_LOADING !! 1820 config CPU_BMIPS5000
1343 bool "Late microcode loading (DANGERO !! 1821 bool
1344 default n !! 1822 select MIPS_CPU_SCACHE
1345 depends on MICROCODE && SMP !! 1823 select MIPS_L1_CACHE_SHIFT_7
1346 help !! 1824 select SYS_SUPPORTS_SMP
1347 Loading microcode late, when the sy !! 1825 select SYS_SUPPORTS_HOTPLUG_CPU
1348 is a tricky business and should be !! 1826 select CPU_HAS_RIXI
1349 of synchronizing all cores and SMT <<
1350 not guarantee that cores might not <<
1351 use this at your own risk. Late loa <<
1352 microcode header indicates that it <<
1353 minimal revision check. This minima <<
1354 the kernel command line with "micro <<
1355 1827
1356 config MICROCODE_LATE_FORCE_MINREV !! 1828 config SYS_HAS_CPU_LOONGSON64
1357 bool "Enforce late microcode loading !! 1829 bool
1358 default n !! 1830 select CPU_SUPPORTS_CPUFREQ
1359 depends on MICROCODE_LATE_LOADING !! 1831 select CPU_HAS_RIXI
1360 help <<
1361 To prevent that users load microcod <<
1362 in use features, newer microcode pa <<
1363 in the microcode header, which tell <<
1364 revision must be active in the CPU <<
1365 late into the running system. If di <<
1366 be enforced but the kernel will be <<
1367 revision check fails. <<
1368 <<
1369 This minimal revision check can als <<
1370 "microcode.minrev" parameter on the <<
1371 <<
1372 If unsure say Y. <<
1373 <<
1374 config X86_MSR <<
1375 tristate "/dev/cpu/*/msr - Model-spec <<
1376 help <<
1377 This device gives privileged proces <<
1378 Model-Specific Registers (MSRs). I <<
1379 major 202 and minors 0 to 31 for /d <<
1380 MSR accesses are directed to a spec <<
1381 systems. <<
1382 1832
1383 config X86_CPUID !! 1833 config SYS_HAS_CPU_LOONGSON2E
1384 tristate "/dev/cpu/*/cpuid - CPU info !! 1834 bool
1385 help <<
1386 This device gives processes access <<
1387 be executed on a specific processor <<
1388 with major 203 and minors 0 to 31 f <<
1389 /dev/cpu/31/cpuid. <<
1390 1835
1391 choice !! 1836 config SYS_HAS_CPU_LOONGSON2F
1392 prompt "High Memory Support" !! 1837 bool
1393 default HIGHMEM4G !! 1838 select CPU_SUPPORTS_CPUFREQ
1394 depends on X86_32 !! 1839 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1395 <<
1396 config NOHIGHMEM <<
1397 bool "off" <<
1398 help <<
1399 Linux can use up to 64 Gigabytes of <<
1400 However, the address space of 32-bi <<
1401 Gigabytes large. That means that, i <<
1402 physical memory, not all of it can <<
1403 kernel. The physical memory that's <<
1404 "high memory". <<
1405 <<
1406 If you are compiling a kernel which <<
1407 more than 1 Gigabyte total physical <<
1408 choice and suitable for most users) <<
1409 split: 3GB are mapped so that each <<
1410 space and the remaining part of the <<
1411 by the kernel to permanently map as <<
1412 possible. <<
1413 <<
1414 If the machine has between 1 and 4 <<
1415 answer "4GB" here. <<
1416 <<
1417 If more than 4 Gigabytes is used th <<
1418 selection turns Intel PAE (Physical <<
1419 PAE implements 3-level paging on IA <<
1420 supported by Linux, PAE mode is imp <<
1421 processors (Pentium Pro and better) <<
1422 then the kernel will not boot on CP <<
1423 <<
1424 The actual amount of total physical <<
1425 auto detected or can be forced by u <<
1426 such as "mem=256M". (Try "man bootp <<
1427 your boot loader (lilo or loadlin) <<
1428 kernel at boot time.) <<
1429 <<
1430 If unsure, say "off". <<
1431 <<
1432 config HIGHMEM4G <<
1433 bool "4GB" <<
1434 help <<
1435 Select this if you have a 32-bit pr <<
1436 gigabytes of physical RAM. <<
1437 <<
1438 config HIGHMEM64G <<
1439 bool "64GB" <<
1440 depends on X86_HAVE_PAE <<
1441 select X86_PAE <<
1442 help <<
1443 Select this if you have a 32-bit pr <<
1444 gigabytes of physical RAM. <<
1445 1840
1446 endchoice !! 1841 config SYS_HAS_CPU_LOONGSON1B
>> 1842 bool
1447 1843
1448 choice !! 1844 config SYS_HAS_CPU_LOONGSON1C
1449 prompt "Memory split" if EXPERT !! 1845 bool
1450 default VMSPLIT_3G <<
1451 depends on X86_32 <<
1452 help <<
1453 Select the desired split between ke <<
1454 <<
1455 If the address range available to t <<
1456 physical memory installed, the rema <<
1457 as "high memory". Accessing high me <<
1458 than low memory, as it needs to be <<
1459 Note that increasing the kernel add <<
1460 available to user programs, making <<
1461 tighter. Selecting anything other <<
1462 will also likely make your kernel i <<
1463 kernel modules. <<
1464 <<
1465 If you are not absolutely sure what <<
1466 option alone! <<
1467 <<
1468 config VMSPLIT_3G <<
1469 bool "3G/1G user/kernel split <<
1470 config VMSPLIT_3G_OPT <<
1471 depends on !X86_PAE <<
1472 bool "3G/1G user/kernel split <<
1473 config VMSPLIT_2G <<
1474 bool "2G/2G user/kernel split <<
1475 config VMSPLIT_2G_OPT <<
1476 depends on !X86_PAE <<
1477 bool "2G/2G user/kernel split <<
1478 config VMSPLIT_1G <<
1479 bool "1G/3G user/kernel split <<
1480 endchoice <<
1481 1846
1482 config PAGE_OFFSET !! 1847 config SYS_HAS_CPU_MIPS32_R1
1483 hex !! 1848 bool
1484 default 0xB0000000 if VMSPLIT_3G_OPT <<
1485 default 0x80000000 if VMSPLIT_2G <<
1486 default 0x78000000 if VMSPLIT_2G_OPT <<
1487 default 0x40000000 if VMSPLIT_1G <<
1488 default 0xC0000000 <<
1489 depends on X86_32 <<
1490 1849
1491 config HIGHMEM !! 1850 config SYS_HAS_CPU_MIPS32_R2
1492 def_bool y !! 1851 bool
1493 depends on X86_32 && (HIGHMEM64G || H <<
1494 1852
1495 config X86_PAE !! 1853 config SYS_HAS_CPU_MIPS32_R3_5
1496 bool "PAE (Physical Address Extension !! 1854 bool
1497 depends on X86_32 && X86_HAVE_PAE <<
1498 select PHYS_ADDR_T_64BIT <<
1499 select SWIOTLB <<
1500 help <<
1501 PAE is required for NX support, and <<
1502 larger swapspace support for non-ov <<
1503 has the cost of more pagetable look <<
1504 consumes more pagetable space per p <<
1505 1855
1506 config X86_5LEVEL !! 1856 config SYS_HAS_CPU_MIPS32_R5
1507 bool "Enable 5-level page tables supp !! 1857 bool
1508 default y !! 1858 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1509 select DYNAMIC_MEMORY_LAYOUT <<
1510 select SPARSEMEM_VMEMMAP <<
1511 depends on X86_64 <<
1512 help <<
1513 5-level paging enables access to la <<
1514 up to 128 PiB of virtual address sp <<
1515 physical address space. <<
1516 1859
1517 It will be supported by future Inte !! 1860 config SYS_HAS_CPU_MIPS32_R6
>> 1861 bool
>> 1862 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1518 1863
1519 A kernel with the option enabled ca !! 1864 config SYS_HAS_CPU_MIPS64_R1
1520 support 4- or 5-level paging. !! 1865 bool
1521 1866
1522 See Documentation/arch/x86/x86_64/5 !! 1867 config SYS_HAS_CPU_MIPS64_R2
1523 information. !! 1868 bool
1524 1869
1525 Say N if unsure. !! 1870 config SYS_HAS_CPU_MIPS64_R5
>> 1871 bool
>> 1872 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1526 1873
1527 config X86_DIRECT_GBPAGES !! 1874 config SYS_HAS_CPU_MIPS64_R6
1528 def_bool y !! 1875 bool
1529 depends on X86_64 !! 1876 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1530 help <<
1531 Certain kernel features effectively <<
1532 linear 1 GB mappings (even if the C <<
1533 supports them), so don't confuse th <<
1534 that we have them enabled. <<
1535 <<
1536 config X86_CPA_STATISTICS <<
1537 bool "Enable statistic for Change Pag <<
1538 depends on DEBUG_FS <<
1539 help <<
1540 Expose statistics about the Change <<
1541 helps to determine the effectivenes <<
1542 page mappings when mapping protecti <<
1543 <<
1544 config X86_MEM_ENCRYPT <<
1545 select ARCH_HAS_FORCE_DMA_UNENCRYPTED <<
1546 select DYNAMIC_PHYSICAL_MASK <<
1547 def_bool n <<
1548 1877
1549 config AMD_MEM_ENCRYPT !! 1878 config SYS_HAS_CPU_P5600
1550 bool "AMD Secure Memory Encryption (S !! 1879 bool
1551 depends on X86_64 && CPU_SUP_AMD !! 1880 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1552 depends on EFI_STUB <<
1553 select DMA_COHERENT_POOL <<
1554 select ARCH_USE_MEMREMAP_PROT <<
1555 select INSTRUCTION_DECODER <<
1556 select ARCH_HAS_CC_PLATFORM <<
1557 select X86_MEM_ENCRYPT <<
1558 select UNACCEPTED_MEMORY <<
1559 help <<
1560 Say yes to enable support for the e <<
1561 This requires an AMD processor that <<
1562 Encryption (SME). <<
1563 1881
1564 # Common NUMA Features !! 1882 config SYS_HAS_CPU_R3000
1565 config NUMA !! 1883 bool
1566 bool "NUMA Memory Allocation and Sche <<
1567 depends on SMP <<
1568 depends on X86_64 || (X86_32 && HIGHM <<
1569 default y if X86_BIGSMP <<
1570 select USE_PERCPU_NUMA_NODE_ID <<
1571 select OF_NUMA if OF <<
1572 help <<
1573 Enable NUMA (Non-Uniform Memory Acc <<
1574 1884
1575 The kernel will try to allocate mem !! 1885 config SYS_HAS_CPU_R4300
1576 local memory controller of the CPU !! 1886 bool
1577 NUMA awareness to the kernel. <<
1578 1887
1579 For 64-bit this is recommended if t !! 1888 config SYS_HAS_CPU_R4X00
1580 (or later), AMD Opteron, or EM64T N !! 1889 bool
1581 1890
1582 For 32-bit this is only needed if y !! 1891 config SYS_HAS_CPU_TX49XX
1583 kernel on a 64-bit NUMA platform. !! 1892 bool
1584 1893
1585 Otherwise, you should say N. !! 1894 config SYS_HAS_CPU_R5000
>> 1895 bool
1586 1896
1587 config AMD_NUMA !! 1897 config SYS_HAS_CPU_R5500
1588 def_bool y !! 1898 bool
1589 prompt "Old style AMD Opteron NUMA de <<
1590 depends on X86_64 && NUMA && PCI <<
1591 help <<
1592 Enable AMD NUMA node topology detec <<
1593 you have a multi processor AMD syst <<
1594 read the NUMA configuration directl <<
1595 of Opteron. It is recommended to us <<
1596 which also takes priority if both a <<
1597 1899
1598 config X86_64_ACPI_NUMA !! 1900 config SYS_HAS_CPU_NEVADA
1599 def_bool y !! 1901 bool
1600 prompt "ACPI NUMA detection" <<
1601 depends on X86_64 && NUMA && ACPI && <<
1602 select ACPI_NUMA <<
1603 help <<
1604 Enable ACPI SRAT based node topolog <<
1605 1902
1606 config NODES_SHIFT !! 1903 config SYS_HAS_CPU_R10000
1607 int "Maximum NUMA Nodes (as a power o !! 1904 bool
1608 range 1 10 !! 1905 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1609 default "10" if MAXSMP <<
1610 default "6" if X86_64 <<
1611 default "3" <<
1612 depends on NUMA <<
1613 help <<
1614 Specify the maximum number of NUMA <<
1615 system. Increases memory reserved <<
1616 1906
1617 config ARCH_FLATMEM_ENABLE !! 1907 config SYS_HAS_CPU_RM7000
1618 def_bool y !! 1908 bool
1619 depends on X86_32 && !NUMA <<
1620 1909
1621 config ARCH_SPARSEMEM_ENABLE !! 1910 config SYS_HAS_CPU_SB1
1622 def_bool y !! 1911 bool
1623 depends on X86_64 || NUMA || X86_32 | <<
1624 select SPARSEMEM_STATIC if X86_32 <<
1625 select SPARSEMEM_VMEMMAP_ENABLE if X8 <<
1626 1912
1627 config ARCH_SPARSEMEM_DEFAULT !! 1913 config SYS_HAS_CPU_CAVIUM_OCTEON
1628 def_bool X86_64 || (NUMA && X86_32) !! 1914 bool
1629 1915
1630 config ARCH_SELECT_MEMORY_MODEL !! 1916 config SYS_HAS_CPU_BMIPS
1631 def_bool y !! 1917 bool
1632 depends on ARCH_SPARSEMEM_ENABLE && A <<
1633 1918
1634 config ARCH_MEMORY_PROBE !! 1919 config SYS_HAS_CPU_BMIPS32_3300
1635 bool "Enable sysfs memory/probe inter !! 1920 bool
1636 depends on MEMORY_HOTPLUG !! 1921 select SYS_HAS_CPU_BMIPS
1637 help <<
1638 This option enables a sysfs memory/ <<
1639 See Documentation/admin-guide/mm/me <<
1640 If you are unsure how to answer thi <<
1641 1922
1642 config ARCH_PROC_KCORE_TEXT !! 1923 config SYS_HAS_CPU_BMIPS4350
1643 def_bool y !! 1924 bool
1644 depends on X86_64 && PROC_KCORE !! 1925 select SYS_HAS_CPU_BMIPS
1645 1926
1646 config ILLEGAL_POINTER_VALUE !! 1927 config SYS_HAS_CPU_BMIPS4380
1647 hex !! 1928 bool
1648 default 0 if X86_32 !! 1929 select SYS_HAS_CPU_BMIPS
1649 default 0xdead000000000000 if X86_64 <<
1650 <<
1651 config X86_PMEM_LEGACY_DEVICE <<
1652 bool <<
1653 <<
1654 config X86_PMEM_LEGACY <<
1655 tristate "Support non-standard NVDIMM <<
1656 depends on PHYS_ADDR_T_64BIT <<
1657 depends on BLK_DEV <<
1658 select X86_PMEM_LEGACY_DEVICE <<
1659 select NUMA_KEEP_MEMINFO if NUMA <<
1660 select LIBNVDIMM <<
1661 help <<
1662 Treat memory marked using the non-s <<
1663 by the Intel Sandy Bridge-EP refere <<
1664 The kernel will offer these regions <<
1665 they can be used for persistent sto <<
1666 <<
1667 Say Y if unsure. <<
1668 <<
1669 config HIGHPTE <<
1670 bool "Allocate 3rd-level pagetables f <<
1671 depends on HIGHMEM <<
1672 help <<
1673 The VM uses one page table entry fo <<
1674 For systems with a lot of RAM, this <<
1675 low memory. Setting this option wi <<
1676 entries in high memory. <<
1677 <<
1678 config X86_CHECK_BIOS_CORRUPTION <<
1679 bool "Check for low memory corruption <<
1680 help <<
1681 Periodically check for memory corru <<
1682 is suspected to be caused by BIOS. <<
1683 configuration, it is disabled at ru <<
1684 setting "memory_corruption_check=1" <<
1685 line. By default it scans the low <<
1686 seconds; see the memory_corruption_ <<
1687 memory_corruption_check_period para <<
1688 Documentation/admin-guide/kernel-pa <<
1689 <<
1690 When enabled with the default param <<
1691 almost no overhead, as it reserves <<
1692 of memory and scans it infrequently <<
1693 and prevents it from affecting the <<
1694 <<
1695 It is, however, intended as a diagn <<
1696 BIOS-originated corruption always a <<
1697 you can use memmap= to prevent the <<
1698 memory. <<
1699 <<
1700 config X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK <<
1701 bool "Set the default setting of memo <<
1702 depends on X86_CHECK_BIOS_CORRUPTION <<
1703 default y <<
1704 help <<
1705 Set whether the default state of me <<
1706 on or off. <<
1707 1930
1708 config MATH_EMULATION !! 1931 config SYS_HAS_CPU_BMIPS5000
1709 bool 1932 bool
1710 depends on MODIFY_LDT_SYSCALL !! 1933 select SYS_HAS_CPU_BMIPS
1711 prompt "Math emulation" if X86_32 && !! 1934 select ARCH_HAS_SYNC_DMA_FOR_CPU
1712 help <<
1713 Linux can emulate a math coprocesso <<
1714 operations) if you don't have one. <<
1715 a math coprocessor built in, 486SX <<
1716 a 487DX or 387, respectively. (The <<
1717 give you some hints here ["man dmes <<
1718 coprocessor or this emulation. <<
1719 <<
1720 If you don't have a math coprocesso <<
1721 say Y here even though you have a c <<
1722 be used nevertheless. (This behavio <<
1723 command line option "no387", which <<
1724 is broken. Try "man bootparam" or s <<
1725 loader (lilo or loadlin) about how <<
1726 boot time.) This means that it is a <<
1727 intend to use this kernel on differ <<
1728 1935
1729 More information about the internal !! 1936 #
1730 emulation can be found in <file:arc !! 1937 # CPU may reorder R->R, R->W, W->R, W->W
>> 1938 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1939 #
>> 1940 config WEAK_ORDERING
>> 1941 bool
1731 1942
1732 If you are not sure, say Y; apart f !! 1943 #
1733 kernel, it won't hurt. !! 1944 # CPU may reorder reads and writes beyond LL/SC
>> 1945 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 1946 #
>> 1947 config WEAK_REORDERING_BEYOND_LLSC
>> 1948 bool
>> 1949 endmenu
1734 1950
1735 config MTRR !! 1951 #
1736 def_bool y !! 1952 # These two indicate any level of the MIPS32 and MIPS64 architecture
1737 prompt "MTRR (Memory Type Range Regis !! 1953 #
1738 help !! 1954 config CPU_MIPS32
1739 On Intel P6 family processors (Pent !! 1955 bool
1740 the Memory Type Range Registers (MT !! 1956 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
1741 processor access to memory ranges. !! 1957 CPU_MIPS32_R6 || CPU_P5600
1742 a video (VGA) card on a PCI or AGP <<
1743 allows bus write transfers to be co <<
1744 before bursting over the PCI/AGP bu <<
1745 of image write operations 2.5 times <<
1746 /proc/mtrr file which may be used t <<
1747 MTRRs. Typically the X server shoul <<
1748 <<
1749 This code has a reasonably generic <<
1750 control registers on other processo <<
1751 as well: <<
1752 <<
1753 The Cyrix 6x86, 6x86MX and M II pro <<
1754 Registers (ARRs) which provide a si <<
1755 these, the ARRs are used to emulate <<
1756 The AMD K6-2 (stepping 8 and above) <<
1757 MTRRs. The Centaur C6 (WinChip) has <<
1758 write-combining. All of these proce <<
1759 and it makes sense to say Y here if <<
1760 <<
1761 Saying Y here also fixes a problem <<
1762 set the MTRRs for the boot CPU and <<
1763 can lead to all sorts of problems, <<
1764 1958
1765 You can safely say Y even if your m !! 1959 config CPU_MIPS64
1766 just add about 9 KB to your kernel. !! 1960 bool
>> 1961 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1962 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
1767 1963
1768 See <file:Documentation/arch/x86/mt !! 1964 #
>> 1965 # These indicate the revision of the architecture
>> 1966 #
>> 1967 config CPU_MIPSR1
>> 1968 bool
>> 1969 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
1769 1970
1770 config MTRR_SANITIZER !! 1971 config CPU_MIPSR2
1771 def_bool y !! 1972 bool
1772 prompt "MTRR cleanup support" !! 1973 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1773 depends on MTRR !! 1974 select CPU_HAS_RIXI
1774 help !! 1975 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
1775 Convert MTRR layout from continuous !! 1976 select MIPS_SPRAM
1776 add writeback entries. <<
1777 1977
1778 Can be disabled with disable_mtrr_c !! 1978 config CPU_MIPSR5
1779 The largest mtrr entry size for a c !! 1979 bool
1780 mtrr_chunk_size. !! 1980 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 1981 select CPU_HAS_RIXI
>> 1982 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1983 select MIPS_SPRAM
1781 1984
1782 If unsure, say Y. !! 1985 config CPU_MIPSR6
>> 1986 bool
>> 1987 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 1988 select CPU_HAS_RIXI
>> 1989 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1990 select HAVE_ARCH_BITREVERSE
>> 1991 select MIPS_ASID_BITS_VARIABLE
>> 1992 select MIPS_CRC_SUPPORT
>> 1993 select MIPS_SPRAM
1783 1994
1784 config MTRR_SANITIZER_ENABLE_DEFAULT !! 1995 config TARGET_ISA_REV
1785 int "MTRR cleanup enable value (0-1)" !! 1996 int
1786 range 0 1 !! 1997 default 1 if CPU_MIPSR1
1787 default "0" !! 1998 default 2 if CPU_MIPSR2
1788 depends on MTRR_SANITIZER !! 1999 default 5 if CPU_MIPSR5
1789 help !! 2000 default 6 if CPU_MIPSR6
1790 Enable mtrr cleanup default value !! 2001 default 0
1791 <<
1792 config MTRR_SANITIZER_SPARE_REG_NR_DEFAULT <<
1793 int "MTRR cleanup spare reg num (0-7) <<
1794 range 0 7 <<
1795 default "1" <<
1796 depends on MTRR_SANITIZER <<
1797 help 2002 help
1798 mtrr cleanup spare entries default, !! 2003 Reflects the ISA revision being targeted by the kernel build. This
1799 mtrr_spare_reg_nr=N on the kernel c !! 2004 is effectively the Kconfig equivalent of MIPS_ISA_REV.
1800 2005
1801 config X86_PAT !! 2006 config EVA
1802 def_bool y !! 2007 bool
1803 prompt "x86 PAT support" if EXPERT <<
1804 depends on MTRR <<
1805 select ARCH_USES_PG_ARCH_2 <<
1806 help <<
1807 Use PAT attributes to setup page le <<
1808 2008
1809 PATs are the modern equivalents of !! 2009 config XPA
1810 flexible than MTRRs. !! 2010 bool
1811 2011
1812 Say N here if you see bootup proble !! 2012 config SYS_SUPPORTS_32BIT_KERNEL
1813 spontaneous reboots) or a non-worki !! 2013 bool
>> 2014 config SYS_SUPPORTS_64BIT_KERNEL
>> 2015 bool
>> 2016 config CPU_SUPPORTS_32BIT_KERNEL
>> 2017 bool
>> 2018 config CPU_SUPPORTS_64BIT_KERNEL
>> 2019 bool
>> 2020 config CPU_SUPPORTS_CPUFREQ
>> 2021 bool
>> 2022 config CPU_SUPPORTS_ADDRWINCFG
>> 2023 bool
>> 2024 config CPU_SUPPORTS_HUGEPAGES
>> 2025 bool
>> 2026 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2027 config MIPS_PGD_C0_CONTEXT
>> 2028 bool
>> 2029 depends on 64BIT
>> 2030 default y if (CPU_MIPSR2 || CPU_MIPSR6)
1814 2031
1815 If unsure, say Y. !! 2032 #
>> 2033 # Set to y for ptrace access to watch registers.
>> 2034 #
>> 2035 config HARDWARE_WATCHPOINTS
>> 2036 bool
>> 2037 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
1816 2038
1817 config X86_UMIP !! 2039 menu "Kernel type"
1818 def_bool y <<
1819 prompt "User Mode Instruction Prevent <<
1820 help <<
1821 User Mode Instruction Prevention (U <<
1822 some x86 processors. If enabled, a <<
1823 issued if the SGDT, SLDT, SIDT, SMS <<
1824 executed in user mode. These instru <<
1825 information about the hardware stat <<
1826 <<
1827 The vast majority of applications d <<
1828 For the very few that do, software <<
1829 specific cases in protected and vir <<
1830 results are dummy. <<
1831 <<
1832 config CC_HAS_IBT <<
1833 # GCC >= 9 and binutils >= 2.29 <<
1834 # Retpoline check to work around http <<
1835 # Clang/LLVM >= 14 <<
1836 # https://github.com/llvm/llvm-projec <<
1837 # https://github.com/llvm/llvm-projec <<
1838 def_bool ((CC_IS_GCC && $(cc-option, <<
1839 (CC_IS_CLANG && CLANG_VERSI <<
1840 $(as-instr,endbr64) <<
1841 2040
1842 config X86_CET !! 2041 choice
1843 def_bool n !! 2042 prompt "Kernel code model"
1844 help 2043 help
1845 CET features configured (Shadow sta !! 2044 You should only select this option if you have a workload that
1846 !! 2045 actually benefits from 64-bit processing or if your machine has
1847 config X86_KERNEL_IBT !! 2046 large memory. You will only be presented a single option in this
1848 prompt "Indirect Branch Tracking" !! 2047 menu if your system does not support both 32-bit and 64-bit kernels.
1849 def_bool y !! 2048
1850 depends on X86_64 && CC_HAS_IBT && HA !! 2049 config 32BIT
1851 # https://github.com/llvm/llvm-projec !! 2050 bool "32-bit kernel"
1852 depends on !LD_IS_LLD || LLD_VERSION !! 2051 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
1853 select OBJTOOL !! 2052 select TRAD_SIGNALS
1854 select X86_CET !! 2053 help
1855 help !! 2054 Select this option if you want to build a 32-bit kernel.
1856 Build the kernel with support for I <<
1857 hardware support course-grain forwa <<
1858 protection. It enforces that all in <<
1859 an ENDBR instruction, as such, the <<
1860 code with them to make this happen. <<
1861 <<
1862 In addition to building the kernel <<
1863 are not indirect call targets, avoi <<
1864 <<
1865 This requires LTO like objtool runs <<
1866 does significantly reduce the numbe <<
1867 kernel image. <<
1868 2055
1869 config X86_INTEL_MEMORY_PROTECTION_KEYS !! 2056 config 64BIT
1870 prompt "Memory Protection Keys" !! 2057 bool "64-bit kernel"
1871 def_bool y !! 2058 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1872 # Note: only available in 64-bit mode !! 2059 help
1873 depends on X86_64 && (CPU_SUP_INTEL | !! 2060 Select this option if you want to build a 64-bit kernel.
1874 select ARCH_USES_HIGH_VMA_FLAGS <<
1875 select ARCH_HAS_PKEYS <<
1876 help <<
1877 Memory Protection Keys provides a m <<
1878 page-based protections, but without <<
1879 page tables when an application cha <<
1880 2061
1881 For details, see Documentation/core !! 2062 endchoice
1882 2063
1883 If unsure, say y. !! 2064 config MIPS_VA_BITS_48
>> 2065 bool "48 bits virtual memory"
>> 2066 depends on 64BIT
>> 2067 help
>> 2068 Support a maximum at least 48 bits of application virtual
>> 2069 memory. Default is 40 bits or less, depending on the CPU.
>> 2070 For page sizes 16k and above, this option results in a small
>> 2071 memory overhead for page tables. For 4k page size, a fourth
>> 2072 level of page tables is added which imposes both a memory
>> 2073 overhead as well as slower TLB fault handling.
1884 2074
1885 config ARCH_PKEY_BITS !! 2075 If unsure, say N.
1886 int <<
1887 default 4 <<
1888 2076
1889 choice !! 2077 config ZBOOT_LOAD_ADDRESS
1890 prompt "TSX enable mode" !! 2078 hex "Compressed kernel load address"
1891 depends on CPU_SUP_INTEL !! 2079 default 0xffffffff80400000 if BCM47XX
1892 default X86_INTEL_TSX_MODE_OFF !! 2080 default 0x0
>> 2081 depends on SYS_SUPPORTS_ZBOOT
1893 help 2082 help
1894 Intel's TSX (Transactional Synchron !! 2083 The address to load compressed kernel, aka vmlinuz.
1895 allows to optimize locking protocol <<
1896 can lead to a noticeable performanc <<
1897 2084
1898 On the other hand it has been shown !! 2085 This is only used if non-zero.
1899 to form side channel attacks (e.g. <<
1900 will be more of those attacks disco <<
1901 2086
1902 Therefore TSX is not enabled by def !! 2087 choice
1903 might override this decision by tsx !! 2088 prompt "Kernel page size"
1904 Even with TSX enabled, the kernel w !! 2089 default PAGE_SIZE_4KB
1905 possible TAA mitigation setting dep <<
1906 for the particular machine. <<
1907 2090
1908 This option allows to set the defau !! 2091 config PAGE_SIZE_4KB
1909 and =auto. See Documentation/admin- !! 2092 bool "4kB"
1910 details. !! 2093 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2094 help
>> 2095 This option select the standard 4kB Linux page size. On some
>> 2096 R3000-family processors this is the only available page size. Using
>> 2097 4kB page size will minimize memory consumption and is therefore
>> 2098 recommended for low memory systems.
>> 2099
>> 2100 config PAGE_SIZE_8KB
>> 2101 bool "8kB"
>> 2102 depends on CPU_CAVIUM_OCTEON
>> 2103 depends on !MIPS_VA_BITS_48
>> 2104 help
>> 2105 Using 8kB page size will result in higher performance kernel at
>> 2106 the price of higher memory consumption. This option is available
>> 2107 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2108 distribution to support this.
>> 2109
>> 2110 config PAGE_SIZE_16KB
>> 2111 bool "16kB"
>> 2112 depends on !CPU_R3000
>> 2113 help
>> 2114 Using 16kB page size will result in higher performance kernel at
>> 2115 the price of higher memory consumption. This option is available on
>> 2116 all non-R3000 family processors. Note that you will need a suitable
>> 2117 Linux distribution to support this.
>> 2118
>> 2119 config PAGE_SIZE_32KB
>> 2120 bool "32kB"
>> 2121 depends on CPU_CAVIUM_OCTEON
>> 2122 depends on !MIPS_VA_BITS_48
>> 2123 help
>> 2124 Using 32kB page size will result in higher performance kernel at
>> 2125 the price of higher memory consumption. This option is available
>> 2126 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2127 distribution to support this.
>> 2128
>> 2129 config PAGE_SIZE_64KB
>> 2130 bool "64kB"
>> 2131 depends on !CPU_R3000
>> 2132 help
>> 2133 Using 64kB page size will result in higher performance kernel at
>> 2134 the price of higher memory consumption. This option is available on
>> 2135 all non-R3000 family processor. Not that at the time of this
>> 2136 writing this option is still high experimental.
1911 2137
1912 Say off if not sure, auto if TSX is !! 2138 endchoice
1913 platforms or on if TSX is in use an <<
1914 relevant. <<
1915 2139
1916 config X86_INTEL_TSX_MODE_OFF !! 2140 config ARCH_FORCE_MAX_ORDER
1917 bool "off" !! 2141 int "Maximum zone order"
1918 help !! 2142 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
1919 TSX is disabled if possible - equal !! 2143 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2144 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2145 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2146 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2147 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2148 range 0 64
>> 2149 default "11"
>> 2150 help
>> 2151 The kernel memory allocator divides physically contiguous memory
>> 2152 blocks into "zones", where each zone is a power of two number of
>> 2153 pages. This option selects the largest power of two that the kernel
>> 2154 keeps in the memory allocator. If you need to allocate very large
>> 2155 blocks of physically contiguous memory, then you may need to
>> 2156 increase this value.
1920 2157
1921 config X86_INTEL_TSX_MODE_ON !! 2158 This config option is actually maximum order plus one. For example,
1922 bool "on" !! 2159 a value of 11 means that the largest free memory block is 2^10 pages.
1923 help <<
1924 TSX is always enabled on TSX capabl <<
1925 line parameter. <<
1926 2160
1927 config X86_INTEL_TSX_MODE_AUTO !! 2161 The page size is not necessarily 4KB. Keep this in mind
1928 bool "auto" !! 2162 when choosing a value for this option.
1929 help <<
1930 TSX is enabled on TSX capable HW th <<
1931 side channel attacks- equals the ts <<
1932 endchoice <<
1933 2163
1934 config X86_SGX !! 2164 config BOARD_SCACHE
1935 bool "Software Guard eXtensions (SGX) !! 2165 bool
1936 depends on X86_64 && CPU_SUP_INTEL && <<
1937 depends on CRYPTO=y <<
1938 depends on CRYPTO_SHA256=y <<
1939 select MMU_NOTIFIER <<
1940 select NUMA_KEEP_MEMINFO if NUMA <<
1941 select XARRAY_MULTI <<
1942 help <<
1943 Intel(R) Software Guard eXtensions <<
1944 that can be used by applications to <<
1945 and data, referred to as enclaves. <<
1946 only be accessed by code running wi <<
1947 outside the enclave, including othe <<
1948 hardware. <<
1949 2166
1950 If unsure, say N. !! 2167 config IP22_CPU_SCACHE
>> 2168 bool
>> 2169 select BOARD_SCACHE
1951 2170
1952 config X86_USER_SHADOW_STACK !! 2171 #
1953 bool "X86 userspace shadow stack" !! 2172 # Support for a MIPS32 / MIPS64 style S-caches
1954 depends on AS_WRUSS !! 2173 #
1955 depends on X86_64 !! 2174 config MIPS_CPU_SCACHE
1956 select ARCH_USES_HIGH_VMA_FLAGS !! 2175 bool
1957 select X86_CET !! 2176 select BOARD_SCACHE
1958 help <<
1959 Shadow stack protection is a hardwa <<
1960 return address corruption. This he <<
1961 Applications must be enabled to use <<
1962 get protection "for free". <<
1963 2177
1964 CPUs supporting shadow stacks were !! 2178 config R5000_CPU_SCACHE
>> 2179 bool
>> 2180 select BOARD_SCACHE
1965 2181
1966 See Documentation/arch/x86/shstk.rs !! 2182 config RM7000_CPU_SCACHE
>> 2183 bool
>> 2184 select BOARD_SCACHE
1967 2185
1968 If unsure, say N. !! 2186 config SIBYTE_DMA_PAGEOPS
>> 2187 bool "Use DMA to clear/copy pages"
>> 2188 depends on CPU_SB1
>> 2189 help
>> 2190 Instead of using the CPU to zero and copy pages, use a Data Mover
>> 2191 channel. These DMA channels are otherwise unused by the standard
>> 2192 SiByte Linux port. Seems to give a small performance benefit.
1969 2193
1970 config INTEL_TDX_HOST !! 2194 config CPU_HAS_PREFETCH
1971 bool "Intel Trust Domain Extensions ( !! 2195 bool
1972 depends on CPU_SUP_INTEL <<
1973 depends on X86_64 <<
1974 depends on KVM_INTEL <<
1975 depends on X86_X2APIC <<
1976 select ARCH_KEEP_MEMBLOCK <<
1977 depends on CONTIG_ALLOC <<
1978 depends on !KEXEC_CORE <<
1979 depends on X86_MCE <<
1980 help <<
1981 Intel Trust Domain Extensions (TDX) <<
1982 host and certain physical attacks. <<
1983 support in the host kernel to run c <<
1984 2196
1985 If unsure, say N. !! 2197 config CPU_GENERIC_DUMP_TLB
>> 2198 bool
>> 2199 default y if !CPU_R3000
1986 2200
1987 config EFI !! 2201 config MIPS_FP_SUPPORT
1988 bool "EFI runtime service support" !! 2202 bool "Floating Point support" if EXPERT
1989 depends on ACPI <<
1990 select UCS2_STRING <<
1991 select EFI_RUNTIME_WRAPPERS <<
1992 select ARCH_USE_MEMREMAP_PROT <<
1993 select EFI_RUNTIME_MAP if KEXEC_CORE <<
1994 help <<
1995 This enables the kernel to use EFI <<
1996 available (such as the EFI variable <<
1997 <<
1998 This option is only useful on syste <<
1999 In addition, you should use the lat <<
2000 at <http://elilo.sourceforge.net> i <<
2001 of EFI runtime services. However, e <<
2002 resultant kernel should continue to <<
2003 platforms. <<
2004 <<
2005 config EFI_STUB <<
2006 bool "EFI stub support" <<
2007 depends on EFI <<
2008 select RELOCATABLE <<
2009 help <<
2010 This kernel feature allows a bzImag <<
2011 by EFI firmware without the use of <<
2012 <<
2013 See Documentation/admin-guide/efi-s <<
2014 <<
2015 config EFI_HANDOVER_PROTOCOL <<
2016 bool "EFI handover protocol (DEPRECAT <<
2017 depends on EFI_STUB <<
2018 default y 2203 default y
2019 help 2204 help
2020 Select this in order to include sup !! 2205 Select y to include support for floating point in the kernel
2021 handover protocol, which defines al !! 2206 including initialization of FPU hardware, FP context save & restore
2022 EFI stub. This is a practice that !! 2207 and emulation of an FPU where necessary. Without this support any
2023 specification, and requires a prior !! 2208 userland program attempting to use floating point instructions will
2024 bootloader about Linux/x86 specific !! 2209 receive a SIGILL.
2025 and initrd, and where in memory tho <<
2026 <<
2027 If in doubt, say Y. Even though the <<
2028 present in upstream GRUB or other b <<
2029 GRUB with numerous downstream patch <<
2030 handover protocol as as result. <<
2031 <<
2032 config EFI_MIXED <<
2033 bool "EFI mixed-mode support" <<
2034 depends on EFI_STUB && X86_64 <<
2035 help <<
2036 Enabling this feature allows a 64-b <<
2037 on a 32-bit firmware, provided that <<
2038 mode. <<
2039 <<
2040 Note that it is not possible to boo <<
2041 kernel via the EFI boot stub - a bo <<
2042 the EFI handover protocol must be u <<
2043 2210
2044 If unsure, say N. !! 2211 If you know that your userland will not attempt to use floating point
2045 !! 2212 instructions then you can say n here to shrink the kernel a little.
2046 config EFI_RUNTIME_MAP <<
2047 bool "Export EFI runtime maps to sysf <<
2048 depends on EFI <<
2049 help <<
2050 Export EFI runtime memory regions t <<
2051 That memory map is required by the <<
2052 mappings after kexec, but can also <<
2053 2213
2054 See also Documentation/ABI/testing/ !! 2214 If unsure, say y.
2055 2215
2056 source "kernel/Kconfig.hz" !! 2216 config CPU_R2300_FPU
>> 2217 bool
>> 2218 depends on MIPS_FP_SUPPORT
>> 2219 default y if CPU_R3000
2057 2220
2058 config ARCH_SUPPORTS_KEXEC !! 2221 config CPU_R3K_TLB
2059 def_bool y !! 2222 bool
2060 2223
2061 config ARCH_SUPPORTS_KEXEC_FILE !! 2224 config CPU_R4K_FPU
2062 def_bool X86_64 !! 2225 bool
>> 2226 depends on MIPS_FP_SUPPORT
>> 2227 default y if !CPU_R2300_FPU
2063 2228
2064 config ARCH_SELECTS_KEXEC_FILE !! 2229 config CPU_R4K_CACHE_TLB
2065 def_bool y !! 2230 bool
2066 depends on KEXEC_FILE !! 2231 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
2067 select HAVE_IMA_KEXEC if IMA <<
2068 2232
2069 config ARCH_SUPPORTS_KEXEC_PURGATORY !! 2233 config MIPS_MT_SMP
2070 def_bool y !! 2234 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2235 default y
>> 2236 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2237 select CPU_MIPSR2_IRQ_VI
>> 2238 select CPU_MIPSR2_IRQ_EI
>> 2239 select SYNC_R4K
>> 2240 select MIPS_MT
>> 2241 select SMP
>> 2242 select SMP_UP
>> 2243 select SYS_SUPPORTS_SMP
>> 2244 select SYS_SUPPORTS_SCHED_SMT
>> 2245 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2246 help
>> 2247 This is a kernel model which is known as SMVP. This is supported
>> 2248 on cores with the MT ASE and uses the available VPEs to implement
>> 2249 virtual processors which supports SMP. This is equivalent to the
>> 2250 Intel Hyperthreading feature. For further information go to
>> 2251 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2071 2252
2072 config ARCH_SUPPORTS_KEXEC_SIG !! 2253 config MIPS_MT
2073 def_bool y !! 2254 bool
2074 2255
2075 config ARCH_SUPPORTS_KEXEC_SIG_FORCE !! 2256 config SCHED_SMT
2076 def_bool y !! 2257 bool "SMT (multithreading) scheduler support"
>> 2258 depends on SYS_SUPPORTS_SCHED_SMT
>> 2259 default n
>> 2260 help
>> 2261 SMT scheduler support improves the CPU scheduler's decision making
>> 2262 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2263 increased overhead in some places. If unsure say N here.
2077 2264
2078 config ARCH_SUPPORTS_KEXEC_BZIMAGE_VERIFY_SIG !! 2265 config SYS_SUPPORTS_SCHED_SMT
2079 def_bool y !! 2266 bool
2080 2267
2081 config ARCH_SUPPORTS_KEXEC_JUMP !! 2268 config SYS_SUPPORTS_MULTITHREADING
2082 def_bool y !! 2269 bool
2083 2270
2084 config ARCH_SUPPORTS_CRASH_DUMP !! 2271 config MIPS_MT_FPAFF
2085 def_bool X86_64 || (X86_32 && HIGHMEM !! 2272 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2273 default y
>> 2274 depends on MIPS_MT_SMP
2086 2275
2087 config ARCH_SUPPORTS_CRASH_HOTPLUG !! 2276 config MIPSR2_TO_R6_EMULATOR
2088 def_bool y !! 2277 bool "MIPS R2-to-R6 emulator"
>> 2278 depends on CPU_MIPSR6
>> 2279 depends on MIPS_FP_SUPPORT
>> 2280 default y
>> 2281 help
>> 2282 Choose this option if you want to run non-R6 MIPS userland code.
>> 2283 Even if you say 'Y' here, the emulator will still be disabled by
>> 2284 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2285 The only reason this is a build-time option is to save ~14K from the
>> 2286 final kernel image.
2089 2287
2090 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATI !! 2288 config SYS_SUPPORTS_VPE_LOADER
2091 def_bool CRASH_RESERVE !! 2289 bool
>> 2290 depends on SYS_SUPPORTS_MULTITHREADING
>> 2291 help
>> 2292 Indicates that the platform supports the VPE loader, and provides
>> 2293 physical_memsize.
2092 2294
2093 config PHYSICAL_START !! 2295 config MIPS_VPE_LOADER
2094 hex "Physical address where the kerne !! 2296 bool "VPE loader support."
2095 default "0x1000000" !! 2297 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2298 select CPU_MIPSR2_IRQ_VI
>> 2299 select CPU_MIPSR2_IRQ_EI
>> 2300 select MIPS_MT
2096 help 2301 help
2097 This gives the physical address whe !! 2302 Includes a loader for loading an elf relocatable object
>> 2303 onto another VPE and running it.
2098 2304
2099 If the kernel is not relocatable (C !! 2305 config MIPS_VPE_LOADER_CMP
2100 will decompress itself to above phy !! 2306 bool
2101 Otherwise, bzImage will run from th !! 2307 default "y"
2102 by the boot loader. The only except !! 2308 depends on MIPS_VPE_LOADER && MIPS_CMP
2103 above physical address, in which ca <<
2104 <<
2105 In normal kdump cases one does not <<
2106 as now bzImage can be compiled as a <<
2107 (CONFIG_RELOCATABLE=y) and be used <<
2108 address. This option is mainly usef <<
2109 to use a bzImage for capturing the <<
2110 vmlinux instead. vmlinux is not rel <<
2111 to be specifically compiled to run <<
2112 (normally a reserved region) and th <<
2113 <<
2114 So if you are using bzImage for cap <<
2115 leave the value here unchanged to 0 <<
2116 CONFIG_RELOCATABLE=y. Otherwise if <<
2117 for capturing the crash dump change <<
2118 the reserved region. In other word <<
2119 the "X" value as specified in the " <<
2120 command line boot parameter passed <<
2121 kernel. Please take a look at Docum <<
2122 for more details about crash dumps. <<
2123 <<
2124 Usage of bzImage for capturing the <<
2125 one does not have to build two kern <<
2126 as production kernel and capture ke <<
2127 gone away after relocatable bzImage <<
2128 is present because there are users <<
2129 vmlinux for dump capture. This opti <<
2130 line. <<
2131 2309
2132 Don't change this unless you know w !! 2310 config MIPS_VPE_LOADER_MT
>> 2311 bool
>> 2312 default "y"
>> 2313 depends on MIPS_VPE_LOADER && !MIPS_CMP
2133 2314
2134 config RELOCATABLE !! 2315 config MIPS_VPE_LOADER_TOM
2135 bool "Build a relocatable kernel" !! 2316 bool "Load VPE program into memory hidden from linux"
>> 2317 depends on MIPS_VPE_LOADER
2136 default y 2318 default y
2137 help 2319 help
2138 This builds a kernel image that ret !! 2320 The loader can use memory that is present but has been hidden from
2139 so it can be loaded someplace besid !! 2321 Linux using the kernel command line option "mem=xxMB". It's up to
2140 The relocations tend to make the ke !! 2322 you to ensure the amount you put in the option and the space your
2141 but are discarded at runtime. !! 2323 program requires is less or equal to the amount physically present.
2142 2324
2143 One use is for the kexec on panic c !! 2325 config MIPS_VPE_APSP_API
2144 must live at a different physical a !! 2326 bool "Enable support for AP/SP API (RTLX)"
2145 kernel. !! 2327 depends on MIPS_VPE_LOADER
2146 <<
2147 Note: If CONFIG_RELOCATABLE=y, then <<
2148 it has been loaded at and the compi <<
2149 (CONFIG_PHYSICAL_START) is used as <<
2150 2328
2151 config RANDOMIZE_BASE !! 2329 config MIPS_VPE_APSP_API_CMP
2152 bool "Randomize the address of the ke !! 2330 bool
2153 depends on RELOCATABLE !! 2331 default "y"
2154 default y !! 2332 depends on MIPS_VPE_APSP_API && MIPS_CMP
2155 help <<
2156 In support of Kernel Address Space <<
2157 this randomizes the physical addres <<
2158 is decompressed and the virtual add <<
2159 image is mapped, as a security feat <<
2160 attempts relying on knowledge of th <<
2161 code internals. <<
2162 <<
2163 On 64-bit, the kernel physical and <<
2164 randomized separately. The physical <<
2165 between 16MB and the top of physica <<
2166 virtual address will be randomized <<
2167 of entropy). Note that this also re <<
2168 available to kernel modules from 1. <<
2169 <<
2170 On 32-bit, the kernel physical and <<
2171 randomized together. They will be r <<
2172 512MB (8 bits of entropy). <<
2173 <<
2174 Entropy is generated using the RDRA <<
2175 supported. If RDTSC is supported, i <<
2176 the entropy pool as well. If neithe <<
2177 supported, then entropy is read fro <<
2178 usable entropy is limited by the ke <<
2179 2GB addressing, and that PHYSICAL_A <<
2180 minimum of 2MB. As a result, only 1 <<
2181 theoretically possible, but the imp <<
2182 limited due to memory layouts. <<
2183 <<
2184 If unsure, say Y. <<
2185 2333
2186 # Relocation on x86 needs some additional bui !! 2334 config MIPS_VPE_APSP_API_MT
2187 config X86_NEED_RELOCS !! 2335 bool
2188 def_bool y !! 2336 default "y"
2189 depends on RANDOMIZE_BASE || (X86_32 !! 2337 depends on MIPS_VPE_APSP_API && !MIPS_CMP
2190 2338
2191 config PHYSICAL_ALIGN !! 2339 config MIPS_CMP
2192 hex "Alignment value to which kernel !! 2340 bool "MIPS CMP framework support (DEPRECATED)"
2193 default "0x200000" !! 2341 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
2194 range 0x2000 0x1000000 if X86_32 !! 2342 select SMP
2195 range 0x200000 0x1000000 if X86_64 !! 2343 select SYNC_R4K
>> 2344 select SYS_SUPPORTS_SMP
>> 2345 select WEAK_ORDERING
>> 2346 default n
2196 help 2347 help
2197 This value puts the alignment restr !! 2348 Select this if you are using a bootloader which implements the "CMP
2198 where kernel is loaded and run from !! 2349 framework" protocol (ie. YAMON) and want your kernel to make use of
2199 address which meets above alignment !! 2350 its ability to start secondary CPUs.
>> 2351
>> 2352 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2353 instead of this.
>> 2354
>> 2355 config MIPS_CPS
>> 2356 bool "MIPS Coherent Processing System support"
>> 2357 depends on SYS_SUPPORTS_MIPS_CPS
>> 2358 select MIPS_CM
>> 2359 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2360 select SMP
>> 2361 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2362 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2363 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2364 select SYS_SUPPORTS_SMP
>> 2365 select WEAK_ORDERING
>> 2366 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2367 help
>> 2368 Select this if you wish to run an SMP kernel across multiple cores
>> 2369 within a MIPS Coherent Processing System. When this option is
>> 2370 enabled the kernel will probe for other cores and boot them with
>> 2371 no external assistance. It is safe to enable this when hardware
>> 2372 support is unavailable.
2200 2373
2201 If bootloader loads the kernel at a !! 2374 config MIPS_CPS_PM
2202 CONFIG_RELOCATABLE is set, kernel w !! 2375 depends on MIPS_CPS
2203 address aligned to above value and !! 2376 bool
2204 2377
2205 If bootloader loads the kernel at a !! 2378 config MIPS_CM
2206 CONFIG_RELOCATABLE is not set, kern !! 2379 bool
2207 load address and decompress itself !! 2380 select MIPS_CPC
2208 compiled for and run from there. Th <<
2209 compiled already meets above alignm <<
2210 end result is that kernel runs from <<
2211 above alignment restrictions. <<
2212 2381
2213 On 32-bit this value must be a mult !! 2382 config MIPS_CPC
2214 this value must be a multiple of 0x !! 2383 bool
2215 2384
2216 Don't change this unless you know w !! 2385 config SB1_PASS_2_WORKAROUNDS
>> 2386 bool
>> 2387 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2388 default y
2217 2389
2218 config DYNAMIC_MEMORY_LAYOUT !! 2390 config SB1_PASS_2_1_WORKAROUNDS
2219 bool 2391 bool
>> 2392 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2393 default y
>> 2394
>> 2395 choice
>> 2396 prompt "SmartMIPS or microMIPS ASE support"
>> 2397
>> 2398 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
>> 2399 bool "None"
2220 help 2400 help
2221 This option makes base addresses of !! 2401 Select this if you want neither microMIPS nor SmartMIPS support
2222 __PAGE_OFFSET movable during boot. <<
2223 2402
2224 config RANDOMIZE_MEMORY !! 2403 config CPU_HAS_SMARTMIPS
2225 bool "Randomize the kernel memory sec !! 2404 depends on SYS_SUPPORTS_SMARTMIPS
2226 depends on X86_64 !! 2405 bool "SmartMIPS"
2227 depends on RANDOMIZE_BASE !! 2406 help
2228 select DYNAMIC_MEMORY_LAYOUT !! 2407 SmartMIPS is a extension of the MIPS32 architecture aimed at
2229 default RANDOMIZE_BASE !! 2408 increased security at both hardware and software level for
>> 2409 smartcards. Enabling this option will allow proper use of the
>> 2410 SmartMIPS instructions by Linux applications. However a kernel with
>> 2411 this option will not work on a MIPS core without SmartMIPS core. If
>> 2412 you don't know you probably don't have SmartMIPS and should say N
>> 2413 here.
>> 2414
>> 2415 config CPU_MICROMIPS
>> 2416 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2417 bool "microMIPS"
2230 help 2418 help
2231 Randomizes the base virtual address !! 2419 When this option is enabled the kernel will be built using the
2232 (physical memory mapping, vmalloc & !! 2420 microMIPS ISA
2233 makes exploits relying on predictab !! 2421
2234 !! 2422 endchoice
2235 The order of allocations remains un !! 2423
2236 the same way as RANDOMIZE_BASE. Cur !! 2424 config CPU_HAS_MSA
2237 configuration have in average 30,00 !! 2425 bool "Support for the MIPS SIMD Architecture"
2238 addresses for each memory section. !! 2426 depends on CPU_SUPPORTS_MSA
>> 2427 depends on MIPS_FP_SUPPORT
>> 2428 depends on 64BIT || MIPS_O32_FP64_SUPPORT
>> 2429 help
>> 2430 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2431 and a set of SIMD instructions to operate on them. When this option
>> 2432 is enabled the kernel will support allocating & switching MSA
>> 2433 vector register contexts. If you know that your kernel will only be
>> 2434 running on CPUs which do not support MSA or that your userland will
>> 2435 not be making use of it then you may wish to say N here to reduce
>> 2436 the size & complexity of your kernel.
2239 2437
2240 If unsure, say Y. 2438 If unsure, say Y.
2241 2439
2242 config RANDOMIZE_MEMORY_PHYSICAL_PADDING !! 2440 config CPU_HAS_WB
2243 hex "Physical memory mapping padding" !! 2441 bool
2244 depends on RANDOMIZE_MEMORY <<
2245 default "0xa" if MEMORY_HOTPLUG <<
2246 default "0x0" <<
2247 range 0x1 0x40 if MEMORY_HOTPLUG <<
2248 range 0x0 0x40 <<
2249 help <<
2250 Define the padding in terabytes add <<
2251 memory size during kernel memory ra <<
2252 for memory hotplug support but redu <<
2253 address randomization. <<
2254 2442
2255 If unsure, leave at the default val !! 2443 config XKS01
>> 2444 bool
2256 2445
2257 config ADDRESS_MASKING !! 2446 config CPU_HAS_DIEI
2258 bool "Linear Address Masking support" !! 2447 depends on !CPU_DIEI_BROKEN
2259 depends on X86_64 !! 2448 bool
2260 depends on COMPILE_TEST || !CPU_MITIG <<
2261 help <<
2262 Linear Address Masking (LAM) modifi <<
2263 to 64-bit linear addresses, allowin <<
2264 untranslated address bits for metad <<
2265 2449
2266 The capability can be used for effi !! 2450 config CPU_DIEI_BROKEN
2267 implementation and for optimization !! 2451 bool
2268 2452
2269 config HOTPLUG_CPU !! 2453 config CPU_HAS_RIXI
2270 def_bool y !! 2454 bool
2271 depends on SMP <<
2272 2455
2273 config COMPAT_VDSO !! 2456 config CPU_NO_LOAD_STORE_LR
2274 def_bool n !! 2457 bool
2275 prompt "Disable the 32-bit vDSO (need <<
2276 depends on COMPAT_32 <<
2277 help 2458 help
2278 Certain buggy versions of glibc wil !! 2459 CPU lacks support for unaligned load and store instructions:
2279 presented with a 32-bit vDSO that i !! 2460 LWL, LWR, SWL, SWR (Load/store word left/right).
2280 indicated in its segment table. !! 2461 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
2281 !! 2462 systems).
2282 The bug was introduced by f866314b8 <<
2283 and fixed by 3b3ddb4f7db98ec9e912cc <<
2284 49ad572a70b8aeb91e57483a11dd1b77e31 <<
2285 the only released version with the <<
2286 contains a buggy "glibc 2.3.2". <<
2287 <<
2288 The symptom of the bug is that ever <<
2289 dl_main: Assertion `(void *) ph->p_ <<
2290 <<
2291 Saying Y here changes the default v <<
2292 option from 1 to 0, which turns off <<
2293 This works around the glibc bug but <<
2294 2463
2295 If unsure, say N: if you are compil !! 2464 #
2296 are unlikely to be using a buggy ve !! 2465 # Vectored interrupt mode is an R2 feature
>> 2466 #
>> 2467 config CPU_MIPSR2_IRQ_VI
>> 2468 bool
2297 2469
2298 choice !! 2470 #
2299 prompt "vsyscall table for legacy app !! 2471 # Extended interrupt mode is an R2 feature
2300 depends on X86_64 !! 2472 #
2301 default LEGACY_VSYSCALL_XONLY !! 2473 config CPU_MIPSR2_IRQ_EI
2302 help !! 2474 bool
2303 Legacy user code that does not know <<
2304 to be able to issue three syscalls <<
2305 kernel space. Since this location i <<
2306 it can be used to assist security v <<
2307 <<
2308 This setting can be changed at boot <<
2309 line parameter vsyscall=[emulate|xo <<
2310 is deprecated and can only be enabl <<
2311 line. <<
2312 <<
2313 On a system with recent enough glib <<
2314 static binaries, you can say None w <<
2315 to improve security. <<
2316 2475
2317 If unsure, select "Emulate executio !! 2476 config CPU_HAS_SYNC
>> 2477 bool
>> 2478 depends on !CPU_R3000
>> 2479 default y
2318 2480
2319 config LEGACY_VSYSCALL_XONLY !! 2481 #
2320 bool "Emulate execution only" !! 2482 # CPU non-features
2321 help !! 2483 #
2322 The kernel traps and emulat <<
2323 address mapping and does no <<
2324 configuration is recommende <<
2325 legacy vsyscall area but su <<
2326 instrumentation of legacy c <<
2327 certain uses of the vsyscal <<
2328 buffer. <<
2329 2484
2330 config LEGACY_VSYSCALL_NONE !! 2485 # Work around the "daddi" and "daddiu" CPU errata:
2331 bool "None" !! 2486 #
2332 help !! 2487 # - The `daddi' instruction fails to trap on overflow.
2333 There will be no vsyscall m !! 2488 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2334 eliminate any risk of ASLR !! 2489 # erratum #23
2335 fixed address mapping. Atte !! 2490 #
2336 will be reported to dmesg, !! 2491 # - The `daddiu' instruction can produce an incorrect result.
2337 malicious userspace program !! 2492 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2493 # erratum #41
>> 2494 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2495 # #15
>> 2496 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2497 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2498 config CPU_DADDI_WORKAROUNDS
>> 2499 bool
2338 2500
2339 endchoice !! 2501 # Work around certain R4000 CPU errata (as implemented by GCC):
>> 2502 #
>> 2503 # - A double-word or a variable shift may give an incorrect result
>> 2504 # if executed immediately after starting an integer division:
>> 2505 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2506 # erratum #28
>> 2507 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2508 # #19
>> 2509 #
>> 2510 # - A double-word or a variable shift may give an incorrect result
>> 2511 # if executed while an integer multiplication is in progress:
>> 2512 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2513 # errata #16 & #28
>> 2514 #
>> 2515 # - An integer division may give an incorrect result if started in
>> 2516 # a delay slot of a taken branch or a jump:
>> 2517 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2518 # erratum #52
>> 2519 config CPU_R4000_WORKAROUNDS
>> 2520 bool
>> 2521 select CPU_R4400_WORKAROUNDS
2340 2522
2341 config CMDLINE_BOOL !! 2523 # Work around certain R4400 CPU errata (as implemented by GCC):
2342 bool "Built-in kernel command line" !! 2524 #
2343 help !! 2525 # - A double-word or a variable shift may give an incorrect result
2344 Allow for specifying boot arguments !! 2526 # if executed immediately after starting an integer division:
2345 build time. On some systems (e.g. !! 2527 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
2346 necessary or convenient to provide !! 2528 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
2347 kernel boot arguments with the kern !! 2529 config CPU_R4400_WORKAROUNDS
2348 to not rely on the boot loader to p !! 2530 bool
2349 <<
2350 To compile command line arguments i <<
2351 set this option to 'Y', then fill i <<
2352 boot arguments in CONFIG_CMDLINE. <<
2353 <<
2354 Systems with fully functional boot <<
2355 should leave this option set to 'N' <<
2356 <<
2357 config CMDLINE <<
2358 string "Built-in kernel command strin <<
2359 depends on CMDLINE_BOOL <<
2360 default "" <<
2361 help <<
2362 Enter arguments here that should be <<
2363 image and used at boot time. If th <<
2364 command line at boot time, it is ap <<
2365 form the full kernel command line, <<
2366 <<
2367 However, you can use the CONFIG_CMD <<
2368 change this behavior. <<
2369 <<
2370 In most cases, the command line (wh <<
2371 by the boot loader) should specify <<
2372 file system. <<
2373 <<
2374 config CMDLINE_OVERRIDE <<
2375 bool "Built-in command line overrides <<
2376 depends on CMDLINE_BOOL && CMDLINE != <<
2377 help <<
2378 Set this option to 'Y' to have the <<
2379 command line, and use ONLY the buil <<
2380 2531
2381 This is used to work around broken !! 2532 config CPU_R4X00_BUGS64
2382 be set to 'N' under normal conditio !! 2533 bool
>> 2534 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
2383 2535
2384 config MODIFY_LDT_SYSCALL !! 2536 config MIPS_ASID_SHIFT
2385 bool "Enable the LDT (local descripto !! 2537 int
2386 default y !! 2538 default 6 if CPU_R3000
2387 help !! 2539 default 0
2388 Linux can allow user programs to in <<
2389 Local Descriptor Table (LDT) using <<
2390 call. This is required to run 16-b <<
2391 DOSEMU or some Wine programs. It i <<
2392 threading libraries. <<
2393 <<
2394 Enabling this feature adds a small <<
2395 context switches and increases the <<
2396 surface. Disabling it removes the <<
2397 <<
2398 Saying 'N' here may make sense for <<
2399 <<
2400 config STRICT_SIGALTSTACK_SIZE <<
2401 bool "Enforce strict size checking fo <<
2402 depends on DYNAMIC_SIGFRAME <<
2403 help <<
2404 For historical reasons MINSIGSTKSZ <<
2405 already too small with AVX512 suppo <<
2406 enforce strict checking of the siga <<
2407 real size of the FPU frame. This op <<
2408 by default. It can also be controll <<
2409 line option 'strict_sas_size' indep <<
2410 switch. Enabling it might break exi <<
2411 allocate a too small sigaltstack bu <<
2412 never get a signal delivered. <<
2413 <<
2414 Say 'N' unless you want to really e <<
2415 <<
2416 config CFI_AUTO_DEFAULT <<
2417 bool "Attempt to use FineIBT by defau <<
2418 depends on FINEIBT <<
2419 default y <<
2420 help <<
2421 Attempt to use FineIBT by default a <<
2422 this is the same as booting with "c <<
2423 this is the same as booting with "c <<
2424 2540
2425 source "kernel/livepatch/Kconfig" !! 2541 config MIPS_ASID_BITS
>> 2542 int
>> 2543 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2544 default 6 if CPU_R3000
>> 2545 default 8
2426 2546
2427 endmenu !! 2547 config MIPS_ASID_BITS_VARIABLE
>> 2548 bool
2428 2549
2429 config CC_HAS_NAMED_AS !! 2550 config MIPS_CRC_SUPPORT
2430 def_bool $(success,echo 'int __seg_fs !! 2551 bool
2431 depends on CC_IS_GCC <<
2432 2552
2433 config CC_HAS_NAMED_AS_FIXED_SANITIZERS !! 2553 # R4600 erratum. Due to the lack of errata information the exact
2434 def_bool CC_IS_GCC && GCC_VERSION >= !! 2554 # technical details aren't known. I've experimentally found that disabling
>> 2555 # interrupts during indexed I-cache flushes seems to be sufficient to deal
>> 2556 # with the issue.
>> 2557 config WAR_R4600_V1_INDEX_ICACHEOP
>> 2558 bool
2435 2559
2436 config USE_X86_SEG_SUPPORT !! 2560 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
2437 def_bool y !! 2561 #
2438 depends on CC_HAS_NAMED_AS !! 2562 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
2439 # !! 2563 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
2440 # -fsanitize=kernel-address (KASAN) a !! 2564 # executed if there is no other dcache activity. If the dcache is
2441 # (KCSAN) are incompatible with named !! 2565 # accessed for another instruction immediately preceding when these
2442 # GCC < 13.3 - see GCC PR sanitizer/1 !! 2566 # cache instructions are executing, it is possible that the dcache
2443 # !! 2567 # tag match outputs used by these cache instructions will be
2444 depends on !(KASAN || KCSAN) || CC_HA !! 2568 # incorrect. These cache instructions should be preceded by at least
>> 2569 # four instructions that are not any kind of load or store
>> 2570 # instruction.
>> 2571 #
>> 2572 # This is not allowed: lw
>> 2573 # nop
>> 2574 # nop
>> 2575 # nop
>> 2576 # cache Hit_Writeback_Invalidate_D
>> 2577 #
>> 2578 # This is allowed: lw
>> 2579 # nop
>> 2580 # nop
>> 2581 # nop
>> 2582 # nop
>> 2583 # cache Hit_Writeback_Invalidate_D
>> 2584 config WAR_R4600_V1_HIT_CACHEOP
>> 2585 bool
2445 2586
2446 config CC_HAS_SLS !! 2587 # Writeback and invalidate the primary cache dcache before DMA.
2447 def_bool $(cc-option,-mharden-sls=all !! 2588 #
>> 2589 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2590 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2591 # operate correctly if the internal data cache refill buffer is empty. These
>> 2592 # CACHE instructions should be separated from any potential data cache miss
>> 2593 # by a load instruction to an uncached address to empty the response buffer."
>> 2594 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2595 # in .pdf format.)
>> 2596 config WAR_R4600_V2_HIT_CACHEOP
>> 2597 bool
2448 2598
2449 config CC_HAS_RETURN_THUNK !! 2599 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
2450 def_bool $(cc-option,-mfunction-retur !! 2600 # the line which this instruction itself exists, the following
>> 2601 # operation is not guaranteed."
>> 2602 #
>> 2603 # Workaround: do two phase flushing for Index_Invalidate_I
>> 2604 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2605 bool
2451 2606
2452 config CC_HAS_ENTRY_PADDING !! 2607 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2453 def_bool $(cc-option,-fpatchable-func !! 2608 # opposes it being called that) where invalid instructions in the same
>> 2609 # I-cache line worth of instructions being fetched may case spurious
>> 2610 # exceptions.
>> 2611 config WAR_ICACHE_REFILLS
>> 2612 bool
2454 2613
2455 config FUNCTION_PADDING_CFI !! 2614 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
2456 int !! 2615 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2457 default 59 if FUNCTION_ALIGNMENT_64B !! 2616 config WAR_R10000_LLSC
2458 default 27 if FUNCTION_ALIGNMENT_32B !! 2617 bool
2459 default 11 if FUNCTION_ALIGNMENT_16B <<
2460 default 3 if FUNCTION_ALIGNMENT_8B <<
2461 default 0 <<
2462 <<
2463 # Basically: FUNCTION_ALIGNMENT - 5*CFI_CLANG <<
2464 # except Kconfig can't do arithmetic :/ <<
2465 config FUNCTION_PADDING_BYTES <<
2466 int <<
2467 default FUNCTION_PADDING_CFI if CFI_C <<
2468 default FUNCTION_ALIGNMENT <<
2469 2618
2470 config CALL_PADDING !! 2619 # 34K core erratum: "Problems Executing the TLBR Instruction"
2471 def_bool n !! 2620 config WAR_MIPS34K_MISSED_ITLB
2472 depends on CC_HAS_ENTRY_PADDING && OB !! 2621 bool
2473 select FUNCTION_ALIGNMENT_16B <<
2474 2622
2475 config FINEIBT !! 2623 #
2476 def_bool y !! 2624 # - Highmem only makes sense for the 32-bit kernel.
2477 depends on X86_KERNEL_IBT && CFI_CLAN !! 2625 # - The current highmem code will only work properly on physically indexed
2478 select CALL_PADDING !! 2626 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2627 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2628 # moment we protect the user and offer the highmem option only on machines
>> 2629 # where it's known to be safe. This will not offer highmem on a few systems
>> 2630 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2631 # indexed CPUs but we're playing safe.
>> 2632 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2633 # know they might have memory configurations that could make use of highmem
>> 2634 # support.
>> 2635 #
>> 2636 config HIGHMEM
>> 2637 bool "High Memory Support"
>> 2638 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2639 select KMAP_LOCAL
2479 2640
2480 config HAVE_CALL_THUNKS !! 2641 config CPU_SUPPORTS_HIGHMEM
2481 def_bool y !! 2642 bool
2482 depends on CC_HAS_ENTRY_PADDING && MI <<
2483 2643
2484 config CALL_THUNKS !! 2644 config SYS_SUPPORTS_HIGHMEM
2485 def_bool n !! 2645 bool
2486 select CALL_PADDING <<
2487 2646
2488 config PREFIX_SYMBOLS !! 2647 config SYS_SUPPORTS_SMARTMIPS
2489 def_bool y !! 2648 bool
2490 depends on CALL_PADDING && !CFI_CLANG <<
2491 2649
2492 menuconfig CPU_MITIGATIONS !! 2650 config SYS_SUPPORTS_MICROMIPS
2493 bool "Mitigations for CPU vulnerabili !! 2651 bool
2494 default y !! 2652
>> 2653 config SYS_SUPPORTS_MIPS16
>> 2654 bool
2495 help 2655 help
2496 Say Y here to enable options which !! 2656 This option must be set if a kernel might be executed on a MIPS16-
2497 vulnerabilities (usually related to !! 2657 enabled CPU even if MIPS16 is not actually being used. In other
2498 Mitigations can be disabled or rest !! 2658 words, it makes the kernel MIPS16-tolerant.
2499 via the "mitigations" kernel parame <<
2500 2659
2501 If you say N, all mitigations will !! 2660 config CPU_SUPPORTS_MSA
2502 overridden at runtime. !! 2661 bool
2503 2662
2504 Say 'Y', unless you really know wha !! 2663 config ARCH_FLATMEM_ENABLE
>> 2664 def_bool y
>> 2665 depends on !NUMA && !CPU_LOONGSON2EF
2505 2666
2506 if CPU_MITIGATIONS !! 2667 config ARCH_SPARSEMEM_ENABLE
>> 2668 bool
2507 2669
2508 config MITIGATION_PAGE_TABLE_ISOLATION !! 2670 config NUMA
2509 bool "Remove the kernel mapping in us !! 2671 bool "NUMA Support"
2510 default y !! 2672 depends on SYS_SUPPORTS_NUMA
2511 depends on (X86_64 || X86_PAE) !! 2673 select SMP
>> 2674 select HAVE_SETUP_PER_CPU_AREA
>> 2675 select NEED_PER_CPU_EMBED_FIRST_CHUNK
2512 help 2676 help
2513 This feature reduces the number of !! 2677 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2514 ensuring that the majority of kerne !! 2678 Access). This option improves performance on systems with more
2515 into userspace. !! 2679 than two nodes; on two node systems it is generally better to
>> 2680 leave it disabled; on single node systems leave this option
>> 2681 disabled.
2516 2682
2517 See Documentation/arch/x86/pti.rst !! 2683 config SYS_SUPPORTS_NUMA
>> 2684 bool
2518 2685
2519 config MITIGATION_RETPOLINE !! 2686 config HAVE_ARCH_NODEDATA_EXTENSION
2520 bool "Avoid speculative indirect bran !! 2687 bool
2521 select OBJTOOL if HAVE_OBJTOOL <<
2522 default y <<
2523 help <<
2524 Compile kernel with the retpoline c <<
2525 kernel-to-user data leaks by avoidi <<
2526 branches. Requires a compiler with <<
2527 support for full protection. The ke <<
2528 <<
2529 config MITIGATION_RETHUNK <<
2530 bool "Enable return-thunks" <<
2531 depends on MITIGATION_RETPOLINE && CC <<
2532 select OBJTOOL if HAVE_OBJTOOL <<
2533 default y if X86_64 <<
2534 help <<
2535 Compile the kernel with the return- <<
2536 against kernel-to-user data leaks b <<
2537 Requires a compiler with -mfunction <<
2538 support for full protection. The ke <<
2539 <<
2540 config MITIGATION_UNRET_ENTRY <<
2541 bool "Enable UNRET on kernel entry" <<
2542 depends on CPU_SUP_AMD && MITIGATION_ <<
2543 default y <<
2544 help <<
2545 Compile the kernel with support for <<
2546 2688
2547 config MITIGATION_CALL_DEPTH_TRACKING !! 2689 config RELOCATABLE
2548 bool "Mitigate RSB underflow with cal !! 2690 bool "Relocatable kernel"
2549 depends on CPU_SUP_INTEL && HAVE_CALL !! 2691 depends on SYS_SUPPORTS_RELOCATABLE
2550 select HAVE_DYNAMIC_FTRACE_NO_PATCHAB !! 2692 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
2551 select CALL_THUNKS !! 2693 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
2552 default y !! 2694 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
2553 help !! 2695 CPU_P5600 || CAVIUM_OCTEON_SOC || \
2554 Compile the kernel with call depth !! 2696 CPU_LOONGSON64
2555 SKL Return-Speculation-Buffer (RSB) <<
2556 mitigation is off by default and ne <<
2557 kernel command line via the retblee <<
2558 non-affected systems the overhead o <<
2559 the call depth tracking is using ru <<
2560 in a compiler generated padding are <<
2561 increases text size by ~5%. For non <<
2562 is unused. On affected SKL systems <<
2563 performance gain over the IBRS miti <<
2564 <<
2565 config CALL_THUNKS_DEBUG <<
2566 bool "Enable call thunks and call dep <<
2567 depends on MITIGATION_CALL_DEPTH_TRAC <<
2568 select FUNCTION_ALIGNMENT_32B <<
2569 default n <<
2570 help <<
2571 Enable call/ret counters for imbala <<
2572 a noisy dmesg about callthunks gene <<
2573 trouble shooting. The debug prints <<
2574 kernel command line with 'debug-cal <<
2575 Only enable this when you are debug <<
2576 creates a noticeable runtime overhe <<
2577 <<
2578 config MITIGATION_IBPB_ENTRY <<
2579 bool "Enable IBPB on kernel entry" <<
2580 depends on CPU_SUP_AMD && X86_64 <<
2581 default y <<
2582 help 2697 help
2583 Compile the kernel with support for !! 2698 This builds a kernel image that retains relocation information
>> 2699 so it can be loaded someplace besides the default 1MB.
>> 2700 The relocations make the kernel binary about 15% larger,
>> 2701 but are discarded at runtime
2584 2702
2585 config MITIGATION_IBRS_ENTRY !! 2703 config RELOCATION_TABLE_SIZE
2586 bool "Enable IBRS on kernel entry" !! 2704 hex "Relocation table size"
2587 depends on CPU_SUP_INTEL && X86_64 !! 2705 depends on RELOCATABLE
2588 default y !! 2706 range 0x0 0x01000000
>> 2707 default "0x00200000" if CPU_LOONGSON64
>> 2708 default "0x00100000"
2589 help 2709 help
2590 Compile the kernel with support for !! 2710 A table of relocation data will be appended to the kernel binary
2591 This mitigates both spectre_v2 and !! 2711 and parsed at boot to fix up the relocated kernel.
2592 performance. <<
2593 2712
2594 config MITIGATION_SRSO !! 2713 This option allows the amount of space reserved for the table to be
2595 bool "Mitigate speculative RAS overfl !! 2714 adjusted, although the default of 1Mb should be ok in most cases.
2596 depends on CPU_SUP_AMD && X86_64 && M <<
2597 default y <<
2598 help <<
2599 Enable the SRSO mitigation needed o <<
2600 2715
2601 config MITIGATION_SLS !! 2716 The build will fail and a valid size suggested if this is too small.
2602 bool "Mitigate Straight-Line-Speculat !! 2717
2603 depends on CC_HAS_SLS && X86_64 !! 2718 If unsure, leave at the default value.
2604 select OBJTOOL if HAVE_OBJTOOL !! 2719
2605 default n !! 2720 config RANDOMIZE_BASE
2606 help !! 2721 bool "Randomize the address of the kernel image"
2607 Compile the kernel with straight-li !! 2722 depends on RELOCATABLE
2608 against straight line speculation. <<
2609 larger. <<
2610 <<
2611 config MITIGATION_GDS <<
2612 bool "Mitigate Gather Data Sampling" <<
2613 depends on CPU_SUP_INTEL <<
2614 default y <<
2615 help <<
2616 Enable mitigation for Gather Data S <<
2617 vulnerability which allows unprivil <<
2618 which was previously stored in vect <<
2619 instructions to infer the stale vec <<
2620 <<
2621 config MITIGATION_RFDS <<
2622 bool "RFDS Mitigation" <<
2623 depends on CPU_SUP_INTEL <<
2624 default y <<
2625 help <<
2626 Enable mitigation for Register File <<
2627 RFDS is a hardware vulnerability wh <<
2628 allows unprivileged speculative acc <<
2629 stored in floating point, vector an <<
2630 See also <file:Documentation/admin- <<
2631 <<
2632 config MITIGATION_SPECTRE_BHI <<
2633 bool "Mitigate Spectre-BHB (Branch Hi <<
2634 depends on CPU_SUP_INTEL <<
2635 default y <<
2636 help <<
2637 Enable BHI mitigations. BHI attacks <<
2638 where the branch history buffer is <<
2639 indirect branches. <<
2640 See <file:Documentation/admin-guide <<
2641 <<
2642 config MITIGATION_MDS <<
2643 bool "Mitigate Microarchitectural Dat <<
2644 depends on CPU_SUP_INTEL <<
2645 default y <<
2646 help <<
2647 Enable mitigation for Microarchitec <<
2648 a hardware vulnerability which allo <<
2649 to data which is available in vario <<
2650 See also <file:Documentation/admin- <<
2651 <<
2652 config MITIGATION_TAA <<
2653 bool "Mitigate TSX Asynchronous Abort <<
2654 depends on CPU_SUP_INTEL <<
2655 default y <<
2656 help <<
2657 Enable mitigation for TSX Asynchron <<
2658 vulnerability that allows unprivile <<
2659 which is available in various CPU i <<
2660 asynchronous aborts within an Intel <<
2661 See also <file:Documentation/admin- <<
2662 <<
2663 config MITIGATION_MMIO_STALE_DATA <<
2664 bool "Mitigate MMIO Stale Data hardwa <<
2665 depends on CPU_SUP_INTEL <<
2666 default y <<
2667 help <<
2668 Enable mitigation for MMIO Stale Da <<
2669 Stale Data Vulnerabilities are a cl <<
2670 vulnerabilities that can expose dat <<
2671 attacker to have access to MMIO. <<
2672 See also <<
2673 <file:Documentation/admin-guide/hw- <<
2674 <<
2675 config MITIGATION_L1TF <<
2676 bool "Mitigate L1 Terminal Fault (L1T <<
2677 depends on CPU_SUP_INTEL <<
2678 default y <<
2679 help <<
2680 Mitigate L1 Terminal Fault (L1TF) h <<
2681 hardware vulnerability which allows <<
2682 available in the Level 1 Data Cache <<
2683 See <file:Documentation/admin-guide <<
2684 <<
2685 config MITIGATION_RETBLEED <<
2686 bool "Mitigate RETBleed hardware bug" <<
2687 depends on (CPU_SUP_INTEL && MITIGATI <<
2688 default y <<
2689 help 2723 help
2690 Enable mitigation for RETBleed (Arb !! 2724 Randomizes the physical and virtual address at which the
2691 with Return Instructions) vulnerabi !! 2725 kernel image is loaded, as a security feature that
2692 execution attack which takes advant !! 2726 deters exploit attempts relying on knowledge of the location
2693 in many modern microprocessors, sim !! 2727 of kernel internals.
2694 unprivileged attacker can use these !! 2728
2695 memory security restrictions to gai !! 2729 Entropy is generated using any coprocessor 0 registers available.
2696 that would otherwise be inaccessibl !! 2730
>> 2731 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
2697 2732
2698 config MITIGATION_SPECTRE_V1 !! 2733 If unsure, say N.
2699 bool "Mitigate SPECTRE V1 hardware bu !! 2734
>> 2735 config RANDOMIZE_BASE_MAX_OFFSET
>> 2736 hex "Maximum kASLR offset" if EXPERT
>> 2737 depends on RANDOMIZE_BASE
>> 2738 range 0x0 0x40000000 if EVA || 64BIT
>> 2739 range 0x0 0x08000000
>> 2740 default "0x01000000"
>> 2741 help
>> 2742 When kASLR is active, this provides the maximum offset that will
>> 2743 be applied to the kernel image. It should be set according to the
>> 2744 amount of physical RAM available in the target system minus
>> 2745 PHYSICAL_START and must be a power of 2.
>> 2746
>> 2747 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2748 EVA or 64-bit. The default is 16Mb.
>> 2749
>> 2750 config NODES_SHIFT
>> 2751 int
>> 2752 default "6"
>> 2753 depends on NUMA
>> 2754
>> 2755 config HW_PERF_EVENTS
>> 2756 bool "Enable hardware performance counter support for perf events"
>> 2757 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
2700 default y 2758 default y
2701 help 2759 help
2702 Enable mitigation for Spectre V1 (B !! 2760 Enable hardware performance counter support for perf events. If
2703 class of side channel attacks that !! 2761 disabled, perf events will use software events only.
2704 execution that bypasses conditional <<
2705 memory access bounds check. <<
2706 See also <file:Documentation/admin- <<
2707 2762
2708 config MITIGATION_SPECTRE_V2 !! 2763 config DMI
2709 bool "Mitigate SPECTRE V2 hardware bu !! 2764 bool "Enable DMI scanning"
>> 2765 depends on MACH_LOONGSON64
>> 2766 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
2710 default y 2767 default y
2711 help 2768 help
2712 Enable mitigation for Spectre V2 (B !! 2769 Enabled scanning of DMI to identify machine quirks. Say Y
2713 V2 is a class of side channel attac !! 2770 here unless you have verified that your setup is not
2714 indirect branch predictors inside t !! 2771 affected by entries in the DMI blacklist. Required by PNP
2715 attacks, the attacker can steer spe !! 2772 BIOS code.
2716 victim to gadget code by poisoning !! 2773
2717 used for predicting indirect branch !! 2774 config SMP
2718 See also <file:Documentation/admin- !! 2775 bool "Multi-Processing support"
2719 !! 2776 depends on SYS_SUPPORTS_SMP
2720 config MITIGATION_SRBDS <<
2721 bool "Mitigate Special Register Buffe <<
2722 depends on CPU_SUP_INTEL <<
2723 default y <<
2724 help 2777 help
2725 Enable mitigation for Special Regis !! 2778 This enables support for systems with more than one CPU. If you have
2726 SRBDS is a hardware vulnerability t !! 2779 a system with only one CPU, say N. If you have a system with more
2727 Sampling (MDS) techniques to infer !! 2780 than one CPU, say Y.
2728 register accesses. An unprivileged <<
2729 from RDRAND and RDSEED executed on <<
2730 using MDS techniques. <<
2731 See also <<
2732 <file:Documentation/admin-guide/hw- <<
2733 2781
2734 config MITIGATION_SSB !! 2782 If you say N here, the kernel will run on uni- and multiprocessor
2735 bool "Mitigate Speculative Store Bypa !! 2783 machines, but will use only one CPU of a multiprocessor machine. If
2736 default y !! 2784 you say Y here, the kernel will run on many, but not all,
>> 2785 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2786 will run faster if you say N here.
>> 2787
>> 2788 People using multiprocessor machines who say Y here should also say
>> 2789 Y to "Enhanced Real Time Clock Support", below.
>> 2790
>> 2791 See also the SMP-HOWTO available at
>> 2792 <https://www.tldp.org/docs.html#howto>.
>> 2793
>> 2794 If you don't know what to do here, say N.
>> 2795
>> 2796 config HOTPLUG_CPU
>> 2797 bool "Support for hot-pluggable CPUs"
>> 2798 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
2737 help 2799 help
2738 Enable mitigation for Speculative S !! 2800 Say Y here to allow turning CPUs off and on. CPUs can be
2739 hardware security vulnerability and !! 2801 controlled through /sys/devices/system/cpu.
2740 of speculative execution in a simil !! 2802 (Note: power management support will enable this option
2741 security vulnerabilities. !! 2803 automatically on SMP systems. )
>> 2804 Say N if you want to disable CPU hotplug.
2742 2805
2743 endif !! 2806 config SMP_UP
>> 2807 bool
2744 2808
2745 config ARCH_HAS_ADD_PAGES !! 2809 config SYS_SUPPORTS_MIPS_CMP
2746 def_bool y !! 2810 bool
2747 depends on ARCH_ENABLE_MEMORY_HOTPLUG <<
2748 2811
2749 menu "Power management and ACPI options" !! 2812 config SYS_SUPPORTS_MIPS_CPS
>> 2813 bool
2750 2814
2751 config ARCH_HIBERNATION_HEADER !! 2815 config SYS_SUPPORTS_SMP
2752 def_bool y !! 2816 bool
2753 depends on HIBERNATION <<
2754 2817
2755 source "kernel/power/Kconfig" !! 2818 config NR_CPUS_DEFAULT_4
>> 2819 bool
2756 2820
2757 source "drivers/acpi/Kconfig" !! 2821 config NR_CPUS_DEFAULT_8
>> 2822 bool
2758 2823
2759 config X86_APM_BOOT !! 2824 config NR_CPUS_DEFAULT_16
2760 def_bool y !! 2825 bool
2761 depends on APM <<
2762 2826
2763 menuconfig APM !! 2827 config NR_CPUS_DEFAULT_32
2764 tristate "APM (Advanced Power Managem !! 2828 bool
2765 depends on X86_32 && PM_SLEEP <<
2766 help <<
2767 APM is a BIOS specification for sav <<
2768 techniques. This is mostly useful f <<
2769 APM compliant BIOSes. If you say Y <<
2770 reset after a RESUME operation, the <<
2771 battery status information, and use <<
2772 notification of APM "events" (e.g. <<
2773 <<
2774 If you select "Y" here, you can dis <<
2775 BIOS by passing the "apm=off" optio <<
2776 <<
2777 Note that the APM support is almost <<
2778 machines with more than one CPU. <<
2779 <<
2780 In order to use APM, you will need <<
2781 and more information, read <file:Do <<
2782 and the Battery Powered Linux mini- <<
2783 <http://www.tldp.org/docs.html#howt <<
2784 <<
2785 This driver does not spin down disk <<
2786 manpage ("man 8 hdparm") for that), <<
2787 VESA-compliant "green" monitors. <<
2788 <<
2789 This driver does not support the TI <<
2790 486/DX4/75 because they don't have <<
2791 desktop machines also don't have co <<
2792 may cause those machines to panic d <<
2793 <<
2794 Generally, if you don't have a batt <<
2795 much point in using this driver and <<
2796 random kernel OOPSes or reboots tha <<
2797 anything, try disabling/enabling th <<
2798 APM in your BIOS). <<
2799 <<
2800 Some other things you should try wh <<
2801 "weird" problems: <<
2802 <<
2803 1) make sure that you have enough s <<
2804 enabled. <<
2805 2) pass the "idle=poll" option to t <<
2806 3) switch on floating point emulati <<
2807 the "no387" option to the kernel <<
2808 4) pass the "floppy=nodma" option t <<
2809 5) pass the "mem=4M" option to the <<
2810 all but the first 4 MB of RAM) <<
2811 6) make sure that the CPU is not ov <<
2812 7) read the sig11 FAQ at <http://ww <<
2813 8) disable the cache from your BIOS <<
2814 9) install a fan for the video card <<
2815 10) install a better fan for the CP <<
2816 11) exchange RAM chips <<
2817 12) exchange the motherboard. <<
2818 <<
2819 To compile this driver as a module, <<
2820 module will be called apm. <<
2821 <<
2822 if APM <<
2823 <<
2824 config APM_IGNORE_USER_SUSPEND <<
2825 bool "Ignore USER SUSPEND" <<
2826 help <<
2827 This option will ignore USER SUSPEN <<
2828 compliant APM BIOS, you want to say <<
2829 series notebooks, it is necessary t <<
2830 <<
2831 config APM_DO_ENABLE <<
2832 bool "Enable PM at boot time" <<
2833 help <<
2834 Enable APM features at boot time. F <<
2835 specification: "When disabled, the <<
2836 power manage devices, enter the Sta <<
2837 State, or take power saving steps i <<
2838 This driver will make CPU Idle call <<
2839 feature is turned off -- see "Do CP <<
2840 should always save battery power, b <<
2841 will be dependent on your BIOS impl <<
2842 this option off if your computer ha <<
2843 support, or if it beeps continuousl <<
2844 this off if you have a NEC UltraLit <<
2845 T400CDT. This is off by default sin <<
2846 this feature. <<
2847 <<
2848 config APM_CPU_IDLE <<
2849 depends on CPU_IDLE <<
2850 bool "Make CPU Idle calls when idle" <<
2851 help <<
2852 Enable calls to APM CPU Idle/CPU Bu <<
2853 On some machines, this can activate <<
2854 a slowed CPU clock rate, when the m <<
2855 are made after the idle loop has ru <<
2856 333 mS). On some machines, this wil <<
2857 whenever the CPU becomes idle. (On <<
2858 this option does nothing.) <<
2859 <<
2860 config APM_DISPLAY_BLANK <<
2861 bool "Enable console blanking using A <<
2862 help <<
2863 Enable console blanking using the A <<
2864 turn off the LCD backlight when the <<
2865 virtual console blanks the screen. <<
2866 the virtual console screen blanker, <<
2867 when using the X Window system. Thi <<
2868 do with your VESA-compliant power-s <<
2869 option doesn't work for all laptops <<
2870 backlight at all, or it might print <<
2871 especially if you are using gpm. <<
2872 <<
2873 config APM_ALLOW_INTS <<
2874 bool "Allow interrupts during APM BIO <<
2875 help <<
2876 Normally we disable external interr <<
2877 the APM BIOS as a measure to lessen <<
2878 BIOS implementation. The BIOS shou <<
2879 needs to. Unfortunately, some BIOS <<
2880 many of the newer IBM Thinkpads. I <<
2881 suspend, try setting this to Y. Ot <<
2882 2829
2883 endif # APM !! 2830 config NR_CPUS_DEFAULT_64
>> 2831 bool
2884 2832
2885 source "drivers/cpufreq/Kconfig" !! 2833 config NR_CPUS
>> 2834 int "Maximum number of CPUs (2-256)"
>> 2835 range 2 256
>> 2836 depends on SMP
>> 2837 default "4" if NR_CPUS_DEFAULT_4
>> 2838 default "8" if NR_CPUS_DEFAULT_8
>> 2839 default "16" if NR_CPUS_DEFAULT_16
>> 2840 default "32" if NR_CPUS_DEFAULT_32
>> 2841 default "64" if NR_CPUS_DEFAULT_64
>> 2842 help
>> 2843 This allows you to specify the maximum number of CPUs which this
>> 2844 kernel will support. The maximum supported value is 32 for 32-bit
>> 2845 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2846 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2847 and 2 for all others.
>> 2848
>> 2849 This is purely to save memory - each supported CPU adds
>> 2850 approximately eight kilobytes to the kernel image. For best
>> 2851 performance should round up your number of processors to the next
>> 2852 power of two.
2886 2853
2887 source "drivers/cpuidle/Kconfig" !! 2854 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2855 bool
2888 2856
2889 source "drivers/idle/Kconfig" !! 2857 config MIPS_NR_CPU_NR_MAP_1024
>> 2858 bool
2890 2859
2891 endmenu !! 2860 config MIPS_NR_CPU_NR_MAP
>> 2861 int
>> 2862 depends on SMP
>> 2863 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2864 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
2892 2865
2893 menu "Bus options (PCI etc.)" !! 2866 #
>> 2867 # Timer Interrupt Frequency Configuration
>> 2868 #
2894 2869
2895 choice 2870 choice
2896 prompt "PCI access mode" !! 2871 prompt "Timer frequency"
2897 depends on X86_32 && PCI !! 2872 default HZ_250
2898 default PCI_GOANY !! 2873 help
2899 help !! 2874 Allows the configuration of the timer frequency.
2900 On PCI systems, the BIOS can be use !! 2875
2901 determine their configuration. Howe !! 2876 config HZ_24
2902 have BIOS bugs and may crash if thi !! 2877 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
2903 PCI-based systems don't have any BI !! 2878
2904 detect the PCI hardware directly wi !! 2879 config HZ_48
2905 !! 2880 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
2906 With this option, you can specify h !! 2881
2907 PCI devices. If you choose "BIOS", !! 2882 config HZ_100
2908 if you choose "Direct", the BIOS wo !! 2883 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
2909 choose "MMConfig", then PCI Express !! 2884
2910 If you choose "Any", the kernel wil !! 2885 config HZ_128
2911 direct access method and falls back !! 2886 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
2912 work. If unsure, go with the defaul !! 2887
2913 !! 2888 config HZ_250
2914 config PCI_GOBIOS !! 2889 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
2915 bool "BIOS" !! 2890
2916 !! 2891 config HZ_256
2917 config PCI_GOMMCONFIG !! 2892 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
2918 bool "MMConfig" <<
2919 <<
2920 config PCI_GODIRECT <<
2921 bool "Direct" <<
2922 <<
2923 config PCI_GOOLPC <<
2924 bool "OLPC XO-1" <<
2925 depends on OLPC <<
2926 2893
2927 config PCI_GOANY !! 2894 config HZ_1000
2928 bool "Any" !! 2895 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2896
>> 2897 config HZ_1024
>> 2898 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
2929 2899
2930 endchoice 2900 endchoice
2931 2901
2932 config PCI_BIOS !! 2902 config SYS_SUPPORTS_24HZ
2933 def_bool y !! 2903 bool
2934 depends on X86_32 && PCI && (PCI_GOBI <<
2935 2904
2936 # x86-64 doesn't support PCI BIOS access from !! 2905 config SYS_SUPPORTS_48HZ
2937 config PCI_DIRECT !! 2906 bool
2938 def_bool y <<
2939 depends on PCI && (X86_64 || (PCI_GOD <<
2940 2907
2941 config PCI_MMCONFIG !! 2908 config SYS_SUPPORTS_100HZ
2942 bool "Support mmconfig PCI config spa !! 2909 bool
2943 default y <<
2944 depends on PCI && (ACPI || JAILHOUSE_ <<
2945 depends on X86_64 || (PCI_GOANY || PC <<
2946 2910
2947 config PCI_OLPC !! 2911 config SYS_SUPPORTS_128HZ
2948 def_bool y !! 2912 bool
2949 depends on PCI && OLPC && (PCI_GOOLPC <<
2950 2913
2951 config PCI_XEN !! 2914 config SYS_SUPPORTS_250HZ
2952 def_bool y !! 2915 bool
2953 depends on PCI && XEN <<
2954 2916
2955 config MMCONF_FAM10H !! 2917 config SYS_SUPPORTS_256HZ
2956 def_bool y !! 2918 bool
2957 depends on X86_64 && PCI_MMCONFIG && <<
2958 2919
2959 config PCI_CNB20LE_QUIRK !! 2920 config SYS_SUPPORTS_1000HZ
2960 bool "Read CNB20LE Host Bridge Window !! 2921 bool
2961 depends on PCI <<
2962 help <<
2963 Read the PCI windows out of the CNB <<
2964 PCI hotplug to work on systems with <<
2965 not have ACPI. <<
2966 2922
2967 There's no public spec for this chi !! 2923 config SYS_SUPPORTS_1024HZ
2968 is known to be incomplete. !! 2924 bool
2969 2925
2970 You should say N unless you know yo !! 2926 config SYS_SUPPORTS_ARBIT_HZ
>> 2927 bool
>> 2928 default y if !SYS_SUPPORTS_24HZ && \
>> 2929 !SYS_SUPPORTS_48HZ && \
>> 2930 !SYS_SUPPORTS_100HZ && \
>> 2931 !SYS_SUPPORTS_128HZ && \
>> 2932 !SYS_SUPPORTS_250HZ && \
>> 2933 !SYS_SUPPORTS_256HZ && \
>> 2934 !SYS_SUPPORTS_1000HZ && \
>> 2935 !SYS_SUPPORTS_1024HZ
2971 2936
2972 config ISA_BUS !! 2937 config HZ
2973 bool "ISA bus support on modern syste !! 2938 int
2974 help !! 2939 default 24 if HZ_24
2975 Expose ISA bus device drivers and o !! 2940 default 48 if HZ_48
2976 configuration. Enable this option i !! 2941 default 100 if HZ_100
2977 bus. ISA is an older system, displa !! 2942 default 128 if HZ_128
2978 architectures -- if your target mac !! 2943 default 250 if HZ_250
2979 not have an ISA bus. !! 2944 default 256 if HZ_256
>> 2945 default 1000 if HZ_1000
>> 2946 default 1024 if HZ_1024
>> 2947
>> 2948 config SCHED_HRTICK
>> 2949 def_bool HIGH_RES_TIMERS
>> 2950
>> 2951 config KEXEC
>> 2952 bool "Kexec system call"
>> 2953 select KEXEC_CORE
>> 2954 help
>> 2955 kexec is a system call that implements the ability to shutdown your
>> 2956 current kernel, and to start another kernel. It is like a reboot
>> 2957 but it is independent of the system firmware. And like a reboot
>> 2958 you can start any kernel with it, not just Linux.
>> 2959
>> 2960 The name comes from the similarity to the exec system call.
>> 2961
>> 2962 It is an ongoing process to be certain the hardware in a machine
>> 2963 is properly shutdown, so do not be surprised if this code does not
>> 2964 initially work for you. As of this writing the exact hardware
>> 2965 interface is strongly in flux, so no good recommendation can be
>> 2966 made.
>> 2967
>> 2968 config CRASH_DUMP
>> 2969 bool "Kernel crash dumps"
>> 2970 help
>> 2971 Generate crash dump after being started by kexec.
>> 2972 This should be normally only set in special crash dump kernels
>> 2973 which are loaded in the main kernel with kexec-tools into
>> 2974 a specially reserved region and then later executed after
>> 2975 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2976 to a memory address not used by the main kernel or firmware using
>> 2977 PHYSICAL_START.
>> 2978
>> 2979 config PHYSICAL_START
>> 2980 hex "Physical address where the kernel is loaded"
>> 2981 default "0xffffffff84000000"
>> 2982 depends on CRASH_DUMP
>> 2983 help
>> 2984 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2985 If you plan to use kernel for capturing the crash dump change
>> 2986 this value to start of the reserved region (the "X" value as
>> 2987 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2988 passed to the panic-ed kernel).
>> 2989
>> 2990 config MIPS_O32_FP64_SUPPORT
>> 2991 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2992 depends on 32BIT || MIPS32_O32
>> 2993 help
>> 2994 When this is enabled, the kernel will support use of 64-bit floating
>> 2995 point registers with binaries using the O32 ABI along with the
>> 2996 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2997 32-bit MIPS systems this support is at the cost of increasing the
>> 2998 size and complexity of the compiled FPU emulator. Thus if you are
>> 2999 running a MIPS32 system and know that none of your userland binaries
>> 3000 will require 64-bit floating point, you may wish to reduce the size
>> 3001 of your kernel & potentially improve FP emulation performance by
>> 3002 saying N here.
>> 3003
>> 3004 Although binutils currently supports use of this flag the details
>> 3005 concerning its effect upon the O32 ABI in userland are still being
>> 3006 worked on. In order to avoid userland becoming dependent upon current
>> 3007 behaviour before the details have been finalised, this option should
>> 3008 be considered experimental and only enabled by those working upon
>> 3009 said details.
2980 3010
2981 If unsure, say N. 3011 If unsure, say N.
2982 3012
2983 # x86_64 have no ISA slots, but can have ISA- !! 3013 config USE_OF
2984 config ISA_DMA_API !! 3014 bool
2985 bool "ISA-style DMA support" if (X86_ !! 3015 select OF
2986 default y !! 3016 select OF_EARLY_FLATTREE
2987 help !! 3017 select IRQ_DOMAIN
2988 Enables ISA-style DMA support for d <<
2989 If unsure, say Y. <<
2990 3018
2991 if X86_32 !! 3019 config UHI_BOOT
>> 3020 bool
2992 3021
2993 config ISA !! 3022 config BUILTIN_DTB
2994 bool "ISA support" !! 3023 bool
2995 help !! 3024
2996 Find out whether you have ISA slots !! 3025 choice
2997 name of a bus system, i.e. the way !! 3026 prompt "Kernel appended dtb support" if USE_OF
2998 inside your box. Other bus systems !! 3027 default MIPS_NO_APPENDED_DTB
2999 (MCA) or VESA. ISA is an older sys !! 3028
3000 newer boards don't support it. If !! 3029 config MIPS_NO_APPENDED_DTB
3001 !! 3030 bool "None"
3002 config SCx200 !! 3031 help
3003 tristate "NatSemi SCx200 support" !! 3032 Do not enable appended dtb support.
3004 help !! 3033
3005 This provides basic support for Nat !! 3034 config MIPS_ELF_APPENDED_DTB
3006 (now AMD's) Geode processors. The !! 3035 bool "vmlinux"
3007 PCI-IDs of several on-chip devices, !! 3036 help
3008 for other scx200_* drivers. !! 3037 With this option, the boot code will look for a device tree binary
3009 !! 3038 DTB) included in the vmlinux ELF section .appended_dtb. By default
3010 If compiled as a module, the driver !! 3039 it is empty and the DTB can be appended using binutils command
3011 !! 3040 objcopy:
3012 config SCx200HR_TIMER !! 3041
3013 tristate "NatSemi SCx200 27MHz High-R !! 3042 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
3014 depends on SCx200 !! 3043
>> 3044 This is meant as a backward compatibility convenience for those
>> 3045 systems with a bootloader that can't be upgraded to accommodate
>> 3046 the documented boot protocol using a device tree.
>> 3047
>> 3048 config MIPS_RAW_APPENDED_DTB
>> 3049 bool "vmlinux.bin or vmlinuz.bin"
>> 3050 help
>> 3051 With this option, the boot code will look for a device tree binary
>> 3052 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3053 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3054
>> 3055 This is meant as a backward compatibility convenience for those
>> 3056 systems with a bootloader that can't be upgraded to accommodate
>> 3057 the documented boot protocol using a device tree.
>> 3058
>> 3059 Beware that there is very little in terms of protection against
>> 3060 this option being confused by leftover garbage in memory that might
>> 3061 look like a DTB header after a reboot if no actual DTB is appended
>> 3062 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3063 if you don't intend to always append a DTB.
>> 3064 endchoice
>> 3065
>> 3066 choice
>> 3067 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
>> 3068 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 3069 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 3070 !CAVIUM_OCTEON_SOC
>> 3071 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 3072
>> 3073 config MIPS_CMDLINE_FROM_DTB
>> 3074 depends on USE_OF
>> 3075 bool "Dtb kernel arguments if available"
>> 3076
>> 3077 config MIPS_CMDLINE_DTB_EXTEND
>> 3078 depends on USE_OF
>> 3079 bool "Extend dtb kernel arguments with bootloader arguments"
>> 3080
>> 3081 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 3082 bool "Bootloader kernel arguments if available"
>> 3083
>> 3084 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3085 depends on CMDLINE_BOOL
>> 3086 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3087 endchoice
>> 3088
>> 3089 endmenu
>> 3090
>> 3091 config LOCKDEP_SUPPORT
>> 3092 bool
3015 default y 3093 default y
3016 help <<
3017 This driver provides a clocksource <<
3018 27MHz high-resolution timer. Its a <<
3019 NSC Geode SC-1100's buggy TSC, whic <<
3020 processor goes idle (as is done by <<
3021 other workaround is idle=poll boot <<
3022 <<
3023 config OLPC <<
3024 bool "One Laptop Per Child support" <<
3025 depends on !X86_PAE <<
3026 select GPIOLIB <<
3027 select OF <<
3028 select OF_PROMTREE <<
3029 select IRQ_DOMAIN <<
3030 select OLPC_EC <<
3031 help <<
3032 Add support for detecting the uniqu <<
3033 XO hardware. <<
3034 3094
3035 config OLPC_XO1_PM !! 3095 config STACKTRACE_SUPPORT
3036 bool "OLPC XO-1 Power Management" !! 3096 bool
3037 depends on OLPC && MFD_CS5535=y && PM !! 3097 default y
3038 help <<
3039 Add support for poweroff and suspen <<
3040 3098
3041 config OLPC_XO1_RTC !! 3099 config PGTABLE_LEVELS
3042 bool "OLPC XO-1 Real Time Clock" !! 3100 int
3043 depends on OLPC_XO1_PM && RTC_DRV_CMO !! 3101 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
3044 help !! 3102 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
3045 Add support for the XO-1 real time !! 3103 default 2
3046 programmable wakeup source. <<
3047 3104
3048 config OLPC_XO1_SCI !! 3105 config MIPS_AUTO_PFN_OFFSET
3049 bool "OLPC XO-1 SCI extras" !! 3106 bool
3050 depends on OLPC && OLPC_XO1_PM && GPI <<
3051 depends on INPUT=y <<
3052 select POWER_SUPPLY <<
3053 help <<
3054 Add support for SCI-based features <<
3055 - EC-driven system wakeups <<
3056 - Power button <<
3057 - Ebook switch <<
3058 - Lid switch <<
3059 - AC adapter status updates <<
3060 - Battery status updates <<
3061 3107
3062 config OLPC_XO15_SCI !! 3108 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
3063 bool "OLPC XO-1.5 SCI extras" <<
3064 depends on OLPC && ACPI <<
3065 select POWER_SUPPLY <<
3066 help <<
3067 Add support for SCI-based features <<
3068 - EC-driven system wakeups <<
3069 - AC adapter status updates <<
3070 - Battery status updates <<
3071 3109
3072 config GEODE_COMMON !! 3110 config PCI_DRIVERS_GENERIC
>> 3111 select PCI_DOMAINS_GENERIC if PCI
3073 bool 3112 bool
3074 3113
3075 config ALIX !! 3114 config PCI_DRIVERS_LEGACY
3076 bool "PCEngines ALIX System Support ( !! 3115 def_bool !PCI_DRIVERS_GENERIC
3077 select GPIOLIB !! 3116 select NO_GENERIC_PCI_IOPORT_MAP
3078 select GEODE_COMMON !! 3117 select PCI_DOMAINS if PCI
3079 help <<
3080 This option enables system support <<
3081 At present this just sets up LEDs f <<
3082 ALIX2/3/6 boards. However, other s <<
3083 get added here. <<
3084 3118
3085 Note: You must still enable the dri !! 3119 #
3086 (GPIO_CS5535 & LEDS_GPIO) to actual !! 3120 # ISA support is now enabled via select. Too many systems still have the one
>> 3121 # or other ISA chip on the board that users don't know about so don't expect
>> 3122 # users to choose the right thing ...
>> 3123 #
>> 3124 config ISA
>> 3125 bool
3087 3126
3088 Note: You have to set alix.force=1 !! 3127 config TC
>> 3128 bool "TURBOchannel support"
>> 3129 depends on MACH_DECSTATION
>> 3130 help
>> 3131 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3132 processors. TURBOchannel programming specifications are available
>> 3133 at:
>> 3134 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3135 and:
>> 3136 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3137 Linux driver support status is documented at:
>> 3138 <http://www.linux-mips.org/wiki/DECstation>
3089 3139
3090 config NET5501 !! 3140 config MMU
3091 bool "Soekris Engineering net5501 Sys !! 3141 bool
3092 select GPIOLIB !! 3142 default y
3093 select GEODE_COMMON <<
3094 help <<
3095 This option enables system support <<
3096 3143
3097 config GEOS !! 3144 config ARCH_MMAP_RND_BITS_MIN
3098 bool "Traverse Technologies GEOS Syst !! 3145 default 12 if 64BIT
3099 select GPIOLIB !! 3146 default 8
3100 select GEODE_COMMON <<
3101 depends on DMI <<
3102 help <<
3103 This option enables system support <<
3104 3147
3105 config TS5500 !! 3148 config ARCH_MMAP_RND_BITS_MAX
3106 bool "Technologic Systems TS-5500 pla !! 3149 default 18 if 64BIT
3107 depends on MELAN !! 3150 default 15
3108 select CHECK_SIGNATURE <<
3109 select NEW_LEDS <<
3110 select LEDS_CLASS <<
3111 help <<
3112 This option enables system support <<
3113 3151
3114 endif # X86_32 !! 3152 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3153 default 8
3115 3154
3116 config AMD_NB !! 3155 config ARCH_MMAP_RND_COMPAT_BITS_MAX
3117 def_bool y !! 3156 default 15
3118 depends on CPU_SUP_AMD && PCI <<
3119 3157
>> 3158 config I8253
>> 3159 bool
>> 3160 select CLKSRC_I8253
>> 3161 select CLKEVT_I8253
>> 3162 select MIPS_EXTERNAL_TIMER
3120 endmenu 3163 endmenu
3121 3164
3122 menu "Binary Emulations" !! 3165 config TRAD_SIGNALS
>> 3166 bool
3123 3167
3124 config IA32_EMULATION !! 3168 config MIPS32_COMPAT
3125 bool "IA32 Emulation" !! 3169 bool
3126 depends on X86_64 !! 3170
>> 3171 config COMPAT
>> 3172 bool
>> 3173
>> 3174 config MIPS32_O32
>> 3175 bool "Kernel support for o32 binaries"
>> 3176 depends on 64BIT
3127 select ARCH_WANT_OLD_COMPAT_IPC 3177 select ARCH_WANT_OLD_COMPAT_IPC
3128 select BINFMT_ELF !! 3178 select COMPAT
3129 select COMPAT_OLD_SIGACTION !! 3179 select MIPS32_COMPAT
3130 help 3180 help
3131 Include code to run legacy 32-bit p !! 3181 Select this option if you want to run o32 binaries. These are pure
3132 64-bit kernel. You should likely tu !! 3182 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3133 100% sure that you don't have any 3 !! 3183 existing binaries are in this format.
3134 3184
3135 config IA32_EMULATION_DEFAULT_DISABLED !! 3185 If unsure, say Y.
3136 bool "IA32 emulation disabled by defa !! 3186
3137 default n !! 3187 config MIPS32_N32
3138 depends on IA32_EMULATION !! 3188 bool "Kernel support for n32 binaries"
3139 help !! 3189 depends on 64BIT
3140 Make IA32 emulation disabled by def !! 3190 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
3141 processes and access to 32-bit sysc !! 3191 select COMPAT
3142 default value. !! 3192 select MIPS32_COMPAT
3143 !! 3193 help
3144 config X86_X32_ABI !! 3194 Select this option if you want to run n32 binaries. These are
3145 bool "x32 ABI for 64-bit mode" !! 3195 64-bit binaries using 32-bit quantities for addressing and certain
3146 depends on X86_64 !! 3196 data that would normally be 64-bit. They are used in special
3147 # llvm-objcopy does not convert x86_6 !! 3197 cases.
3148 # compressed debug sections to x86_x3 <<
3149 # https://github.com/ClangBuiltLinux/ <<
3150 # https://github.com/ClangBuiltLinux/ <<
3151 depends on $(success,$(OBJCOPY) --ver <<
3152 help <<
3153 Include code to run binaries for th <<
3154 for 64-bit processors. An x32 proc <<
3155 full 64-bit register file and wide <<
3156 pointers at 32 bits for smaller mem <<
3157 3198
3158 config COMPAT_32 !! 3199 If unsure, say N.
>> 3200
>> 3201 config CC_HAS_MNO_BRANCH_LIKELY
3159 def_bool y 3202 def_bool y
3160 depends on IA32_EMULATION || X86_32 !! 3203 depends on $(cc-option,-mno-branch-likely)
3161 select HAVE_UID16 <<
3162 select OLD_SIGSUSPEND3 <<
3163 3204
3164 config COMPAT !! 3205 # https://github.com/llvm/llvm-project/issues/61045
>> 3206 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>> 3207 def_bool y if CC_IS_CLANG
>> 3208
>> 3209 menu "Power management options"
>> 3210
>> 3211 config ARCH_HIBERNATION_POSSIBLE
3165 def_bool y 3212 def_bool y
3166 depends on IA32_EMULATION || X86_X32_ !! 3213 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
3167 3214
3168 config COMPAT_FOR_U64_ALIGNMENT !! 3215 config ARCH_SUSPEND_POSSIBLE
3169 def_bool y 3216 def_bool y
3170 depends on COMPAT !! 3217 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3218
>> 3219 source "kernel/power/Kconfig"
3171 3220
3172 endmenu 3221 endmenu
3173 3222
3174 config HAVE_ATOMIC_IOMAP !! 3223 config MIPS_EXTERNAL_TIMER
3175 def_bool y !! 3224 bool
3176 depends on X86_32 !! 3225
>> 3226 menu "CPU Power Management"
>> 3227
>> 3228 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3229 source "drivers/cpufreq/Kconfig"
>> 3230 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3231
>> 3232 source "drivers/cpuidle/Kconfig"
>> 3233
>> 3234 endmenu
3177 3235
3178 source "arch/x86/kvm/Kconfig" !! 3236 source "arch/mips/kvm/Kconfig"
3179 3237
3180 source "arch/x86/Kconfig.assembler" !! 3238 source "arch/mips/vdso/Kconfig"
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