1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 #ifndef _ASM_X86_APICDEF_H 3 #define _ASM_X86_APICDEF_H 4 5 #include <linux/bits.h> 6 7 /* 8 * Constants for various Intel APICs. (local A 9 * 10 * Alan Cox <Alan.Cox@linux.org>, 1995. 11 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 12 */ 13 14 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec0 15 #define APIC_DEFAULT_PHYS_BASE 0xfee0 16 17 /* 18 * This is the IO-APIC register space as speci 19 * by Intel docs: 20 */ 21 #define IO_APIC_SLOT_SIZE 1024 22 23 #define APIC_DELIVERY_MODE_FIXED 0 24 #define APIC_DELIVERY_MODE_LOWESTPRIO 1 25 #define APIC_DELIVERY_MODE_SMI 2 26 #define APIC_DELIVERY_MODE_NMI 4 27 #define APIC_DELIVERY_MODE_INIT 5 28 #define APIC_DELIVERY_MODE_EXTINT 7 29 30 #define APIC_ID 0x20 31 32 #define APIC_LVR 0x30 33 #define APIC_LVR_MASK 0xFF00 34 #define APIC_LVR_DIRECTED_EOI (1 << 35 #define GET_APIC_VERSION(x) ((x) & 36 #define GET_APIC_MAXLVT(x) (((x) 37 #ifdef CONFIG_X86_32 38 # define APIC_INTEGRATED(x) ((x) & 39 #else 40 # define APIC_INTEGRATED(x) (1) 41 #endif 42 #define APIC_XAPIC(x) ((x) > 43 #define APIC_EXT_SPACE(x) ((x) & 44 #define APIC_TASKPRI 0x80 45 #define APIC_TPRI_MASK 0xFFu 46 #define APIC_ARBPRI 0x90 47 #define APIC_ARBPRI_MASK 0xFFu 48 #define APIC_PROCPRI 0xA0 49 #define APIC_EOI 0xB0 50 #define APIC_EOI_ACK 0x0 /* 51 #define APIC_RRR 0xC0 52 #define APIC_LDR 0xD0 53 #define APIC_LDR_MASK (0xFFu 54 #define GET_APIC_LOGICAL_ID(x) (((x) 55 #define SET_APIC_LOGICAL_ID(x) (((x) 56 #define APIC_ALL_CPUS 0xFFu 57 #define APIC_DFR 0xE0 58 #define APIC_DFR_CLUSTER 59 #define APIC_DFR_FLAT 60 #define APIC_SPIV 0xF0 61 #define APIC_SPIV_DIRECTED_EOI 62 #define APIC_SPIV_FOCUS_DISABLED 63 #define APIC_SPIV_APIC_ENABLED 64 #define APIC_ISR 0x100 65 #define APIC_ISR_NR 0x8 /* Number of 3 66 #define APIC_TMR 0x180 67 #define APIC_IRR 0x200 68 #define APIC_ESR 0x280 69 #define APIC_ESR_SEND_CS 0x0000 70 #define APIC_ESR_RECV_CS 0x0000 71 #define APIC_ESR_SEND_ACC 0x0000 72 #define APIC_ESR_RECV_ACC 0x0000 73 #define APIC_ESR_SENDILL 0x0002 74 #define APIC_ESR_RECVILL 0x0004 75 #define APIC_ESR_ILLREGA 0x0008 76 #define APIC_LVTCMCI 0x2f0 77 #define APIC_ICR 0x300 78 #define APIC_DEST_SELF 0x4000 79 #define APIC_DEST_ALLINC 0x8000 80 #define APIC_DEST_ALLBUT 0xC000 81 #define APIC_ICR_RR_MASK 0x3000 82 #define APIC_ICR_RR_INVALID 0x0000 83 #define APIC_ICR_RR_INPROG 0x1000 84 #define APIC_ICR_RR_VALID 0x2000 85 #define APIC_INT_LEVELTRIG 0x0800 86 #define APIC_INT_ASSERT 0x0400 87 #define APIC_ICR_BUSY 0x0100 88 #define APIC_DEST_LOGICAL 0x0080 89 #define APIC_DEST_PHYSICAL 0x0000 90 #define APIC_DM_FIXED 0x0000 91 #define APIC_DM_FIXED_MASK 0x0070 92 #define APIC_DM_LOWEST 0x0010 93 #define APIC_DM_SMI 0x0020 94 #define APIC_DM_REMRD 0x0030 95 #define APIC_DM_NMI 0x0040 96 #define APIC_DM_INIT 0x0050 97 #define APIC_DM_STARTUP 0x0060 98 #define APIC_DM_EXTINT 0x0070 99 #define APIC_VECTOR_MASK 0x000F 100 #define APIC_ICR2 0x310 101 #define GET_XAPIC_DEST_FIELD(x) (((x) 102 #define SET_XAPIC_DEST_FIELD(x) ((x) < 103 #define APIC_LVTT 0x320 104 #define APIC_LVTTHMR 0x330 105 #define APIC_LVTPC 0x340 106 #define APIC_LVT0 0x350 107 #define APIC_LVT_TIMER_ONESHOT 108 #define APIC_LVT_TIMER_PERIODIC 109 #define APIC_LVT_TIMER_TSCDEADLINE 110 #define APIC_LVT_MASKED 111 #define APIC_LVT_LEVEL_TRIGGER 112 #define APIC_LVT_REMOTE_IRR 113 #define APIC_INPUT_POLARITY 114 #define APIC_SEND_PENDING 115 #define APIC_MODE_MASK 116 #define GET_APIC_DELIVERY_MODE(x) 117 #define SET_APIC_DELIVERY_MODE(x, y) 118 #define APIC_MODE_FIXED 119 #define APIC_MODE_NMI 120 #define APIC_MODE_EXTINT 121 #define APIC_LVT1 0x360 122 #define APIC_LVTERR 0x370 123 #define APIC_TMICT 0x380 124 #define APIC_TMCCT 0x390 125 #define APIC_TDCR 0x3E0 126 #define APIC_SELF_IPI 0x3F0 127 #define APIC_TDR_DIV_TMBASE (1 << 128 #define APIC_TDR_DIV_1 0xB 129 #define APIC_TDR_DIV_2 0x0 130 #define APIC_TDR_DIV_4 0x1 131 #define APIC_TDR_DIV_8 0x2 132 #define APIC_TDR_DIV_16 0x3 133 #define APIC_TDR_DIV_32 0x8 134 #define APIC_TDR_DIV_64 0x9 135 #define APIC_TDR_DIV_128 0xA 136 #define APIC_EFEAT 0x400 137 #define APIC_ECTRL 0x410 138 #define APIC_EILVTn(n) (0x500 + 0x10 * n) 139 #define APIC_EILVT_NR_AMD_K8 1 140 #define APIC_EILVT_NR_AMD_10H 4 141 #define APIC_EILVT_NR_MAX APIC_E 142 #define APIC_EILVT_LVTOFF(x) (((x) 143 #define APIC_EILVT_MSG_FIX 0x0 144 #define APIC_EILVT_MSG_SMI 0x2 145 #define APIC_EILVT_MSG_NMI 0x4 146 #define APIC_EILVT_MSG_EXT 0x7 147 #define APIC_EILVT_MASKED (1 << 148 149 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) 150 #define APIC_BASE_MSR 0x800 151 #define APIC_X2APIC_ID_MSR 0x802 152 #define XAPIC_ENABLE BIT(11) 153 #define X2APIC_ENABLE BIT(10) 154 155 #ifdef CONFIG_X86_32 156 # define MAX_IO_APICS 64 157 # define MAX_LOCAL_APIC 256 158 #else 159 # define MAX_IO_APICS 128 160 # define MAX_LOCAL_APIC 32768 161 #endif 162 163 /* 164 * All x86-64 systems are xAPIC compatible. 165 * In the following, "apicid" is a physical AP 166 */ 167 #define XAPIC_DEST_CPUS_SHIFT 4 168 #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_ 169 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CP 170 #define APIC_CLUSTER(apicid) ((apicid) & XA 171 #define APIC_CLUSTERID(apicid) (APIC_CLUSTER( 172 #define APIC_CPUID(apicid) ((apicid) & XA 173 #define NUM_APIC_CLUSTERS ((BAD_APICID + 174 175 #ifdef CONFIG_X86_32 176 #define BAD_APICID 0xFFu 177 #else 178 #define BAD_APICID 0xFFFFu 179 #endif 180 181 #endif /* _ASM_X86_APICDEF_H */ 182
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