1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 #ifndef _ASM_X86_DEBUGREG_H
3 #define _ASM_X86_DEBUGREG_H
4
5 #include <linux/bug.h>
6 #include <linux/percpu.h>
7 #include <uapi/asm/debugreg.h>
8
9 #include <asm/cpufeature.h>
10 #include <asm/msr.h>
11
12 DECLARE_PER_CPU(unsigned long, cpu_dr7);
13
14 #ifndef CONFIG_PARAVIRT_XXL
15 /*
16 * These special macros can be used to get or
17 */
18 #define get_debugreg(var, register)
19 (var) = native_get_debugreg(register)
20 #define set_debugreg(value, register)
21 native_set_debugreg(register, value)
22 #endif
23
24 static __always_inline unsigned long native_ge
25 {
26 unsigned long val = 0; /* Damn you, g
27
28 switch (regno) {
29 case 0:
30 asm("mov %%db0, %0" :"=r" (val
31 break;
32 case 1:
33 asm("mov %%db1, %0" :"=r" (val
34 break;
35 case 2:
36 asm("mov %%db2, %0" :"=r" (val
37 break;
38 case 3:
39 asm("mov %%db3, %0" :"=r" (val
40 break;
41 case 6:
42 asm("mov %%db6, %0" :"=r" (val
43 break;
44 case 7:
45 /*
46 * Apply __FORCE_ORDER to DR7
47 * with other code.
48 *
49 * This is needed because a DR
50 * when running under SEV-ES.
51 * safe thing to do just anywh
52 * re-ordering might place the
53 *
54 * This happened in the NMI ha
55 * re-ordered to happen before
56 * causing stack recursion.
57 */
58 asm volatile("mov %%db7, %0" :
59 break;
60 default:
61 BUG();
62 }
63 return val;
64 }
65
66 static __always_inline void native_set_debugre
67 {
68 switch (regno) {
69 case 0:
70 asm("mov %0, %%db0" ::"r"
71 break;
72 case 1:
73 asm("mov %0, %%db1" ::"r"
74 break;
75 case 2:
76 asm("mov %0, %%db2" ::"r"
77 break;
78 case 3:
79 asm("mov %0, %%db3" ::"r"
80 break;
81 case 6:
82 asm("mov %0, %%db6" ::"r"
83 break;
84 case 7:
85 /*
86 * Apply __FORCE_ORDER to DR7
87 * with other code.
88 *
89 * While is didn't happen with
90 * comment above which explain
91 * __FORCE_ORDER here too to a
92 * future.
93 */
94 asm volatile("mov %0, %%db7"
95 break;
96 default:
97 BUG();
98 }
99 }
100
101 static inline void hw_breakpoint_disable(void)
102 {
103 /* Zero the control register for HW Br
104 set_debugreg(0UL, 7);
105
106 /* Zero-out the individual HW breakpoi
107 set_debugreg(0UL, 0);
108 set_debugreg(0UL, 1);
109 set_debugreg(0UL, 2);
110 set_debugreg(0UL, 3);
111 }
112
113 static __always_inline bool hw_breakpoint_acti
114 {
115 return __this_cpu_read(cpu_dr7) & DR_G
116 }
117
118 extern void hw_breakpoint_restore(void);
119
120 static __always_inline unsigned long local_db_
121 {
122 unsigned long dr7;
123
124 if (static_cpu_has(X86_FEATURE_HYPERVI
125 return 0;
126
127 get_debugreg(dr7, 7);
128 dr7 &= ~0x400; /* architecturally set
129 if (dr7)
130 set_debugreg(0, 7);
131 /*
132 * Ensure the compiler doesn't lower t
133 * the critical section; disabling bre
134 * be good.
135 */
136 barrier();
137
138 return dr7;
139 }
140
141 static __always_inline void local_db_restore(u
142 {
143 /*
144 * Ensure the compiler doesn't raise t
145 * the critical section; enabling brea
146 * not be good.
147 */
148 barrier();
149 if (dr7)
150 set_debugreg(dr7, 7);
151 }
152
153 #ifdef CONFIG_CPU_SUP_AMD
154 extern void amd_set_dr_addr_mask(unsigned long
155 extern unsigned long amd_get_dr_addr_mask(unsi
156 #else
157 static inline void amd_set_dr_addr_mask(unsign
158 static inline unsigned long amd_get_dr_addr_ma
159 {
160 return 0;
161 }
162 #endif
163
164 static inline unsigned long get_debugctlmsr(vo
165 {
166 unsigned long debugctlmsr = 0;
167
168 #ifndef CONFIG_X86_DEBUGCTLMSR
169 if (boot_cpu_data.x86 < 6)
170 return 0;
171 #endif
172 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlm
173
174 return debugctlmsr;
175 }
176
177 static inline void update_debugctlmsr(unsigned
178 {
179 #ifndef CONFIG_X86_DEBUGCTLMSR
180 if (boot_cpu_data.x86 < 6)
181 return;
182 #endif
183 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlm
184 }
185
186 #endif /* _ASM_X86_DEBUGREG_H */
187
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