1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /**
3 * Copyright(c) 2016-20 Intel Corporation.
4 *
5 * Intel Software Guard Extensions (SGX) suppo
6 */
7 #ifndef _ASM_X86_SGX_H
8 #define _ASM_X86_SGX_H
9
10 #include <linux/bits.h>
11 #include <linux/types.h>
12
13 /*
14 * This file contains both data structures def
15 * defined software data structures and functi
16 * together for better readability. The archi
17 */
18
19 /* The SGX specific CPUID function. */
20 #define SGX_CPUID 0x12
21 /* EPC enumeration. */
22 #define SGX_CPUID_EPC 2
23 /* An invalid EPC section, i.e. the end marker
24 #define SGX_CPUID_EPC_INVALID 0x0
25 /* A valid EPC section. */
26 #define SGX_CPUID_EPC_SECTION 0x1
27 /* The bitmask for the EPC section type. */
28 #define SGX_CPUID_EPC_MASK GENMASK(3, 0)
29
30 enum sgx_encls_function {
31 ECREATE = 0x00,
32 EADD = 0x01,
33 EINIT = 0x02,
34 EREMOVE = 0x03,
35 EDGBRD = 0x04,
36 EDGBWR = 0x05,
37 EEXTEND = 0x06,
38 ELDU = 0x08,
39 EBLOCK = 0x09,
40 EPA = 0x0A,
41 EWB = 0x0B,
42 ETRACK = 0x0C,
43 EAUG = 0x0D,
44 EMODPR = 0x0E,
45 EMODT = 0x0F,
46 };
47
48 /**
49 * SGX_ENCLS_FAULT_FLAG - flag signifying an E
50 *
51 * ENCLS has its own (positive value) error co
52 * ENCLS specific #GP and #PF faults. And the
53 * with system error codes as everything perco
54 * Unfortunately (for us), we need to precisel
55 * error code, e.g. the action taken if EWB fa
56 * type of fault and on the exact SGX error co
57 * convert all faults to -EFAULT.
58 *
59 * To make all three error types coexist, we s
60 * ENCLS fault. Bit 31 (technically bits N:31
61 * between positive (faults and SGX error code
62 * error codes) values.
63 */
64 #define SGX_ENCLS_FAULT_FLAG 0x40000000
65
66 /**
67 * enum sgx_return_code - The return code type
68 * %SGX_EPC_PAGE_CONFLICT: Page is being
69 * %SGX_NOT_TRACKED: Previous ETRAC
70 * been completed
71 * %SGX_CHILD_PRESENT SECS has child
72 * %SGX_INVALID_EINITTOKEN: EINITTOKEN is
73 * public key doe
74 * %SGX_PAGE_NOT_MODIFIABLE: The EPC page c
75 * is in the PEND
76 * %SGX_UNMASKED_EVENT: An unmasked ev
77 */
78 enum sgx_return_code {
79 SGX_EPC_PAGE_CONFLICT = 7,
80 SGX_NOT_TRACKED = 11,
81 SGX_CHILD_PRESENT = 13,
82 SGX_INVALID_EINITTOKEN = 16,
83 SGX_PAGE_NOT_MODIFIABLE = 20,
84 SGX_UNMASKED_EVENT = 128,
85 };
86
87 /* The modulus size for 3072-bit RSA keys. */
88 #define SGX_MODULUS_SIZE 384
89
90 /**
91 * enum sgx_miscselect - additional informatio
92 * %SGX_MISC_EXINFO: Report #PF or #GP to t
93 *
94 * Save State Area (SSA) is a stack inside the
95 * state when an exception or interrupt occurs
96 * information stored to an SSA frame.
97 */
98 enum sgx_miscselect {
99 SGX_MISC_EXINFO = BIT(0),
100 };
101
102 #define SGX_MISC_RESERVED_MASK GENMASK_ULL(63
103
104 #define SGX_SSA_GPRS_SIZE 184
105 #define SGX_SSA_MISC_EXINFO_SIZE 16
106
107 /**
108 * enum sgx_attributes - the attributes field
109 * %SGX_ATTR_INIT: Enclave can be
110 * %SGX_ATTR_DEBUG: Allow ENCLS(ED
111 * %SGX_ATTR_MODE64BIT: Tell that this
112 * %SGX_ATTR_PROVISIONKEY: Allow to use p
113 * attestation.
114 * %SGX_ATTR_KSS: Allow to use k
115 * %SGX_ATTR_EINITTOKENKEY: Allow to use t
116 * sign cryptogra
117 * EINIT as an au
118 * %SGX_ATTR_ASYNC_EXIT_NOTIFY: Allow enclaves
119 * asynchronous e
120 */
121 enum sgx_attribute {
122 SGX_ATTR_INIT = BIT(0),
123 SGX_ATTR_DEBUG = BIT(1),
124 SGX_ATTR_MODE64BIT = BIT(2),
125 /* BIT(3) is
126 SGX_ATTR_PROVISIONKEY = BIT(4),
127 SGX_ATTR_EINITTOKENKEY = BIT(5),
128 /* BIT(6) is
129 SGX_ATTR_KSS = BIT(7),
130 /* BIT(8) is
131 /* BIT(9) is
132 SGX_ATTR_ASYNC_EXIT_NOTIFY = BIT(10),
133 };
134
135 #define SGX_ATTR_RESERVED_MASK (BIT_ULL(3) |
136 BIT_ULL(6) |
137 BIT_ULL(8) |
138 BIT_ULL(9) |
139 GENMASK_ULL(6
140
141 #define SGX_ATTR_UNPRIV_MASK (SGX_ATTR_DEBU
142 SGX_ATTR_MODE
143 SGX_ATTR_KSS
144 SGX_ATTR_ASYN
145
146 #define SGX_ATTR_PRIV_MASK (SGX_ATTR_PROV
147 SGX_ATTR_EINI
148
149 /**
150 * struct sgx_secs - SGX Enclave Control Struc
151 * @size: size of the address sp
152 * @base: base address of the a
153 * @ssa_frame_size: size of an SSA frame
154 * @miscselect: additional information
155 * @attributes: attributes for enclave
156 * @xfrm: XSave-Feature Request
157 * @mrenclave: SHA256-hash of the enc
158 * @mrsigner: SHA256-hash of the pub
159 * @config_id: a user-defined value t
160 * @isv_prod_id: a user-defined value t
161 * @isv_svn: a user-defined value t
162 * @config_svn: a user-defined value t
163 *
164 * SGX Enclave Control Structure (SECS) is a s
165 * visible in the address space. In fact, this
166 * range and other global attributes for the e
167 * page created for any enclave. It is moved f
168 * by the means of ENCLS[ECREATE] function.
169 */
170 struct sgx_secs {
171 u64 size;
172 u64 base;
173 u32 ssa_frame_size;
174 u32 miscselect;
175 u8 reserved1[24];
176 u64 attributes;
177 u64 xfrm;
178 u32 mrenclave[8];
179 u8 reserved2[32];
180 u32 mrsigner[8];
181 u8 reserved3[32];
182 u32 config_id[16];
183 u16 isv_prod_id;
184 u16 isv_svn;
185 u16 config_svn;
186 u8 reserved4[3834];
187 } __packed;
188
189 /**
190 * enum sgx_tcs_flags - execution flags for TC
191 * %SGX_TCS_DBGOPTIN: If enabled allows sing
192 * inside an enclave. It
193 * be set later with EDBG
194 */
195 enum sgx_tcs_flags {
196 SGX_TCS_DBGOPTIN = 0x01,
197 };
198
199 #define SGX_TCS_RESERVED_MASK GENMASK_ULL(63
200 #define SGX_TCS_RESERVED_SIZE 4024
201
202 /**
203 * struct sgx_tcs - Thread Control Structure (
204 * @state: used to mark an entere
205 * @flags: execution flags (clear
206 * @ssa_offset: SSA stack offset relat
207 * @ssa_index: the current SSA frame
208 * @nr_ssa_frames: the number of frame in
209 * @entry_offset: entry point offset rel
210 * @exit_addr: address outside the en
211 * interrupt
212 * @fs_offset: offset relative to the
213 * segment inside the enc
214 * @gs_offset: offset relative to the
215 * segment inside the enc
216 * @fs_limit: size to become a new F
217 * @gs_limit: size to become a new G
218 *
219 * Thread Control Structure (TCS) is an enclav
220 * space that defines an entry point inside th
221 * an enclave by supplying address of TCS to E
222 * by only one thread at a time.
223 */
224 struct sgx_tcs {
225 u64 state;
226 u64 flags;
227 u64 ssa_offset;
228 u32 ssa_index;
229 u32 nr_ssa_frames;
230 u64 entry_offset;
231 u64 exit_addr;
232 u64 fs_offset;
233 u64 gs_offset;
234 u32 fs_limit;
235 u32 gs_limit;
236 u8 reserved[SGX_TCS_RESERVED_SIZE];
237 } __packed;
238
239 /**
240 * struct sgx_pageinfo - an enclave page descr
241 * @addr: address of the enclave page
242 * @contents: pointer to the page contents
243 * @metadata: pointer either to a SECINFO or
244 * @secs: address of the SECS page
245 */
246 struct sgx_pageinfo {
247 u64 addr;
248 u64 contents;
249 u64 metadata;
250 u64 secs;
251 } __packed __aligned(32);
252
253
254 /**
255 * enum sgx_page_type - bits in the SECINFO fl
256 * %SGX_PAGE_TYPE_SECS: a SECS page
257 * %SGX_PAGE_TYPE_TCS: a TCS page
258 * %SGX_PAGE_TYPE_REG: a regular page
259 * %SGX_PAGE_TYPE_VA: a VA page
260 * %SGX_PAGE_TYPE_TRIM: a page in trimmed stat
261 *
262 * Make sure when making changes to this enum
263 * in the bitfield within &struct sgx_encl_pag
264 */
265 enum sgx_page_type {
266 SGX_PAGE_TYPE_SECS,
267 SGX_PAGE_TYPE_TCS,
268 SGX_PAGE_TYPE_REG,
269 SGX_PAGE_TYPE_VA,
270 SGX_PAGE_TYPE_TRIM,
271 };
272
273 #define SGX_NR_PAGE_TYPES 5
274 #define SGX_PAGE_TYPE_MASK GENMASK(7, 0)
275
276 /**
277 * enum sgx_secinfo_flags - the flags field in
278 * %SGX_SECINFO_R: allow read
279 * %SGX_SECINFO_W: allow write
280 * %SGX_SECINFO_X: allow execution
281 * %SGX_SECINFO_SECS: a SECS page
282 * %SGX_SECINFO_TCS: a TCS page
283 * %SGX_SECINFO_REG: a regular page
284 * %SGX_SECINFO_VA: a VA page
285 * %SGX_SECINFO_TRIM: a page in trimmed stat
286 */
287 enum sgx_secinfo_flags {
288 SGX_SECINFO_R = BIT(
289 SGX_SECINFO_W = BIT(
290 SGX_SECINFO_X = BIT(
291 SGX_SECINFO_SECS = (SGX
292 SGX_SECINFO_TCS = (SGX
293 SGX_SECINFO_REG = (SGX
294 SGX_SECINFO_VA = (SGX
295 SGX_SECINFO_TRIM = (SGX
296 };
297
298 #define SGX_SECINFO_PERMISSION_MASK GENMAS
299 #define SGX_SECINFO_PAGE_TYPE_MASK (SGX_P
300 #define SGX_SECINFO_RESERVED_MASK ~(SGX_
301 SGX_
302
303 /**
304 * struct sgx_secinfo - describes attributes o
305 * @flags: permissions and type
306 *
307 * Used together with ENCLS leaves that add or
308 * enclave to define page permissions and type
309 */
310 struct sgx_secinfo {
311 u64 flags;
312 u8 reserved[56];
313 } __packed __aligned(64);
314
315 #define SGX_PCMD_RESERVED_SIZE 40
316
317 /**
318 * struct sgx_pcmd - Paging Crypto Metadata (P
319 * @enclave_id: enclave identifier
320 * @mac: MAC over PCMD, page contents a
321 *
322 * PCMD is stored for every swapped page to th
323 * the page back it recalculates the MAC by us
324 * VA page. Together these two structures brin
325 * protection.
326 */
327 struct sgx_pcmd {
328 struct sgx_secinfo secinfo;
329 u64 enclave_id;
330 u8 reserved[SGX_PCMD_RESERVED_SIZE];
331 u8 mac[16];
332 } __packed __aligned(128);
333
334 #define SGX_SIGSTRUCT_RESERVED1_SIZE 84
335 #define SGX_SIGSTRUCT_RESERVED2_SIZE 20
336 #define SGX_SIGSTRUCT_RESERVED3_SIZE 32
337 #define SGX_SIGSTRUCT_RESERVED4_SIZE 12
338
339 /**
340 * struct sgx_sigstruct_header - defines auth
341 * @header1: constant byte string
342 * @vendor: must be either 0x0000
343 * @date: YYYYMMDD in BCD
344 * @header2: constant byte string
345 * @swdefined: software defined value
346 */
347 struct sgx_sigstruct_header {
348 u64 header1[2];
349 u32 vendor;
350 u32 date;
351 u64 header2[2];
352 u32 swdefined;
353 u8 reserved1[84];
354 } __packed;
355
356 /**
357 * struct sgx_sigstruct_body - defines content
358 * @miscselect: additional information
359 * @misc_mask: required miscselect in
360 * @attributes: attributes for enclave
361 * @xfrm: XSave-Feature Request
362 * @attributes_mask: required attributes in
363 * @xfrm_mask: required XFRM in SECS
364 * @mrenclave: SHA256-hash of the enc
365 * @isvprodid: a user-defined value t
366 * @isvsvn: a user-defined value t
367 */
368 struct sgx_sigstruct_body {
369 u32 miscselect;
370 u32 misc_mask;
371 u8 reserved2[20];
372 u64 attributes;
373 u64 xfrm;
374 u64 attributes_mask;
375 u64 xfrm_mask;
376 u8 mrenclave[32];
377 u8 reserved3[32];
378 u16 isvprodid;
379 u16 isvsvn;
380 } __packed;
381
382 /**
383 * struct sgx_sigstruct - an enclave signature
384 * @header: defines author of the
385 * @modulus: the modulus of the pub
386 * @exponent: the exponent of the pu
387 * @signature: the signature calculat
388 * @body: defines contents of th
389 * @q1: a value used in RSA si
390 * @q2: a value used in RSA si
391 *
392 * Header and body are the parts that are actu
393 * define the signature of the enclave.
394 */
395 struct sgx_sigstruct {
396 struct sgx_sigstruct_header header;
397 u8 modulus[SGX_MODULUS_SIZE];
398 u32 exponent;
399 u8 signature[SGX_MODULUS_SIZE];
400 struct sgx_sigstruct_body body;
401 u8 reserved4[12];
402 u8 q1[SGX_MODULUS_SIZE];
403 u8 q2[SGX_MODULUS_SIZE];
404 } __packed;
405
406 #define SGX_LAUNCH_TOKEN_SIZE 304
407
408 /*
409 * Do not put any hardware-defined SGX structu
410 * comment!
411 */
412
413 #ifdef CONFIG_X86_SGX_KVM
414 int sgx_virt_ecreate(struct sgx_pageinfo *page
415 int *trapnr);
416 int sgx_virt_einit(void __user *sigstruct, voi
417 void __user *secs, u64 *lep
418 #endif
419
420 int sgx_set_attribute(unsigned long *allowed_a
421 unsigned int attribute_f
422
423 #endif /* _ASM_X86_SGX_H */
424
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