1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * vmx.h: VMX Architecture related definitions
4 * Copyright (c) 2004, Intel Corporation.
5 *
6 * A few random additions are:
7 * Copyright (C) 2006 Qumranet
8 * Avi Kivity <avi@qumranet.com>
9 * Yaniv Kamay <yaniv@qumranet.com>
10 */
11 #ifndef VMX_H
12 #define VMX_H
13
14
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/types.h>
18
19 #include <uapi/asm/vmx.h>
20 #include <asm/trapnr.h>
21 #include <asm/vmxfeatures.h>
22
23 #define VMCS_CONTROL_BIT(x) BIT(VMX_FEATUR
24
25 /*
26 * Definitions of Primary Processor-Based VM-E
27 */
28 #define CPU_BASED_INTR_WINDOW_EXITING
29 #define CPU_BASED_USE_TSC_OFFSETTING
30 #define CPU_BASED_HLT_EXITING
31 #define CPU_BASED_INVLPG_EXITING
32 #define CPU_BASED_MWAIT_EXITING
33 #define CPU_BASED_RDPMC_EXITING
34 #define CPU_BASED_RDTSC_EXITING
35 #define CPU_BASED_CR3_LOAD_EXITING
36 #define CPU_BASED_CR3_STORE_EXITING
37 #define CPU_BASED_ACTIVATE_TERTIARY_CONTROLS
38 #define CPU_BASED_CR8_LOAD_EXITING
39 #define CPU_BASED_CR8_STORE_EXITING
40 #define CPU_BASED_TPR_SHADOW
41 #define CPU_BASED_NMI_WINDOW_EXITING
42 #define CPU_BASED_MOV_DR_EXITING
43 #define CPU_BASED_UNCOND_IO_EXITING
44 #define CPU_BASED_USE_IO_BITMAPS
45 #define CPU_BASED_MONITOR_TRAP_FLAG
46 #define CPU_BASED_USE_MSR_BITMAPS
47 #define CPU_BASED_MONITOR_EXITING
48 #define CPU_BASED_PAUSE_EXITING
49 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
50
51 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
52
53 /*
54 * Definitions of Secondary Processor-Based VM
55 */
56 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSE
57 #define SECONDARY_EXEC_ENABLE_EPT
58 #define SECONDARY_EXEC_DESC
59 #define SECONDARY_EXEC_ENABLE_RDTSCP
60 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
61 #define SECONDARY_EXEC_ENABLE_VPID
62 #define SECONDARY_EXEC_WBINVD_EXITING
63 #define SECONDARY_EXEC_UNRESTRICTED_GUEST
64 #define SECONDARY_EXEC_APIC_REGISTER_VIRT
65 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
66 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING
67 #define SECONDARY_EXEC_RDRAND_EXITING
68 #define SECONDARY_EXEC_ENABLE_INVPCID
69 #define SECONDARY_EXEC_ENABLE_VMFUNC
70 #define SECONDARY_EXEC_SHADOW_VMCS
71 #define SECONDARY_EXEC_ENCLS_EXITING
72 #define SECONDARY_EXEC_RDSEED_EXITING
73 #define SECONDARY_EXEC_ENABLE_PML
74 #define SECONDARY_EXEC_EPT_VIOLATION_VE
75 #define SECONDARY_EXEC_PT_CONCEAL_VMX
76 #define SECONDARY_EXEC_ENABLE_XSAVES
77 #define SECONDARY_EXEC_MODE_BASED_EPT_EXEC
78 #define SECONDARY_EXEC_PT_USE_GPA
79 #define SECONDARY_EXEC_TSC_SCALING
80 #define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE
81 #define SECONDARY_EXEC_BUS_LOCK_DETECTION
82 #define SECONDARY_EXEC_NOTIFY_VM_EXITING
83
84 /*
85 * Definitions of Tertiary Processor-Based VM-
86 */
87 #define TERTIARY_EXEC_IPI_VIRT
88
89 #define PIN_BASED_EXT_INTR_MASK
90 #define PIN_BASED_NMI_EXITING
91 #define PIN_BASED_VIRTUAL_NMIS
92 #define PIN_BASED_VMX_PREEMPTION_TIMER
93 #define PIN_BASED_POSTED_INTR
94
95 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
96
97 #define VM_EXIT_SAVE_DEBUG_CONTROLS
98 #define VM_EXIT_HOST_ADDR_SPACE_SIZE
99 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
100 #define VM_EXIT_ACK_INTR_ON_EXIT
101 #define VM_EXIT_SAVE_IA32_PAT
102 #define VM_EXIT_LOAD_IA32_PAT
103 #define VM_EXIT_SAVE_IA32_EFER
104 #define VM_EXIT_LOAD_IA32_EFER
105 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
106 #define VM_EXIT_CLEAR_BNDCFGS
107 #define VM_EXIT_PT_CONCEAL_PIP
108 #define VM_EXIT_CLEAR_IA32_RTIT_CTL
109
110 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
111
112 #define VM_ENTRY_LOAD_DEBUG_CONTROLS
113 #define VM_ENTRY_IA32E_MODE
114 #define VM_ENTRY_SMM
115 #define VM_ENTRY_DEACT_DUAL_MONITOR
116 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
117 #define VM_ENTRY_LOAD_IA32_PAT
118 #define VM_ENTRY_LOAD_IA32_EFER
119 #define VM_ENTRY_LOAD_BNDCFGS
120 #define VM_ENTRY_PT_CONCEAL_PIP
121 #define VM_ENTRY_LOAD_IA32_RTIT_CTL
122
123 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
124
125 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK
126 #define VMX_MISC_SAVE_EFER_LMA
127 #define VMX_MISC_ACTIVITY_HLT
128 #define VMX_MISC_ACTIVITY_WAIT_SIPI
129 #define VMX_MISC_ZERO_LEN_INS
130 #define VMX_MISC_MSR_LIST_MULTIPLIER
131
132 /* VMFUNC functions */
133 #define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATU
134
135 #define VMX_VMFUNC_EPTP_SWITCHING
136 #define VMFUNC_EPTP_ENTRIES 512
137
138 static inline u32 vmx_basic_vmcs_revision_id(u
139 {
140 return vmx_basic & GENMASK_ULL(30, 0);
141 }
142
143 static inline u32 vmx_basic_vmcs_size(u64 vmx_
144 {
145 return (vmx_basic & GENMASK_ULL(44, 32
146 }
147
148 static inline int vmx_misc_preemption_timer_ra
149 {
150 return vmx_misc & VMX_MISC_PREEMPTION_
151 }
152
153 static inline int vmx_misc_cr3_count(u64 vmx_m
154 {
155 return (vmx_misc & GENMASK_ULL(24, 16)
156 }
157
158 static inline int vmx_misc_max_msr(u64 vmx_mis
159 {
160 return (vmx_misc & GENMASK_ULL(27, 25)
161 }
162
163 static inline int vmx_misc_mseg_revid(u64 vmx_
164 {
165 return (vmx_misc & GENMASK_ULL(63, 32)
166 }
167
168 /* VMCS Encodings */
169 enum vmcs_field {
170 VIRTUAL_PROCESSOR_ID = 0x00
171 POSTED_INTR_NV = 0x00
172 LAST_PID_POINTER_INDEX = 0x00
173 GUEST_ES_SELECTOR = 0x00
174 GUEST_CS_SELECTOR = 0x00
175 GUEST_SS_SELECTOR = 0x00
176 GUEST_DS_SELECTOR = 0x00
177 GUEST_FS_SELECTOR = 0x00
178 GUEST_GS_SELECTOR = 0x00
179 GUEST_LDTR_SELECTOR = 0x00
180 GUEST_TR_SELECTOR = 0x00
181 GUEST_INTR_STATUS = 0x00
182 GUEST_PML_INDEX = 0x00
183 HOST_ES_SELECTOR = 0x00
184 HOST_CS_SELECTOR = 0x00
185 HOST_SS_SELECTOR = 0x00
186 HOST_DS_SELECTOR = 0x00
187 HOST_FS_SELECTOR = 0x00
188 HOST_GS_SELECTOR = 0x00
189 HOST_TR_SELECTOR = 0x00
190 IO_BITMAP_A = 0x00
191 IO_BITMAP_A_HIGH = 0x00
192 IO_BITMAP_B = 0x00
193 IO_BITMAP_B_HIGH = 0x00
194 MSR_BITMAP = 0x00
195 MSR_BITMAP_HIGH = 0x00
196 VM_EXIT_MSR_STORE_ADDR = 0x00
197 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00
198 VM_EXIT_MSR_LOAD_ADDR = 0x00
199 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00
200 VM_ENTRY_MSR_LOAD_ADDR = 0x00
201 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x00
202 PML_ADDRESS = 0x00
203 PML_ADDRESS_HIGH = 0x00
204 TSC_OFFSET = 0x00
205 TSC_OFFSET_HIGH = 0x00
206 VIRTUAL_APIC_PAGE_ADDR = 0x00
207 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00
208 APIC_ACCESS_ADDR = 0x00
209 APIC_ACCESS_ADDR_HIGH = 0x00
210 POSTED_INTR_DESC_ADDR = 0x00
211 POSTED_INTR_DESC_ADDR_HIGH = 0x00
212 VM_FUNCTION_CONTROL = 0x00
213 VM_FUNCTION_CONTROL_HIGH = 0x00
214 EPT_POINTER = 0x00
215 EPT_POINTER_HIGH = 0x00
216 EOI_EXIT_BITMAP0 = 0x00
217 EOI_EXIT_BITMAP0_HIGH = 0x00
218 EOI_EXIT_BITMAP1 = 0x00
219 EOI_EXIT_BITMAP1_HIGH = 0x00
220 EOI_EXIT_BITMAP2 = 0x00
221 EOI_EXIT_BITMAP2_HIGH = 0x00
222 EOI_EXIT_BITMAP3 = 0x00
223 EOI_EXIT_BITMAP3_HIGH = 0x00
224 EPTP_LIST_ADDRESS = 0x00
225 EPTP_LIST_ADDRESS_HIGH = 0x00
226 VMREAD_BITMAP = 0x00
227 VMREAD_BITMAP_HIGH = 0x00
228 VMWRITE_BITMAP = 0x00
229 VMWRITE_BITMAP_HIGH = 0x00
230 VE_INFORMATION_ADDRESS = 0x00
231 VE_INFORMATION_ADDRESS_HIGH = 0x00
232 XSS_EXIT_BITMAP = 0x00
233 XSS_EXIT_BITMAP_HIGH = 0x00
234 ENCLS_EXITING_BITMAP = 0x00
235 ENCLS_EXITING_BITMAP_HIGH = 0x00
236 TSC_MULTIPLIER = 0x00
237 TSC_MULTIPLIER_HIGH = 0x00
238 TERTIARY_VM_EXEC_CONTROL = 0x00
239 TERTIARY_VM_EXEC_CONTROL_HIGH = 0x00
240 PID_POINTER_TABLE = 0x00
241 PID_POINTER_TABLE_HIGH = 0x00
242 GUEST_PHYSICAL_ADDRESS = 0x00
243 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00
244 VMCS_LINK_POINTER = 0x00
245 VMCS_LINK_POINTER_HIGH = 0x00
246 GUEST_IA32_DEBUGCTL = 0x00
247 GUEST_IA32_DEBUGCTL_HIGH = 0x00
248 GUEST_IA32_PAT = 0x00
249 GUEST_IA32_PAT_HIGH = 0x00
250 GUEST_IA32_EFER = 0x00
251 GUEST_IA32_EFER_HIGH = 0x00
252 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00
253 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00
254 GUEST_PDPTR0 = 0x00
255 GUEST_PDPTR0_HIGH = 0x00
256 GUEST_PDPTR1 = 0x00
257 GUEST_PDPTR1_HIGH = 0x00
258 GUEST_PDPTR2 = 0x00
259 GUEST_PDPTR2_HIGH = 0x00
260 GUEST_PDPTR3 = 0x00
261 GUEST_PDPTR3_HIGH = 0x00
262 GUEST_BNDCFGS = 0x00
263 GUEST_BNDCFGS_HIGH = 0x00
264 GUEST_IA32_RTIT_CTL = 0x00
265 GUEST_IA32_RTIT_CTL_HIGH = 0x00
266 HOST_IA32_PAT = 0x00
267 HOST_IA32_PAT_HIGH = 0x00
268 HOST_IA32_EFER = 0x00
269 HOST_IA32_EFER_HIGH = 0x00
270 HOST_IA32_PERF_GLOBAL_CTRL = 0x00
271 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00
272 PIN_BASED_VM_EXEC_CONTROL = 0x00
273 CPU_BASED_VM_EXEC_CONTROL = 0x00
274 EXCEPTION_BITMAP = 0x00
275 PAGE_FAULT_ERROR_CODE_MASK = 0x00
276 PAGE_FAULT_ERROR_CODE_MATCH = 0x00
277 CR3_TARGET_COUNT = 0x00
278 VM_EXIT_CONTROLS = 0x00
279 VM_EXIT_MSR_STORE_COUNT = 0x00
280 VM_EXIT_MSR_LOAD_COUNT = 0x00
281 VM_ENTRY_CONTROLS = 0x00
282 VM_ENTRY_MSR_LOAD_COUNT = 0x00
283 VM_ENTRY_INTR_INFO_FIELD = 0x00
284 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00
285 VM_ENTRY_INSTRUCTION_LEN = 0x00
286 TPR_THRESHOLD = 0x00
287 SECONDARY_VM_EXEC_CONTROL = 0x00
288 PLE_GAP = 0x00
289 PLE_WINDOW = 0x00
290 NOTIFY_WINDOW = 0x00
291 VM_INSTRUCTION_ERROR = 0x00
292 VM_EXIT_REASON = 0x00
293 VM_EXIT_INTR_INFO = 0x00
294 VM_EXIT_INTR_ERROR_CODE = 0x00
295 IDT_VECTORING_INFO_FIELD = 0x00
296 IDT_VECTORING_ERROR_CODE = 0x00
297 VM_EXIT_INSTRUCTION_LEN = 0x00
298 VMX_INSTRUCTION_INFO = 0x00
299 GUEST_ES_LIMIT = 0x00
300 GUEST_CS_LIMIT = 0x00
301 GUEST_SS_LIMIT = 0x00
302 GUEST_DS_LIMIT = 0x00
303 GUEST_FS_LIMIT = 0x00
304 GUEST_GS_LIMIT = 0x00
305 GUEST_LDTR_LIMIT = 0x00
306 GUEST_TR_LIMIT = 0x00
307 GUEST_GDTR_LIMIT = 0x00
308 GUEST_IDTR_LIMIT = 0x00
309 GUEST_ES_AR_BYTES = 0x00
310 GUEST_CS_AR_BYTES = 0x00
311 GUEST_SS_AR_BYTES = 0x00
312 GUEST_DS_AR_BYTES = 0x00
313 GUEST_FS_AR_BYTES = 0x00
314 GUEST_GS_AR_BYTES = 0x00
315 GUEST_LDTR_AR_BYTES = 0x00
316 GUEST_TR_AR_BYTES = 0x00
317 GUEST_INTERRUPTIBILITY_INFO = 0x00
318 GUEST_ACTIVITY_STATE = 0x00
319 GUEST_SYSENTER_CS = 0x00
320 VMX_PREEMPTION_TIMER_VALUE = 0x00
321 HOST_IA32_SYSENTER_CS = 0x00
322 CR0_GUEST_HOST_MASK = 0x00
323 CR4_GUEST_HOST_MASK = 0x00
324 CR0_READ_SHADOW = 0x00
325 CR4_READ_SHADOW = 0x00
326 CR3_TARGET_VALUE0 = 0x00
327 CR3_TARGET_VALUE1 = 0x00
328 CR3_TARGET_VALUE2 = 0x00
329 CR3_TARGET_VALUE3 = 0x00
330 EXIT_QUALIFICATION = 0x00
331 GUEST_LINEAR_ADDRESS = 0x00
332 GUEST_CR0 = 0x00
333 GUEST_CR3 = 0x00
334 GUEST_CR4 = 0x00
335 GUEST_ES_BASE = 0x00
336 GUEST_CS_BASE = 0x00
337 GUEST_SS_BASE = 0x00
338 GUEST_DS_BASE = 0x00
339 GUEST_FS_BASE = 0x00
340 GUEST_GS_BASE = 0x00
341 GUEST_LDTR_BASE = 0x00
342 GUEST_TR_BASE = 0x00
343 GUEST_GDTR_BASE = 0x00
344 GUEST_IDTR_BASE = 0x00
345 GUEST_DR7 = 0x00
346 GUEST_RSP = 0x00
347 GUEST_RIP = 0x00
348 GUEST_RFLAGS = 0x00
349 GUEST_PENDING_DBG_EXCEPTIONS = 0x00
350 GUEST_SYSENTER_ESP = 0x00
351 GUEST_SYSENTER_EIP = 0x00
352 HOST_CR0 = 0x00
353 HOST_CR3 = 0x00
354 HOST_CR4 = 0x00
355 HOST_FS_BASE = 0x00
356 HOST_GS_BASE = 0x00
357 HOST_TR_BASE = 0x00
358 HOST_GDTR_BASE = 0x00
359 HOST_IDTR_BASE = 0x00
360 HOST_IA32_SYSENTER_ESP = 0x00
361 HOST_IA32_SYSENTER_EIP = 0x00
362 HOST_RSP = 0x00
363 HOST_RIP = 0x00
364 };
365
366 /*
367 * Interruption-information format
368 */
369 #define INTR_INFO_VECTOR_MASK 0xff
370 #define INTR_INFO_INTR_TYPE_MASK 0x700
371 #define INTR_INFO_DELIVER_CODE_MASK 0x800
372 #define INTR_INFO_UNBLOCK_NMI 0x1000
373 #define INTR_INFO_VALID_MASK 0x8000
374 #define INTR_INFO_RESVD_BITS_MASK 0x7fff
375
376 #define VECTORING_INFO_VECTOR_MASK
377 #define VECTORING_INFO_TYPE_MASK
378 #define VECTORING_INFO_DELIVER_CODE_MASK
379 #define VECTORING_INFO_VALID_MASK
380
381 #define INTR_TYPE_EXT_INTR (EVENT
382 #define INTR_TYPE_RESERVED (EVENT
383 #define INTR_TYPE_NMI_INTR (EVENT
384 #define INTR_TYPE_HARD_EXCEPTION (EVENT
385 #define INTR_TYPE_SOFT_INTR (EVENT
386 #define INTR_TYPE_PRIV_SW_EXCEPTION (EVENT
387 #define INTR_TYPE_SOFT_EXCEPTION (EVENT
388 #define INTR_TYPE_OTHER_EVENT (EVENT
389
390 /* GUEST_INTERRUPTIBILITY_INFO flags. */
391 #define GUEST_INTR_STATE_STI 0x0000
392 #define GUEST_INTR_STATE_MOV_SS 0x0000
393 #define GUEST_INTR_STATE_SMI 0x0000
394 #define GUEST_INTR_STATE_NMI 0x0000
395 #define GUEST_INTR_STATE_ENCLAVE_INTR 0x0000
396
397 /* GUEST_ACTIVITY_STATE flags */
398 #define GUEST_ACTIVITY_ACTIVE 0
399 #define GUEST_ACTIVITY_HLT 1
400 #define GUEST_ACTIVITY_SHUTDOWN 2
401 #define GUEST_ACTIVITY_WAIT_SIPI 3
402
403 /*
404 * Exit Qualifications for MOV for Control Reg
405 */
406 #define CONTROL_REG_ACCESS_NUM 0x7
407 #define CONTROL_REG_ACCESS_TYPE 0x30
408 #define CONTROL_REG_ACCESS_REG 0xf00
409 #define LMSW_SOURCE_DATA_SHIFT 16
410 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOUR
411 #define REG_EAX (0 <<
412 #define REG_ECX (1 <<
413 #define REG_EDX (2 <<
414 #define REG_EBX (3 <<
415 #define REG_ESP (4 <<
416 #define REG_EBP (5 <<
417 #define REG_ESI (6 <<
418 #define REG_EDI (7 <<
419 #define REG_R8 (8 << 8
420 #define REG_R9 (9 << 8
421 #define REG_R10 (10 <<
422 #define REG_R11 (11 <<
423 #define REG_R12 (12 <<
424 #define REG_R13 (13 <<
425 #define REG_R14 (14 <<
426 #define REG_R15 (15 <<
427
428 /*
429 * Exit Qualifications for MOV for Debug Regis
430 */
431 #define DEBUG_REG_ACCESS_NUM 0x7
432 #define DEBUG_REG_ACCESS_TYPE 0x10
433 #define TYPE_MOV_TO_DR (0 <<
434 #define TYPE_MOV_FROM_DR (1 <<
435 #define DEBUG_REG_ACCESS_REG(eq) (((eq)
436
437
438 /*
439 * Exit Qualifications for APIC-Access
440 */
441 #define APIC_ACCESS_OFFSET 0xfff
442 #define APIC_ACCESS_TYPE 0xf000
443 #define TYPE_LINEAR_APIC_INST_READ (0 <<
444 #define TYPE_LINEAR_APIC_INST_WRITE (1 <<
445 #define TYPE_LINEAR_APIC_INST_FETCH (2 <<
446 #define TYPE_LINEAR_APIC_EVENT (3 <<
447 #define TYPE_PHYSICAL_APIC_EVENT (10 <<
448 #define TYPE_PHYSICAL_APIC_INST (15 <<
449
450 /* segment AR in VMCS -- these are different f
451 #define VMX_SEGMENT_AR_L_MASK (1 << 13)
452
453 #define VMX_AR_TYPE_ACCESSES_MASK 1
454 #define VMX_AR_TYPE_READABLE_MASK (1 << 1)
455 #define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
456 #define VMX_AR_TYPE_CODE_MASK (1 << 3)
457 #define VMX_AR_TYPE_MASK 0x0f
458 #define VMX_AR_TYPE_BUSY_64_TSS 11
459 #define VMX_AR_TYPE_BUSY_32_TSS 11
460 #define VMX_AR_TYPE_BUSY_16_TSS 3
461 #define VMX_AR_TYPE_LDT 2
462
463 #define VMX_AR_UNUSABLE_MASK (1 << 16)
464 #define VMX_AR_S_MASK (1 << 4)
465 #define VMX_AR_P_MASK (1 << 7)
466 #define VMX_AR_L_MASK (1 << 13)
467 #define VMX_AR_DB_MASK (1 << 14)
468 #define VMX_AR_G_MASK (1 << 15)
469 #define VMX_AR_DPL_SHIFT 5
470 #define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SH
471
472 #define VMX_AR_RESERVD_MASK 0xfffe0f00
473
474 #define TSS_PRIVATE_MEMSLOT
475 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
476 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
477
478 #define VMX_NR_VPIDS
479 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR
480 #define VMX_VPID_EXTENT_SINGLE_CONTEXT
481 #define VMX_VPID_EXTENT_ALL_CONTEXT
482 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
483
484 #define VMX_EPT_EXTENT_CONTEXT
485 #define VMX_EPT_EXTENT_GLOBAL
486 #define VMX_EPT_EXTENT_SHIFT
487
488 #define VMX_EPT_EXECUTE_ONLY_BIT
489 #define VMX_EPT_PAGE_WALK_4_BIT
490 #define VMX_EPT_PAGE_WALK_5_BIT
491 #define VMX_EPTP_UC_BIT
492 #define VMX_EPTP_WB_BIT
493 #define VMX_EPT_2MB_PAGE_BIT
494 #define VMX_EPT_1GB_PAGE_BIT
495 #define VMX_EPT_INVEPT_BIT
496 #define VMX_EPT_AD_BIT
497 #define VMX_EPT_EXTENT_CONTEXT_BIT
498 #define VMX_EPT_EXTENT_GLOBAL_BIT
499
500 #define VMX_VPID_INVVPID_BIT
501 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT
502 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
503 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
504 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT
505
506 #define VMX_EPT_MT_EPTE_SHIFT
507 #define VMX_EPTP_PWL_MASK
508 #define VMX_EPTP_PWL_4
509 #define VMX_EPTP_PWL_5
510 #define VMX_EPTP_AD_ENABLE_BIT
511 #define VMX_EPTP_MT_MASK
512 #define VMX_EPTP_MT_WB
513 #define VMX_EPTP_MT_UC
514 #define VMX_EPT_READABLE_MASK
515 #define VMX_EPT_WRITABLE_MASK
516 #define VMX_EPT_EXECUTABLE_MASK
517 #define VMX_EPT_IPAT_BIT
518 #define VMX_EPT_ACCESS_BIT
519 #define VMX_EPT_DIRTY_BIT
520 #define VMX_EPT_SUPPRESS_VE_BIT
521 #define VMX_EPT_RWX_MASK
522
523
524 #define VMX_EPT_MT_MASK
525
526 static inline u8 vmx_eptp_page_walk_level(u64
527 {
528 u64 encoded_level = eptp & VMX_EPTP_PW
529
530 if (encoded_level == VMX_EPTP_PWL_5)
531 return 5;
532
533 /* @eptp must be pre-validated by the
534 WARN_ON_ONCE(encoded_level != VMX_EPTP
535 return 4;
536 }
537
538 /* The mask to use to trigger an EPT Misconfig
539 #define VMX_EPT_MISCONFIG_WX_VALUE
540
541
542 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR
543
544 struct vmx_msr_entry {
545 u32 index;
546 u32 reserved;
547 u64 value;
548 } __aligned(16);
549
550 /*
551 * Exit Qualifications for entry failure durin
552 */
553 enum vm_entry_failure_code {
554 ENTRY_FAIL_DEFAULT = 0,
555 ENTRY_FAIL_PDPTE = 2,
556 ENTRY_FAIL_NMI = 3,
557 ENTRY_FAIL_VMCS_LINK_PTR = 4,
558 };
559
560 /*
561 * Exit Qualifications for EPT Violations
562 */
563 #define EPT_VIOLATION_ACC_READ_BIT 0
564 #define EPT_VIOLATION_ACC_WRITE_BIT 1
565 #define EPT_VIOLATION_ACC_INSTR_BIT 2
566 #define EPT_VIOLATION_RWX_SHIFT 3
567 #define EPT_VIOLATION_GVA_IS_VALID_BIT 7
568 #define EPT_VIOLATION_GVA_TRANSLATED_BIT 8
569 #define EPT_VIOLATION_ACC_READ (1 <<
570 #define EPT_VIOLATION_ACC_WRITE (1 <<
571 #define EPT_VIOLATION_ACC_INSTR (1 <<
572 #define EPT_VIOLATION_RWX_MASK (VMX_E
573 #define EPT_VIOLATION_GVA_IS_VALID (1 <<
574 #define EPT_VIOLATION_GVA_TRANSLATED (1 <<
575
576 /*
577 * Exit Qualifications for NOTIFY VM EXIT
578 */
579 #define NOTIFY_VM_CONTEXT_INVALID BIT(0)
580
581 /*
582 * VM-instruction error numbers
583 */
584 enum vm_instruction_error_number {
585 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION =
586 VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
587 VMXERR_VMCLEAR_VMXON_POINTER = 3,
588 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
589 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
590 VMXERR_VMRESUME_AFTER_VMXOFF = 6,
591 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7
592 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
593 VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
594 VMXERR_VMPTRLD_VMXON_POINTER = 10,
595 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION
596 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12
597 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONEN
598 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 1
599 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_PO
600 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMC
601 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NO
602 VMXERR_VMCALL_NONCLEAR_VMCS = 19,
603 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_
604 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_
605 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREAT
606 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEAT
607 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONT
608 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
609 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVP
610 };
611
612 /*
613 * VM-instruction errors that can be encounter
614 * nested VM-Enter failures reported by hardwa
615 * from a SMI Transfer Monitor are not include
616 * sideways if we get one of those...
617 */
618 #define VMX_VMENTER_INSTRUCTION_ERRORS \
619 { VMXERR_VMLAUNCH_NONCLEAR_VMCS,
620 { VMXERR_VMRESUME_NONLAUNCHED_VMCS,
621 { VMXERR_VMRESUME_AFTER_VMXOFF,
622 { VMXERR_ENTRY_INVALID_CONTROL_FIELD,
623 { VMXERR_ENTRY_INVALID_HOST_STATE_FIEL
624 { VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_S
625
626 enum vmx_l1d_flush_state {
627 VMENTER_L1D_FLUSH_AUTO,
628 VMENTER_L1D_FLUSH_NEVER,
629 VMENTER_L1D_FLUSH_COND,
630 VMENTER_L1D_FLUSH_ALWAYS,
631 VMENTER_L1D_FLUSH_EPT_DISABLED,
632 VMENTER_L1D_FLUSH_NOT_REQUIRED,
633 };
634
635 extern enum vmx_l1d_flush_state l1tf_vmx_mitig
636
637 struct vmx_ve_information {
638 u32 exit_reason;
639 u32 delivery;
640 u64 exit_qualification;
641 u64 guest_linear_address;
642 u64 guest_physical_address;
643 u16 eptp_index;
644 };
645
646 #endif
647
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