1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * vmx.h: VMX Architecture related definitions
4 * Copyright (c) 2004, Intel Corporation.
5 *
6 * A few random additions are:
7 * Copyright (C) 2006 Qumranet
8 * Avi Kivity <avi@qumranet.com>
9 * Yaniv Kamay <yaniv@qumranet.com>
10 */
11 #ifndef VMX_H
12 #define VMX_H
13
14
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/types.h>
18
19 #include <uapi/asm/vmx.h>
20 #include <asm/trapnr.h>
21 #include <asm/vmxfeatures.h>
22
23 #define VMCS_CONTROL_BIT(x) BIT(VMX_FEATUR
24
25 /*
26 * Definitions of Primary Processor-Based VM-E
27 */
28 #define CPU_BASED_INTR_WINDOW_EXITING
29 #define CPU_BASED_USE_TSC_OFFSETTING
30 #define CPU_BASED_HLT_EXITING
31 #define CPU_BASED_INVLPG_EXITING
32 #define CPU_BASED_MWAIT_EXITING
33 #define CPU_BASED_RDPMC_EXITING
34 #define CPU_BASED_RDTSC_EXITING
35 #define CPU_BASED_CR3_LOAD_EXITING
36 #define CPU_BASED_CR3_STORE_EXITING
37 #define CPU_BASED_ACTIVATE_TERTIARY_CONTROLS
38 #define CPU_BASED_CR8_LOAD_EXITING
39 #define CPU_BASED_CR8_STORE_EXITING
40 #define CPU_BASED_TPR_SHADOW
41 #define CPU_BASED_NMI_WINDOW_EXITING
42 #define CPU_BASED_MOV_DR_EXITING
43 #define CPU_BASED_UNCOND_IO_EXITING
44 #define CPU_BASED_USE_IO_BITMAPS
45 #define CPU_BASED_MONITOR_TRAP_FLAG
46 #define CPU_BASED_USE_MSR_BITMAPS
47 #define CPU_BASED_MONITOR_EXITING
48 #define CPU_BASED_PAUSE_EXITING
49 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
50
51 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
52
53 /*
54 * Definitions of Secondary Processor-Based VM
55 */
56 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSE
57 #define SECONDARY_EXEC_ENABLE_EPT
58 #define SECONDARY_EXEC_DESC
59 #define SECONDARY_EXEC_ENABLE_RDTSCP
60 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
61 #define SECONDARY_EXEC_ENABLE_VPID
62 #define SECONDARY_EXEC_WBINVD_EXITING
63 #define SECONDARY_EXEC_UNRESTRICTED_GUEST
64 #define SECONDARY_EXEC_APIC_REGISTER_VIRT
65 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
66 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING
67 #define SECONDARY_EXEC_RDRAND_EXITING
68 #define SECONDARY_EXEC_ENABLE_INVPCID
69 #define SECONDARY_EXEC_ENABLE_VMFUNC
70 #define SECONDARY_EXEC_SHADOW_VMCS
71 #define SECONDARY_EXEC_ENCLS_EXITING
72 #define SECONDARY_EXEC_RDSEED_EXITING
73 #define SECONDARY_EXEC_ENABLE_PML
74 #define SECONDARY_EXEC_EPT_VIOLATION_VE
75 #define SECONDARY_EXEC_PT_CONCEAL_VMX
76 #define SECONDARY_EXEC_ENABLE_XSAVES
77 #define SECONDARY_EXEC_MODE_BASED_EPT_EXEC
78 #define SECONDARY_EXEC_PT_USE_GPA
79 #define SECONDARY_EXEC_TSC_SCALING
80 #define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE
81 #define SECONDARY_EXEC_BUS_LOCK_DETECTION
82 #define SECONDARY_EXEC_NOTIFY_VM_EXITING
83
84 /*
85 * Definitions of Tertiary Processor-Based VM-
86 */
87 #define TERTIARY_EXEC_IPI_VIRT
88
89 #define PIN_BASED_EXT_INTR_MASK
90 #define PIN_BASED_NMI_EXITING
91 #define PIN_BASED_VIRTUAL_NMIS
92 #define PIN_BASED_VMX_PREEMPTION_TIMER
93 #define PIN_BASED_POSTED_INTR
94
95 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
96
97 #define VM_EXIT_SAVE_DEBUG_CONTROLS
98 #define VM_EXIT_HOST_ADDR_SPACE_SIZE
99 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
100 #define VM_EXIT_ACK_INTR_ON_EXIT
101 #define VM_EXIT_SAVE_IA32_PAT
102 #define VM_EXIT_LOAD_IA32_PAT
103 #define VM_EXIT_SAVE_IA32_EFER
104 #define VM_EXIT_LOAD_IA32_EFER
105 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
106 #define VM_EXIT_CLEAR_BNDCFGS
107 #define VM_EXIT_PT_CONCEAL_PIP
108 #define VM_EXIT_CLEAR_IA32_RTIT_CTL
109
110 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
111
112 #define VM_ENTRY_LOAD_DEBUG_CONTROLS
113 #define VM_ENTRY_IA32E_MODE
114 #define VM_ENTRY_SMM
115 #define VM_ENTRY_DEACT_DUAL_MONITOR
116 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
117 #define VM_ENTRY_LOAD_IA32_PAT
118 #define VM_ENTRY_LOAD_IA32_EFER
119 #define VM_ENTRY_LOAD_BNDCFGS
120 #define VM_ENTRY_PT_CONCEAL_PIP
121 #define VM_ENTRY_LOAD_IA32_RTIT_CTL
122
123 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
124
125 /* VMFUNC functions */
126 #define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATU
127
128 #define VMX_VMFUNC_EPTP_SWITCHING
129 #define VMFUNC_EPTP_ENTRIES 512
130
131 #define VMX_BASIC_32BIT_PHYS_ADDR_ONLY
132 #define VMX_BASIC_DUAL_MONITOR_TREATMENT
133 #define VMX_BASIC_INOUT
134 #define VMX_BASIC_TRUE_CTLS
135
136 static inline u32 vmx_basic_vmcs_revision_id(u
137 {
138 return vmx_basic & GENMASK_ULL(30, 0);
139 }
140
141 static inline u32 vmx_basic_vmcs_size(u64 vmx_
142 {
143 return (vmx_basic & GENMASK_ULL(44, 32
144 }
145
146 static inline u32 vmx_basic_vmcs_mem_type(u64
147 {
148 return (vmx_basic & GENMASK_ULL(53, 50
149 }
150
151 static inline u64 vmx_basic_encode_vmcs_info(u
152 {
153 return revision | ((u64)size << 32) |
154 }
155
156 #define VMX_MISC_SAVE_EFER_LMA
157 #define VMX_MISC_ACTIVITY_HLT
158 #define VMX_MISC_ACTIVITY_SHUTDOWN
159 #define VMX_MISC_ACTIVITY_WAIT_SIPI
160 #define VMX_MISC_INTEL_PT
161 #define VMX_MISC_RDMSR_IN_SMM
162 #define VMX_MISC_VMXOFF_BLOCK_SMI
163 #define VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
164 #define VMX_MISC_ZERO_LEN_INS
165 #define VMX_MISC_MSR_LIST_MULTIPLIER
166
167 static inline int vmx_misc_preemption_timer_ra
168 {
169 return vmx_misc & GENMASK_ULL(4, 0);
170 }
171
172 static inline int vmx_misc_cr3_count(u64 vmx_m
173 {
174 return (vmx_misc & GENMASK_ULL(24, 16)
175 }
176
177 static inline int vmx_misc_max_msr(u64 vmx_mis
178 {
179 return (vmx_misc & GENMASK_ULL(27, 25)
180 }
181
182 static inline int vmx_misc_mseg_revid(u64 vmx_
183 {
184 return (vmx_misc & GENMASK_ULL(63, 32)
185 }
186
187 /* VMCS Encodings */
188 enum vmcs_field {
189 VIRTUAL_PROCESSOR_ID = 0x00
190 POSTED_INTR_NV = 0x00
191 LAST_PID_POINTER_INDEX = 0x00
192 GUEST_ES_SELECTOR = 0x00
193 GUEST_CS_SELECTOR = 0x00
194 GUEST_SS_SELECTOR = 0x00
195 GUEST_DS_SELECTOR = 0x00
196 GUEST_FS_SELECTOR = 0x00
197 GUEST_GS_SELECTOR = 0x00
198 GUEST_LDTR_SELECTOR = 0x00
199 GUEST_TR_SELECTOR = 0x00
200 GUEST_INTR_STATUS = 0x00
201 GUEST_PML_INDEX = 0x00
202 HOST_ES_SELECTOR = 0x00
203 HOST_CS_SELECTOR = 0x00
204 HOST_SS_SELECTOR = 0x00
205 HOST_DS_SELECTOR = 0x00
206 HOST_FS_SELECTOR = 0x00
207 HOST_GS_SELECTOR = 0x00
208 HOST_TR_SELECTOR = 0x00
209 IO_BITMAP_A = 0x00
210 IO_BITMAP_A_HIGH = 0x00
211 IO_BITMAP_B = 0x00
212 IO_BITMAP_B_HIGH = 0x00
213 MSR_BITMAP = 0x00
214 MSR_BITMAP_HIGH = 0x00
215 VM_EXIT_MSR_STORE_ADDR = 0x00
216 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00
217 VM_EXIT_MSR_LOAD_ADDR = 0x00
218 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00
219 VM_ENTRY_MSR_LOAD_ADDR = 0x00
220 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x00
221 PML_ADDRESS = 0x00
222 PML_ADDRESS_HIGH = 0x00
223 TSC_OFFSET = 0x00
224 TSC_OFFSET_HIGH = 0x00
225 VIRTUAL_APIC_PAGE_ADDR = 0x00
226 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00
227 APIC_ACCESS_ADDR = 0x00
228 APIC_ACCESS_ADDR_HIGH = 0x00
229 POSTED_INTR_DESC_ADDR = 0x00
230 POSTED_INTR_DESC_ADDR_HIGH = 0x00
231 VM_FUNCTION_CONTROL = 0x00
232 VM_FUNCTION_CONTROL_HIGH = 0x00
233 EPT_POINTER = 0x00
234 EPT_POINTER_HIGH = 0x00
235 EOI_EXIT_BITMAP0 = 0x00
236 EOI_EXIT_BITMAP0_HIGH = 0x00
237 EOI_EXIT_BITMAP1 = 0x00
238 EOI_EXIT_BITMAP1_HIGH = 0x00
239 EOI_EXIT_BITMAP2 = 0x00
240 EOI_EXIT_BITMAP2_HIGH = 0x00
241 EOI_EXIT_BITMAP3 = 0x00
242 EOI_EXIT_BITMAP3_HIGH = 0x00
243 EPTP_LIST_ADDRESS = 0x00
244 EPTP_LIST_ADDRESS_HIGH = 0x00
245 VMREAD_BITMAP = 0x00
246 VMREAD_BITMAP_HIGH = 0x00
247 VMWRITE_BITMAP = 0x00
248 VMWRITE_BITMAP_HIGH = 0x00
249 VE_INFORMATION_ADDRESS = 0x00
250 VE_INFORMATION_ADDRESS_HIGH = 0x00
251 XSS_EXIT_BITMAP = 0x00
252 XSS_EXIT_BITMAP_HIGH = 0x00
253 ENCLS_EXITING_BITMAP = 0x00
254 ENCLS_EXITING_BITMAP_HIGH = 0x00
255 TSC_MULTIPLIER = 0x00
256 TSC_MULTIPLIER_HIGH = 0x00
257 TERTIARY_VM_EXEC_CONTROL = 0x00
258 TERTIARY_VM_EXEC_CONTROL_HIGH = 0x00
259 PID_POINTER_TABLE = 0x00
260 PID_POINTER_TABLE_HIGH = 0x00
261 GUEST_PHYSICAL_ADDRESS = 0x00
262 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00
263 VMCS_LINK_POINTER = 0x00
264 VMCS_LINK_POINTER_HIGH = 0x00
265 GUEST_IA32_DEBUGCTL = 0x00
266 GUEST_IA32_DEBUGCTL_HIGH = 0x00
267 GUEST_IA32_PAT = 0x00
268 GUEST_IA32_PAT_HIGH = 0x00
269 GUEST_IA32_EFER = 0x00
270 GUEST_IA32_EFER_HIGH = 0x00
271 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00
272 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00
273 GUEST_PDPTR0 = 0x00
274 GUEST_PDPTR0_HIGH = 0x00
275 GUEST_PDPTR1 = 0x00
276 GUEST_PDPTR1_HIGH = 0x00
277 GUEST_PDPTR2 = 0x00
278 GUEST_PDPTR2_HIGH = 0x00
279 GUEST_PDPTR3 = 0x00
280 GUEST_PDPTR3_HIGH = 0x00
281 GUEST_BNDCFGS = 0x00
282 GUEST_BNDCFGS_HIGH = 0x00
283 GUEST_IA32_RTIT_CTL = 0x00
284 GUEST_IA32_RTIT_CTL_HIGH = 0x00
285 HOST_IA32_PAT = 0x00
286 HOST_IA32_PAT_HIGH = 0x00
287 HOST_IA32_EFER = 0x00
288 HOST_IA32_EFER_HIGH = 0x00
289 HOST_IA32_PERF_GLOBAL_CTRL = 0x00
290 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00
291 PIN_BASED_VM_EXEC_CONTROL = 0x00
292 CPU_BASED_VM_EXEC_CONTROL = 0x00
293 EXCEPTION_BITMAP = 0x00
294 PAGE_FAULT_ERROR_CODE_MASK = 0x00
295 PAGE_FAULT_ERROR_CODE_MATCH = 0x00
296 CR3_TARGET_COUNT = 0x00
297 VM_EXIT_CONTROLS = 0x00
298 VM_EXIT_MSR_STORE_COUNT = 0x00
299 VM_EXIT_MSR_LOAD_COUNT = 0x00
300 VM_ENTRY_CONTROLS = 0x00
301 VM_ENTRY_MSR_LOAD_COUNT = 0x00
302 VM_ENTRY_INTR_INFO_FIELD = 0x00
303 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00
304 VM_ENTRY_INSTRUCTION_LEN = 0x00
305 TPR_THRESHOLD = 0x00
306 SECONDARY_VM_EXEC_CONTROL = 0x00
307 PLE_GAP = 0x00
308 PLE_WINDOW = 0x00
309 NOTIFY_WINDOW = 0x00
310 VM_INSTRUCTION_ERROR = 0x00
311 VM_EXIT_REASON = 0x00
312 VM_EXIT_INTR_INFO = 0x00
313 VM_EXIT_INTR_ERROR_CODE = 0x00
314 IDT_VECTORING_INFO_FIELD = 0x00
315 IDT_VECTORING_ERROR_CODE = 0x00
316 VM_EXIT_INSTRUCTION_LEN = 0x00
317 VMX_INSTRUCTION_INFO = 0x00
318 GUEST_ES_LIMIT = 0x00
319 GUEST_CS_LIMIT = 0x00
320 GUEST_SS_LIMIT = 0x00
321 GUEST_DS_LIMIT = 0x00
322 GUEST_FS_LIMIT = 0x00
323 GUEST_GS_LIMIT = 0x00
324 GUEST_LDTR_LIMIT = 0x00
325 GUEST_TR_LIMIT = 0x00
326 GUEST_GDTR_LIMIT = 0x00
327 GUEST_IDTR_LIMIT = 0x00
328 GUEST_ES_AR_BYTES = 0x00
329 GUEST_CS_AR_BYTES = 0x00
330 GUEST_SS_AR_BYTES = 0x00
331 GUEST_DS_AR_BYTES = 0x00
332 GUEST_FS_AR_BYTES = 0x00
333 GUEST_GS_AR_BYTES = 0x00
334 GUEST_LDTR_AR_BYTES = 0x00
335 GUEST_TR_AR_BYTES = 0x00
336 GUEST_INTERRUPTIBILITY_INFO = 0x00
337 GUEST_ACTIVITY_STATE = 0x00
338 GUEST_SYSENTER_CS = 0x00
339 VMX_PREEMPTION_TIMER_VALUE = 0x00
340 HOST_IA32_SYSENTER_CS = 0x00
341 CR0_GUEST_HOST_MASK = 0x00
342 CR4_GUEST_HOST_MASK = 0x00
343 CR0_READ_SHADOW = 0x00
344 CR4_READ_SHADOW = 0x00
345 CR3_TARGET_VALUE0 = 0x00
346 CR3_TARGET_VALUE1 = 0x00
347 CR3_TARGET_VALUE2 = 0x00
348 CR3_TARGET_VALUE3 = 0x00
349 EXIT_QUALIFICATION = 0x00
350 GUEST_LINEAR_ADDRESS = 0x00
351 GUEST_CR0 = 0x00
352 GUEST_CR3 = 0x00
353 GUEST_CR4 = 0x00
354 GUEST_ES_BASE = 0x00
355 GUEST_CS_BASE = 0x00
356 GUEST_SS_BASE = 0x00
357 GUEST_DS_BASE = 0x00
358 GUEST_FS_BASE = 0x00
359 GUEST_GS_BASE = 0x00
360 GUEST_LDTR_BASE = 0x00
361 GUEST_TR_BASE = 0x00
362 GUEST_GDTR_BASE = 0x00
363 GUEST_IDTR_BASE = 0x00
364 GUEST_DR7 = 0x00
365 GUEST_RSP = 0x00
366 GUEST_RIP = 0x00
367 GUEST_RFLAGS = 0x00
368 GUEST_PENDING_DBG_EXCEPTIONS = 0x00
369 GUEST_SYSENTER_ESP = 0x00
370 GUEST_SYSENTER_EIP = 0x00
371 HOST_CR0 = 0x00
372 HOST_CR3 = 0x00
373 HOST_CR4 = 0x00
374 HOST_FS_BASE = 0x00
375 HOST_GS_BASE = 0x00
376 HOST_TR_BASE = 0x00
377 HOST_GDTR_BASE = 0x00
378 HOST_IDTR_BASE = 0x00
379 HOST_IA32_SYSENTER_ESP = 0x00
380 HOST_IA32_SYSENTER_EIP = 0x00
381 HOST_RSP = 0x00
382 HOST_RIP = 0x00
383 };
384
385 /*
386 * Interruption-information format
387 */
388 #define INTR_INFO_VECTOR_MASK 0xff
389 #define INTR_INFO_INTR_TYPE_MASK 0x700
390 #define INTR_INFO_DELIVER_CODE_MASK 0x800
391 #define INTR_INFO_UNBLOCK_NMI 0x1000
392 #define INTR_INFO_VALID_MASK 0x8000
393 #define INTR_INFO_RESVD_BITS_MASK 0x7fff
394
395 #define VECTORING_INFO_VECTOR_MASK
396 #define VECTORING_INFO_TYPE_MASK
397 #define VECTORING_INFO_DELIVER_CODE_MASK
398 #define VECTORING_INFO_VALID_MASK
399
400 #define INTR_TYPE_EXT_INTR (EVENT
401 #define INTR_TYPE_RESERVED (EVENT
402 #define INTR_TYPE_NMI_INTR (EVENT
403 #define INTR_TYPE_HARD_EXCEPTION (EVENT
404 #define INTR_TYPE_SOFT_INTR (EVENT
405 #define INTR_TYPE_PRIV_SW_EXCEPTION (EVENT
406 #define INTR_TYPE_SOFT_EXCEPTION (EVENT
407 #define INTR_TYPE_OTHER_EVENT (EVENT
408
409 /* GUEST_INTERRUPTIBILITY_INFO flags. */
410 #define GUEST_INTR_STATE_STI 0x0000
411 #define GUEST_INTR_STATE_MOV_SS 0x0000
412 #define GUEST_INTR_STATE_SMI 0x0000
413 #define GUEST_INTR_STATE_NMI 0x0000
414 #define GUEST_INTR_STATE_ENCLAVE_INTR 0x0000
415
416 /* GUEST_ACTIVITY_STATE flags */
417 #define GUEST_ACTIVITY_ACTIVE 0
418 #define GUEST_ACTIVITY_HLT 1
419 #define GUEST_ACTIVITY_SHUTDOWN 2
420 #define GUEST_ACTIVITY_WAIT_SIPI 3
421
422 /*
423 * Exit Qualifications for MOV for Control Reg
424 */
425 #define CONTROL_REG_ACCESS_NUM 0x7
426 #define CONTROL_REG_ACCESS_TYPE 0x30
427 #define CONTROL_REG_ACCESS_REG 0xf00
428 #define LMSW_SOURCE_DATA_SHIFT 16
429 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOUR
430 #define REG_EAX (0 <<
431 #define REG_ECX (1 <<
432 #define REG_EDX (2 <<
433 #define REG_EBX (3 <<
434 #define REG_ESP (4 <<
435 #define REG_EBP (5 <<
436 #define REG_ESI (6 <<
437 #define REG_EDI (7 <<
438 #define REG_R8 (8 << 8
439 #define REG_R9 (9 << 8
440 #define REG_R10 (10 <<
441 #define REG_R11 (11 <<
442 #define REG_R12 (12 <<
443 #define REG_R13 (13 <<
444 #define REG_R14 (14 <<
445 #define REG_R15 (15 <<
446
447 /*
448 * Exit Qualifications for MOV for Debug Regis
449 */
450 #define DEBUG_REG_ACCESS_NUM 0x7
451 #define DEBUG_REG_ACCESS_TYPE 0x10
452 #define TYPE_MOV_TO_DR (0 <<
453 #define TYPE_MOV_FROM_DR (1 <<
454 #define DEBUG_REG_ACCESS_REG(eq) (((eq)
455
456
457 /*
458 * Exit Qualifications for APIC-Access
459 */
460 #define APIC_ACCESS_OFFSET 0xfff
461 #define APIC_ACCESS_TYPE 0xf000
462 #define TYPE_LINEAR_APIC_INST_READ (0 <<
463 #define TYPE_LINEAR_APIC_INST_WRITE (1 <<
464 #define TYPE_LINEAR_APIC_INST_FETCH (2 <<
465 #define TYPE_LINEAR_APIC_EVENT (3 <<
466 #define TYPE_PHYSICAL_APIC_EVENT (10 <<
467 #define TYPE_PHYSICAL_APIC_INST (15 <<
468
469 /* segment AR in VMCS -- these are different f
470 #define VMX_SEGMENT_AR_L_MASK (1 << 13)
471
472 #define VMX_AR_TYPE_ACCESSES_MASK 1
473 #define VMX_AR_TYPE_READABLE_MASK (1 << 1)
474 #define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
475 #define VMX_AR_TYPE_CODE_MASK (1 << 3)
476 #define VMX_AR_TYPE_MASK 0x0f
477 #define VMX_AR_TYPE_BUSY_64_TSS 11
478 #define VMX_AR_TYPE_BUSY_32_TSS 11
479 #define VMX_AR_TYPE_BUSY_16_TSS 3
480 #define VMX_AR_TYPE_LDT 2
481
482 #define VMX_AR_UNUSABLE_MASK (1 << 16)
483 #define VMX_AR_S_MASK (1 << 4)
484 #define VMX_AR_P_MASK (1 << 7)
485 #define VMX_AR_L_MASK (1 << 13)
486 #define VMX_AR_DB_MASK (1 << 14)
487 #define VMX_AR_G_MASK (1 << 15)
488 #define VMX_AR_DPL_SHIFT 5
489 #define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SH
490
491 #define VMX_AR_RESERVD_MASK 0xfffe0f00
492
493 #define TSS_PRIVATE_MEMSLOT
494 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
495 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
496
497 #define VMX_NR_VPIDS
498 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR
499 #define VMX_VPID_EXTENT_SINGLE_CONTEXT
500 #define VMX_VPID_EXTENT_ALL_CONTEXT
501 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
502
503 #define VMX_EPT_EXTENT_CONTEXT
504 #define VMX_EPT_EXTENT_GLOBAL
505 #define VMX_EPT_EXTENT_SHIFT
506
507 #define VMX_EPT_EXECUTE_ONLY_BIT
508 #define VMX_EPT_PAGE_WALK_4_BIT
509 #define VMX_EPT_PAGE_WALK_5_BIT
510 #define VMX_EPTP_UC_BIT
511 #define VMX_EPTP_WB_BIT
512 #define VMX_EPT_2MB_PAGE_BIT
513 #define VMX_EPT_1GB_PAGE_BIT
514 #define VMX_EPT_INVEPT_BIT
515 #define VMX_EPT_AD_BIT
516 #define VMX_EPT_EXTENT_CONTEXT_BIT
517 #define VMX_EPT_EXTENT_GLOBAL_BIT
518
519 #define VMX_VPID_INVVPID_BIT
520 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT
521 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
522 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
523 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT
524
525 #define VMX_EPT_MT_EPTE_SHIFT
526 #define VMX_EPTP_PWL_MASK
527 #define VMX_EPTP_PWL_4
528 #define VMX_EPTP_PWL_5
529 #define VMX_EPTP_AD_ENABLE_BIT
530 /* The EPTP memtype is encoded in bits 2:0, i.
531 #define VMX_EPTP_MT_MASK
532 #define VMX_EPTP_MT_WB
533 #define VMX_EPTP_MT_UC
534 #define VMX_EPT_READABLE_MASK
535 #define VMX_EPT_WRITABLE_MASK
536 #define VMX_EPT_EXECUTABLE_MASK
537 #define VMX_EPT_IPAT_BIT
538 #define VMX_EPT_ACCESS_BIT
539 #define VMX_EPT_DIRTY_BIT
540 #define VMX_EPT_SUPPRESS_VE_BIT
541 #define VMX_EPT_RWX_MASK
542
543
544 #define VMX_EPT_MT_MASK
545
546 static inline u8 vmx_eptp_page_walk_level(u64
547 {
548 u64 encoded_level = eptp & VMX_EPTP_PW
549
550 if (encoded_level == VMX_EPTP_PWL_5)
551 return 5;
552
553 /* @eptp must be pre-validated by the
554 WARN_ON_ONCE(encoded_level != VMX_EPTP
555 return 4;
556 }
557
558 /* The mask to use to trigger an EPT Misconfig
559 #define VMX_EPT_MISCONFIG_WX_VALUE
560
561
562 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR
563
564 struct vmx_msr_entry {
565 u32 index;
566 u32 reserved;
567 u64 value;
568 } __aligned(16);
569
570 /*
571 * Exit Qualifications for entry failure durin
572 */
573 enum vm_entry_failure_code {
574 ENTRY_FAIL_DEFAULT = 0,
575 ENTRY_FAIL_PDPTE = 2,
576 ENTRY_FAIL_NMI = 3,
577 ENTRY_FAIL_VMCS_LINK_PTR = 4,
578 };
579
580 /*
581 * Exit Qualifications for EPT Violations
582 */
583 #define EPT_VIOLATION_ACC_READ_BIT 0
584 #define EPT_VIOLATION_ACC_WRITE_BIT 1
585 #define EPT_VIOLATION_ACC_INSTR_BIT 2
586 #define EPT_VIOLATION_RWX_SHIFT 3
587 #define EPT_VIOLATION_GVA_IS_VALID_BIT 7
588 #define EPT_VIOLATION_GVA_TRANSLATED_BIT 8
589 #define EPT_VIOLATION_ACC_READ (1 <<
590 #define EPT_VIOLATION_ACC_WRITE (1 <<
591 #define EPT_VIOLATION_ACC_INSTR (1 <<
592 #define EPT_VIOLATION_RWX_MASK (VMX_E
593 #define EPT_VIOLATION_GVA_IS_VALID (1 <<
594 #define EPT_VIOLATION_GVA_TRANSLATED (1 <<
595
596 /*
597 * Exit Qualifications for NOTIFY VM EXIT
598 */
599 #define NOTIFY_VM_CONTEXT_INVALID BIT(0)
600
601 /*
602 * VM-instruction error numbers
603 */
604 enum vm_instruction_error_number {
605 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION =
606 VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
607 VMXERR_VMCLEAR_VMXON_POINTER = 3,
608 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
609 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
610 VMXERR_VMRESUME_AFTER_VMXOFF = 6,
611 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7
612 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
613 VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
614 VMXERR_VMPTRLD_VMXON_POINTER = 10,
615 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION
616 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12
617 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONEN
618 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 1
619 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_PO
620 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMC
621 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NO
622 VMXERR_VMCALL_NONCLEAR_VMCS = 19,
623 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_
624 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_
625 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREAT
626 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEAT
627 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONT
628 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
629 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVP
630 };
631
632 /*
633 * VM-instruction errors that can be encounter
634 * nested VM-Enter failures reported by hardwa
635 * from a SMI Transfer Monitor are not include
636 * sideways if we get one of those...
637 */
638 #define VMX_VMENTER_INSTRUCTION_ERRORS \
639 { VMXERR_VMLAUNCH_NONCLEAR_VMCS,
640 { VMXERR_VMRESUME_NONLAUNCHED_VMCS,
641 { VMXERR_VMRESUME_AFTER_VMXOFF,
642 { VMXERR_ENTRY_INVALID_CONTROL_FIELD,
643 { VMXERR_ENTRY_INVALID_HOST_STATE_FIEL
644 { VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_S
645
646 enum vmx_l1d_flush_state {
647 VMENTER_L1D_FLUSH_AUTO,
648 VMENTER_L1D_FLUSH_NEVER,
649 VMENTER_L1D_FLUSH_COND,
650 VMENTER_L1D_FLUSH_ALWAYS,
651 VMENTER_L1D_FLUSH_EPT_DISABLED,
652 VMENTER_L1D_FLUSH_NOT_REQUIRED,
653 };
654
655 extern enum vmx_l1d_flush_state l1tf_vmx_mitig
656
657 struct vmx_ve_information {
658 u32 exit_reason;
659 u32 delivery;
660 u64 exit_qualification;
661 u64 guest_linear_address;
662 u64 guest_physical_address;
663 u16 eptp_index;
664 };
665
666 #endif
667
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