1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 #ifndef _ASM_X86_PERF_REGS_H !! 2 #ifndef _ASM_MIPS_PERF_REGS_H
3 #define _ASM_X86_PERF_REGS_H !! 3 #define _ASM_MIPS_PERF_REGS_H
4 4
5 enum perf_event_x86_regs { !! 5 enum perf_event_mips_regs {
6 PERF_REG_X86_AX, !! 6 PERF_REG_MIPS_PC,
7 PERF_REG_X86_BX, !! 7 PERF_REG_MIPS_R1,
8 PERF_REG_X86_CX, !! 8 PERF_REG_MIPS_R2,
9 PERF_REG_X86_DX, !! 9 PERF_REG_MIPS_R3,
10 PERF_REG_X86_SI, !! 10 PERF_REG_MIPS_R4,
11 PERF_REG_X86_DI, !! 11 PERF_REG_MIPS_R5,
12 PERF_REG_X86_BP, !! 12 PERF_REG_MIPS_R6,
13 PERF_REG_X86_SP, !! 13 PERF_REG_MIPS_R7,
14 PERF_REG_X86_IP, !! 14 PERF_REG_MIPS_R8,
15 PERF_REG_X86_FLAGS, !! 15 PERF_REG_MIPS_R9,
16 PERF_REG_X86_CS, !! 16 PERF_REG_MIPS_R10,
17 PERF_REG_X86_SS, !! 17 PERF_REG_MIPS_R11,
18 PERF_REG_X86_DS, !! 18 PERF_REG_MIPS_R12,
19 PERF_REG_X86_ES, !! 19 PERF_REG_MIPS_R13,
20 PERF_REG_X86_FS, !! 20 PERF_REG_MIPS_R14,
21 PERF_REG_X86_GS, !! 21 PERF_REG_MIPS_R15,
22 PERF_REG_X86_R8, !! 22 PERF_REG_MIPS_R16,
23 PERF_REG_X86_R9, !! 23 PERF_REG_MIPS_R17,
24 PERF_REG_X86_R10, !! 24 PERF_REG_MIPS_R18,
25 PERF_REG_X86_R11, !! 25 PERF_REG_MIPS_R19,
26 PERF_REG_X86_R12, !! 26 PERF_REG_MIPS_R20,
27 PERF_REG_X86_R13, !! 27 PERF_REG_MIPS_R21,
28 PERF_REG_X86_R14, !! 28 PERF_REG_MIPS_R22,
29 PERF_REG_X86_R15, !! 29 PERF_REG_MIPS_R23,
30 /* These are the limits for the GPRs. !! 30 PERF_REG_MIPS_R24,
31 PERF_REG_X86_32_MAX = PERF_REG_X86_GS !! 31 PERF_REG_MIPS_R25,
32 PERF_REG_X86_64_MAX = PERF_REG_X86_R15 !! 32 PERF_REG_MIPS_R26,
33 !! 33 PERF_REG_MIPS_R27,
34 /* These all need two bits set because !! 34 PERF_REG_MIPS_R28,
35 PERF_REG_X86_XMM0 = 32, !! 35 PERF_REG_MIPS_R29,
36 PERF_REG_X86_XMM1 = 34, !! 36 PERF_REG_MIPS_R30,
37 PERF_REG_X86_XMM2 = 36, !! 37 PERF_REG_MIPS_R31,
38 PERF_REG_X86_XMM3 = 38, !! 38 PERF_REG_MIPS_MAX = PERF_REG_MIPS_R31 + 1,
39 PERF_REG_X86_XMM4 = 40, <<
40 PERF_REG_X86_XMM5 = 42, <<
41 PERF_REG_X86_XMM6 = 44, <<
42 PERF_REG_X86_XMM7 = 46, <<
43 PERF_REG_X86_XMM8 = 48, <<
44 PERF_REG_X86_XMM9 = 50, <<
45 PERF_REG_X86_XMM10 = 52, <<
46 PERF_REG_X86_XMM11 = 54, <<
47 PERF_REG_X86_XMM12 = 56, <<
48 PERF_REG_X86_XMM13 = 58, <<
49 PERF_REG_X86_XMM14 = 60, <<
50 PERF_REG_X86_XMM15 = 62, <<
51 <<
52 /* These include both GPRs and XMMX re <<
53 PERF_REG_X86_XMM_MAX = PERF_REG_X86_XM <<
54 }; 39 };
55 !! 40 #endif /* _ASM_MIPS_PERF_REGS_H */
56 #define PERF_REG_EXTENDED_MASK (~((1ULL << PE <<
57 <<
58 #endif /* _ASM_X86_PERF_REGS_H */ <<
59 41
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