1 // SPDX-License-Identifier: GPL-2.0-or-later 1
2 /*
3 * Intel SMP support routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@l
6 * (c) 1998-99, 2000, 2009 Ingo Molnar <m
7 * (c) 2002,2003 Andi Kleen, SuSE Labs.
8 *
9 * i386 and x86_64 integration by Glauber
10 */
11
12 #include <linux/init.h>
13
14 #include <linux/mm.h>
15 #include <linux/delay.h>
16 #include <linux/spinlock.h>
17 #include <linux/export.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/cache.h>
21 #include <linux/interrupt.h>
22 #include <linux/cpu.h>
23 #include <linux/gfp.h>
24 #include <linux/kexec.h>
25
26 #include <asm/mtrr.h>
27 #include <asm/tlbflush.h>
28 #include <asm/mmu_context.h>
29 #include <asm/proto.h>
30 #include <asm/apic.h>
31 #include <asm/cpu.h>
32 #include <asm/idtentry.h>
33 #include <asm/nmi.h>
34 #include <asm/mce.h>
35 #include <asm/trace/irq_vectors.h>
36 #include <asm/kexec.h>
37 #include <asm/reboot.h>
38
39 /*
40 * Some notes on x86 processor bugs affec
41 *
42 * Pentium, Pentium Pro, II, III (and all
43 * The Linux implications for SMP are han
44 *
45 * Pentium III / [Xeon]
46 * None of the E1AP-E3AP errata a
47 *
48 * E1AP. see PII A1AP
49 * E2AP. see PII A2AP
50 * E3AP. see PII A3AP
51 *
52 * Pentium II / [Xeon]
53 * None of the A1AP-A3AP errata a
54 *
55 * A1AP. see PPro 1AP
56 * A2AP. see PPro 2AP
57 * A3AP. see PPro 7AP
58 *
59 * Pentium Pro
60 * None of 1AP-9AP errata are vis
61 * except occasional delivery of 'spuriou
62 * This is very rare and a non-problem.
63 *
64 * 1AP. Linux maps APIC as non-cacheab
65 * 2AP. worked around in hardware
66 * 3AP. fixed in C0 and above stepping
67 * Linux does not use excessive S
68 * 4AP. worked around in hardware
69 * 5AP. symmetric IO mode (normal Linu
70 * 'noapic' mode has vector 0xf f
71 * 6AP. 'noapic' mode might be affecte
72 * 7AP. We do not assume writes to the
73 * 8AP. We do not enable low power mod
74 * 9AP. We do not use mixed mode
75 *
76 * Pentium
77 * There is a marginal case where
78 * machines with B stepping processors ca
79 * an L1cache=Writethrough or L1cache=off
80 *
81 * B stepping CPUs may hang. Ther
82 * for this. We warn about it in case you
83 * arounds. Basically that's so I can tel
84 * CPU and SMP problems "tough".
85 *
86 * Specific items [From Pentium Processor
87 *
88 * 1AP. Linux doesn't use remote read
89 * 2AP. Linux doesn't trust APIC error
90 * 3AP. We work around this
91 * 4AP. Linux never generated 3 interr
92 * to cause a lost local interrup
93 * 5AP. Remote read is never used
94 * 6AP. not affected - worked around i
95 * 7AP. not affected - worked around i
96 * 8AP. worked around in hardware - we
97 * 9AP. only 'noapic' mode affected. M
98 * interrupts, we log only the fi
99 * rest silently.
100 * 10AP. not affected - worked around i
101 * 11AP. Linux reads the APIC between w
102 * the documentation. Make sure y
103 * the C stepping chips too.
104 * 12AP. not affected - worked around i
105 * 13AP. not affected - worked around i
106 * 14AP. we always deassert INIT during
107 * 15AP. not affected - worked around i
108 * 16AP. not affected - worked around i
109 * 17AP. not affected - worked around i
110 * 18AP. not affected - worked around i
111 * 19AP. not affected - worked around i
112 *
113 * If this sounds worrying believe me the
114 * or are signal timing bugs worked aroun
115 * about nothing of note with C stepping
116 */
117
118 static atomic_t stopping_cpu = ATOMIC_INIT(-1)
119 static bool smp_no_nmi_ipi = false;
120
121 static int smp_stop_nmi_callback(unsigned int
122 {
123 /* We are registered on stopping cpu t
124 if (raw_smp_processor_id() == atomic_r
125 return NMI_HANDLED;
126
127 cpu_emergency_disable_virtualization()
128 stop_this_cpu(NULL);
129
130 return NMI_HANDLED;
131 }
132
133 /*
134 * this function calls the 'stop' function on
135 */
136 DEFINE_IDTENTRY_SYSVEC(sysvec_reboot)
137 {
138 apic_eoi();
139 cpu_emergency_disable_virtualization()
140 stop_this_cpu(NULL);
141 }
142
143 static int register_stop_handler(void)
144 {
145 return register_nmi_handler(NMI_LOCAL,
146 NMI_FLAG_F
147 }
148
149 static void native_stop_other_cpus(int wait)
150 {
151 unsigned int old_cpu, this_cpu;
152 unsigned long flags, timeout;
153
154 if (reboot_force)
155 return;
156
157 /* Only proceed if this is the first C
158 old_cpu = -1;
159 this_cpu = smp_processor_id();
160 if (!atomic_try_cmpxchg(&stopping_cpu,
161 return;
162
163 /* For kexec, ensure that offline CPUs
164 if (kexec_in_progress)
165 smp_kick_mwait_play_dead();
166
167 /*
168 * 1) Send an IPI on the reboot vector
169 *
170 * The other CPUs should react on i
171 * sections and re-enabling interru
172 * locks, but there is nothing whic
173 *
174 * 2) Wait for all other CPUs to repor
175 * HLT loop in stop_this_cpu()
176 *
177 * 3) If #2 timed out send an NMI to t
178 * yet report
179 *
180 * 4) Wait for all other CPUs to repor
181 * HLT loop in stop_this_cpu()
182 *
183 * #3 can obviously race against a CPU
184 * That CPU will have reported already
185 * reached HLT" condition will be true
186 * other CPU is still handling the NMI
187 * protection against that as "disable
188 * NMIs.
189 */
190 cpumask_copy(&cpus_stop_mask, cpu_onli
191 cpumask_clear_cpu(this_cpu, &cpus_stop
192
193 if (!cpumask_empty(&cpus_stop_mask)) {
194 apic_send_IPI_allbutself(REBOO
195
196 /*
197 * Don't wait longer than a se
198 * wait request is not checked
199 * prevent an NMI shutdown att
200 * CPUs reach shutdown state.
201 */
202 timeout = USEC_PER_SEC;
203 while (!cpumask_empty(&cpus_st
204 udelay(1);
205 }
206
207 /* if the REBOOT_VECTOR didn't work, t
208 if (!cpumask_empty(&cpus_stop_mask)) {
209 /*
210 * If NMI IPI is enabled, try
211 * and send the IPI. In any ca
212 * CPUs to stop.
213 */
214 if (!smp_no_nmi_ipi && !regist
215 unsigned int cpu;
216
217 pr_emerg("Shutting dow
218
219 for_each_cpu(cpu, &cpu
220 __apic_send_IP
221 }
222 /*
223 * Don't wait longer than 10 m
224 * request it. If wait is true
225 * one or more CPUs do not rea
226 */
227 timeout = USEC_PER_MSEC * 10;
228 while (!cpumask_empty(&cpus_st
229 udelay(1);
230 }
231
232 local_irq_save(flags);
233 disable_local_APIC();
234 mcheck_cpu_clear(this_cpu_ptr(&cpu_inf
235 local_irq_restore(flags);
236
237 /*
238 * Ensure that the cpus_stop_mask cach
239 * the other CPUs. See comment vs. SME
240 */
241 cpumask_clear(&cpus_stop_mask);
242 }
243
244 /*
245 * Reschedule call back. KVM uses this interru
246 * guest mode.
247 */
248 DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_reschedul
249 {
250 apic_eoi();
251 trace_reschedule_entry(RESCHEDULE_VECT
252 inc_irq_stat(irq_resched_count);
253 scheduler_ipi();
254 trace_reschedule_exit(RESCHEDULE_VECTO
255 }
256
257 DEFINE_IDTENTRY_SYSVEC(sysvec_call_function)
258 {
259 apic_eoi();
260 trace_call_function_entry(CALL_FUNCTIO
261 inc_irq_stat(irq_call_count);
262 generic_smp_call_function_interrupt();
263 trace_call_function_exit(CALL_FUNCTION
264 }
265
266 DEFINE_IDTENTRY_SYSVEC(sysvec_call_function_si
267 {
268 apic_eoi();
269 trace_call_function_single_entry(CALL_
270 inc_irq_stat(irq_call_count);
271 generic_smp_call_function_single_inter
272 trace_call_function_single_exit(CALL_F
273 }
274
275 static int __init nonmi_ipi_setup(char *str)
276 {
277 smp_no_nmi_ipi = true;
278 return 1;
279 }
280
281 __setup("nonmi_ipi", nonmi_ipi_setup);
282
283 struct smp_ops smp_ops = {
284 .smp_prepare_boot_cpu = native_smp_p
285 .smp_prepare_cpus = native_smp_p
286 .smp_cpus_done = native_smp_c
287
288 .stop_other_cpus = native_stop_
289 #if defined(CONFIG_CRASH_DUMP)
290 .crash_stop_other_cpus = kdump_nmi_sh
291 #endif
292 .smp_send_reschedule = native_smp_s
293
294 .kick_ap_alive = native_kick_
295 .cpu_disable = native_cpu_d
296 .play_dead = native_play_
297
298 .send_call_func_ipi = native_send_
299 .send_call_func_single_ipi = native_se
300 };
301 EXPORT_SYMBOL_GPL(smp_ops);
302
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.