1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 config XTENSA !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ARCH_32BIT_OFF_T !! 4 default y
5 select ARCH_HAS_CPU_CACHE_ALIASING !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_HAS_BINFMT_FLAT if !MMU !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CURRENT_STACK_POINTER !! 7 select ARCH_CLOCKSOURCE_DATA
8 select ARCH_HAS_DEBUG_VM_PGTABLE !! 8 select ARCH_DISCARD_MEMBLOCK
9 select ARCH_HAS_DMA_PREP_COHERENT if M !! 9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_GCOV_PROFILE_ALL !! 10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_HAS_KCOV !! 11 select ARCH_HAS_UBSAN_SANITIZE_ALL
12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MM !! 12 select ARCH_SUPPORTS_UPROBES
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if !! 13 select ARCH_USE_BUILTIN_BSWAP
14 select ARCH_HAS_DMA_SET_UNCACHED if MM !! 14 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
15 select ARCH_HAS_STRNCPY_FROM_USER if ! <<
16 select ARCH_HAS_STRNLEN_USER <<
17 select ARCH_NEED_CMPXCHG_1_EMU <<
18 select ARCH_USE_MEMTEST <<
19 select ARCH_USE_QUEUED_RWLOCKS 15 select ARCH_USE_QUEUED_RWLOCKS
20 select ARCH_USE_QUEUED_SPINLOCKS 16 select ARCH_USE_QUEUED_SPINLOCKS
21 select ARCH_WANT_IPC_PARSE_VERSION 17 select ARCH_WANT_IPC_PARSE_VERSION
22 select BUILDTIME_TABLE_SORT !! 18 select BUILDTIME_EXTABLE_SORT
23 select CLONE_BACKWARDS 19 select CLONE_BACKWARDS
24 select COMMON_CLK !! 20 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
25 select DMA_NONCOHERENT_MMAP if MMU !! 21 select CPU_PM if CPU_IDLE
26 select GENERIC_ATOMIC64 !! 22 select GENERIC_ATOMIC64 if !64BIT
>> 23 select GENERIC_CLOCKEVENTS
>> 24 select GENERIC_CMOS_UPDATE
>> 25 select GENERIC_CPU_AUTOPROBE
>> 26 select GENERIC_IOMAP
>> 27 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW 28 select GENERIC_IRQ_SHOW
>> 29 select GENERIC_ISA_DMA if EISA
>> 30 select GENERIC_LIB_ASHLDI3
>> 31 select GENERIC_LIB_ASHRDI3
28 select GENERIC_LIB_CMPDI2 32 select GENERIC_LIB_CMPDI2
29 select GENERIC_LIB_MULDI3 !! 33 select GENERIC_LIB_LSHRDI3
30 select GENERIC_LIB_UCMPDI2 34 select GENERIC_LIB_UCMPDI2
31 select GENERIC_PCI_IOMAP !! 35 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
32 select GENERIC_SCHED_CLOCK !! 36 select GENERIC_SMP_IDLE_THREAD
33 select GENERIC_IOREMAP if MMU !! 37 select GENERIC_TIME_VSYSCALL
34 select HAVE_ARCH_AUDITSYSCALL !! 38 select HANDLE_DOMAIN_IRQ
35 select HAVE_ARCH_JUMP_LABEL if !XIP_KE !! 39 select HAVE_ARCH_COMPILER_H
36 select HAVE_ARCH_KASAN if MMU && !XIP_ !! 40 select HAVE_ARCH_JUMP_LABEL
37 select HAVE_ARCH_KCSAN !! 41 select HAVE_ARCH_KGDB
>> 42 select HAVE_ARCH_MMAP_RND_BITS if MMU
>> 43 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
38 select HAVE_ARCH_SECCOMP_FILTER 44 select HAVE_ARCH_SECCOMP_FILTER
39 select HAVE_ARCH_TRACEHOOK 45 select HAVE_ARCH_TRACEHOOK
40 select HAVE_ASM_MODVERSIONS !! 46 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
41 select HAVE_CONTEXT_TRACKING_USER !! 47 select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
>> 48 select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
>> 49 select HAVE_CONTEXT_TRACKING
>> 50 select HAVE_COPY_THREAD_TLS
>> 51 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK 52 select HAVE_DEBUG_KMEMLEAK
>> 53 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_DMA_CONTIGUOUS 54 select HAVE_DMA_CONTIGUOUS
>> 55 select HAVE_DYNAMIC_FTRACE
44 select HAVE_EXIT_THREAD 56 select HAVE_EXIT_THREAD
>> 57 select HAVE_FTRACE_MCOUNT_RECORD
>> 58 select HAVE_FUNCTION_GRAPH_TRACER
45 select HAVE_FUNCTION_TRACER 59 select HAVE_FUNCTION_TRACER
46 select HAVE_GCC_PLUGINS if GCC_VERSION !! 60 select HAVE_IDE
47 select HAVE_HW_BREAKPOINT if PERF_EVEN !! 61 select HAVE_IOREMAP_PROT
>> 62 select HAVE_IRQ_EXIT_ON_IRQ_STACK
48 select HAVE_IRQ_TIME_ACCOUNTING 63 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_PAGE_SIZE_4KB !! 64 select HAVE_KPROBES
50 select HAVE_PCI !! 65 select HAVE_KRETPROBES
>> 66 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 67 select HAVE_MEMBLOCK_NODE_MAP
>> 68 select HAVE_MOD_ARCH_SPECIFIC
>> 69 select HAVE_NMI
>> 70 select HAVE_OPROFILE
51 select HAVE_PERF_EVENTS 71 select HAVE_PERF_EVENTS
>> 72 select HAVE_REGS_AND_STACK_ACCESS_API
>> 73 select HAVE_RSEQ
52 select HAVE_STACKPROTECTOR 74 select HAVE_STACKPROTECTOR
53 select HAVE_SYSCALL_TRACEPOINTS 75 select HAVE_SYSCALL_TRACEPOINTS
54 select HAVE_VIRT_CPU_ACCOUNTING_GEN !! 76 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
55 select IRQ_DOMAIN !! 77 select IRQ_FORCED_THREADING
56 select LOCK_MM_AND_FIND_VMA !! 78 select ISA if EISA
57 select MODULES_USE_ELF_RELA !! 79 select MODULES_USE_ELF_RELA if MODULES && 64BIT
>> 80 select MODULES_USE_ELF_REL if MODULES
58 select PERF_USE_VMALLOC 81 select PERF_USE_VMALLOC
59 select TRACE_IRQFLAGS_SUPPORT !! 82 select RTC_LIB
>> 83 select SYSCTL_EXCEPTION_TRACE
>> 84 select VIRT_TO_BUS
>> 85
>> 86 menu "Machine selection"
>> 87
>> 88 choice
>> 89 prompt "System type"
>> 90 default MIPS_GENERIC
>> 91
>> 92 config MIPS_GENERIC
>> 93 bool "Generic board-agnostic MIPS kernel"
>> 94 select BOOT_RAW
>> 95 select BUILTIN_DTB
>> 96 select CEVT_R4K
>> 97 select CLKSRC_MIPS_GIC
>> 98 select COMMON_CLK
>> 99 select CPU_MIPSR2_IRQ_VI
>> 100 select CPU_MIPSR2_IRQ_EI
>> 101 select CSRC_R4K
>> 102 select DMA_PERDEV_COHERENT
>> 103 select HAVE_PCI
>> 104 select IRQ_MIPS_CPU
>> 105 select LIBFDT
>> 106 select MIPS_AUTO_PFN_OFFSET
>> 107 select MIPS_CPU_SCACHE
>> 108 select MIPS_GIC
>> 109 select MIPS_L1_CACHE_SHIFT_7
>> 110 select NO_EXCEPT_FILL
>> 111 select PCI_DRIVERS_GENERIC
>> 112 select PINCTRL
>> 113 select SMP_UP if SMP
>> 114 select SWAP_IO_SPACE
>> 115 select SYS_HAS_CPU_MIPS32_R1
>> 116 select SYS_HAS_CPU_MIPS32_R2
>> 117 select SYS_HAS_CPU_MIPS32_R6
>> 118 select SYS_HAS_CPU_MIPS64_R1
>> 119 select SYS_HAS_CPU_MIPS64_R2
>> 120 select SYS_HAS_CPU_MIPS64_R6
>> 121 select SYS_SUPPORTS_32BIT_KERNEL
>> 122 select SYS_SUPPORTS_64BIT_KERNEL
>> 123 select SYS_SUPPORTS_BIG_ENDIAN
>> 124 select SYS_SUPPORTS_HIGHMEM
>> 125 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 126 select SYS_SUPPORTS_MICROMIPS
>> 127 select SYS_SUPPORTS_MIPS_CPS
>> 128 select SYS_SUPPORTS_MIPS16
>> 129 select SYS_SUPPORTS_MULTITHREADING
>> 130 select SYS_SUPPORTS_RELOCATABLE
>> 131 select SYS_SUPPORTS_SMARTMIPS
>> 132 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 133 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 134 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 135 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 136 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 137 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 138 select USE_OF
>> 139 select UHI_BOOT
>> 140 help
>> 141 Select this to build a kernel which aims to support multiple boards,
>> 142 generally using a flattened device tree passed from the bootloader
>> 143 using the boot protocol defined in the UHI (Unified Hosting
>> 144 Interface) specification.
>> 145
>> 146 config MIPS_ALCHEMY
>> 147 bool "Alchemy processor based machines"
>> 148 select PHYS_ADDR_T_64BIT
>> 149 select CEVT_R4K
>> 150 select CSRC_R4K
>> 151 select IRQ_MIPS_CPU
>> 152 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 153 select SYS_HAS_CPU_MIPS32_R1
>> 154 select SYS_SUPPORTS_32BIT_KERNEL
>> 155 select SYS_SUPPORTS_APM_EMULATION
>> 156 select GPIOLIB
>> 157 select SYS_SUPPORTS_ZBOOT
>> 158 select COMMON_CLK
>> 159
>> 160 config AR7
>> 161 bool "Texas Instruments AR7"
>> 162 select BOOT_ELF32
>> 163 select DMA_NONCOHERENT
>> 164 select CEVT_R4K
>> 165 select CSRC_R4K
>> 166 select IRQ_MIPS_CPU
>> 167 select NO_EXCEPT_FILL
>> 168 select SWAP_IO_SPACE
>> 169 select SYS_HAS_CPU_MIPS32_R1
>> 170 select SYS_HAS_EARLY_PRINTK
>> 171 select SYS_SUPPORTS_32BIT_KERNEL
>> 172 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 173 select SYS_SUPPORTS_MIPS16
>> 174 select SYS_SUPPORTS_ZBOOT_UART16550
>> 175 select GPIOLIB
>> 176 select VLYNQ
>> 177 select HAVE_CLK
>> 178 help
>> 179 Support for the Texas Instruments AR7 System-on-a-Chip
>> 180 family: TNETD7100, 7200 and 7300.
>> 181
>> 182 config ATH25
>> 183 bool "Atheros AR231x/AR531x SoC support"
>> 184 select CEVT_R4K
>> 185 select CSRC_R4K
>> 186 select DMA_NONCOHERENT
>> 187 select IRQ_MIPS_CPU
>> 188 select IRQ_DOMAIN
>> 189 select SYS_HAS_CPU_MIPS32_R1
>> 190 select SYS_SUPPORTS_BIG_ENDIAN
>> 191 select SYS_SUPPORTS_32BIT_KERNEL
>> 192 select SYS_HAS_EARLY_PRINTK
>> 193 help
>> 194 Support for Atheros AR231x and Atheros AR531x based boards
>> 195
>> 196 config ATH79
>> 197 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 198 select ARCH_HAS_RESET_CONTROLLER
>> 199 select BOOT_RAW
>> 200 select CEVT_R4K
>> 201 select CSRC_R4K
>> 202 select DMA_NONCOHERENT
>> 203 select GPIOLIB
>> 204 select PINCTRL
>> 205 select HAVE_CLK
>> 206 select COMMON_CLK
>> 207 select CLKDEV_LOOKUP
>> 208 select IRQ_MIPS_CPU
>> 209 select SYS_HAS_CPU_MIPS32_R2
>> 210 select SYS_HAS_EARLY_PRINTK
>> 211 select SYS_SUPPORTS_32BIT_KERNEL
>> 212 select SYS_SUPPORTS_BIG_ENDIAN
>> 213 select SYS_SUPPORTS_MIPS16
>> 214 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 215 select USE_OF
>> 216 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 217 help
>> 218 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 219
>> 220 config BMIPS_GENERIC
>> 221 bool "Broadcom Generic BMIPS kernel"
>> 222 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 223 select ARCH_HAS_PHYS_TO_DMA
>> 224 select BOOT_RAW
>> 225 select NO_EXCEPT_FILL
>> 226 select USE_OF
>> 227 select CEVT_R4K
>> 228 select CSRC_R4K
>> 229 select SYNC_R4K
>> 230 select COMMON_CLK
>> 231 select BCM6345_L1_IRQ
>> 232 select BCM7038_L1_IRQ
>> 233 select BCM7120_L2_IRQ
>> 234 select BRCMSTB_L2_IRQ
>> 235 select IRQ_MIPS_CPU
>> 236 select DMA_NONCOHERENT
>> 237 select SYS_SUPPORTS_32BIT_KERNEL
>> 238 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 239 select SYS_SUPPORTS_BIG_ENDIAN
>> 240 select SYS_SUPPORTS_HIGHMEM
>> 241 select SYS_HAS_CPU_BMIPS32_3300
>> 242 select SYS_HAS_CPU_BMIPS4350
>> 243 select SYS_HAS_CPU_BMIPS4380
>> 244 select SYS_HAS_CPU_BMIPS5000
>> 245 select SWAP_IO_SPACE
>> 246 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 247 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 248 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 249 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 250 select HARDIRQS_SW_RESEND
>> 251 help
>> 252 Build a generic DT-based kernel image that boots on select
>> 253 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 254 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 255 must be set appropriately for your board.
>> 256
>> 257 config BCM47XX
>> 258 bool "Broadcom BCM47XX based boards"
>> 259 select BOOT_RAW
>> 260 select CEVT_R4K
>> 261 select CSRC_R4K
>> 262 select DMA_NONCOHERENT
>> 263 select HAVE_PCI
>> 264 select IRQ_MIPS_CPU
>> 265 select SYS_HAS_CPU_MIPS32_R1
>> 266 select NO_EXCEPT_FILL
>> 267 select SYS_SUPPORTS_32BIT_KERNEL
>> 268 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 269 select SYS_SUPPORTS_MIPS16
>> 270 select SYS_SUPPORTS_ZBOOT
>> 271 select SYS_HAS_EARLY_PRINTK
>> 272 select USE_GENERIC_EARLY_PRINTK_8250
>> 273 select GPIOLIB
>> 274 select LEDS_GPIO_REGISTER
>> 275 select BCM47XX_NVRAM
>> 276 select BCM47XX_SPROM
>> 277 select BCM47XX_SSB if !BCM47XX_BCMA
>> 278 help
>> 279 Support for BCM47XX based boards
>> 280
>> 281 config BCM63XX
>> 282 bool "Broadcom BCM63XX based boards"
>> 283 select BOOT_RAW
>> 284 select CEVT_R4K
>> 285 select CSRC_R4K
>> 286 select SYNC_R4K
>> 287 select DMA_NONCOHERENT
>> 288 select IRQ_MIPS_CPU
>> 289 select SYS_SUPPORTS_32BIT_KERNEL
>> 290 select SYS_SUPPORTS_BIG_ENDIAN
>> 291 select SYS_HAS_EARLY_PRINTK
>> 292 select SWAP_IO_SPACE
>> 293 select GPIOLIB
>> 294 select HAVE_CLK
>> 295 select MIPS_L1_CACHE_SHIFT_4
>> 296 select CLKDEV_LOOKUP
>> 297 help
>> 298 Support for BCM63XX based boards
>> 299
>> 300 config MIPS_COBALT
>> 301 bool "Cobalt Server"
>> 302 select CEVT_R4K
>> 303 select CSRC_R4K
>> 304 select CEVT_GT641XX
>> 305 select DMA_NONCOHERENT
>> 306 select FORCE_PCI
>> 307 select I8253
>> 308 select I8259
>> 309 select IRQ_MIPS_CPU
>> 310 select IRQ_GT641XX
>> 311 select PCI_GT64XXX_PCI0
>> 312 select SYS_HAS_CPU_NEVADA
>> 313 select SYS_HAS_EARLY_PRINTK
>> 314 select SYS_SUPPORTS_32BIT_KERNEL
>> 315 select SYS_SUPPORTS_64BIT_KERNEL
>> 316 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 317 select USE_GENERIC_EARLY_PRINTK_8250
>> 318
>> 319 config MACH_DECSTATION
>> 320 bool "DECstations"
>> 321 select BOOT_ELF32
>> 322 select CEVT_DS1287
>> 323 select CEVT_R4K if CPU_R4X00
>> 324 select CSRC_IOASIC
>> 325 select CSRC_R4K if CPU_R4X00
>> 326 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 327 select CPU_R4000_WORKAROUNDS if 64BIT
>> 328 select CPU_R4400_WORKAROUNDS if 64BIT
>> 329 select DMA_NONCOHERENT
>> 330 select NO_IOPORT_MAP
>> 331 select IRQ_MIPS_CPU
>> 332 select SYS_HAS_CPU_R3000
>> 333 select SYS_HAS_CPU_R4X00
>> 334 select SYS_SUPPORTS_32BIT_KERNEL
>> 335 select SYS_SUPPORTS_64BIT_KERNEL
>> 336 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 337 select SYS_SUPPORTS_128HZ
>> 338 select SYS_SUPPORTS_256HZ
>> 339 select SYS_SUPPORTS_1024HZ
>> 340 select MIPS_L1_CACHE_SHIFT_4
>> 341 help
>> 342 This enables support for DEC's MIPS based workstations. For details
>> 343 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 344 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 345
>> 346 If you have one of the following DECstation Models you definitely
>> 347 want to choose R4xx0 for the CPU Type:
>> 348
>> 349 DECstation 5000/50
>> 350 DECstation 5000/150
>> 351 DECstation 5000/260
>> 352 DECsystem 5900/260
>> 353
>> 354 otherwise choose R3000.
>> 355
>> 356 config MACH_JAZZ
>> 357 bool "Jazz family of machines"
>> 358 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 359 select ARCH_MIGHT_HAVE_PC_SERIO
>> 360 select FW_ARC
>> 361 select FW_ARC32
>> 362 select ARCH_MAY_HAVE_PC_FDC
>> 363 select CEVT_R4K
>> 364 select CSRC_R4K
>> 365 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 366 select GENERIC_ISA_DMA
>> 367 select HAVE_PCSPKR_PLATFORM
>> 368 select IRQ_MIPS_CPU
>> 369 select I8253
>> 370 select I8259
>> 371 select ISA
>> 372 select SYS_HAS_CPU_R4X00
>> 373 select SYS_SUPPORTS_32BIT_KERNEL
>> 374 select SYS_SUPPORTS_64BIT_KERNEL
>> 375 select SYS_SUPPORTS_100HZ
>> 376 help
>> 377 This a family of machines based on the MIPS R4030 chipset which was
>> 378 used by several vendors to build RISC/os and Windows NT workstations.
>> 379 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 380 Olivetti M700-10 workstations.
>> 381
>> 382 config MACH_INGENIC
>> 383 bool "Ingenic SoC based machines"
>> 384 select SYS_SUPPORTS_32BIT_KERNEL
>> 385 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 386 select SYS_SUPPORTS_ZBOOT_UART16550
>> 387 select DMA_NONCOHERENT
>> 388 select IRQ_MIPS_CPU
>> 389 select PINCTRL
>> 390 select GPIOLIB
>> 391 select COMMON_CLK
>> 392 select GENERIC_IRQ_CHIP
>> 393 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 394 select USE_OF
>> 395 select LIBFDT
>> 396
>> 397 config LANTIQ
>> 398 bool "Lantiq based platforms"
>> 399 select DMA_NONCOHERENT
>> 400 select IRQ_MIPS_CPU
>> 401 select CEVT_R4K
>> 402 select CSRC_R4K
>> 403 select SYS_HAS_CPU_MIPS32_R1
>> 404 select SYS_HAS_CPU_MIPS32_R2
>> 405 select SYS_SUPPORTS_BIG_ENDIAN
>> 406 select SYS_SUPPORTS_32BIT_KERNEL
>> 407 select SYS_SUPPORTS_MIPS16
>> 408 select SYS_SUPPORTS_MULTITHREADING
>> 409 select SYS_SUPPORTS_VPE_LOADER
>> 410 select SYS_HAS_EARLY_PRINTK
>> 411 select GPIOLIB
>> 412 select SWAP_IO_SPACE
>> 413 select BOOT_RAW
>> 414 select CLKDEV_LOOKUP
>> 415 select USE_OF
>> 416 select PINCTRL
>> 417 select PINCTRL_LANTIQ
>> 418 select ARCH_HAS_RESET_CONTROLLER
>> 419 select RESET_CONTROLLER
>> 420
>> 421 config LASAT
>> 422 bool "LASAT Networks platforms"
>> 423 select CEVT_R4K
>> 424 select CRC32
>> 425 select CSRC_R4K
>> 426 select DMA_NONCOHERENT
>> 427 select SYS_HAS_EARLY_PRINTK
>> 428 select HAVE_PCI
>> 429 select IRQ_MIPS_CPU
>> 430 select PCI_GT64XXX_PCI0
>> 431 select MIPS_NILE4
>> 432 select R5000_CPU_SCACHE
>> 433 select SYS_HAS_CPU_R5000
>> 434 select SYS_SUPPORTS_32BIT_KERNEL
>> 435 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 436 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 437
>> 438 config MACH_LOONGSON32
>> 439 bool "Loongson-1 family of machines"
>> 440 select SYS_SUPPORTS_ZBOOT
>> 441 help
>> 442 This enables support for the Loongson-1 family of machines.
>> 443
>> 444 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 445 the Institute of Computing Technology (ICT), Chinese Academy of
>> 446 Sciences (CAS).
>> 447
>> 448 config MACH_LOONGSON64
>> 449 bool "Loongson-2/3 family of machines"
>> 450 select SYS_SUPPORTS_ZBOOT
>> 451 help
>> 452 This enables the support of Loongson-2/3 family of machines.
>> 453
>> 454 Loongson-2 is a family of single-core CPUs and Loongson-3 is a
>> 455 family of multi-core CPUs. They are both 64-bit general-purpose
>> 456 MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
>> 457 of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
>> 458 in the People's Republic of China. The chief architect is Professor
>> 459 Weiwu Hu.
>> 460
>> 461 config MACH_PISTACHIO
>> 462 bool "IMG Pistachio SoC based boards"
>> 463 select BOOT_ELF32
>> 464 select BOOT_RAW
>> 465 select CEVT_R4K
>> 466 select CLKSRC_MIPS_GIC
>> 467 select COMMON_CLK
>> 468 select CSRC_R4K
>> 469 select DMA_NONCOHERENT
>> 470 select GPIOLIB
>> 471 select IRQ_MIPS_CPU
>> 472 select LIBFDT
>> 473 select MFD_SYSCON
>> 474 select MIPS_CPU_SCACHE
>> 475 select MIPS_GIC
>> 476 select PINCTRL
>> 477 select REGULATOR
>> 478 select SYS_HAS_CPU_MIPS32_R2
>> 479 select SYS_SUPPORTS_32BIT_KERNEL
>> 480 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 481 select SYS_SUPPORTS_MIPS_CPS
>> 482 select SYS_SUPPORTS_MULTITHREADING
>> 483 select SYS_SUPPORTS_RELOCATABLE
>> 484 select SYS_SUPPORTS_ZBOOT
>> 485 select SYS_HAS_EARLY_PRINTK
>> 486 select USE_GENERIC_EARLY_PRINTK_8250
>> 487 select USE_OF
>> 488 help
>> 489 This enables support for the IMG Pistachio SoC platform.
>> 490
>> 491 config MIPS_MALTA
>> 492 bool "MIPS Malta board"
>> 493 select ARCH_MAY_HAVE_PC_FDC
>> 494 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 495 select ARCH_MIGHT_HAVE_PC_SERIO
>> 496 select BOOT_ELF32
>> 497 select BOOT_RAW
>> 498 select BUILTIN_DTB
>> 499 select CEVT_R4K
>> 500 select CLKSRC_MIPS_GIC
>> 501 select COMMON_CLK
>> 502 select CSRC_R4K
>> 503 select DMA_MAYBE_COHERENT
>> 504 select GENERIC_ISA_DMA
>> 505 select HAVE_PCSPKR_PLATFORM
>> 506 select HAVE_PCI
>> 507 select I8253
>> 508 select I8259
>> 509 select IRQ_MIPS_CPU
>> 510 select LIBFDT
>> 511 select MIPS_BONITO64
>> 512 select MIPS_CPU_SCACHE
>> 513 select MIPS_GIC
>> 514 select MIPS_L1_CACHE_SHIFT_6
>> 515 select MIPS_MSC
>> 516 select PCI_GT64XXX_PCI0
>> 517 select SMP_UP if SMP
>> 518 select SWAP_IO_SPACE
>> 519 select SYS_HAS_CPU_MIPS32_R1
>> 520 select SYS_HAS_CPU_MIPS32_R2
>> 521 select SYS_HAS_CPU_MIPS32_R3_5
>> 522 select SYS_HAS_CPU_MIPS32_R5
>> 523 select SYS_HAS_CPU_MIPS32_R6
>> 524 select SYS_HAS_CPU_MIPS64_R1
>> 525 select SYS_HAS_CPU_MIPS64_R2
>> 526 select SYS_HAS_CPU_MIPS64_R6
>> 527 select SYS_HAS_CPU_NEVADA
>> 528 select SYS_HAS_CPU_RM7000
>> 529 select SYS_SUPPORTS_32BIT_KERNEL
>> 530 select SYS_SUPPORTS_64BIT_KERNEL
>> 531 select SYS_SUPPORTS_BIG_ENDIAN
>> 532 select SYS_SUPPORTS_HIGHMEM
>> 533 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 534 select SYS_SUPPORTS_MICROMIPS
>> 535 select SYS_SUPPORTS_MIPS16
>> 536 select SYS_SUPPORTS_MIPS_CMP
>> 537 select SYS_SUPPORTS_MIPS_CPS
>> 538 select SYS_SUPPORTS_MULTITHREADING
>> 539 select SYS_SUPPORTS_RELOCATABLE
>> 540 select SYS_SUPPORTS_SMARTMIPS
>> 541 select SYS_SUPPORTS_VPE_LOADER
>> 542 select SYS_SUPPORTS_ZBOOT
>> 543 select USE_OF
>> 544 select ZONE_DMA32 if 64BIT
>> 545 help
>> 546 This enables support for the MIPS Technologies Malta evaluation
>> 547 board.
>> 548
>> 549 config MACH_PIC32
>> 550 bool "Microchip PIC32 Family"
>> 551 help
>> 552 This enables support for the Microchip PIC32 family of platforms.
>> 553
>> 554 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 555 microcontrollers.
>> 556
>> 557 config NEC_MARKEINS
>> 558 bool "NEC EMMA2RH Mark-eins board"
>> 559 select SOC_EMMA2RH
>> 560 select HAVE_PCI
>> 561 help
>> 562 This enables support for the NEC Electronics Mark-eins boards.
>> 563
>> 564 config MACH_VR41XX
>> 565 bool "NEC VR4100 series based machines"
>> 566 select CEVT_R4K
>> 567 select CSRC_R4K
>> 568 select SYS_HAS_CPU_VR41XX
>> 569 select SYS_SUPPORTS_MIPS16
>> 570 select GPIOLIB
>> 571
>> 572 config NXP_STB220
>> 573 bool "NXP STB220 board"
>> 574 select SOC_PNX833X
>> 575 help
>> 576 Support for NXP Semiconductors STB220 Development Board.
>> 577
>> 578 config NXP_STB225
>> 579 bool "NXP 225 board"
>> 580 select SOC_PNX833X
>> 581 select SOC_PNX8335
>> 582 help
>> 583 Support for NXP Semiconductors STB225 Development Board.
>> 584
>> 585 config PMC_MSP
>> 586 bool "PMC-Sierra MSP chipsets"
>> 587 select CEVT_R4K
>> 588 select CSRC_R4K
>> 589 select DMA_NONCOHERENT
>> 590 select SWAP_IO_SPACE
>> 591 select NO_EXCEPT_FILL
>> 592 select BOOT_RAW
>> 593 select SYS_HAS_CPU_MIPS32_R1
>> 594 select SYS_HAS_CPU_MIPS32_R2
>> 595 select SYS_SUPPORTS_32BIT_KERNEL
>> 596 select SYS_SUPPORTS_BIG_ENDIAN
>> 597 select SYS_SUPPORTS_MIPS16
>> 598 select IRQ_MIPS_CPU
>> 599 select SERIAL_8250
>> 600 select SERIAL_8250_CONSOLE
>> 601 select USB_EHCI_BIG_ENDIAN_MMIO
>> 602 select USB_EHCI_BIG_ENDIAN_DESC
>> 603 help
>> 604 This adds support for the PMC-Sierra family of Multi-Service
>> 605 Processor System-On-A-Chips. These parts include a number
>> 606 of integrated peripherals, interfaces and DSPs in addition to
>> 607 a variety of MIPS cores.
>> 608
>> 609 config RALINK
>> 610 bool "Ralink based machines"
>> 611 select CEVT_R4K
>> 612 select CSRC_R4K
>> 613 select BOOT_RAW
>> 614 select DMA_NONCOHERENT
>> 615 select IRQ_MIPS_CPU
>> 616 select USE_OF
>> 617 select SYS_HAS_CPU_MIPS32_R1
>> 618 select SYS_HAS_CPU_MIPS32_R2
>> 619 select SYS_SUPPORTS_32BIT_KERNEL
>> 620 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 621 select SYS_SUPPORTS_MIPS16
>> 622 select SYS_HAS_EARLY_PRINTK
>> 623 select CLKDEV_LOOKUP
>> 624 select ARCH_HAS_RESET_CONTROLLER
>> 625 select RESET_CONTROLLER
>> 626
>> 627 config SGI_IP22
>> 628 bool "SGI IP22 (Indy/Indigo2)"
>> 629 select FW_ARC
>> 630 select FW_ARC32
>> 631 select ARCH_MIGHT_HAVE_PC_SERIO
>> 632 select BOOT_ELF32
>> 633 select CEVT_R4K
>> 634 select CSRC_R4K
>> 635 select DEFAULT_SGI_PARTITION
>> 636 select DMA_NONCOHERENT
>> 637 select HAVE_EISA
>> 638 select I8253
>> 639 select I8259
>> 640 select IP22_CPU_SCACHE
>> 641 select IRQ_MIPS_CPU
>> 642 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 643 select SGI_HAS_I8042
>> 644 select SGI_HAS_INDYDOG
>> 645 select SGI_HAS_HAL2
>> 646 select SGI_HAS_SEEQ
>> 647 select SGI_HAS_WD93
>> 648 select SGI_HAS_ZILOG
>> 649 select SWAP_IO_SPACE
>> 650 select SYS_HAS_CPU_R4X00
>> 651 select SYS_HAS_CPU_R5000
>> 652 #
>> 653 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 654 # memory during early boot on some machines.
>> 655 #
>> 656 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 657 # for a more details discussion
>> 658 #
>> 659 # select SYS_HAS_EARLY_PRINTK
>> 660 select SYS_SUPPORTS_32BIT_KERNEL
>> 661 select SYS_SUPPORTS_64BIT_KERNEL
>> 662 select SYS_SUPPORTS_BIG_ENDIAN
>> 663 select MIPS_L1_CACHE_SHIFT_7
>> 664 help
>> 665 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 666 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 667 that runs on these, say Y here.
>> 668
>> 669 config SGI_IP27
>> 670 bool "SGI IP27 (Origin200/2000)"
>> 671 select ARCH_HAS_PHYS_TO_DMA
>> 672 select FW_ARC
>> 673 select FW_ARC64
>> 674 select BOOT_ELF64
>> 675 select DEFAULT_SGI_PARTITION
>> 676 select SYS_HAS_EARLY_PRINTK
>> 677 select HAVE_PCI
>> 678 select IRQ_MIPS_CPU
>> 679 select NR_CPUS_DEFAULT_64
>> 680 select SYS_HAS_CPU_R10000
>> 681 select SYS_SUPPORTS_64BIT_KERNEL
>> 682 select SYS_SUPPORTS_BIG_ENDIAN
>> 683 select SYS_SUPPORTS_NUMA
>> 684 select SYS_SUPPORTS_SMP
>> 685 select MIPS_L1_CACHE_SHIFT_7
>> 686 help
>> 687 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 688 workstations. To compile a Linux kernel that runs on these, say Y
>> 689 here.
>> 690
>> 691 config SGI_IP28
>> 692 bool "SGI IP28 (Indigo2 R10k)"
>> 693 select FW_ARC
>> 694 select FW_ARC64
>> 695 select ARCH_MIGHT_HAVE_PC_SERIO
>> 696 select BOOT_ELF64
>> 697 select CEVT_R4K
>> 698 select CSRC_R4K
>> 699 select DEFAULT_SGI_PARTITION
>> 700 select DMA_NONCOHERENT
>> 701 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 702 select IRQ_MIPS_CPU
>> 703 select HAVE_EISA
>> 704 select I8253
>> 705 select I8259
>> 706 select SGI_HAS_I8042
>> 707 select SGI_HAS_INDYDOG
>> 708 select SGI_HAS_HAL2
>> 709 select SGI_HAS_SEEQ
>> 710 select SGI_HAS_WD93
>> 711 select SGI_HAS_ZILOG
>> 712 select SWAP_IO_SPACE
>> 713 select SYS_HAS_CPU_R10000
>> 714 #
>> 715 # Disable EARLY_PRINTK for now since it leads to overwritten prom
>> 716 # memory during early boot on some machines.
>> 717 #
>> 718 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
>> 719 # for a more details discussion
>> 720 #
>> 721 # select SYS_HAS_EARLY_PRINTK
>> 722 select SYS_SUPPORTS_64BIT_KERNEL
>> 723 select SYS_SUPPORTS_BIG_ENDIAN
>> 724 select MIPS_L1_CACHE_SHIFT_7
>> 725 help
>> 726 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 727 kernel that runs on these, say Y here.
>> 728
>> 729 config SGI_IP32
>> 730 bool "SGI IP32 (O2)"
>> 731 select ARCH_HAS_PHYS_TO_DMA
>> 732 select FW_ARC
>> 733 select FW_ARC32
>> 734 select BOOT_ELF32
>> 735 select CEVT_R4K
>> 736 select CSRC_R4K
>> 737 select DMA_NONCOHERENT
>> 738 select HAVE_PCI
>> 739 select IRQ_MIPS_CPU
>> 740 select R5000_CPU_SCACHE
>> 741 select RM7000_CPU_SCACHE
>> 742 select SYS_HAS_CPU_R5000
>> 743 select SYS_HAS_CPU_R10000 if BROKEN
>> 744 select SYS_HAS_CPU_RM7000
>> 745 select SYS_HAS_CPU_NEVADA
>> 746 select SYS_SUPPORTS_64BIT_KERNEL
>> 747 select SYS_SUPPORTS_BIG_ENDIAN
>> 748 help
>> 749 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 750
>> 751 config SIBYTE_CRHINE
>> 752 bool "Sibyte BCM91120C-CRhine"
>> 753 select BOOT_ELF32
>> 754 select SIBYTE_BCM1120
>> 755 select SWAP_IO_SPACE
>> 756 select SYS_HAS_CPU_SB1
>> 757 select SYS_SUPPORTS_BIG_ENDIAN
>> 758 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 759
>> 760 config SIBYTE_CARMEL
>> 761 bool "Sibyte BCM91120x-Carmel"
>> 762 select BOOT_ELF32
>> 763 select SIBYTE_BCM1120
>> 764 select SWAP_IO_SPACE
>> 765 select SYS_HAS_CPU_SB1
>> 766 select SYS_SUPPORTS_BIG_ENDIAN
>> 767 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 768
>> 769 config SIBYTE_CRHONE
>> 770 bool "Sibyte BCM91125C-CRhone"
>> 771 select BOOT_ELF32
>> 772 select SIBYTE_BCM1125
>> 773 select SWAP_IO_SPACE
>> 774 select SYS_HAS_CPU_SB1
>> 775 select SYS_SUPPORTS_BIG_ENDIAN
>> 776 select SYS_SUPPORTS_HIGHMEM
>> 777 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 778
>> 779 config SIBYTE_RHONE
>> 780 bool "Sibyte BCM91125E-Rhone"
>> 781 select BOOT_ELF32
>> 782 select SIBYTE_BCM1125H
>> 783 select SWAP_IO_SPACE
>> 784 select SYS_HAS_CPU_SB1
>> 785 select SYS_SUPPORTS_BIG_ENDIAN
>> 786 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 787
>> 788 config SIBYTE_SWARM
>> 789 bool "Sibyte BCM91250A-SWARM"
>> 790 select BOOT_ELF32
>> 791 select HAVE_PATA_PLATFORM
>> 792 select SIBYTE_SB1250
>> 793 select SWAP_IO_SPACE
>> 794 select SYS_HAS_CPU_SB1
>> 795 select SYS_SUPPORTS_BIG_ENDIAN
>> 796 select SYS_SUPPORTS_HIGHMEM
>> 797 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 798 select ZONE_DMA32 if 64BIT
>> 799 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 800
>> 801 config SIBYTE_LITTLESUR
>> 802 bool "Sibyte BCM91250C2-LittleSur"
>> 803 select BOOT_ELF32
>> 804 select HAVE_PATA_PLATFORM
>> 805 select SIBYTE_SB1250
>> 806 select SWAP_IO_SPACE
>> 807 select SYS_HAS_CPU_SB1
>> 808 select SYS_SUPPORTS_BIG_ENDIAN
>> 809 select SYS_SUPPORTS_HIGHMEM
>> 810 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 811 select ZONE_DMA32 if 64BIT
>> 812
>> 813 config SIBYTE_SENTOSA
>> 814 bool "Sibyte BCM91250E-Sentosa"
>> 815 select BOOT_ELF32
>> 816 select SIBYTE_SB1250
>> 817 select SWAP_IO_SPACE
>> 818 select SYS_HAS_CPU_SB1
>> 819 select SYS_SUPPORTS_BIG_ENDIAN
>> 820 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 821 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 822
>> 823 config SIBYTE_BIGSUR
>> 824 bool "Sibyte BCM91480B-BigSur"
>> 825 select BOOT_ELF32
>> 826 select NR_CPUS_DEFAULT_4
>> 827 select SIBYTE_BCM1x80
>> 828 select SWAP_IO_SPACE
>> 829 select SYS_HAS_CPU_SB1
>> 830 select SYS_SUPPORTS_BIG_ENDIAN
>> 831 select SYS_SUPPORTS_HIGHMEM
>> 832 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 833 select ZONE_DMA32 if 64BIT
>> 834 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 835
>> 836 config SNI_RM
>> 837 bool "SNI RM200/300/400"
>> 838 select FW_ARC if CPU_LITTLE_ENDIAN
>> 839 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 840 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 841 select ARCH_MAY_HAVE_PC_FDC
>> 842 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 843 select ARCH_MIGHT_HAVE_PC_SERIO
>> 844 select BOOT_ELF32
>> 845 select CEVT_R4K
>> 846 select CSRC_R4K
>> 847 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 848 select DMA_NONCOHERENT
>> 849 select GENERIC_ISA_DMA
>> 850 select HAVE_EISA
>> 851 select HAVE_PCSPKR_PLATFORM
>> 852 select HAVE_PCI
>> 853 select IRQ_MIPS_CPU
>> 854 select I8253
>> 855 select I8259
>> 856 select ISA
>> 857 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 858 select SYS_HAS_CPU_R4X00
>> 859 select SYS_HAS_CPU_R5000
>> 860 select SYS_HAS_CPU_R10000
>> 861 select R5000_CPU_SCACHE
>> 862 select SYS_HAS_EARLY_PRINTK
>> 863 select SYS_SUPPORTS_32BIT_KERNEL
>> 864 select SYS_SUPPORTS_64BIT_KERNEL
>> 865 select SYS_SUPPORTS_BIG_ENDIAN
>> 866 select SYS_SUPPORTS_HIGHMEM
>> 867 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 868 help
>> 869 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 870 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 871 Technology and now in turn merged with Fujitsu. Say Y here to
>> 872 support this machine type.
>> 873
>> 874 config MACH_TX39XX
>> 875 bool "Toshiba TX39 series based machines"
>> 876
>> 877 config MACH_TX49XX
>> 878 bool "Toshiba TX49 series based machines"
>> 879
>> 880 config MIKROTIK_RB532
>> 881 bool "Mikrotik RB532 boards"
>> 882 select CEVT_R4K
>> 883 select CSRC_R4K
>> 884 select DMA_NONCOHERENT
>> 885 select HAVE_PCI
>> 886 select IRQ_MIPS_CPU
>> 887 select SYS_HAS_CPU_MIPS32_R1
>> 888 select SYS_SUPPORTS_32BIT_KERNEL
>> 889 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 890 select SWAP_IO_SPACE
>> 891 select BOOT_RAW
>> 892 select GPIOLIB
>> 893 select MIPS_L1_CACHE_SHIFT_4
>> 894 help
>> 895 Support the Mikrotik(tm) RouterBoard 532 series,
>> 896 based on the IDT RC32434 SoC.
>> 897
>> 898 config CAVIUM_OCTEON_SOC
>> 899 bool "Cavium Networks Octeon SoC based boards"
>> 900 select CEVT_R4K
>> 901 select ARCH_HAS_PHYS_TO_DMA
>> 902 select HAVE_RAPIDIO
>> 903 select PHYS_ADDR_T_64BIT
>> 904 select SYS_SUPPORTS_64BIT_KERNEL
>> 905 select SYS_SUPPORTS_BIG_ENDIAN
>> 906 select EDAC_SUPPORT
>> 907 select EDAC_ATOMIC_SCRUB
>> 908 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 909 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 910 select SYS_HAS_EARLY_PRINTK
>> 911 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 912 select HAVE_PCI
>> 913 select ZONE_DMA32
>> 914 select HOLES_IN_ZONE
>> 915 select GPIOLIB
>> 916 select LIBFDT
>> 917 select USE_OF
>> 918 select ARCH_SPARSEMEM_ENABLE
>> 919 select SYS_SUPPORTS_SMP
>> 920 select NR_CPUS_DEFAULT_64
>> 921 select MIPS_NR_CPU_NR_MAP_1024
>> 922 select BUILTIN_DTB
>> 923 select MTD_COMPLEX_MAPPINGS
>> 924 select SWIOTLB
>> 925 select SYS_SUPPORTS_RELOCATABLE
>> 926 help
>> 927 This option supports all of the Octeon reference boards from Cavium
>> 928 Networks. It builds a kernel that dynamically determines the Octeon
>> 929 CPU type and supports all known board reference implementations.
>> 930 Some of the supported boards are:
>> 931 EBT3000
>> 932 EBH3000
>> 933 EBH3100
>> 934 Thunder
>> 935 Kodama
>> 936 Hikari
>> 937 Say Y here for most Octeon reference boards.
>> 938
>> 939 config NLM_XLR_BOARD
>> 940 bool "Netlogic XLR/XLS based systems"
>> 941 select BOOT_ELF32
>> 942 select NLM_COMMON
>> 943 select SYS_HAS_CPU_XLR
>> 944 select SYS_SUPPORTS_SMP
>> 945 select HAVE_PCI
>> 946 select SWAP_IO_SPACE
>> 947 select SYS_SUPPORTS_32BIT_KERNEL
>> 948 select SYS_SUPPORTS_64BIT_KERNEL
>> 949 select PHYS_ADDR_T_64BIT
>> 950 select SYS_SUPPORTS_BIG_ENDIAN
>> 951 select SYS_SUPPORTS_HIGHMEM
>> 952 select NR_CPUS_DEFAULT_32
>> 953 select CEVT_R4K
>> 954 select CSRC_R4K
>> 955 select IRQ_MIPS_CPU
>> 956 select ZONE_DMA32 if 64BIT
>> 957 select SYNC_R4K
>> 958 select SYS_HAS_EARLY_PRINTK
>> 959 select SYS_SUPPORTS_ZBOOT
>> 960 select SYS_SUPPORTS_ZBOOT_UART16550
>> 961 help
>> 962 Support for systems based on Netlogic XLR and XLS processors.
>> 963 Say Y here if you have a XLR or XLS based board.
>> 964
>> 965 config NLM_XLP_BOARD
>> 966 bool "Netlogic XLP based systems"
>> 967 select BOOT_ELF32
>> 968 select NLM_COMMON
>> 969 select SYS_HAS_CPU_XLP
>> 970 select SYS_SUPPORTS_SMP
>> 971 select HAVE_PCI
>> 972 select SYS_SUPPORTS_32BIT_KERNEL
>> 973 select SYS_SUPPORTS_64BIT_KERNEL
>> 974 select PHYS_ADDR_T_64BIT
>> 975 select GPIOLIB
>> 976 select SYS_SUPPORTS_BIG_ENDIAN
>> 977 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 978 select SYS_SUPPORTS_HIGHMEM
>> 979 select NR_CPUS_DEFAULT_32
>> 980 select CEVT_R4K
>> 981 select CSRC_R4K
>> 982 select IRQ_MIPS_CPU
>> 983 select ZONE_DMA32 if 64BIT
>> 984 select SYNC_R4K
>> 985 select SYS_HAS_EARLY_PRINTK
>> 986 select USE_OF
>> 987 select SYS_SUPPORTS_ZBOOT
>> 988 select SYS_SUPPORTS_ZBOOT_UART16550
>> 989 help
>> 990 This board is based on Netlogic XLP Processor.
>> 991 Say Y here if you have a XLP based board.
>> 992
>> 993 config MIPS_PARAVIRT
>> 994 bool "Para-Virtualized guest system"
>> 995 select CEVT_R4K
>> 996 select CSRC_R4K
>> 997 select SYS_SUPPORTS_64BIT_KERNEL
>> 998 select SYS_SUPPORTS_32BIT_KERNEL
>> 999 select SYS_SUPPORTS_BIG_ENDIAN
>> 1000 select SYS_SUPPORTS_SMP
>> 1001 select NR_CPUS_DEFAULT_4
>> 1002 select SYS_HAS_EARLY_PRINTK
>> 1003 select SYS_HAS_CPU_MIPS32_R2
>> 1004 select SYS_HAS_CPU_MIPS64_R2
>> 1005 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1006 select HAVE_PCI
>> 1007 select SWAP_IO_SPACE
60 help 1008 help
61 Xtensa processors are 32-bit RISC ma !! 1009 This option supports guest running under ????
62 primarily for embedded systems. The !! 1010
63 configurable and extensible. The Li !! 1011 endchoice
64 architecture supports all processor !! 1012
65 with reasonable minimum requirements !! 1013 source "arch/mips/alchemy/Kconfig"
66 a home page at <http://www.linux-xte !! 1014 source "arch/mips/ath25/Kconfig"
>> 1015 source "arch/mips/ath79/Kconfig"
>> 1016 source "arch/mips/bcm47xx/Kconfig"
>> 1017 source "arch/mips/bcm63xx/Kconfig"
>> 1018 source "arch/mips/bmips/Kconfig"
>> 1019 source "arch/mips/generic/Kconfig"
>> 1020 source "arch/mips/jazz/Kconfig"
>> 1021 source "arch/mips/jz4740/Kconfig"
>> 1022 source "arch/mips/lantiq/Kconfig"
>> 1023 source "arch/mips/lasat/Kconfig"
>> 1024 source "arch/mips/pic32/Kconfig"
>> 1025 source "arch/mips/pistachio/Kconfig"
>> 1026 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1027 source "arch/mips/ralink/Kconfig"
>> 1028 source "arch/mips/sgi-ip27/Kconfig"
>> 1029 source "arch/mips/sibyte/Kconfig"
>> 1030 source "arch/mips/txx9/Kconfig"
>> 1031 source "arch/mips/vr41xx/Kconfig"
>> 1032 source "arch/mips/cavium-octeon/Kconfig"
>> 1033 source "arch/mips/loongson32/Kconfig"
>> 1034 source "arch/mips/loongson64/Kconfig"
>> 1035 source "arch/mips/netlogic/Kconfig"
>> 1036 source "arch/mips/paravirt/Kconfig"
>> 1037
>> 1038 endmenu
>> 1039
>> 1040 config RWSEM_GENERIC_SPINLOCK
>> 1041 bool
>> 1042 default y
>> 1043
>> 1044 config RWSEM_XCHGADD_ALGORITHM
>> 1045 bool
67 1046
68 config GENERIC_HWEIGHT 1047 config GENERIC_HWEIGHT
69 def_bool y !! 1048 bool
>> 1049 default y
70 1050
71 config ARCH_HAS_ILOG2_U32 !! 1051 config GENERIC_CALIBRATE_DELAY
72 def_bool n !! 1052 bool
>> 1053 default y
73 1054
74 config ARCH_HAS_ILOG2_U64 !! 1055 config SCHED_OMIT_FRAME_POINTER
75 def_bool n !! 1056 bool
>> 1057 default y
76 1058
77 config ARCH_MTD_XIP !! 1059 #
78 def_bool y !! 1060 # Select some configuration options automatically based on user selections.
>> 1061 #
>> 1062 config FW_ARC
>> 1063 bool
>> 1064
>> 1065 config ARCH_MAY_HAVE_PC_FDC
>> 1066 bool
>> 1067
>> 1068 config BOOT_RAW
>> 1069 bool
>> 1070
>> 1071 config CEVT_BCM1480
>> 1072 bool
>> 1073
>> 1074 config CEVT_DS1287
>> 1075 bool
>> 1076
>> 1077 config CEVT_GT641XX
>> 1078 bool
>> 1079
>> 1080 config CEVT_R4K
>> 1081 bool
>> 1082
>> 1083 config CEVT_SB1250
>> 1084 bool
>> 1085
>> 1086 config CEVT_TXX9
>> 1087 bool
>> 1088
>> 1089 config CSRC_BCM1480
>> 1090 bool
>> 1091
>> 1092 config CSRC_IOASIC
>> 1093 bool
>> 1094
>> 1095 config CSRC_R4K
>> 1096 bool
>> 1097
>> 1098 config CSRC_SB1250
>> 1099 bool
>> 1100
>> 1101 config MIPS_CLOCK_VSYSCALL
>> 1102 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1103
>> 1104 config GPIO_TXX9
>> 1105 select GPIOLIB
>> 1106 bool
>> 1107
>> 1108 config FW_CFE
>> 1109 bool
>> 1110
>> 1111 config ARCH_SUPPORTS_UPROBES
>> 1112 bool
>> 1113
>> 1114 config DMA_MAYBE_COHERENT
>> 1115 select ARCH_HAS_DMA_COHERENCE_H
>> 1116 select DMA_NONCOHERENT
>> 1117 bool
>> 1118
>> 1119 config DMA_PERDEV_COHERENT
>> 1120 bool
>> 1121 select ARCH_HAS_SETUP_DMA_OPS
>> 1122 select DMA_NONCOHERENT
>> 1123
>> 1124 config DMA_NONCOHERENT
>> 1125 bool
>> 1126 select ARCH_HAS_DMA_MMAP_PGPROT
>> 1127 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1128 select NEED_DMA_MAP_STATE
>> 1129 select ARCH_HAS_DMA_COHERENT_TO_PFN
>> 1130 select DMA_NONCOHERENT_CACHE_SYNC
>> 1131
>> 1132 config SYS_HAS_EARLY_PRINTK
>> 1133 bool
>> 1134
>> 1135 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1136 bool
>> 1137
>> 1138 config MIPS_BONITO64
>> 1139 bool
>> 1140
>> 1141 config MIPS_MSC
>> 1142 bool
>> 1143
>> 1144 config MIPS_NILE4
>> 1145 bool
>> 1146
>> 1147 config SYNC_R4K
>> 1148 bool
>> 1149
>> 1150 config MIPS_MACHINE
>> 1151 def_bool n
79 1152
80 config NO_IOPORT_MAP 1153 config NO_IOPORT_MAP
81 def_bool n 1154 def_bool n
82 1155
83 config HZ !! 1156 config GENERIC_CSUM
84 int !! 1157 bool
85 default 100 !! 1158 default y if !CPU_HAS_LOAD_STORE_LR
86 1159
87 config LOCKDEP_SUPPORT !! 1160 config GENERIC_ISA_DMA
88 def_bool y !! 1161 bool
>> 1162 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1163 select ISA_DMA_API
89 1164
90 config STACKTRACE_SUPPORT !! 1165 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1166 bool
>> 1167 select GENERIC_ISA_DMA
>> 1168
>> 1169 config ISA_DMA_API
>> 1170 bool
>> 1171
>> 1172 config HOLES_IN_ZONE
>> 1173 bool
>> 1174
>> 1175 config SYS_SUPPORTS_RELOCATABLE
>> 1176 bool
>> 1177 help
>> 1178 Selected if the platform supports relocating the kernel.
>> 1179 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1180 to allow access to command line and entropy sources.
>> 1181
>> 1182 config MIPS_CBPF_JIT
91 def_bool y 1183 def_bool y
>> 1184 depends on BPF_JIT && HAVE_CBPF_JIT
92 1185
93 config MMU !! 1186 config MIPS_EBPF_JIT
94 def_bool n !! 1187 def_bool y
95 select PFAULT !! 1188 depends on BPF_JIT && HAVE_EBPF_JIT
96 1189
97 config HAVE_XTENSA_GPIO32 <<
98 def_bool n <<
99 1190
100 config KASAN_SHADOW_OFFSET !! 1191 #
101 hex !! 1192 # Endianness selection. Sufficiently obscure so many users don't know what to
102 default 0x6e400000 !! 1193 # answer,so we try hard to limit the available choices. Also the use of a
>> 1194 # choice statement should be more obvious to the user.
>> 1195 #
>> 1196 choice
>> 1197 prompt "Endianness selection"
>> 1198 help
>> 1199 Some MIPS machines can be configured for either little or big endian
>> 1200 byte order. These modes require different kernels and a different
>> 1201 Linux distribution. In general there is one preferred byteorder for a
>> 1202 particular system but some systems are just as commonly used in the
>> 1203 one or the other endianness.
103 1204
104 config CPU_BIG_ENDIAN 1205 config CPU_BIG_ENDIAN
105 def_bool $(success,test "$(shell,echo !! 1206 bool "Big endian"
>> 1207 depends on SYS_SUPPORTS_BIG_ENDIAN
106 1208
107 config CPU_LITTLE_ENDIAN 1209 config CPU_LITTLE_ENDIAN
108 def_bool !CPU_BIG_ENDIAN !! 1210 bool "Little endian"
>> 1211 depends on SYS_SUPPORTS_LITTLE_ENDIAN
109 1212
110 config CC_HAVE_CALL0_ABI !! 1213 endchoice
111 def_bool $(success,test "$(shell,echo <<
112 1214
113 menu "Processor type and features" !! 1215 config EXPORT_UASM
>> 1216 bool
114 1217
115 choice !! 1218 config SYS_SUPPORTS_APM_EMULATION
116 prompt "Xtensa Processor Configuration !! 1219 bool
117 default XTENSA_VARIANT_FSF <<
118 1220
119 config XTENSA_VARIANT_FSF !! 1221 config SYS_SUPPORTS_BIG_ENDIAN
120 bool "fsf - default (not generic) conf !! 1222 bool
121 select MMU <<
122 1223
123 config XTENSA_VARIANT_DC232B !! 1224 config SYS_SUPPORTS_LITTLE_ENDIAN
124 bool "dc232b - Diamond 232L Standard C !! 1225 bool
125 select MMU <<
126 select HAVE_XTENSA_GPIO32 <<
127 help <<
128 This variant refers to Tensilica's D <<
129 1226
130 config XTENSA_VARIANT_DC233C !! 1227 config SYS_SUPPORTS_HUGETLBFS
131 bool "dc233c - Diamond 233L Standard C !! 1228 bool
132 select MMU !! 1229 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
133 select HAVE_XTENSA_GPIO32 !! 1230 default y
134 help !! 1231
135 This variant refers to Tensilica's D !! 1232 config MIPS_HUGE_TLB_SUPPORT
>> 1233 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
>> 1234
>> 1235 config IRQ_CPU_RM7K
>> 1236 bool
>> 1237
>> 1238 config IRQ_MSP_SLP
>> 1239 bool
>> 1240
>> 1241 config IRQ_MSP_CIC
>> 1242 bool
>> 1243
>> 1244 config IRQ_TXX9
>> 1245 bool
>> 1246
>> 1247 config IRQ_GT641XX
>> 1248 bool
>> 1249
>> 1250 config PCI_GT64XXX_PCI0
>> 1251 bool
>> 1252
>> 1253 config NO_EXCEPT_FILL
>> 1254 bool
>> 1255
>> 1256 config SOC_EMMA2RH
>> 1257 bool
>> 1258 select CEVT_R4K
>> 1259 select CSRC_R4K
>> 1260 select DMA_NONCOHERENT
>> 1261 select IRQ_MIPS_CPU
>> 1262 select SWAP_IO_SPACE
>> 1263 select SYS_HAS_CPU_R5500
>> 1264 select SYS_SUPPORTS_32BIT_KERNEL
>> 1265 select SYS_SUPPORTS_64BIT_KERNEL
>> 1266 select SYS_SUPPORTS_BIG_ENDIAN
136 1267
137 config XTENSA_VARIANT_CUSTOM !! 1268 config SOC_PNX833X
138 bool "Custom Xtensa processor configur !! 1269 bool
139 select HAVE_XTENSA_GPIO32 !! 1270 select CEVT_R4K
>> 1271 select CSRC_R4K
>> 1272 select IRQ_MIPS_CPU
>> 1273 select DMA_NONCOHERENT
>> 1274 select SYS_HAS_CPU_MIPS32_R2
>> 1275 select SYS_SUPPORTS_32BIT_KERNEL
>> 1276 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1277 select SYS_SUPPORTS_BIG_ENDIAN
>> 1278 select SYS_SUPPORTS_MIPS16
>> 1279 select CPU_MIPSR2_IRQ_VI
>> 1280
>> 1281 config SOC_PNX8335
>> 1282 bool
>> 1283 select SOC_PNX833X
>> 1284
>> 1285 config MIPS_SPRAM
>> 1286 bool
>> 1287
>> 1288 config SWAP_IO_SPACE
>> 1289 bool
>> 1290
>> 1291 config SGI_HAS_INDYDOG
>> 1292 bool
>> 1293
>> 1294 config SGI_HAS_HAL2
>> 1295 bool
>> 1296
>> 1297 config SGI_HAS_SEEQ
>> 1298 bool
>> 1299
>> 1300 config SGI_HAS_WD93
>> 1301 bool
>> 1302
>> 1303 config SGI_HAS_ZILOG
>> 1304 bool
>> 1305
>> 1306 config SGI_HAS_I8042
>> 1307 bool
>> 1308
>> 1309 config DEFAULT_SGI_PARTITION
>> 1310 bool
>> 1311
>> 1312 config FW_ARC32
>> 1313 bool
>> 1314
>> 1315 config FW_SNIPROM
>> 1316 bool
>> 1317
>> 1318 config BOOT_ELF32
>> 1319 bool
>> 1320
>> 1321 config MIPS_L1_CACHE_SHIFT_4
>> 1322 bool
>> 1323
>> 1324 config MIPS_L1_CACHE_SHIFT_5
>> 1325 bool
>> 1326
>> 1327 config MIPS_L1_CACHE_SHIFT_6
>> 1328 bool
>> 1329
>> 1330 config MIPS_L1_CACHE_SHIFT_7
>> 1331 bool
>> 1332
>> 1333 config MIPS_L1_CACHE_SHIFT
>> 1334 int
>> 1335 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1336 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1337 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1338 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1339 default "5"
>> 1340
>> 1341 config HAVE_STD_PC_SERIAL_PORT
>> 1342 bool
>> 1343
>> 1344 config ARC_CONSOLE
>> 1345 bool "ARC console support"
>> 1346 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
>> 1347
>> 1348 config ARC_MEMORY
>> 1349 bool
>> 1350 depends on MACH_JAZZ || SNI_RM || SGI_IP32
>> 1351 default y
>> 1352
>> 1353 config ARC_PROMLIB
>> 1354 bool
>> 1355 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
>> 1356 default y
>> 1357
>> 1358 config FW_ARC64
>> 1359 bool
>> 1360
>> 1361 config BOOT_ELF64
>> 1362 bool
>> 1363
>> 1364 menu "CPU selection"
>> 1365
>> 1366 choice
>> 1367 prompt "CPU type"
>> 1368 default CPU_R4X00
>> 1369
>> 1370 config CPU_LOONGSON3
>> 1371 bool "Loongson 3 CPU"
>> 1372 depends on SYS_HAS_CPU_LOONGSON3
>> 1373 select ARCH_HAS_PHYS_TO_DMA
>> 1374 select CPU_SUPPORTS_64BIT_KERNEL
>> 1375 select CPU_SUPPORTS_HIGHMEM
>> 1376 select CPU_SUPPORTS_HUGEPAGES
>> 1377 select CPU_HAS_LOAD_STORE_LR
>> 1378 select WEAK_ORDERING
>> 1379 select WEAK_REORDERING_BEYOND_LLSC
>> 1380 select MIPS_PGD_C0_CONTEXT
>> 1381 select MIPS_L1_CACHE_SHIFT_6
>> 1382 select GPIOLIB
>> 1383 select SWIOTLB
140 help 1384 help
141 Select this variant to use a custom !! 1385 The Loongson 3 processor implements the MIPS64R2 instruction
142 You will be prompted for a processor !! 1386 set with many extensions.
143 endchoice <<
144 1387
145 config XTENSA_VARIANT_CUSTOM_NAME !! 1388 config LOONGSON3_ENHANCEMENT
146 string "Xtensa Processor Custom Core V !! 1389 bool "New Loongson 3 CPU Enhancements"
147 depends on XTENSA_VARIANT_CUSTOM <<
148 help <<
149 Provide the name of a custom Xtensa <<
150 This CORENAME selects arch/xtensa/va <<
151 Don't forget you have to select MMU <<
152 <<
153 config XTENSA_VARIANT_NAME <<
154 string <<
155 default "dc232b" <<
156 default "dc233c" <<
157 default "fsf" <<
158 default XTENSA_VARIANT_CUSTOM_NAME <<
159 <<
160 config XTENSA_VARIANT_MMU <<
161 bool "Core variant has a Full MMU (TLB <<
162 depends on XTENSA_VARIANT_CUSTOM <<
163 default y <<
164 select MMU <<
165 help <<
166 Build a Conventional Kernel with ful <<
167 ie: it supports a TLB with auto-load <<
168 <<
169 config XTENSA_VARIANT_HAVE_PERF_EVENTS <<
170 bool "Core variant has Performance Mon <<
171 depends on XTENSA_VARIANT_CUSTOM <<
172 default n 1390 default n
>> 1391 select CPU_MIPSR2
>> 1392 select CPU_HAS_PREFETCH
>> 1393 depends on CPU_LOONGSON3
>> 1394 help
>> 1395 New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
>> 1396 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1397 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
>> 1398 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1399 Fast TLB refill support, etc.
>> 1400
>> 1401 This option enable those enhancements which are not probed at run
>> 1402 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1403 please say 'N' here. If you want a high-performance kernel to run on
>> 1404 new Loongson 3 machines only, please say 'Y' here.
>> 1405
>> 1406 config CPU_LOONGSON3_WORKAROUNDS
>> 1407 bool "Old Loongson 3 LLSC Workarounds"
>> 1408 default y if SMP
>> 1409 depends on CPU_LOONGSON3
>> 1410 help
>> 1411 Loongson 3 processors have the llsc issues which require workarounds.
>> 1412 Without workarounds the system may hang unexpectedly.
>> 1413
>> 1414 Newer Loongson 3 will fix these issues and no workarounds are needed.
>> 1415 The workarounds have no significant side effect on them but may
>> 1416 decrease the performance of the system so this option should be
>> 1417 disabled unless the kernel is intended to be run on old systems.
>> 1418
>> 1419 If unsure, please say Y.
>> 1420
>> 1421 config CPU_LOONGSON2E
>> 1422 bool "Loongson 2E"
>> 1423 depends on SYS_HAS_CPU_LOONGSON2E
>> 1424 select CPU_LOONGSON2
>> 1425 help
>> 1426 The Loongson 2E processor implements the MIPS III instruction set
>> 1427 with many extensions.
>> 1428
>> 1429 It has an internal FPGA northbridge, which is compatible to
>> 1430 bonito64.
>> 1431
>> 1432 config CPU_LOONGSON2F
>> 1433 bool "Loongson 2F"
>> 1434 depends on SYS_HAS_CPU_LOONGSON2F
>> 1435 select CPU_LOONGSON2
>> 1436 select GPIOLIB
>> 1437 help
>> 1438 The Loongson 2F processor implements the MIPS III instruction set
>> 1439 with many extensions.
>> 1440
>> 1441 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1442 have a similar programming interface with FPGA northbridge used in
>> 1443 Loongson2E.
>> 1444
>> 1445 config CPU_LOONGSON1B
>> 1446 bool "Loongson 1B"
>> 1447 depends on SYS_HAS_CPU_LOONGSON1B
>> 1448 select CPU_LOONGSON1
>> 1449 select LEDS_GPIO_REGISTER
>> 1450 help
>> 1451 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1452 Release 1 instruction set and part of the MIPS32 Release 2
>> 1453 instruction set.
>> 1454
>> 1455 config CPU_LOONGSON1C
>> 1456 bool "Loongson 1C"
>> 1457 depends on SYS_HAS_CPU_LOONGSON1C
>> 1458 select CPU_LOONGSON1
>> 1459 select LEDS_GPIO_REGISTER
>> 1460 help
>> 1461 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1462 Release 1 instruction set and part of the MIPS32 Release 2
>> 1463 instruction set.
>> 1464
>> 1465 config CPU_MIPS32_R1
>> 1466 bool "MIPS32 Release 1"
>> 1467 depends on SYS_HAS_CPU_MIPS32_R1
>> 1468 select CPU_HAS_PREFETCH
>> 1469 select CPU_HAS_LOAD_STORE_LR
>> 1470 select CPU_SUPPORTS_32BIT_KERNEL
>> 1471 select CPU_SUPPORTS_HIGHMEM
>> 1472 help
>> 1473 Choose this option to build a kernel for release 1 or later of the
>> 1474 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1475 MIPS processor are based on a MIPS32 processor. If you know the
>> 1476 specific type of processor in your system, choose those that one
>> 1477 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1478 Release 2 of the MIPS32 architecture is available since several
>> 1479 years so chances are you even have a MIPS32 Release 2 processor
>> 1480 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1481 performance.
>> 1482
>> 1483 config CPU_MIPS32_R2
>> 1484 bool "MIPS32 Release 2"
>> 1485 depends on SYS_HAS_CPU_MIPS32_R2
>> 1486 select CPU_HAS_PREFETCH
>> 1487 select CPU_HAS_LOAD_STORE_LR
>> 1488 select CPU_SUPPORTS_32BIT_KERNEL
>> 1489 select CPU_SUPPORTS_HIGHMEM
>> 1490 select CPU_SUPPORTS_MSA
>> 1491 select HAVE_KVM
>> 1492 help
>> 1493 Choose this option to build a kernel for release 2 or later of the
>> 1494 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1495 MIPS processor are based on a MIPS32 processor. If you know the
>> 1496 specific type of processor in your system, choose those that one
>> 1497 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1498
>> 1499 config CPU_MIPS32_R6
>> 1500 bool "MIPS32 Release 6"
>> 1501 depends on SYS_HAS_CPU_MIPS32_R6
>> 1502 select CPU_HAS_PREFETCH
>> 1503 select CPU_SUPPORTS_32BIT_KERNEL
>> 1504 select CPU_SUPPORTS_HIGHMEM
>> 1505 select CPU_SUPPORTS_MSA
>> 1506 select HAVE_KVM
>> 1507 select MIPS_O32_FP64_SUPPORT
>> 1508 help
>> 1509 Choose this option to build a kernel for release 6 or later of the
>> 1510 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1511 family, are based on a MIPS32r6 processor. If you own an older
>> 1512 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1513
>> 1514 config CPU_MIPS64_R1
>> 1515 bool "MIPS64 Release 1"
>> 1516 depends on SYS_HAS_CPU_MIPS64_R1
>> 1517 select CPU_HAS_PREFETCH
>> 1518 select CPU_HAS_LOAD_STORE_LR
>> 1519 select CPU_SUPPORTS_32BIT_KERNEL
>> 1520 select CPU_SUPPORTS_64BIT_KERNEL
>> 1521 select CPU_SUPPORTS_HIGHMEM
>> 1522 select CPU_SUPPORTS_HUGEPAGES
>> 1523 help
>> 1524 Choose this option to build a kernel for release 1 or later of the
>> 1525 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1526 MIPS processor are based on a MIPS64 processor. If you know the
>> 1527 specific type of processor in your system, choose those that one
>> 1528 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1529 Release 2 of the MIPS64 architecture is available since several
>> 1530 years so chances are you even have a MIPS64 Release 2 processor
>> 1531 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1532 performance.
>> 1533
>> 1534 config CPU_MIPS64_R2
>> 1535 bool "MIPS64 Release 2"
>> 1536 depends on SYS_HAS_CPU_MIPS64_R2
>> 1537 select CPU_HAS_PREFETCH
>> 1538 select CPU_HAS_LOAD_STORE_LR
>> 1539 select CPU_SUPPORTS_32BIT_KERNEL
>> 1540 select CPU_SUPPORTS_64BIT_KERNEL
>> 1541 select CPU_SUPPORTS_HIGHMEM
>> 1542 select CPU_SUPPORTS_HUGEPAGES
>> 1543 select CPU_SUPPORTS_MSA
>> 1544 select HAVE_KVM
>> 1545 help
>> 1546 Choose this option to build a kernel for release 2 or later of the
>> 1547 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1548 MIPS processor are based on a MIPS64 processor. If you know the
>> 1549 specific type of processor in your system, choose those that one
>> 1550 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1551
>> 1552 config CPU_MIPS64_R6
>> 1553 bool "MIPS64 Release 6"
>> 1554 depends on SYS_HAS_CPU_MIPS64_R6
>> 1555 select CPU_HAS_PREFETCH
>> 1556 select CPU_SUPPORTS_32BIT_KERNEL
>> 1557 select CPU_SUPPORTS_64BIT_KERNEL
>> 1558 select CPU_SUPPORTS_HIGHMEM
>> 1559 select CPU_SUPPORTS_HUGEPAGES
>> 1560 select CPU_SUPPORTS_MSA
>> 1561 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1562 select HAVE_KVM
>> 1563 help
>> 1564 Choose this option to build a kernel for release 6 or later of the
>> 1565 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1566 family, are based on a MIPS64r6 processor. If you own an older
>> 1567 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1568
>> 1569 config CPU_R3000
>> 1570 bool "R3000"
>> 1571 depends on SYS_HAS_CPU_R3000
>> 1572 select CPU_HAS_WB
>> 1573 select CPU_HAS_LOAD_STORE_LR
>> 1574 select CPU_SUPPORTS_32BIT_KERNEL
>> 1575 select CPU_SUPPORTS_HIGHMEM
>> 1576 help
>> 1577 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1578 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1579 *not* work on R4000 machines and vice versa. However, since most
>> 1580 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1581 might be a safe bet. If the resulting kernel does not work,
>> 1582 try to recompile with R3000.
>> 1583
>> 1584 config CPU_TX39XX
>> 1585 bool "R39XX"
>> 1586 depends on SYS_HAS_CPU_TX39XX
>> 1587 select CPU_SUPPORTS_32BIT_KERNEL
>> 1588 select CPU_HAS_LOAD_STORE_LR
>> 1589
>> 1590 config CPU_VR41XX
>> 1591 bool "R41xx"
>> 1592 depends on SYS_HAS_CPU_VR41XX
>> 1593 select CPU_SUPPORTS_32BIT_KERNEL
>> 1594 select CPU_SUPPORTS_64BIT_KERNEL
>> 1595 select CPU_HAS_LOAD_STORE_LR
>> 1596 help
>> 1597 The options selects support for the NEC VR4100 series of processors.
>> 1598 Only choose this option if you have one of these processors as a
>> 1599 kernel built with this option will not run on any other type of
>> 1600 processor or vice versa.
>> 1601
>> 1602 config CPU_R4300
>> 1603 bool "R4300"
>> 1604 depends on SYS_HAS_CPU_R4300
>> 1605 select CPU_SUPPORTS_32BIT_KERNEL
>> 1606 select CPU_SUPPORTS_64BIT_KERNEL
>> 1607 select CPU_HAS_LOAD_STORE_LR
>> 1608 help
>> 1609 MIPS Technologies R4300-series processors.
>> 1610
>> 1611 config CPU_R4X00
>> 1612 bool "R4x00"
>> 1613 depends on SYS_HAS_CPU_R4X00
>> 1614 select CPU_SUPPORTS_32BIT_KERNEL
>> 1615 select CPU_SUPPORTS_64BIT_KERNEL
>> 1616 select CPU_SUPPORTS_HUGEPAGES
>> 1617 select CPU_HAS_LOAD_STORE_LR
>> 1618 help
>> 1619 MIPS Technologies R4000-series processors other than 4300, including
>> 1620 the R4000, R4400, R4600, and 4700.
>> 1621
>> 1622 config CPU_TX49XX
>> 1623 bool "R49XX"
>> 1624 depends on SYS_HAS_CPU_TX49XX
>> 1625 select CPU_HAS_PREFETCH
>> 1626 select CPU_HAS_LOAD_STORE_LR
>> 1627 select CPU_SUPPORTS_32BIT_KERNEL
>> 1628 select CPU_SUPPORTS_64BIT_KERNEL
>> 1629 select CPU_SUPPORTS_HUGEPAGES
>> 1630
>> 1631 config CPU_R5000
>> 1632 bool "R5000"
>> 1633 depends on SYS_HAS_CPU_R5000
>> 1634 select CPU_SUPPORTS_32BIT_KERNEL
>> 1635 select CPU_SUPPORTS_64BIT_KERNEL
>> 1636 select CPU_SUPPORTS_HUGEPAGES
>> 1637 select CPU_HAS_LOAD_STORE_LR
>> 1638 help
>> 1639 MIPS Technologies R5000-series processors other than the Nevada.
>> 1640
>> 1641 config CPU_R5432
>> 1642 bool "R5432"
>> 1643 depends on SYS_HAS_CPU_R5432
>> 1644 select CPU_SUPPORTS_32BIT_KERNEL
>> 1645 select CPU_SUPPORTS_64BIT_KERNEL
>> 1646 select CPU_SUPPORTS_HUGEPAGES
>> 1647 select CPU_HAS_LOAD_STORE_LR
>> 1648
>> 1649 config CPU_R5500
>> 1650 bool "R5500"
>> 1651 depends on SYS_HAS_CPU_R5500
>> 1652 select CPU_SUPPORTS_32BIT_KERNEL
>> 1653 select CPU_SUPPORTS_64BIT_KERNEL
>> 1654 select CPU_SUPPORTS_HUGEPAGES
>> 1655 select CPU_HAS_LOAD_STORE_LR
>> 1656 help
>> 1657 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1658 instruction set.
>> 1659
>> 1660 config CPU_NEVADA
>> 1661 bool "RM52xx"
>> 1662 depends on SYS_HAS_CPU_NEVADA
>> 1663 select CPU_SUPPORTS_32BIT_KERNEL
>> 1664 select CPU_SUPPORTS_64BIT_KERNEL
>> 1665 select CPU_SUPPORTS_HUGEPAGES
>> 1666 select CPU_HAS_LOAD_STORE_LR
>> 1667 help
>> 1668 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1669
>> 1670 config CPU_R8000
>> 1671 bool "R8000"
>> 1672 depends on SYS_HAS_CPU_R8000
>> 1673 select CPU_HAS_PREFETCH
>> 1674 select CPU_HAS_LOAD_STORE_LR
>> 1675 select CPU_SUPPORTS_64BIT_KERNEL
>> 1676 help
>> 1677 MIPS Technologies R8000 processors. Note these processors are
>> 1678 uncommon and the support for them is incomplete.
>> 1679
>> 1680 config CPU_R10000
>> 1681 bool "R10000"
>> 1682 depends on SYS_HAS_CPU_R10000
>> 1683 select CPU_HAS_PREFETCH
>> 1684 select CPU_HAS_LOAD_STORE_LR
>> 1685 select CPU_SUPPORTS_32BIT_KERNEL
>> 1686 select CPU_SUPPORTS_64BIT_KERNEL
>> 1687 select CPU_SUPPORTS_HIGHMEM
>> 1688 select CPU_SUPPORTS_HUGEPAGES
>> 1689 help
>> 1690 MIPS Technologies R10000-series processors.
>> 1691
>> 1692 config CPU_RM7000
>> 1693 bool "RM7000"
>> 1694 depends on SYS_HAS_CPU_RM7000
>> 1695 select CPU_HAS_PREFETCH
>> 1696 select CPU_HAS_LOAD_STORE_LR
>> 1697 select CPU_SUPPORTS_32BIT_KERNEL
>> 1698 select CPU_SUPPORTS_64BIT_KERNEL
>> 1699 select CPU_SUPPORTS_HIGHMEM
>> 1700 select CPU_SUPPORTS_HUGEPAGES
>> 1701
>> 1702 config CPU_SB1
>> 1703 bool "SB1"
>> 1704 depends on SYS_HAS_CPU_SB1
>> 1705 select CPU_HAS_LOAD_STORE_LR
>> 1706 select CPU_SUPPORTS_32BIT_KERNEL
>> 1707 select CPU_SUPPORTS_64BIT_KERNEL
>> 1708 select CPU_SUPPORTS_HIGHMEM
>> 1709 select CPU_SUPPORTS_HUGEPAGES
>> 1710 select WEAK_ORDERING
>> 1711
>> 1712 config CPU_CAVIUM_OCTEON
>> 1713 bool "Cavium Octeon processor"
>> 1714 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1715 select CPU_HAS_PREFETCH
>> 1716 select CPU_HAS_LOAD_STORE_LR
>> 1717 select CPU_SUPPORTS_64BIT_KERNEL
>> 1718 select WEAK_ORDERING
>> 1719 select CPU_SUPPORTS_HIGHMEM
>> 1720 select CPU_SUPPORTS_HUGEPAGES
>> 1721 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1722 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1723 select MIPS_L1_CACHE_SHIFT_7
>> 1724 select HAVE_KVM
>> 1725 help
>> 1726 The Cavium Octeon processor is a highly integrated chip containing
>> 1727 many ethernet hardware widgets for networking tasks. The processor
>> 1728 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1729 Full details can be found at http://www.caviumnetworks.com.
>> 1730
>> 1731 config CPU_BMIPS
>> 1732 bool "Broadcom BMIPS"
>> 1733 depends on SYS_HAS_CPU_BMIPS
>> 1734 select CPU_MIPS32
>> 1735 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1736 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1737 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1738 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1739 select CPU_SUPPORTS_32BIT_KERNEL
>> 1740 select DMA_NONCOHERENT
>> 1741 select IRQ_MIPS_CPU
>> 1742 select SWAP_IO_SPACE
>> 1743 select WEAK_ORDERING
>> 1744 select CPU_SUPPORTS_HIGHMEM
>> 1745 select CPU_HAS_PREFETCH
>> 1746 select CPU_HAS_LOAD_STORE_LR
>> 1747 select CPU_SUPPORTS_CPUFREQ
>> 1748 select MIPS_EXTERNAL_TIMER
>> 1749 help
>> 1750 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1751
>> 1752 config CPU_XLR
>> 1753 bool "Netlogic XLR SoC"
>> 1754 depends on SYS_HAS_CPU_XLR
>> 1755 select CPU_HAS_LOAD_STORE_LR
>> 1756 select CPU_SUPPORTS_32BIT_KERNEL
>> 1757 select CPU_SUPPORTS_64BIT_KERNEL
>> 1758 select CPU_SUPPORTS_HIGHMEM
>> 1759 select CPU_SUPPORTS_HUGEPAGES
>> 1760 select WEAK_ORDERING
>> 1761 select WEAK_REORDERING_BEYOND_LLSC
>> 1762 help
>> 1763 Netlogic Microsystems XLR/XLS processors.
>> 1764
>> 1765 config CPU_XLP
>> 1766 bool "Netlogic XLP SoC"
>> 1767 depends on SYS_HAS_CPU_XLP
>> 1768 select CPU_SUPPORTS_32BIT_KERNEL
>> 1769 select CPU_SUPPORTS_64BIT_KERNEL
>> 1770 select CPU_SUPPORTS_HIGHMEM
>> 1771 select WEAK_ORDERING
>> 1772 select WEAK_REORDERING_BEYOND_LLSC
>> 1773 select CPU_HAS_PREFETCH
>> 1774 select CPU_HAS_LOAD_STORE_LR
>> 1775 select CPU_MIPSR2
>> 1776 select CPU_SUPPORTS_HUGEPAGES
>> 1777 select MIPS_ASID_BITS_VARIABLE
173 help 1778 help
174 Enable if core variant has Performan !! 1779 Netlogic Microsystems XLP processors.
175 External Registers Interface. !! 1780 endchoice
176 <<
177 If unsure, say N. <<
178 1781
179 config XTENSA_FAKE_NMI !! 1782 config CPU_MIPS32_3_5_FEATURES
180 bool "Treat PMM IRQ as NMI" !! 1783 bool "MIPS32 Release 3.5 Features"
181 depends on XTENSA_VARIANT_HAVE_PERF_EV !! 1784 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1785 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1786 help
>> 1787 Choose this option to build a kernel for release 2 or later of the
>> 1788 MIPS32 architecture including features from the 3.5 release such as
>> 1789 support for Enhanced Virtual Addressing (EVA).
>> 1790
>> 1791 config CPU_MIPS32_3_5_EVA
>> 1792 bool "Enhanced Virtual Addressing (EVA)"
>> 1793 depends on CPU_MIPS32_3_5_FEATURES
>> 1794 select EVA
>> 1795 default y
>> 1796 help
>> 1797 Choose this option if you want to enable the Enhanced Virtual
>> 1798 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1799 One of its primary benefits is an increase in the maximum size
>> 1800 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1801
>> 1802 config CPU_MIPS32_R5_FEATURES
>> 1803 bool "MIPS32 Release 5 Features"
>> 1804 depends on SYS_HAS_CPU_MIPS32_R5
>> 1805 depends on CPU_MIPS32_R2
>> 1806 help
>> 1807 Choose this option to build a kernel for release 2 or later of the
>> 1808 MIPS32 architecture including features from release 5 such as
>> 1809 support for Extended Physical Addressing (XPA).
>> 1810
>> 1811 config CPU_MIPS32_R5_XPA
>> 1812 bool "Extended Physical Addressing (XPA)"
>> 1813 depends on CPU_MIPS32_R5_FEATURES
>> 1814 depends on !EVA
>> 1815 depends on !PAGE_SIZE_4KB
>> 1816 depends on SYS_SUPPORTS_HIGHMEM
>> 1817 select XPA
>> 1818 select HIGHMEM
>> 1819 select PHYS_ADDR_T_64BIT
182 default n 1820 default n
183 help 1821 help
184 If PMM IRQ is the only IRQ at EXCM l !! 1822 Choose this option if you want to enable the Extended Physical
185 treat it as NMI, which improves accu !! 1823 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1824 benefit is to increase physical addressing equal to or greater
>> 1825 than 40 bits. Note that this has the side effect of turning on
>> 1826 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1827 If unsure, say 'N' here.
186 1828
187 If there are other interrupts at or !! 1829 if CPU_LOONGSON2F
188 but not above the EXCM level, PMM IR !! 1830 config CPU_NOP_WORKAROUNDS
189 but only if these IRQs are not used. !! 1831 bool
190 saying that this is not safe, and a <<
191 actually fire. <<
192 1832
193 If unsure, say N. !! 1833 config CPU_JUMP_WORKAROUNDS
>> 1834 bool
194 1835
195 config PFAULT !! 1836 config CPU_LOONGSON2F_WORKAROUNDS
196 bool "Handle protection faults" if EXP !! 1837 bool "Loongson 2F Workarounds"
197 default y 1838 default y
>> 1839 select CPU_NOP_WORKAROUNDS
>> 1840 select CPU_JUMP_WORKAROUNDS
198 help 1841 help
199 Handle protection faults. MMU config !! 1842 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
200 noMMU configurations may disable it !! 1843 require workarounds. Without workarounds the system may hang
201 generates protection faults or fault !! 1844 unexpectedly. For more information please refer to the gas
>> 1845 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1846
>> 1847 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1848 are needed. The workarounds have no significant side effect on them
>> 1849 but may decrease the performance of the system so this option should
>> 1850 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1851 systems.
202 1852
203 If unsure, say Y. !! 1853 If unsure, please say Y.
>> 1854 endif # CPU_LOONGSON2F
204 1855
205 config XTENSA_UNALIGNED_USER !! 1856 config SYS_SUPPORTS_ZBOOT
206 bool "Unaligned memory access in user !! 1857 bool
207 help !! 1858 select HAVE_KERNEL_GZIP
208 The Xtensa architecture currently do !! 1859 select HAVE_KERNEL_BZIP2
209 memory accesses in hardware but thro !! 1860 select HAVE_KERNEL_LZ4
210 Per default, unaligned memory access !! 1861 select HAVE_KERNEL_LZMA
>> 1862 select HAVE_KERNEL_LZO
>> 1863 select HAVE_KERNEL_XZ
211 1864
212 Say Y here to enable unaligned memor !! 1865 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1866 bool
>> 1867 select SYS_SUPPORTS_ZBOOT
213 1868
214 config XTENSA_LOAD_STORE !! 1869 config SYS_SUPPORTS_ZBOOT_UART_PROM
215 bool "Load/store exception handler for !! 1870 bool
216 help !! 1871 select SYS_SUPPORTS_ZBOOT
217 The Xtensa architecture only allows <<
218 instruction bus with l32r and l32i i <<
219 instructions raise an exception with <<
220 This makes it hard to use some confi <<
221 literals in FLASH memory attached to <<
222 1872
223 Say Y here to enable exception handl !! 1873 config CPU_LOONGSON2
224 byte and 2-byte access to memory att !! 1874 bool
>> 1875 select CPU_SUPPORTS_32BIT_KERNEL
>> 1876 select CPU_SUPPORTS_64BIT_KERNEL
>> 1877 select CPU_SUPPORTS_HIGHMEM
>> 1878 select CPU_SUPPORTS_HUGEPAGES
>> 1879 select ARCH_HAS_PHYS_TO_DMA
>> 1880 select CPU_HAS_LOAD_STORE_LR
225 1881
226 config HAVE_SMP !! 1882 config CPU_LOONGSON1
227 bool "System Supports SMP (MX)" !! 1883 bool
228 depends on XTENSA_VARIANT_CUSTOM !! 1884 select CPU_MIPS32
229 select XTENSA_MX !! 1885 select CPU_MIPSR2
230 help !! 1886 select CPU_HAS_PREFETCH
231 This option is used to indicate that !! 1887 select CPU_HAS_LOAD_STORE_LR
232 supports Multiprocessing. Multiproce !! 1888 select CPU_SUPPORTS_32BIT_KERNEL
233 the CPU core definition and currentl !! 1889 select CPU_SUPPORTS_HIGHMEM
>> 1890 select CPU_SUPPORTS_CPUFREQ
234 1891
235 Multiprocessor support is implemente !! 1892 config CPU_BMIPS32_3300
236 interrupt controllers. !! 1893 select SMP_UP if SMP
>> 1894 bool
237 1895
238 The MX interrupt distributer adds In !! 1896 config CPU_BMIPS4350
239 and causes the IRQ numbers to be inc !! 1897 bool
240 like the open cores ethernet driver !! 1898 select SYS_SUPPORTS_SMP
>> 1899 select SYS_SUPPORTS_HOTPLUG_CPU
241 1900
242 You still have to select "Enable SMP !! 1901 config CPU_BMIPS4380
>> 1902 bool
>> 1903 select MIPS_L1_CACHE_SHIFT_6
>> 1904 select SYS_SUPPORTS_SMP
>> 1905 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1906 select CPU_HAS_RIXI
243 1907
244 config SMP !! 1908 config CPU_BMIPS5000
245 bool "Enable Symmetric multi-processin !! 1909 bool
246 depends on HAVE_SMP !! 1910 select MIPS_CPU_SCACHE
247 select GENERIC_SMP_IDLE_THREAD !! 1911 select MIPS_L1_CACHE_SHIFT_7
248 help !! 1912 select SYS_SUPPORTS_SMP
249 Enabled SMP Software; allows more th !! 1913 select SYS_SUPPORTS_HOTPLUG_CPU
250 to be activated during startup. !! 1914 select CPU_HAS_RIXI
251 1915
252 config NR_CPUS !! 1916 config SYS_HAS_CPU_LOONGSON3
253 depends on SMP !! 1917 bool
254 int "Maximum number of CPUs (2-32)" !! 1918 select CPU_SUPPORTS_CPUFREQ
255 range 2 32 !! 1919 select CPU_HAS_RIXI
256 default "4" <<
257 1920
258 config HOTPLUG_CPU !! 1921 config SYS_HAS_CPU_LOONGSON2E
259 bool "Enable CPU hotplug support" !! 1922 bool
260 depends on SMP !! 1923
>> 1924 config SYS_HAS_CPU_LOONGSON2F
>> 1925 bool
>> 1926 select CPU_SUPPORTS_CPUFREQ
>> 1927 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1928 select CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 1929
>> 1930 config SYS_HAS_CPU_LOONGSON1B
>> 1931 bool
>> 1932
>> 1933 config SYS_HAS_CPU_LOONGSON1C
>> 1934 bool
>> 1935
>> 1936 config SYS_HAS_CPU_MIPS32_R1
>> 1937 bool
>> 1938
>> 1939 config SYS_HAS_CPU_MIPS32_R2
>> 1940 bool
>> 1941
>> 1942 config SYS_HAS_CPU_MIPS32_R3_5
>> 1943 bool
>> 1944
>> 1945 config SYS_HAS_CPU_MIPS32_R5
>> 1946 bool
>> 1947 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1948
>> 1949 config SYS_HAS_CPU_MIPS32_R6
>> 1950 bool
>> 1951 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1952
>> 1953 config SYS_HAS_CPU_MIPS64_R1
>> 1954 bool
>> 1955
>> 1956 config SYS_HAS_CPU_MIPS64_R2
>> 1957 bool
>> 1958
>> 1959 config SYS_HAS_CPU_MIPS64_R6
>> 1960 bool
>> 1961 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1962
>> 1963 config SYS_HAS_CPU_R3000
>> 1964 bool
>> 1965
>> 1966 config SYS_HAS_CPU_TX39XX
>> 1967 bool
>> 1968
>> 1969 config SYS_HAS_CPU_VR41XX
>> 1970 bool
>> 1971
>> 1972 config SYS_HAS_CPU_R4300
>> 1973 bool
>> 1974
>> 1975 config SYS_HAS_CPU_R4X00
>> 1976 bool
>> 1977
>> 1978 config SYS_HAS_CPU_TX49XX
>> 1979 bool
>> 1980
>> 1981 config SYS_HAS_CPU_R5000
>> 1982 bool
>> 1983
>> 1984 config SYS_HAS_CPU_R5432
>> 1985 bool
>> 1986
>> 1987 config SYS_HAS_CPU_R5500
>> 1988 bool
>> 1989
>> 1990 config SYS_HAS_CPU_NEVADA
>> 1991 bool
>> 1992
>> 1993 config SYS_HAS_CPU_R8000
>> 1994 bool
>> 1995
>> 1996 config SYS_HAS_CPU_R10000
>> 1997 bool
>> 1998 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1999
>> 2000 config SYS_HAS_CPU_RM7000
>> 2001 bool
>> 2002
>> 2003 config SYS_HAS_CPU_SB1
>> 2004 bool
>> 2005
>> 2006 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 2007 bool
>> 2008
>> 2009 config SYS_HAS_CPU_BMIPS
>> 2010 bool
>> 2011
>> 2012 config SYS_HAS_CPU_BMIPS32_3300
>> 2013 bool
>> 2014 select SYS_HAS_CPU_BMIPS
>> 2015
>> 2016 config SYS_HAS_CPU_BMIPS4350
>> 2017 bool
>> 2018 select SYS_HAS_CPU_BMIPS
>> 2019
>> 2020 config SYS_HAS_CPU_BMIPS4380
>> 2021 bool
>> 2022 select SYS_HAS_CPU_BMIPS
>> 2023
>> 2024 config SYS_HAS_CPU_BMIPS5000
>> 2025 bool
>> 2026 select SYS_HAS_CPU_BMIPS
>> 2027 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 2028
>> 2029 config SYS_HAS_CPU_XLR
>> 2030 bool
>> 2031
>> 2032 config SYS_HAS_CPU_XLP
>> 2033 bool
>> 2034
>> 2035 #
>> 2036 # CPU may reorder R->R, R->W, W->R, W->W
>> 2037 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2038 #
>> 2039 config WEAK_ORDERING
>> 2040 bool
>> 2041
>> 2042 #
>> 2043 # CPU may reorder reads and writes beyond LL/SC
>> 2044 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 2045 #
>> 2046 config WEAK_REORDERING_BEYOND_LLSC
>> 2047 bool
>> 2048 endmenu
>> 2049
>> 2050 #
>> 2051 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2052 #
>> 2053 config CPU_MIPS32
>> 2054 bool
>> 2055 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 2056
>> 2057 config CPU_MIPS64
>> 2058 bool
>> 2059 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
>> 2060
>> 2061 #
>> 2062 # These indicate the revision of the architecture
>> 2063 #
>> 2064 config CPU_MIPSR1
>> 2065 bool
>> 2066 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 2067
>> 2068 config CPU_MIPSR2
>> 2069 bool
>> 2070 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2071 select CPU_HAS_RIXI
>> 2072 select MIPS_SPRAM
>> 2073
>> 2074 config CPU_MIPSR6
>> 2075 bool
>> 2076 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2077 select CPU_HAS_RIXI
>> 2078 select HAVE_ARCH_BITREVERSE
>> 2079 select MIPS_ASID_BITS_VARIABLE
>> 2080 select MIPS_CRC_SUPPORT
>> 2081 select MIPS_SPRAM
>> 2082
>> 2083 config TARGET_ISA_REV
>> 2084 int
>> 2085 default 1 if CPU_MIPSR1
>> 2086 default 2 if CPU_MIPSR2
>> 2087 default 6 if CPU_MIPSR6
>> 2088 default 0
261 help 2089 help
262 Say Y here to allow turning CPUs off !! 2090 Reflects the ISA revision being targeted by the kernel build. This
263 controlled through /sys/devices/syst !! 2091 is effectively the Kconfig equivalent of MIPS_ISA_REV.
264 2092
265 Say N if you want to disable CPU hot !! 2093 config EVA
>> 2094 bool
266 2095
267 config SECONDARY_RESET_VECTOR !! 2096 config XPA
268 bool "Secondary cores use alternative !! 2097 bool
269 default y !! 2098
270 depends on HAVE_SMP !! 2099 config SYS_SUPPORTS_32BIT_KERNEL
>> 2100 bool
>> 2101 config SYS_SUPPORTS_64BIT_KERNEL
>> 2102 bool
>> 2103 config CPU_SUPPORTS_32BIT_KERNEL
>> 2104 bool
>> 2105 config CPU_SUPPORTS_64BIT_KERNEL
>> 2106 bool
>> 2107 config CPU_SUPPORTS_CPUFREQ
>> 2108 bool
>> 2109 config CPU_SUPPORTS_ADDRWINCFG
>> 2110 bool
>> 2111 config CPU_SUPPORTS_HUGEPAGES
>> 2112 bool
>> 2113 config CPU_SUPPORTS_UNCACHED_ACCELERATED
>> 2114 bool
>> 2115 config MIPS_PGD_C0_CONTEXT
>> 2116 bool
>> 2117 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
>> 2118
>> 2119 #
>> 2120 # Set to y for ptrace access to watch registers.
>> 2121 #
>> 2122 config HARDWARE_WATCHPOINTS
>> 2123 bool
>> 2124 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
>> 2125
>> 2126 menu "Kernel type"
>> 2127
>> 2128 choice
>> 2129 prompt "Kernel code model"
271 help 2130 help
272 Secondary cores may be configured to !! 2131 You should only select this option if you have a workload that
273 or all cores may use primary reset v !! 2132 actually benefits from 64-bit processing or if your machine has
274 Say Y here to supply handler for the !! 2133 large memory. You will only be presented a single option in this
>> 2134 menu if your system does not support both 32-bit and 64-bit kernels.
275 2135
276 config FAST_SYSCALL_XTENSA !! 2136 config 32BIT
277 bool "Enable fast atomic syscalls" !! 2137 bool "32-bit kernel"
278 default n !! 2138 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2139 select TRAD_SIGNALS
279 help 2140 help
280 fast_syscall_xtensa is a syscall tha !! 2141 Select this option if you want to build a 32-bit kernel.
281 on UP kernel when processor has no s <<
282 2142
283 This syscall is deprecated. It may h !! 2143 config 64BIT
284 invalid arguments. It is provided on !! 2144 bool "64-bit kernel"
285 Only enable it if your userspace sof !! 2145 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
>> 2146 help
>> 2147 Select this option if you want to build a 64-bit kernel.
286 2148
287 If unsure, say N. !! 2149 endchoice
288 2150
289 config FAST_SYSCALL_SPILL_REGISTERS !! 2151 config KVM_GUEST
290 bool "Enable spill registers syscall" !! 2152 bool "KVM Guest Kernel"
291 default n !! 2153 depends on BROKEN_ON_SMP
>> 2154 help
>> 2155 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2156 mode.
>> 2157
>> 2158 config KVM_GUEST_TIMER_FREQ
>> 2159 int "Count/Compare Timer Frequency (MHz)"
>> 2160 depends on KVM_GUEST
>> 2161 default 100
292 help 2162 help
293 fast_syscall_spill_registers is a sy !! 2163 Set this to non-zero if building a guest kernel for KVM to skip RTC
294 register windows of a calling usersp !! 2164 emulation when determining guest CPU Frequency. Instead, the guest's
295 !! 2165 timer frequency is specified directly.
296 This syscall is deprecated. It may h !! 2166
297 invalid arguments. It is provided on !! 2167 config MIPS_VA_BITS_48
298 Only enable it if your userspace sof !! 2168 bool "48 bits virtual memory"
>> 2169 depends on 64BIT
>> 2170 help
>> 2171 Support a maximum at least 48 bits of application virtual
>> 2172 memory. Default is 40 bits or less, depending on the CPU.
>> 2173 For page sizes 16k and above, this option results in a small
>> 2174 memory overhead for page tables. For 4k page size, a fourth
>> 2175 level of page tables is added which imposes both a memory
>> 2176 overhead as well as slower TLB fault handling.
299 2177
300 If unsure, say N. 2178 If unsure, say N.
301 2179
302 choice 2180 choice
303 prompt "Kernel ABI" !! 2181 prompt "Kernel page size"
304 default KERNEL_ABI_DEFAULT !! 2182 default PAGE_SIZE_4KB
305 help !! 2183
306 Select ABI for the kernel code. This !! 2184 config PAGE_SIZE_4KB
307 supported userspace ABI and any comb !! 2185 bool "4kB"
308 kernel/userspace ABI is possible and !! 2186 depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
309 !! 2187 help
310 In case both kernel and userspace su !! 2188 This option select the standard 4kB Linux page size. On some
311 all register windows support code wi !! 2189 R3000-family processors this is the only available page size. Using
312 build. !! 2190 4kB page size will minimize memory consumption and is therefore
313 !! 2191 recommended for low memory systems.
314 If unsure, choose the default ABI. !! 2192
315 !! 2193 config PAGE_SIZE_8KB
316 config KERNEL_ABI_DEFAULT !! 2194 bool "8kB"
317 bool "Default ABI" !! 2195 depends on CPU_R8000 || CPU_CAVIUM_OCTEON
318 help !! 2196 depends on !MIPS_VA_BITS_48
319 Select this option to compile kernel !! 2197 help
320 selected for the toolchain. !! 2198 Using 8kB page size will result in higher performance kernel at
321 Normally cores with windowed registe !! 2199 the price of higher memory consumption. This option is available
322 cores without it use call0 ABI. !! 2200 only on R8000 and cnMIPS processors. Note that you will need a
323 !! 2201 suitable Linux distribution to support this.
324 config KERNEL_ABI_CALL0 !! 2202
325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI !! 2203 config PAGE_SIZE_16KB
326 help !! 2204 bool "16kB"
327 Select this option to compile kernel !! 2205 depends on !CPU_R3000 && !CPU_TX39XX
328 toolchain that defaults to windowed !! 2206 help
329 When this option is not selected the !! 2207 Using 16kB page size will result in higher performance kernel at
330 be used for the kernel code. !! 2208 the price of higher memory consumption. This option is available on
>> 2209 all non-R3000 family processors. Note that you will need a suitable
>> 2210 Linux distribution to support this.
>> 2211
>> 2212 config PAGE_SIZE_32KB
>> 2213 bool "32kB"
>> 2214 depends on CPU_CAVIUM_OCTEON
>> 2215 depends on !MIPS_VA_BITS_48
>> 2216 help
>> 2217 Using 32kB page size will result in higher performance kernel at
>> 2218 the price of higher memory consumption. This option is available
>> 2219 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2220 distribution to support this.
>> 2221
>> 2222 config PAGE_SIZE_64KB
>> 2223 bool "64kB"
>> 2224 depends on !CPU_R3000 && !CPU_TX39XX
>> 2225 help
>> 2226 Using 64kB page size will result in higher performance kernel at
>> 2227 the price of higher memory consumption. This option is available on
>> 2228 all non-R3000 family processor. Not that at the time of this
>> 2229 writing this option is still high experimental.
331 2230
332 endchoice 2231 endchoice
333 2232
334 config USER_ABI_CALL0 !! 2233 config FORCE_MAX_ZONEORDER
>> 2234 int "Maximum zone order"
>> 2235 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2236 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2237 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2238 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2239 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2240 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2241 range 11 64
>> 2242 default "11"
>> 2243 help
>> 2244 The kernel memory allocator divides physically contiguous memory
>> 2245 blocks into "zones", where each zone is a power of two number of
>> 2246 pages. This option selects the largest power of two that the kernel
>> 2247 keeps in the memory allocator. If you need to allocate very large
>> 2248 blocks of physically contiguous memory, then you may need to
>> 2249 increase this value.
>> 2250
>> 2251 This config option is actually maximum order plus one. For example,
>> 2252 a value of 11 means that the largest free memory block is 2^10 pages.
>> 2253
>> 2254 The page size is not necessarily 4KB. Keep this in mind
>> 2255 when choosing a value for this option.
>> 2256
>> 2257 config BOARD_SCACHE
335 bool 2258 bool
336 2259
337 choice !! 2260 config IP22_CPU_SCACHE
338 prompt "Userspace ABI" !! 2261 bool
339 default USER_ABI_DEFAULT !! 2262 select BOARD_SCACHE
340 help <<
341 Select supported userspace ABI. <<
342 2263
343 If unsure, choose the default ABI. !! 2264 #
>> 2265 # Support for a MIPS32 / MIPS64 style S-caches
>> 2266 #
>> 2267 config MIPS_CPU_SCACHE
>> 2268 bool
>> 2269 select BOARD_SCACHE
344 2270
345 config USER_ABI_DEFAULT !! 2271 config R5000_CPU_SCACHE
346 bool "Default ABI only" !! 2272 bool
347 help !! 2273 select BOARD_SCACHE
348 Assume default userspace ABI. For XE <<
349 call0 ABI binaries may be run on suc <<
350 will not work correctly for them. <<
351 2274
352 config USER_ABI_CALL0_ONLY !! 2275 config RM7000_CPU_SCACHE
353 bool "Call0 ABI only" !! 2276 bool
354 select USER_ABI_CALL0 !! 2277 select BOARD_SCACHE
>> 2278
>> 2279 config SIBYTE_DMA_PAGEOPS
>> 2280 bool "Use DMA to clear/copy pages"
>> 2281 depends on CPU_SB1
355 help 2282 help
356 Select this option to support only c !! 2283 Instead of using the CPU to zero and copy pages, use a Data Mover
357 Windowed ABI binaries will crash wit !! 2284 channel. These DMA channels are otherwise unused by the standard
358 an illegal instruction exception on !! 2285 SiByte Linux port. Seems to give a small performance benefit.
359 2286
360 Choose this option if you're plannin !! 2287 config CPU_HAS_PREFETCH
361 built with call0 ABI. !! 2288 bool
>> 2289
>> 2290 config CPU_GENERIC_DUMP_TLB
>> 2291 bool
>> 2292 default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
362 2293
363 config USER_ABI_CALL0_PROBE !! 2294 config MIPS_FP_SUPPORT
364 bool "Support both windowed and call0 !! 2295 bool "Floating Point support" if EXPERT
365 select USER_ABI_CALL0 !! 2296 default y
366 help 2297 help
367 Select this option to support both w !! 2298 Select y to include support for floating point in the kernel
368 ABIs. When enabled all processes are !! 2299 including initialization of FPU hardware, FP context save & restore
369 and a fast user exception handler fo !! 2300 and emulation of an FPU where necessary. Without this support any
370 used to turn on PS.WOE bit on the fi !! 2301 userland program attempting to use floating point instructions will
371 the userspace. !! 2302 receive a SIGILL.
372 2303
373 This option should be enabled for th !! 2304 If you know that your userland will not attempt to use floating point
374 both call0 and windowed ABIs in user !! 2305 instructions then you can say n here to shrink the kernel a little.
375 2306
376 Note that Xtensa ISA does not guaran !! 2307 If unsure, say y.
377 raise an illegal instruction excepti <<
378 PS.WOE is disabled, check whether th <<
379 2308
380 endchoice !! 2309 config CPU_R2300_FPU
>> 2310 bool
>> 2311 depends on MIPS_FP_SUPPORT
>> 2312 default y if CPU_R3000 || CPU_TX39XX
381 2313
382 endmenu !! 2314 config CPU_R4K_FPU
>> 2315 bool
>> 2316 depends on MIPS_FP_SUPPORT
>> 2317 default y if !CPU_R2300_FPU
383 2318
384 config XTENSA_CALIBRATE_CCOUNT !! 2319 config CPU_R4K_CACHE_TLB
385 def_bool n !! 2320 bool
>> 2321 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
>> 2322
>> 2323 config MIPS_MT_SMP
>> 2324 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2325 default y
>> 2326 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2327 select CPU_MIPSR2_IRQ_VI
>> 2328 select CPU_MIPSR2_IRQ_EI
>> 2329 select SYNC_R4K
>> 2330 select MIPS_MT
>> 2331 select SMP
>> 2332 select SMP_UP
>> 2333 select SYS_SUPPORTS_SMP
>> 2334 select SYS_SUPPORTS_SCHED_SMT
>> 2335 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2336 help
>> 2337 This is a kernel model which is known as SMVP. This is supported
>> 2338 on cores with the MT ASE and uses the available VPEs to implement
>> 2339 virtual processors which supports SMP. This is equivalent to the
>> 2340 Intel Hyperthreading feature. For further information go to
>> 2341 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2342
>> 2343 config MIPS_MT
>> 2344 bool
>> 2345
>> 2346 config SCHED_SMT
>> 2347 bool "SMT (multithreading) scheduler support"
>> 2348 depends on SYS_SUPPORTS_SCHED_SMT
>> 2349 default n
386 help 2350 help
387 On some platforms (XT2000, for examp !! 2351 SMT scheduler support improves the CPU scheduler's decision making
388 vary. The frequency can be determin !! 2352 when dealing with MIPS MT enabled cores at a cost of slightly
389 against a well known, fixed frequenc !! 2353 increased overhead in some places. If unsure say N here.
390 2354
391 config SERIAL_CONSOLE !! 2355 config SYS_SUPPORTS_SCHED_SMT
392 def_bool n !! 2356 bool
393 2357
394 config PLATFORM_HAVE_XIP !! 2358 config SYS_SUPPORTS_MULTITHREADING
395 def_bool n !! 2359 bool
396 2360
397 menu "Platform options" !! 2361 config MIPS_MT_FPAFF
>> 2362 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2363 default y
>> 2364 depends on MIPS_MT_SMP
398 2365
399 choice !! 2366 config MIPSR2_TO_R6_EMULATOR
400 prompt "Xtensa System Type" !! 2367 bool "MIPS R2-to-R6 emulator"
401 default XTENSA_PLATFORM_ISS !! 2368 depends on CPU_MIPSR6
>> 2369 depends on MIPS_FP_SUPPORT
>> 2370 default y
>> 2371 help
>> 2372 Choose this option if you want to run non-R6 MIPS userland code.
>> 2373 Even if you say 'Y' here, the emulator will still be disabled by
>> 2374 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2375 The only reason this is a build-time option is to save ~14K from the
>> 2376 final kernel image.
402 2377
403 config XTENSA_PLATFORM_ISS !! 2378 config SYS_SUPPORTS_VPE_LOADER
404 bool "ISS" !! 2379 bool
405 select XTENSA_CALIBRATE_CCOUNT !! 2380 depends on SYS_SUPPORTS_MULTITHREADING
406 select SERIAL_CONSOLE <<
407 help <<
408 ISS is an acronym for Tensilica's In <<
409 <<
410 config XTENSA_PLATFORM_XT2000 <<
411 bool "XT2000" <<
412 help <<
413 XT2000 is the name of Tensilica's fe <<
414 This hardware is capable of running <<
415 <<
416 config XTENSA_PLATFORM_XTFPGA <<
417 bool "XTFPGA" <<
418 select ETHOC if ETHERNET <<
419 select PLATFORM_WANT_DEFAULT_MEM if !M <<
420 select SERIAL_CONSOLE <<
421 select XTENSA_CALIBRATE_CCOUNT <<
422 select PLATFORM_HAVE_XIP <<
423 help 2381 help
424 XTFPGA is the name of Tensilica boar !! 2382 Indicates that the platform supports the VPE loader, and provides
425 This hardware is capable of running !! 2383 physical_memsize.
426 2384
427 endchoice !! 2385 config MIPS_VPE_LOADER
>> 2386 bool "VPE loader support."
>> 2387 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2388 select CPU_MIPSR2_IRQ_VI
>> 2389 select CPU_MIPSR2_IRQ_EI
>> 2390 select MIPS_MT
>> 2391 help
>> 2392 Includes a loader for loading an elf relocatable object
>> 2393 onto another VPE and running it.
428 2394
429 config PLATFORM_NR_IRQS !! 2395 config MIPS_VPE_LOADER_CMP
430 int !! 2396 bool
431 default 3 if XTENSA_PLATFORM_XT2000 !! 2397 default "y"
432 default 0 !! 2398 depends on MIPS_VPE_LOADER && MIPS_CMP
433 2399
434 config XTENSA_CPU_CLOCK !! 2400 config MIPS_VPE_LOADER_MT
435 int "CPU clock rate [MHz]" !! 2401 bool
436 depends on !XTENSA_CALIBRATE_CCOUNT !! 2402 default "y"
437 default 16 !! 2403 depends on MIPS_VPE_LOADER && !MIPS_CMP
438 2404
439 config GENERIC_CALIBRATE_DELAY !! 2405 config MIPS_VPE_LOADER_TOM
440 bool "Auto calibration of the BogoMIPS !! 2406 bool "Load VPE program into memory hidden from linux"
>> 2407 depends on MIPS_VPE_LOADER
>> 2408 default y
441 help 2409 help
442 The BogoMIPS value can easily be der !! 2410 The loader can use memory that is present but has been hidden from
>> 2411 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2412 you to ensure the amount you put in the option and the space your
>> 2413 program requires is less or equal to the amount physically present.
>> 2414
>> 2415 config MIPS_VPE_APSP_API
>> 2416 bool "Enable support for AP/SP API (RTLX)"
>> 2417 depends on MIPS_VPE_LOADER
443 2418
444 config CMDLINE_BOOL !! 2419 config MIPS_VPE_APSP_API_CMP
445 bool "Default bootloader kernel argume !! 2420 bool
>> 2421 default "y"
>> 2422 depends on MIPS_VPE_APSP_API && MIPS_CMP
446 2423
447 config CMDLINE !! 2424 config MIPS_VPE_APSP_API_MT
448 string "Initial kernel command string" !! 2425 bool
449 depends on CMDLINE_BOOL !! 2426 default "y"
450 default "console=ttyS0,38400 root=/dev !! 2427 depends on MIPS_VPE_APSP_API && !MIPS_CMP
451 help <<
452 On some architectures (EBSA110 and C <<
453 for the boot loader to pass argument <<
454 architectures, you should supply som <<
455 time by entering them here. As a min <<
456 memory size and the root device (e.g <<
457 2428
458 config USE_OF !! 2429 config MIPS_CMP
459 bool "Flattened Device Tree support" !! 2430 bool "MIPS CMP framework support (DEPRECATED)"
460 select OF !! 2431 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
461 select OF_EARLY_FLATTREE !! 2432 select SMP
>> 2433 select SYNC_R4K
>> 2434 select SYS_SUPPORTS_SMP
>> 2435 select WEAK_ORDERING
>> 2436 default n
462 help 2437 help
463 Include support for flattened device !! 2438 Select this if you are using a bootloader which implements the "CMP
>> 2439 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2440 its ability to start secondary CPUs.
>> 2441
>> 2442 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2443 instead of this.
>> 2444
>> 2445 config MIPS_CPS
>> 2446 bool "MIPS Coherent Processing System support"
>> 2447 depends on SYS_SUPPORTS_MIPS_CPS
>> 2448 select MIPS_CM
>> 2449 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2450 select SMP
>> 2451 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2452 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2453 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2454 select SYS_SUPPORTS_SMP
>> 2455 select WEAK_ORDERING
>> 2456 help
>> 2457 Select this if you wish to run an SMP kernel across multiple cores
>> 2458 within a MIPS Coherent Processing System. When this option is
>> 2459 enabled the kernel will probe for other cores and boot them with
>> 2460 no external assistance. It is safe to enable this when hardware
>> 2461 support is unavailable.
>> 2462
>> 2463 config MIPS_CPS_PM
>> 2464 depends on MIPS_CPS
>> 2465 bool
>> 2466
>> 2467 config MIPS_CM
>> 2468 bool
>> 2469 select MIPS_CPC
464 2470
465 config BUILTIN_DTB_SOURCE !! 2471 config MIPS_CPC
466 string "DTB to build into the kernel i !! 2472 bool
467 depends on OF <<
468 2473
469 config PARSE_BOOTPARAM !! 2474 config SB1_PASS_2_WORKAROUNDS
470 bool "Parse bootparam block" !! 2475 bool
>> 2476 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2477 default y
>> 2478
>> 2479 config SB1_PASS_2_1_WORKAROUNDS
>> 2480 bool
>> 2481 depends on CPU_SB1 && CPU_SB1_PASS_2
471 default y 2482 default y
472 help <<
473 Parse parameters passed to the kerne <<
474 be disabled if the kernel is known t <<
475 2483
476 If unsure, say Y. <<
477 2484
478 choice 2485 choice
479 prompt "Semihosting interface" !! 2486 prompt "SmartMIPS or microMIPS ASE support"
480 default XTENSA_SIMCALL_ISS <<
481 depends on XTENSA_PLATFORM_ISS <<
482 help <<
483 Choose semihosting interface that wi <<
484 block device and networking. <<
485 2487
486 config XTENSA_SIMCALL_ISS !! 2488 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
487 bool "simcall" !! 2489 bool "None"
488 help 2490 help
489 Use simcall instruction. simcall is !! 2491 Select this if you want neither microMIPS nor SmartMIPS support
490 it does nothing on hardware. <<
491 2492
492 config XTENSA_SIMCALL_GDBIO !! 2493 config CPU_HAS_SMARTMIPS
493 bool "GDBIO" !! 2494 depends on SYS_SUPPORTS_SMARTMIPS
>> 2495 bool "SmartMIPS"
>> 2496 help
>> 2497 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2498 increased security at both hardware and software level for
>> 2499 smartcards. Enabling this option will allow proper use of the
>> 2500 SmartMIPS instructions by Linux applications. However a kernel with
>> 2501 this option will not work on a MIPS core without SmartMIPS core. If
>> 2502 you don't know you probably don't have SmartMIPS and should say N
>> 2503 here.
>> 2504
>> 2505 config CPU_MICROMIPS
>> 2506 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2507 bool "microMIPS"
494 help 2508 help
495 Use break instruction. It is availab !! 2509 When this option is enabled the kernel will be built using the
496 is attached to it via JTAG. !! 2510 microMIPS ISA
497 2511
498 endchoice 2512 endchoice
499 2513
500 config BLK_DEV_SIMDISK !! 2514 config CPU_HAS_MSA
501 tristate "Host file-based simulated bl !! 2515 bool "Support for the MIPS SIMD Architecture"
502 default n !! 2516 depends on CPU_SUPPORTS_MSA
503 depends on XTENSA_PLATFORM_ISS && BLOC !! 2517 depends on MIPS_FP_SUPPORT
>> 2518 depends on 64BIT || MIPS_O32_FP64_SUPPORT
>> 2519 help
>> 2520 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2521 and a set of SIMD instructions to operate on them. When this option
>> 2522 is enabled the kernel will support allocating & switching MSA
>> 2523 vector register contexts. If you know that your kernel will only be
>> 2524 running on CPUs which do not support MSA or that your userland will
>> 2525 not be making use of it then you may wish to say N here to reduce
>> 2526 the size & complexity of your kernel.
>> 2527
>> 2528 If unsure, say Y.
>> 2529
>> 2530 config CPU_HAS_WB
>> 2531 bool
>> 2532
>> 2533 config XKS01
>> 2534 bool
>> 2535
>> 2536 config CPU_HAS_RIXI
>> 2537 bool
>> 2538
>> 2539 config CPU_HAS_LOAD_STORE_LR
>> 2540 bool
504 help 2541 help
505 Create block devices that map to fil !! 2542 CPU has support for unaligned load and store instructions:
506 Device binding to host file may be c !! 2543 LWL, LWR, SWL, SWR (Load/store word left/right).
507 interface provided the device is not !! 2544 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit systems).
508 !! 2545
509 config BLK_DEV_SIMDISK_COUNT !! 2546 #
510 int "Number of host file-based simulat !! 2547 # Vectored interrupt mode is an R2 feature
511 range 1 10 !! 2548 #
512 depends on BLK_DEV_SIMDISK !! 2549 config CPU_MIPSR2_IRQ_VI
513 default 2 !! 2550 bool
>> 2551
>> 2552 #
>> 2553 # Extended interrupt mode is an R2 feature
>> 2554 #
>> 2555 config CPU_MIPSR2_IRQ_EI
>> 2556 bool
>> 2557
>> 2558 config CPU_HAS_SYNC
>> 2559 bool
>> 2560 depends on !CPU_R3000
>> 2561 default y
>> 2562
>> 2563 #
>> 2564 # CPU non-features
>> 2565 #
>> 2566 config CPU_DADDI_WORKAROUNDS
>> 2567 bool
>> 2568
>> 2569 config CPU_R4000_WORKAROUNDS
>> 2570 bool
>> 2571 select CPU_R4400_WORKAROUNDS
>> 2572
>> 2573 config CPU_R4400_WORKAROUNDS
>> 2574 bool
>> 2575
>> 2576 config MIPS_ASID_SHIFT
>> 2577 int
>> 2578 default 6 if CPU_R3000 || CPU_TX39XX
>> 2579 default 4 if CPU_R8000
>> 2580 default 0
>> 2581
>> 2582 config MIPS_ASID_BITS
>> 2583 int
>> 2584 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2585 default 6 if CPU_R3000 || CPU_TX39XX
>> 2586 default 8
>> 2587
>> 2588 config MIPS_ASID_BITS_VARIABLE
>> 2589 bool
>> 2590
>> 2591 config MIPS_CRC_SUPPORT
>> 2592 bool
>> 2593
>> 2594 #
>> 2595 # - Highmem only makes sense for the 32-bit kernel.
>> 2596 # - The current highmem code will only work properly on physically indexed
>> 2597 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2598 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2599 # moment we protect the user and offer the highmem option only on machines
>> 2600 # where it's known to be safe. This will not offer highmem on a few systems
>> 2601 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2602 # indexed CPUs but we're playing safe.
>> 2603 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2604 # know they might have memory configurations that could make use of highmem
>> 2605 # support.
>> 2606 #
>> 2607 config HIGHMEM
>> 2608 bool "High Memory Support"
>> 2609 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2610
>> 2611 config CPU_SUPPORTS_HIGHMEM
>> 2612 bool
>> 2613
>> 2614 config SYS_SUPPORTS_HIGHMEM
>> 2615 bool
>> 2616
>> 2617 config SYS_SUPPORTS_SMARTMIPS
>> 2618 bool
>> 2619
>> 2620 config SYS_SUPPORTS_MICROMIPS
>> 2621 bool
>> 2622
>> 2623 config SYS_SUPPORTS_MIPS16
>> 2624 bool
514 help 2625 help
515 This is the default minimal number o !! 2626 This option must be set if a kernel might be executed on a MIPS16-
516 Kernel/module parameter 'simdisk_cou !! 2627 enabled CPU even if MIPS16 is not actually being used. In other
517 value at runtime. More file names (b !! 2628 words, it makes the kernel MIPS16-tolerant.
518 specified as parameters, simdisk_cou !! 2629
519 !! 2630 config CPU_SUPPORTS_MSA
520 config SIMDISK0_FILENAME !! 2631 bool
521 string "Host filename for the first si !! 2632
522 depends on BLK_DEV_SIMDISK = y !! 2633 config ARCH_FLATMEM_ENABLE
523 default "" !! 2634 def_bool y
524 help !! 2635 depends on !NUMA && !CPU_LOONGSON2
525 Attach a first simdisk to a host fil !! 2636
526 contains a root file system. !! 2637 config ARCH_DISCONTIGMEM_ENABLE
527 !! 2638 bool
528 config SIMDISK1_FILENAME !! 2639 default y if SGI_IP27
529 string "Host filename for the second s <<
530 depends on BLK_DEV_SIMDISK = y && BLK_ <<
531 default "" <<
532 help <<
533 Another simulated disk in a host fil <<
534 storage. <<
535 <<
536 config XTFPGA_LCD <<
537 bool "Enable XTFPGA LCD driver" <<
538 depends on XTENSA_PLATFORM_XTFPGA <<
539 default n <<
540 help 2640 help
541 There's a 2x16 LCD on most of XTFPGA !! 2641 Say Y to support efficient handling of discontiguous physical memory,
542 progress messages there during bootu !! 2642 for architectures which are either NUMA (Non-Uniform Memory Access)
543 during board bringup. !! 2643 or have huge holes in the physical address space for other reasons.
>> 2644 See <file:Documentation/vm/numa.rst> for more.
544 2645
545 If unsure, say N. !! 2646 config ARCH_SPARSEMEM_ENABLE
>> 2647 bool
>> 2648 select SPARSEMEM_STATIC
546 2649
547 config XTFPGA_LCD_BASE_ADDR !! 2650 config NUMA
548 hex "XTFPGA LCD base address" !! 2651 bool "NUMA Support"
549 depends on XTFPGA_LCD !! 2652 depends on SYS_SUPPORTS_NUMA
550 default "0x0d0c0000" !! 2653 help
551 help !! 2654 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
552 Base address of the LCD controller i !! 2655 Access). This option improves performance on systems with more
553 Different boards from XTFPGA family !! 2656 than two nodes; on two node systems it is generally better to
554 addresses. Please consult prototypin !! 2657 leave it disabled; on single node systems disable this option
555 the correct address. Wrong address h !! 2658 disabled.
556 !! 2659
557 config XTFPGA_LCD_8BIT_ACCESS !! 2660 config SYS_SUPPORTS_NUMA
558 bool "Use 8-bit access to XTFPGA LCD" !! 2661 bool
559 depends on XTFPGA_LCD !! 2662
560 default n !! 2663 config RELOCATABLE
>> 2664 bool "Relocatable kernel"
>> 2665 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
>> 2666 help
>> 2667 This builds a kernel image that retains relocation information
>> 2668 so it can be loaded someplace besides the default 1MB.
>> 2669 The relocations make the kernel binary about 15% larger,
>> 2670 but are discarded at runtime
>> 2671
>> 2672 config RELOCATION_TABLE_SIZE
>> 2673 hex "Relocation table size"
>> 2674 depends on RELOCATABLE
>> 2675 range 0x0 0x01000000
>> 2676 default "0x00100000"
>> 2677 ---help---
>> 2678 A table of relocation data will be appended to the kernel binary
>> 2679 and parsed at boot to fix up the relocated kernel.
>> 2680
>> 2681 This option allows the amount of space reserved for the table to be
>> 2682 adjusted, although the default of 1Mb should be ok in most cases.
>> 2683
>> 2684 The build will fail and a valid size suggested if this is too small.
>> 2685
>> 2686 If unsure, leave at the default value.
>> 2687
>> 2688 config RANDOMIZE_BASE
>> 2689 bool "Randomize the address of the kernel image"
>> 2690 depends on RELOCATABLE
>> 2691 ---help---
>> 2692 Randomizes the physical and virtual address at which the
>> 2693 kernel image is loaded, as a security feature that
>> 2694 deters exploit attempts relying on knowledge of the location
>> 2695 of kernel internals.
>> 2696
>> 2697 Entropy is generated using any coprocessor 0 registers available.
>> 2698
>> 2699 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2700
>> 2701 If unsure, say N.
>> 2702
>> 2703 config RANDOMIZE_BASE_MAX_OFFSET
>> 2704 hex "Maximum kASLR offset" if EXPERT
>> 2705 depends on RANDOMIZE_BASE
>> 2706 range 0x0 0x40000000 if EVA || 64BIT
>> 2707 range 0x0 0x08000000
>> 2708 default "0x01000000"
>> 2709 ---help---
>> 2710 When kASLR is active, this provides the maximum offset that will
>> 2711 be applied to the kernel image. It should be set according to the
>> 2712 amount of physical RAM available in the target system minus
>> 2713 PHYSICAL_START and must be a power of 2.
>> 2714
>> 2715 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2716 EVA or 64-bit. The default is 16Mb.
>> 2717
>> 2718 config NODES_SHIFT
>> 2719 int
>> 2720 default "6"
>> 2721 depends on NEED_MULTIPLE_NODES
>> 2722
>> 2723 config HW_PERF_EVENTS
>> 2724 bool "Enable hardware performance counter support for perf events"
>> 2725 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
>> 2726 default y
561 help 2727 help
562 LCD may be connected with 4- or 8-bi !! 2728 Enable hardware performance counter support for perf events. If
563 only be used with 8-bit interface. P !! 2729 disabled, perf events will use software events only.
564 guide for your board for the correct <<
565 <<
566 comment "Kernel memory layout" <<
567 <<
568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX <<
569 bool "Initialize Xtensa MMU inside the <<
570 depends on !XTENSA_VARIANT_FSF && !XTE <<
571 default y if XTENSA_VARIANT_DC233C || <<
572 help <<
573 Earlier version initialized the MMU <<
574 before jumping to _startup in head.S <<
575 it was possible to place a software <<
576 then enter your normal kernel breakp <<
577 to the kernel mappings (0XC0000000). <<
578 <<
579 This unfortunately won't work for U- <<
580 work for using KEXEC to have a hot k <<
581 KDUMP. <<
582 <<
583 So now the MMU is initialized in hea <<
584 use hardware breakpoints (gdb 'hbrea <<
585 xt-gdb can't place a Software Breakp <<
586 to mapping the MMU and after mapping <<
587 was mapped gdb wouldn't remove the b <<
588 PC wouldn't match. Since Hardware Br <<
589 Linux configurations it seems reason <<
590 and leave this older mechanism for u <<
591 not to follow Tensilica's recommenda <<
592 <<
593 Selecting this will cause U-Boot to <<
594 address at 0x00003000 instead of the <<
595 <<
596 If in doubt, say Y. <<
597 <<
598 config XIP_KERNEL <<
599 bool "Kernel Execute-In-Place from ROM <<
600 depends on PLATFORM_HAVE_XIP <<
601 help <<
602 Execute-In-Place allows the kernel t <<
603 directly addressable by the CPU, suc <<
604 space since the text section of the <<
605 to RAM. Read-write sections, such as <<
606 are still copied to RAM. The XIP ker <<
607 it has to run directly from flash, s <<
608 store it. The flash address used to <<
609 and for storing it, is configuration <<
610 say Y here, you must know the proper <<
611 store the kernel image depending on <<
612 <<
613 Also note that the make target becom <<
614 "make Image" or "make uImage". The f <<
615 ROM memory will be arch/xtensa/boot/ <<
616 2730
617 If unsure, say N. !! 2731 config SMP
>> 2732 bool "Multi-Processing support"
>> 2733 depends on SYS_SUPPORTS_SMP
>> 2734 help
>> 2735 This enables support for systems with more than one CPU. If you have
>> 2736 a system with only one CPU, say N. If you have a system with more
>> 2737 than one CPU, say Y.
>> 2738
>> 2739 If you say N here, the kernel will run on uni- and multiprocessor
>> 2740 machines, but will use only one CPU of a multiprocessor machine. If
>> 2741 you say Y here, the kernel will run on many, but not all,
>> 2742 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2743 will run faster if you say N here.
>> 2744
>> 2745 People using multiprocessor machines who say Y here should also say
>> 2746 Y to "Enhanced Real Time Clock Support", below.
>> 2747
>> 2748 See also the SMP-HOWTO available at
>> 2749 <http://www.tldp.org/docs.html#howto>.
>> 2750
>> 2751 If you don't know what to do here, say N.
>> 2752
>> 2753 config HOTPLUG_CPU
>> 2754 bool "Support for hot-pluggable CPUs"
>> 2755 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
>> 2756 help
>> 2757 Say Y here to allow turning CPUs off and on. CPUs can be
>> 2758 controlled through /sys/devices/system/cpu.
>> 2759 (Note: power management support will enable this option
>> 2760 automatically on SMP systems. )
>> 2761 Say N if you want to disable CPU hotplug.
>> 2762
>> 2763 config SMP_UP
>> 2764 bool
>> 2765
>> 2766 config SYS_SUPPORTS_MIPS_CMP
>> 2767 bool
>> 2768
>> 2769 config SYS_SUPPORTS_MIPS_CPS
>> 2770 bool
>> 2771
>> 2772 config SYS_SUPPORTS_SMP
>> 2773 bool
618 2774
619 config MEMMAP_CACHEATTR !! 2775 config NR_CPUS_DEFAULT_4
620 hex "Cache attributes for the memory a !! 2776 bool
621 depends on !MMU !! 2777
622 default 0x22222222 !! 2778 config NR_CPUS_DEFAULT_8
623 help !! 2779 bool
624 These cache attributes are set up fo !! 2780
625 specifies cache attributes for the c !! 2781 config NR_CPUS_DEFAULT_16
626 region: bits 0..3 -- for addresses 0 !! 2782 bool
627 bits 4..7 -- for addresses 0x2000000 <<
628 <<
629 Cache attribute values are specific <<
630 For region protection MMUs: <<
631 1: WT cached, <<
632 2: cache bypass, <<
633 4: WB cached, <<
634 f: illegal. <<
635 For full MMU: <<
636 bit 0: executable, <<
637 bit 1: writable, <<
638 bits 2..3: <<
639 0: cache bypass, <<
640 1: WB cache, <<
641 2: WT cache, <<
642 3: special (c and e are illegal, <<
643 For MPU: <<
644 0: illegal, <<
645 1: WB cache, <<
646 2: WB, no-write-allocate cache, <<
647 3: WT cache, <<
648 4: cache bypass. <<
649 <<
650 config KSEG_PADDR <<
651 hex "Physical address of the KSEG mapp <<
652 depends on INITIALIZE_XTENSA_MMU_INSID <<
653 default 0x00000000 <<
654 help <<
655 This is the physical address where K <<
656 the chosen KSEG layout help for the <<
657 Unpacked kernel image (including vec <<
658 within KSEG. <<
659 Physical memory below this address i <<
660 <<
661 If unsure, leave the default value h <<
662 <<
663 config KERNEL_VIRTUAL_ADDRESS <<
664 hex "Kernel virtual address" <<
665 depends on MMU && XIP_KERNEL <<
666 default 0xd0003000 <<
667 help <<
668 This is the virtual address where th <<
669 XIP kernel may be mapped into KSEG o <<
670 provided here must match kernel load <<
671 KERNEL_LOAD_ADDRESS. <<
672 <<
673 config KERNEL_LOAD_ADDRESS <<
674 hex "Kernel load address" <<
675 default 0x60003000 if !MMU <<
676 default 0x00003000 if MMU && INITIALIZ <<
677 default 0xd0003000 if MMU && !INITIALI <<
678 help <<
679 This is the address where the kernel <<
680 It is virtual address for MMUv2 conf <<
681 for all other configurations. <<
682 2783
683 If unsure, leave the default value h !! 2784 config NR_CPUS_DEFAULT_32
>> 2785 bool
>> 2786
>> 2787 config NR_CPUS_DEFAULT_64
>> 2788 bool
>> 2789
>> 2790 config NR_CPUS
>> 2791 int "Maximum number of CPUs (2-256)"
>> 2792 range 2 256
>> 2793 depends on SMP
>> 2794 default "4" if NR_CPUS_DEFAULT_4
>> 2795 default "8" if NR_CPUS_DEFAULT_8
>> 2796 default "16" if NR_CPUS_DEFAULT_16
>> 2797 default "32" if NR_CPUS_DEFAULT_32
>> 2798 default "64" if NR_CPUS_DEFAULT_64
>> 2799 help
>> 2800 This allows you to specify the maximum number of CPUs which this
>> 2801 kernel will support. The maximum supported value is 32 for 32-bit
>> 2802 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2803 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2804 and 2 for all others.
>> 2805
>> 2806 This is purely to save memory - each supported CPU adds
>> 2807 approximately eight kilobytes to the kernel image. For best
>> 2808 performance should round up your number of processors to the next
>> 2809 power of two.
>> 2810
>> 2811 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2812 bool
>> 2813
>> 2814 config MIPS_NR_CPU_NR_MAP_1024
>> 2815 bool
>> 2816
>> 2817 config MIPS_NR_CPU_NR_MAP
>> 2818 int
>> 2819 depends on SMP
>> 2820 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2821 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
>> 2822
>> 2823 #
>> 2824 # Timer Interrupt Frequency Configuration
>> 2825 #
684 2826
685 choice 2827 choice
686 prompt "Relocatable vectors location" !! 2828 prompt "Timer frequency"
687 default XTENSA_VECTORS_IN_TEXT !! 2829 default HZ_250
688 help 2830 help
689 Choose whether relocatable vectors a !! 2831 Allows the configuration of the timer frequency.
690 or placed separately at runtime. Thi !! 2832
691 configurations without VECBASE regis !! 2833 config HZ_24
692 placed at their hardware-defined loc !! 2834 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
693 !! 2835
694 config XTENSA_VECTORS_IN_TEXT !! 2836 config HZ_48
695 bool "Merge relocatable vectors into k !! 2837 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
696 depends on !MTD_XIP !! 2838
697 help !! 2839 config HZ_100
698 This option puts relocatable vectors !! 2840 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
699 with proper alignment. !! 2841
700 This is a safe choice for most confi !! 2842 config HZ_128
701 !! 2843 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
702 config XTENSA_VECTORS_SEPARATE !! 2844
703 bool "Put relocatable vectors at fixed !! 2845 config HZ_250
704 help !! 2846 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
705 This option puts relocatable vectors !! 2847
706 Vectors are merged with the .init da !! 2848 config HZ_256
707 are copied into their designated loc !! 2849 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
708 Use it to put vectors into IRAM or o !! 2850
709 XIP-aware MTD support. !! 2851 config HZ_1000
>> 2852 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2853
>> 2854 config HZ_1024
>> 2855 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
710 2856
711 endchoice 2857 endchoice
712 2858
713 config VECTORS_ADDR !! 2859 config SYS_SUPPORTS_24HZ
714 hex "Kernel vectors virtual address" !! 2860 bool
715 default 0x00000000 <<
716 depends on XTENSA_VECTORS_SEPARATE <<
717 help <<
718 This is the virtual address of the ( <<
719 It must be within KSEG if MMU is use <<
720 <<
721 config XIP_DATA_ADDR <<
722 hex "XIP kernel data virtual address" <<
723 depends on XIP_KERNEL <<
724 default 0x00000000 <<
725 help <<
726 This is the virtual address where XI <<
727 It must be within KSEG if MMU is use <<
728 2861
729 config PLATFORM_WANT_DEFAULT_MEM !! 2862 config SYS_SUPPORTS_48HZ
730 def_bool n !! 2863 bool
>> 2864
>> 2865 config SYS_SUPPORTS_100HZ
>> 2866 bool
>> 2867
>> 2868 config SYS_SUPPORTS_128HZ
>> 2869 bool
731 2870
732 config DEFAULT_MEM_START !! 2871 config SYS_SUPPORTS_250HZ
733 hex !! 2872 bool
734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !M !! 2873
735 default 0x60000000 if PLATFORM_WANT_DE !! 2874 config SYS_SUPPORTS_256HZ
736 default 0x00000000 !! 2875 bool
>> 2876
>> 2877 config SYS_SUPPORTS_1000HZ
>> 2878 bool
>> 2879
>> 2880 config SYS_SUPPORTS_1024HZ
>> 2881 bool
>> 2882
>> 2883 config SYS_SUPPORTS_ARBIT_HZ
>> 2884 bool
>> 2885 default y if !SYS_SUPPORTS_24HZ && \
>> 2886 !SYS_SUPPORTS_48HZ && \
>> 2887 !SYS_SUPPORTS_100HZ && \
>> 2888 !SYS_SUPPORTS_128HZ && \
>> 2889 !SYS_SUPPORTS_250HZ && \
>> 2890 !SYS_SUPPORTS_256HZ && \
>> 2891 !SYS_SUPPORTS_1000HZ && \
>> 2892 !SYS_SUPPORTS_1024HZ
>> 2893
>> 2894 config HZ
>> 2895 int
>> 2896 default 24 if HZ_24
>> 2897 default 48 if HZ_48
>> 2898 default 100 if HZ_100
>> 2899 default 128 if HZ_128
>> 2900 default 250 if HZ_250
>> 2901 default 256 if HZ_256
>> 2902 default 1000 if HZ_1000
>> 2903 default 1024 if HZ_1024
>> 2904
>> 2905 config SCHED_HRTICK
>> 2906 def_bool HIGH_RES_TIMERS
>> 2907
>> 2908 config KEXEC
>> 2909 bool "Kexec system call"
>> 2910 select KEXEC_CORE
>> 2911 help
>> 2912 kexec is a system call that implements the ability to shutdown your
>> 2913 current kernel, and to start another kernel. It is like a reboot
>> 2914 but it is independent of the system firmware. And like a reboot
>> 2915 you can start any kernel with it, not just Linux.
>> 2916
>> 2917 The name comes from the similarity to the exec system call.
>> 2918
>> 2919 It is an ongoing process to be certain the hardware in a machine
>> 2920 is properly shutdown, so do not be surprised if this code does not
>> 2921 initially work for you. As of this writing the exact hardware
>> 2922 interface is strongly in flux, so no good recommendation can be
>> 2923 made.
>> 2924
>> 2925 config CRASH_DUMP
>> 2926 bool "Kernel crash dumps"
>> 2927 help
>> 2928 Generate crash dump after being started by kexec.
>> 2929 This should be normally only set in special crash dump kernels
>> 2930 which are loaded in the main kernel with kexec-tools into
>> 2931 a specially reserved region and then later executed after
>> 2932 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2933 to a memory address not used by the main kernel or firmware using
>> 2934 PHYSICAL_START.
>> 2935
>> 2936 config PHYSICAL_START
>> 2937 hex "Physical address where the kernel is loaded"
>> 2938 default "0xffffffff84000000"
>> 2939 depends on CRASH_DUMP
>> 2940 help
>> 2941 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2942 If you plan to use kernel for capturing the crash dump change
>> 2943 this value to start of the reserved region (the "X" value as
>> 2944 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2945 passed to the panic-ed kernel).
>> 2946
>> 2947 config SECCOMP
>> 2948 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2949 depends on PROC_FS
>> 2950 default y
737 help 2951 help
738 This is the base address used for bo !! 2952 This kernel feature is useful for number crunching applications
739 in noMMU configurations. !! 2953 that may need to compute untrusted bytecode during their
>> 2954 execution. By using pipes or other transports made available to
>> 2955 the process as file descriptors supporting the read/write
>> 2956 syscalls, it's possible to isolate those applications in
>> 2957 their own address space using seccomp. Once seccomp is
>> 2958 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2959 and the task is only allowed to execute a few safe syscalls
>> 2960 defined by each seccomp mode.
>> 2961
>> 2962 If unsure, say Y. Only embedded should say N here.
>> 2963
>> 2964 config MIPS_O32_FP64_SUPPORT
>> 2965 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2966 depends on 32BIT || MIPS32_O32
>> 2967 help
>> 2968 When this is enabled, the kernel will support use of 64-bit floating
>> 2969 point registers with binaries using the O32 ABI along with the
>> 2970 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2971 32-bit MIPS systems this support is at the cost of increasing the
>> 2972 size and complexity of the compiled FPU emulator. Thus if you are
>> 2973 running a MIPS32 system and know that none of your userland binaries
>> 2974 will require 64-bit floating point, you may wish to reduce the size
>> 2975 of your kernel & potentially improve FP emulation performance by
>> 2976 saying N here.
>> 2977
>> 2978 Although binutils currently supports use of this flag the details
>> 2979 concerning its effect upon the O32 ABI in userland are still being
>> 2980 worked on. In order to avoid userland becoming dependant upon current
>> 2981 behaviour before the details have been finalised, this option should
>> 2982 be considered experimental and only enabled by those working upon
>> 2983 said details.
740 2984
741 If unsure, leave the default value h !! 2985 If unsure, say N.
>> 2986
>> 2987 config USE_OF
>> 2988 bool
>> 2989 select OF
>> 2990 select OF_EARLY_FLATTREE
>> 2991 select IRQ_DOMAIN
>> 2992
>> 2993 config UHI_BOOT
>> 2994 bool
>> 2995
>> 2996 config BUILTIN_DTB
>> 2997 bool
742 2998
743 choice 2999 choice
744 prompt "KSEG layout" !! 3000 prompt "Kernel appended dtb support" if USE_OF
745 depends on MMU !! 3001 default MIPS_NO_APPENDED_DTB
746 default XTENSA_KSEG_MMU_V2 <<
747 <<
748 config XTENSA_KSEG_MMU_V2 <<
749 bool "MMUv2: 128MB cached + 128MB unca <<
750 help <<
751 MMUv2 compatible kernel memory map: <<
752 at KSEG_PADDR to 0xd0000000 with cac <<
753 without cache. <<
754 KSEG_PADDR must be aligned to 128MB. <<
755 <<
756 config XTENSA_KSEG_256M <<
757 bool "256MB cached + 256MB uncached" <<
758 depends on INITIALIZE_XTENSA_MMU_INSID <<
759 help <<
760 TLB way 6 maps 256MB starting at KSE <<
761 with cache and to 0xc0000000 without <<
762 KSEG_PADDR must be aligned to 256MB. <<
763 <<
764 config XTENSA_KSEG_512M <<
765 bool "512MB cached + 512MB uncached" <<
766 depends on INITIALIZE_XTENSA_MMU_INSID <<
767 help <<
768 TLB way 6 maps 512MB starting at KSE <<
769 with cache and to 0xc0000000 without <<
770 KSEG_PADDR must be aligned to 256MB. <<
771 3002
>> 3003 config MIPS_NO_APPENDED_DTB
>> 3004 bool "None"
>> 3005 help
>> 3006 Do not enable appended dtb support.
>> 3007
>> 3008 config MIPS_ELF_APPENDED_DTB
>> 3009 bool "vmlinux"
>> 3010 help
>> 3011 With this option, the boot code will look for a device tree binary
>> 3012 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3013 it is empty and the DTB can be appended using binutils command
>> 3014 objcopy:
>> 3015
>> 3016 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3017
>> 3018 This is meant as a backward compatiblity convenience for those
>> 3019 systems with a bootloader that can't be upgraded to accommodate
>> 3020 the documented boot protocol using a device tree.
>> 3021
>> 3022 config MIPS_RAW_APPENDED_DTB
>> 3023 bool "vmlinux.bin or vmlinuz.bin"
>> 3024 help
>> 3025 With this option, the boot code will look for a device tree binary
>> 3026 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3027 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3028
>> 3029 This is meant as a backward compatibility convenience for those
>> 3030 systems with a bootloader that can't be upgraded to accommodate
>> 3031 the documented boot protocol using a device tree.
>> 3032
>> 3033 Beware that there is very little in terms of protection against
>> 3034 this option being confused by leftover garbage in memory that might
>> 3035 look like a DTB header after a reboot if no actual DTB is appended
>> 3036 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3037 if you don't intend to always append a DTB.
772 endchoice 3038 endchoice
773 3039
774 config HIGHMEM !! 3040 choice
775 bool "High Memory Support" !! 3041 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
776 depends on MMU !! 3042 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
777 select KMAP_LOCAL !! 3043 !MIPS_MALTA && \
778 help !! 3044 !CAVIUM_OCTEON_SOC
779 Linux can use the full amount of RAM !! 3045 default MIPS_CMDLINE_FROM_BOOTLOADER
780 default. However, the default MMUv2 !! 3046
781 lowermost 128 MB of memory linearly !! 3047 config MIPS_CMDLINE_FROM_DTB
782 at 0xd0000000 (cached) and 0xd800000 !! 3048 depends on USE_OF
783 When there are more than 128 MB memo !! 3049 bool "Dtb kernel arguments if available"
784 all of it can be "permanently mapped !! 3050
785 The physical memory that's not perma !! 3051 config MIPS_CMDLINE_DTB_EXTEND
786 "high memory". !! 3052 depends on USE_OF
787 !! 3053 bool "Extend dtb kernel arguments with bootloader arguments"
788 If you are compiling a kernel which !! 3054
789 machine with more than 128 MB total !! 3055 config MIPS_CMDLINE_FROM_BOOTLOADER
790 N here. !! 3056 bool "Bootloader kernel arguments if available"
>> 3057
>> 3058 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3059 depends on CMDLINE_BOOL
>> 3060 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3061 endchoice
791 3062
792 If unsure, say Y. !! 3063 endmenu
>> 3064
>> 3065 config LOCKDEP_SUPPORT
>> 3066 bool
>> 3067 default y
>> 3068
>> 3069 config STACKTRACE_SUPPORT
>> 3070 bool
>> 3071 default y
>> 3072
>> 3073 config HAVE_LATENCYTOP_SUPPORT
>> 3074 bool
>> 3075 default y
>> 3076
>> 3077 config PGTABLE_LEVELS
>> 3078 int
>> 3079 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3080 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 3081 default 2
>> 3082
>> 3083 config MIPS_AUTO_PFN_OFFSET
>> 3084 bool
>> 3085
>> 3086 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
>> 3087
>> 3088 config PCI_DRIVERS_GENERIC
>> 3089 select PCI_DOMAINS_GENERIC if PCI
>> 3090 bool
>> 3091
>> 3092 config PCI_DRIVERS_LEGACY
>> 3093 def_bool !PCI_DRIVERS_GENERIC
>> 3094 select NO_GENERIC_PCI_IOPORT_MAP
>> 3095 select PCI_DOMAINS if PCI
>> 3096
>> 3097 #
>> 3098 # ISA support is now enabled via select. Too many systems still have the one
>> 3099 # or other ISA chip on the board that users don't know about so don't expect
>> 3100 # users to choose the right thing ...
>> 3101 #
>> 3102 config ISA
>> 3103 bool
>> 3104
>> 3105 config TC
>> 3106 bool "TURBOchannel support"
>> 3107 depends on MACH_DECSTATION
>> 3108 help
>> 3109 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3110 processors. TURBOchannel programming specifications are available
>> 3111 at:
>> 3112 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3113 and:
>> 3114 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3115 Linux driver support status is documented at:
>> 3116 <http://www.linux-mips.org/wiki/DECstation>
793 3117
794 config ARCH_FORCE_MAX_ORDER !! 3118 config MMU
795 int "Order of maximal physically conti !! 3119 bool
796 default "10" !! 3120 default y
797 help !! 3121
798 The kernel page allocator limits the !! 3122 config ARCH_MMAP_RND_BITS_MIN
799 contiguous allocations. The limit is !! 3123 default 12 if 64BIT
800 defines the maximal power of two of !! 3124 default 8
801 allocated as a single contiguous blo !! 3125
802 overriding the default setting when !! 3126 config ARCH_MMAP_RND_BITS_MAX
803 large blocks of physically contiguou !! 3127 default 18 if 64BIT
>> 3128 default 15
>> 3129
>> 3130 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3131 default 8
>> 3132
>> 3133 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3134 default 15
>> 3135
>> 3136 config I8253
>> 3137 bool
>> 3138 select CLKSRC_I8253
>> 3139 select CLKEVT_I8253
>> 3140 select MIPS_EXTERNAL_TIMER
>> 3141
>> 3142 config ZONE_DMA
>> 3143 bool
804 3144
805 Don't change if unsure. !! 3145 config ZONE_DMA32
>> 3146 bool
806 3147
807 endmenu 3148 endmenu
808 3149
>> 3150 config TRAD_SIGNALS
>> 3151 bool
>> 3152
>> 3153 config MIPS32_COMPAT
>> 3154 bool
>> 3155
>> 3156 config COMPAT
>> 3157 bool
>> 3158
>> 3159 config SYSVIPC_COMPAT
>> 3160 bool
>> 3161
>> 3162 config MIPS32_O32
>> 3163 bool "Kernel support for o32 binaries"
>> 3164 depends on 64BIT
>> 3165 select ARCH_WANT_OLD_COMPAT_IPC
>> 3166 select COMPAT
>> 3167 select MIPS32_COMPAT
>> 3168 select SYSVIPC_COMPAT if SYSVIPC
>> 3169 help
>> 3170 Select this option if you want to run o32 binaries. These are pure
>> 3171 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3172 existing binaries are in this format.
>> 3173
>> 3174 If unsure, say Y.
>> 3175
>> 3176 config MIPS32_N32
>> 3177 bool "Kernel support for n32 binaries"
>> 3178 depends on 64BIT
>> 3179 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3180 select COMPAT
>> 3181 select MIPS32_COMPAT
>> 3182 select SYSVIPC_COMPAT if SYSVIPC
>> 3183 help
>> 3184 Select this option if you want to run n32 binaries. These are
>> 3185 64-bit binaries using 32-bit quantities for addressing and certain
>> 3186 data that would normally be 64-bit. They are used in special
>> 3187 cases.
>> 3188
>> 3189 If unsure, say N.
>> 3190
>> 3191 config BINFMT_ELF32
>> 3192 bool
>> 3193 default y if MIPS32_O32 || MIPS32_N32
>> 3194 select ELFCORE
>> 3195
809 menu "Power management options" 3196 menu "Power management options"
810 3197
811 config ARCH_HIBERNATION_POSSIBLE 3198 config ARCH_HIBERNATION_POSSIBLE
812 def_bool y 3199 def_bool y
>> 3200 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3201
>> 3202 config ARCH_SUSPEND_POSSIBLE
>> 3203 def_bool y
>> 3204 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
813 3205
814 source "kernel/power/Kconfig" 3206 source "kernel/power/Kconfig"
815 3207
816 endmenu 3208 endmenu
>> 3209
>> 3210 config MIPS_EXTERNAL_TIMER
>> 3211 bool
>> 3212
>> 3213 menu "CPU Power Management"
>> 3214
>> 3215 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3216 source "drivers/cpufreq/Kconfig"
>> 3217 endif
>> 3218
>> 3219 source "drivers/cpuidle/Kconfig"
>> 3220
>> 3221 endmenu
>> 3222
>> 3223 source "drivers/firmware/Kconfig"
>> 3224
>> 3225 source "arch/mips/kvm/Kconfig"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.