1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 config XTENSA !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ARCH_32BIT_OFF_T !! 4 default y
5 select ARCH_HAS_CPU_CACHE_ALIASING !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_HAS_BINFMT_FLAT if !MMU !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CURRENT_STACK_POINTER !! 7 select ARCH_HAS_FORTIFY_SOURCE
8 select ARCH_HAS_DEBUG_VM_PGTABLE <<
9 select ARCH_HAS_DMA_PREP_COHERENT if M <<
10 select ARCH_HAS_GCOV_PROFILE_ALL <<
11 select ARCH_HAS_KCOV 8 select ARCH_HAS_KCOV
12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MM !! 9 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if !! 10 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
14 select ARCH_HAS_DMA_SET_UNCACHED if MM !! 11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
15 select ARCH_HAS_STRNCPY_FROM_USER if ! !! 12 select ARCH_HAS_UBSAN_SANITIZE_ALL
16 select ARCH_HAS_STRNLEN_USER !! 13 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_NEED_CMPXCHG_1_EMU !! 14 select ARCH_KEEP_MEMBLOCK if DEBUG_KERNEL
18 select ARCH_USE_MEMTEST !! 15 select ARCH_SUPPORTS_UPROBES
>> 16 select ARCH_USE_BUILTIN_BSWAP
>> 17 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
19 select ARCH_USE_QUEUED_RWLOCKS 18 select ARCH_USE_QUEUED_RWLOCKS
20 select ARCH_USE_QUEUED_SPINLOCKS 19 select ARCH_USE_QUEUED_SPINLOCKS
>> 20 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
21 select ARCH_WANT_IPC_PARSE_VERSION 21 select ARCH_WANT_IPC_PARSE_VERSION
22 select BUILDTIME_TABLE_SORT 22 select BUILDTIME_TABLE_SORT
23 select CLONE_BACKWARDS 23 select CLONE_BACKWARDS
24 select COMMON_CLK !! 24 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
25 select DMA_NONCOHERENT_MMAP if MMU !! 25 select CPU_PM if CPU_IDLE
26 select GENERIC_ATOMIC64 !! 26 select GENERIC_ATOMIC64 if !64BIT
>> 27 select GENERIC_CMOS_UPDATE
>> 28 select GENERIC_CPU_AUTOPROBE
>> 29 select GENERIC_GETTIMEOFDAY
>> 30 select GENERIC_IOMAP
>> 31 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW 32 select GENERIC_IRQ_SHOW
>> 33 select GENERIC_ISA_DMA if EISA
>> 34 select GENERIC_LIB_ASHLDI3
>> 35 select GENERIC_LIB_ASHRDI3
28 select GENERIC_LIB_CMPDI2 36 select GENERIC_LIB_CMPDI2
29 select GENERIC_LIB_MULDI3 !! 37 select GENERIC_LIB_LSHRDI3
30 select GENERIC_LIB_UCMPDI2 38 select GENERIC_LIB_UCMPDI2
31 select GENERIC_PCI_IOMAP !! 39 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
32 select GENERIC_SCHED_CLOCK !! 40 select GENERIC_SMP_IDLE_THREAD
33 select GENERIC_IOREMAP if MMU !! 41 select GENERIC_TIME_VSYSCALL
34 select HAVE_ARCH_AUDITSYSCALL !! 42 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
35 select HAVE_ARCH_JUMP_LABEL if !XIP_KE !! 43 select HANDLE_DOMAIN_IRQ
36 select HAVE_ARCH_KASAN if MMU && !XIP_ !! 44 select HAVE_ARCH_COMPILER_H
37 select HAVE_ARCH_KCSAN !! 45 select HAVE_ARCH_JUMP_LABEL
>> 46 select HAVE_ARCH_KGDB
>> 47 select HAVE_ARCH_MMAP_RND_BITS if MMU
>> 48 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
38 select HAVE_ARCH_SECCOMP_FILTER 49 select HAVE_ARCH_SECCOMP_FILTER
39 select HAVE_ARCH_TRACEHOOK 50 select HAVE_ARCH_TRACEHOOK
>> 51 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
40 select HAVE_ASM_MODVERSIONS 52 select HAVE_ASM_MODVERSIONS
41 select HAVE_CONTEXT_TRACKING_USER !! 53 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 54 select HAVE_CONTEXT_TRACKING
>> 55 select HAVE_TIF_NOHZ
>> 56 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK 57 select HAVE_DEBUG_KMEMLEAK
>> 58 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_DMA_CONTIGUOUS 59 select HAVE_DMA_CONTIGUOUS
>> 60 select HAVE_DYNAMIC_FTRACE
>> 61 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
44 select HAVE_EXIT_THREAD 62 select HAVE_EXIT_THREAD
>> 63 select HAVE_FAST_GUP
>> 64 select HAVE_FTRACE_MCOUNT_RECORD
>> 65 select HAVE_FUNCTION_GRAPH_TRACER
45 select HAVE_FUNCTION_TRACER 66 select HAVE_FUNCTION_TRACER
46 select HAVE_GCC_PLUGINS if GCC_VERSION !! 67 select HAVE_GCC_PLUGINS
47 select HAVE_HW_BREAKPOINT if PERF_EVEN !! 68 select HAVE_GENERIC_VDSO
>> 69 select HAVE_IDE
>> 70 select HAVE_IOREMAP_PROT
>> 71 select HAVE_IRQ_EXIT_ON_IRQ_STACK
48 select HAVE_IRQ_TIME_ACCOUNTING 72 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_PAGE_SIZE_4KB !! 73 select HAVE_KPROBES
50 select HAVE_PCI !! 74 select HAVE_KRETPROBES
>> 75 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 76 select HAVE_MOD_ARCH_SPECIFIC
>> 77 select HAVE_NMI
>> 78 select HAVE_OPROFILE
51 select HAVE_PERF_EVENTS 79 select HAVE_PERF_EVENTS
>> 80 select HAVE_REGS_AND_STACK_ACCESS_API
>> 81 select HAVE_RSEQ
>> 82 select HAVE_SPARSE_SYSCALL_NR
52 select HAVE_STACKPROTECTOR 83 select HAVE_STACKPROTECTOR
53 select HAVE_SYSCALL_TRACEPOINTS 84 select HAVE_SYSCALL_TRACEPOINTS
54 select HAVE_VIRT_CPU_ACCOUNTING_GEN !! 85 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
55 select IRQ_DOMAIN !! 86 select IRQ_FORCED_THREADING
56 select LOCK_MM_AND_FIND_VMA !! 87 select ISA if EISA
57 select MODULES_USE_ELF_RELA !! 88 select MODULES_USE_ELF_REL if MODULES
>> 89 select MODULES_USE_ELF_RELA if MODULES && 64BIT
58 select PERF_USE_VMALLOC 90 select PERF_USE_VMALLOC
59 select TRACE_IRQFLAGS_SUPPORT !! 91 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
>> 92 select RTC_LIB
>> 93 select SET_FS
>> 94 select SYSCTL_EXCEPTION_TRACE
>> 95 select VIRT_TO_BUS
>> 96
>> 97 config MIPS_FIXUP_BIGPHYS_ADDR
>> 98 bool
>> 99
>> 100 config MIPS_GENERIC
>> 101 bool
>> 102
>> 103 config MACH_INGENIC
>> 104 bool
>> 105 select SYS_SUPPORTS_32BIT_KERNEL
>> 106 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 107 select SYS_SUPPORTS_ZBOOT
>> 108 select DMA_NONCOHERENT
>> 109 select IRQ_MIPS_CPU
>> 110 select PINCTRL
>> 111 select GPIOLIB
>> 112 select COMMON_CLK
>> 113 select GENERIC_IRQ_CHIP
>> 114 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 115 select USE_OF
>> 116 select CPU_SUPPORTS_CPUFREQ
>> 117 select MIPS_EXTERNAL_TIMER
>> 118
>> 119 menu "Machine selection"
>> 120
>> 121 choice
>> 122 prompt "System type"
>> 123 default MIPS_GENERIC_KERNEL
>> 124
>> 125 config MIPS_GENERIC_KERNEL
>> 126 bool "Generic board-agnostic MIPS kernel"
>> 127 select MIPS_GENERIC
>> 128 select BOOT_RAW
>> 129 select BUILTIN_DTB
>> 130 select CEVT_R4K
>> 131 select CLKSRC_MIPS_GIC
>> 132 select COMMON_CLK
>> 133 select CPU_MIPSR2_IRQ_EI
>> 134 select CPU_MIPSR2_IRQ_VI
>> 135 select CSRC_R4K
>> 136 select DMA_PERDEV_COHERENT
>> 137 select HAVE_PCI
>> 138 select IRQ_MIPS_CPU
>> 139 select MIPS_AUTO_PFN_OFFSET
>> 140 select MIPS_CPU_SCACHE
>> 141 select MIPS_GIC
>> 142 select MIPS_L1_CACHE_SHIFT_7
>> 143 select NO_EXCEPT_FILL
>> 144 select PCI_DRIVERS_GENERIC
>> 145 select SMP_UP if SMP
>> 146 select SWAP_IO_SPACE
>> 147 select SYS_HAS_CPU_MIPS32_R1
>> 148 select SYS_HAS_CPU_MIPS32_R2
>> 149 select SYS_HAS_CPU_MIPS32_R6
>> 150 select SYS_HAS_CPU_MIPS64_R1
>> 151 select SYS_HAS_CPU_MIPS64_R2
>> 152 select SYS_HAS_CPU_MIPS64_R6
>> 153 select SYS_SUPPORTS_32BIT_KERNEL
>> 154 select SYS_SUPPORTS_64BIT_KERNEL
>> 155 select SYS_SUPPORTS_BIG_ENDIAN
>> 156 select SYS_SUPPORTS_HIGHMEM
>> 157 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 158 select SYS_SUPPORTS_MICROMIPS
>> 159 select SYS_SUPPORTS_MIPS16
>> 160 select SYS_SUPPORTS_MIPS_CPS
>> 161 select SYS_SUPPORTS_MULTITHREADING
>> 162 select SYS_SUPPORTS_RELOCATABLE
>> 163 select SYS_SUPPORTS_SMARTMIPS
>> 164 select SYS_SUPPORTS_ZBOOT
>> 165 select UHI_BOOT
>> 166 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 167 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 168 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 169 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 170 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 171 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 172 select USE_OF
>> 173 help
>> 174 Select this to build a kernel which aims to support multiple boards,
>> 175 generally using a flattened device tree passed from the bootloader
>> 176 using the boot protocol defined in the UHI (Unified Hosting
>> 177 Interface) specification.
>> 178
>> 179 config MIPS_ALCHEMY
>> 180 bool "Alchemy processor based machines"
>> 181 select PHYS_ADDR_T_64BIT
>> 182 select CEVT_R4K
>> 183 select CSRC_R4K
>> 184 select IRQ_MIPS_CPU
>> 185 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 186 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 187 select SYS_HAS_CPU_MIPS32_R1
>> 188 select SYS_SUPPORTS_32BIT_KERNEL
>> 189 select SYS_SUPPORTS_APM_EMULATION
>> 190 select GPIOLIB
>> 191 select SYS_SUPPORTS_ZBOOT
>> 192 select COMMON_CLK
>> 193
>> 194 config AR7
>> 195 bool "Texas Instruments AR7"
>> 196 select BOOT_ELF32
>> 197 select DMA_NONCOHERENT
>> 198 select CEVT_R4K
>> 199 select CSRC_R4K
>> 200 select IRQ_MIPS_CPU
>> 201 select NO_EXCEPT_FILL
>> 202 select SWAP_IO_SPACE
>> 203 select SYS_HAS_CPU_MIPS32_R1
>> 204 select SYS_HAS_EARLY_PRINTK
>> 205 select SYS_SUPPORTS_32BIT_KERNEL
>> 206 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 207 select SYS_SUPPORTS_MIPS16
>> 208 select SYS_SUPPORTS_ZBOOT_UART16550
>> 209 select GPIOLIB
>> 210 select VLYNQ
>> 211 select HAVE_LEGACY_CLK
>> 212 help
>> 213 Support for the Texas Instruments AR7 System-on-a-Chip
>> 214 family: TNETD7100, 7200 and 7300.
>> 215
>> 216 config ATH25
>> 217 bool "Atheros AR231x/AR531x SoC support"
>> 218 select CEVT_R4K
>> 219 select CSRC_R4K
>> 220 select DMA_NONCOHERENT
>> 221 select IRQ_MIPS_CPU
>> 222 select IRQ_DOMAIN
>> 223 select SYS_HAS_CPU_MIPS32_R1
>> 224 select SYS_SUPPORTS_BIG_ENDIAN
>> 225 select SYS_SUPPORTS_32BIT_KERNEL
>> 226 select SYS_HAS_EARLY_PRINTK
>> 227 help
>> 228 Support for Atheros AR231x and Atheros AR531x based boards
>> 229
>> 230 config ATH79
>> 231 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 232 select ARCH_HAS_RESET_CONTROLLER
>> 233 select BOOT_RAW
>> 234 select CEVT_R4K
>> 235 select CSRC_R4K
>> 236 select DMA_NONCOHERENT
>> 237 select GPIOLIB
>> 238 select PINCTRL
>> 239 select COMMON_CLK
>> 240 select IRQ_MIPS_CPU
>> 241 select SYS_HAS_CPU_MIPS32_R2
>> 242 select SYS_HAS_EARLY_PRINTK
>> 243 select SYS_SUPPORTS_32BIT_KERNEL
>> 244 select SYS_SUPPORTS_BIG_ENDIAN
>> 245 select SYS_SUPPORTS_MIPS16
>> 246 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 247 select USE_OF
>> 248 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 249 help
>> 250 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 251
>> 252 config BMIPS_GENERIC
>> 253 bool "Broadcom Generic BMIPS kernel"
>> 254 select ARCH_HAS_RESET_CONTROLLER
>> 255 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 256 select ARCH_HAS_PHYS_TO_DMA
>> 257 select BOOT_RAW
>> 258 select NO_EXCEPT_FILL
>> 259 select USE_OF
>> 260 select CEVT_R4K
>> 261 select CSRC_R4K
>> 262 select SYNC_R4K
>> 263 select COMMON_CLK
>> 264 select BCM6345_L1_IRQ
>> 265 select BCM7038_L1_IRQ
>> 266 select BCM7120_L2_IRQ
>> 267 select BRCMSTB_L2_IRQ
>> 268 select IRQ_MIPS_CPU
>> 269 select DMA_NONCOHERENT
>> 270 select SYS_SUPPORTS_32BIT_KERNEL
>> 271 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 272 select SYS_SUPPORTS_BIG_ENDIAN
>> 273 select SYS_SUPPORTS_HIGHMEM
>> 274 select SYS_HAS_CPU_BMIPS32_3300
>> 275 select SYS_HAS_CPU_BMIPS4350
>> 276 select SYS_HAS_CPU_BMIPS4380
>> 277 select SYS_HAS_CPU_BMIPS5000
>> 278 select SWAP_IO_SPACE
>> 279 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 280 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 281 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 282 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 283 select HARDIRQS_SW_RESEND
>> 284 help
>> 285 Build a generic DT-based kernel image that boots on select
>> 286 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 287 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 288 must be set appropriately for your board.
>> 289
>> 290 config BCM47XX
>> 291 bool "Broadcom BCM47XX based boards"
>> 292 select BOOT_RAW
>> 293 select CEVT_R4K
>> 294 select CSRC_R4K
>> 295 select DMA_NONCOHERENT
>> 296 select HAVE_PCI
>> 297 select IRQ_MIPS_CPU
>> 298 select SYS_HAS_CPU_MIPS32_R1
>> 299 select NO_EXCEPT_FILL
>> 300 select SYS_SUPPORTS_32BIT_KERNEL
>> 301 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 302 select SYS_SUPPORTS_MIPS16
>> 303 select SYS_SUPPORTS_ZBOOT
>> 304 select SYS_HAS_EARLY_PRINTK
>> 305 select USE_GENERIC_EARLY_PRINTK_8250
>> 306 select GPIOLIB
>> 307 select LEDS_GPIO_REGISTER
>> 308 select BCM47XX_NVRAM
>> 309 select BCM47XX_SPROM
>> 310 select BCM47XX_SSB if !BCM47XX_BCMA
>> 311 help
>> 312 Support for BCM47XX based boards
>> 313
>> 314 config BCM63XX
>> 315 bool "Broadcom BCM63XX based boards"
>> 316 select BOOT_RAW
>> 317 select CEVT_R4K
>> 318 select CSRC_R4K
>> 319 select SYNC_R4K
>> 320 select DMA_NONCOHERENT
>> 321 select IRQ_MIPS_CPU
>> 322 select SYS_SUPPORTS_32BIT_KERNEL
>> 323 select SYS_SUPPORTS_BIG_ENDIAN
>> 324 select SYS_HAS_EARLY_PRINTK
>> 325 select SWAP_IO_SPACE
>> 326 select GPIOLIB
>> 327 select MIPS_L1_CACHE_SHIFT_4
>> 328 select CLKDEV_LOOKUP
>> 329 select HAVE_LEGACY_CLK
>> 330 help
>> 331 Support for BCM63XX based boards
>> 332
>> 333 config MIPS_COBALT
>> 334 bool "Cobalt Server"
>> 335 select CEVT_R4K
>> 336 select CSRC_R4K
>> 337 select CEVT_GT641XX
>> 338 select DMA_NONCOHERENT
>> 339 select FORCE_PCI
>> 340 select I8253
>> 341 select I8259
>> 342 select IRQ_MIPS_CPU
>> 343 select IRQ_GT641XX
>> 344 select PCI_GT64XXX_PCI0
>> 345 select SYS_HAS_CPU_NEVADA
>> 346 select SYS_HAS_EARLY_PRINTK
>> 347 select SYS_SUPPORTS_32BIT_KERNEL
>> 348 select SYS_SUPPORTS_64BIT_KERNEL
>> 349 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 350 select USE_GENERIC_EARLY_PRINTK_8250
>> 351
>> 352 config MACH_DECSTATION
>> 353 bool "DECstations"
>> 354 select BOOT_ELF32
>> 355 select CEVT_DS1287
>> 356 select CEVT_R4K if CPU_R4X00
>> 357 select CSRC_IOASIC
>> 358 select CSRC_R4K if CPU_R4X00
>> 359 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 360 select CPU_R4000_WORKAROUNDS if 64BIT
>> 361 select CPU_R4400_WORKAROUNDS if 64BIT
>> 362 select DMA_NONCOHERENT
>> 363 select NO_IOPORT_MAP
>> 364 select IRQ_MIPS_CPU
>> 365 select SYS_HAS_CPU_R3000
>> 366 select SYS_HAS_CPU_R4X00
>> 367 select SYS_SUPPORTS_32BIT_KERNEL
>> 368 select SYS_SUPPORTS_64BIT_KERNEL
>> 369 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 370 select SYS_SUPPORTS_128HZ
>> 371 select SYS_SUPPORTS_256HZ
>> 372 select SYS_SUPPORTS_1024HZ
>> 373 select MIPS_L1_CACHE_SHIFT_4
>> 374 help
>> 375 This enables support for DEC's MIPS based workstations. For details
>> 376 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 377 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 378
>> 379 If you have one of the following DECstation Models you definitely
>> 380 want to choose R4xx0 for the CPU Type:
>> 381
>> 382 DECstation 5000/50
>> 383 DECstation 5000/150
>> 384 DECstation 5000/260
>> 385 DECsystem 5900/260
>> 386
>> 387 otherwise choose R3000.
>> 388
>> 389 config MACH_JAZZ
>> 390 bool "Jazz family of machines"
>> 391 select ARC_MEMORY
>> 392 select ARC_PROMLIB
>> 393 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 394 select ARCH_MIGHT_HAVE_PC_SERIO
>> 395 select DMA_OPS
>> 396 select FW_ARC
>> 397 select FW_ARC32
>> 398 select ARCH_MAY_HAVE_PC_FDC
>> 399 select CEVT_R4K
>> 400 select CSRC_R4K
>> 401 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 402 select GENERIC_ISA_DMA
>> 403 select HAVE_PCSPKR_PLATFORM
>> 404 select IRQ_MIPS_CPU
>> 405 select I8253
>> 406 select I8259
>> 407 select ISA
>> 408 select SYS_HAS_CPU_R4X00
>> 409 select SYS_SUPPORTS_32BIT_KERNEL
>> 410 select SYS_SUPPORTS_64BIT_KERNEL
>> 411 select SYS_SUPPORTS_100HZ
>> 412 help
>> 413 This a family of machines based on the MIPS R4030 chipset which was
>> 414 used by several vendors to build RISC/os and Windows NT workstations.
>> 415 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 416 Olivetti M700-10 workstations.
>> 417
>> 418 config MACH_INGENIC_SOC
>> 419 bool "Ingenic SoC based machines"
>> 420 select MIPS_GENERIC
>> 421 select MACH_INGENIC
>> 422 select SYS_SUPPORTS_ZBOOT_UART16550
>> 423
>> 424 config LANTIQ
>> 425 bool "Lantiq based platforms"
>> 426 select DMA_NONCOHERENT
>> 427 select IRQ_MIPS_CPU
>> 428 select CEVT_R4K
>> 429 select CSRC_R4K
>> 430 select SYS_HAS_CPU_MIPS32_R1
>> 431 select SYS_HAS_CPU_MIPS32_R2
>> 432 select SYS_SUPPORTS_BIG_ENDIAN
>> 433 select SYS_SUPPORTS_32BIT_KERNEL
>> 434 select SYS_SUPPORTS_MIPS16
>> 435 select SYS_SUPPORTS_MULTITHREADING
>> 436 select SYS_SUPPORTS_VPE_LOADER
>> 437 select SYS_HAS_EARLY_PRINTK
>> 438 select GPIOLIB
>> 439 select SWAP_IO_SPACE
>> 440 select BOOT_RAW
>> 441 select CLKDEV_LOOKUP
>> 442 select HAVE_LEGACY_CLK
>> 443 select USE_OF
>> 444 select PINCTRL
>> 445 select PINCTRL_LANTIQ
>> 446 select ARCH_HAS_RESET_CONTROLLER
>> 447 select RESET_CONTROLLER
>> 448
>> 449 config MACH_LOONGSON32
>> 450 bool "Loongson 32-bit family of machines"
>> 451 select SYS_SUPPORTS_ZBOOT
>> 452 help
>> 453 This enables support for the Loongson-1 family of machines.
>> 454
>> 455 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 456 the Institute of Computing Technology (ICT), Chinese Academy of
>> 457 Sciences (CAS).
>> 458
>> 459 config MACH_LOONGSON2EF
>> 460 bool "Loongson-2E/F family of machines"
>> 461 select SYS_SUPPORTS_ZBOOT
>> 462 help
>> 463 This enables the support of early Loongson-2E/F family of machines.
>> 464
>> 465 config MACH_LOONGSON64
>> 466 bool "Loongson 64-bit family of machines"
>> 467 select ARCH_SPARSEMEM_ENABLE
>> 468 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 469 select ARCH_MIGHT_HAVE_PC_SERIO
>> 470 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 471 select BOOT_ELF32
>> 472 select BOARD_SCACHE
>> 473 select CSRC_R4K
>> 474 select CEVT_R4K
>> 475 select CPU_HAS_WB
>> 476 select FORCE_PCI
>> 477 select ISA
>> 478 select I8259
>> 479 select IRQ_MIPS_CPU
>> 480 select NO_EXCEPT_FILL
>> 481 select NR_CPUS_DEFAULT_64
>> 482 select USE_GENERIC_EARLY_PRINTK_8250
>> 483 select PCI_DRIVERS_GENERIC
>> 484 select SYS_HAS_CPU_LOONGSON64
>> 485 select SYS_HAS_EARLY_PRINTK
>> 486 select SYS_SUPPORTS_SMP
>> 487 select SYS_SUPPORTS_HOTPLUG_CPU
>> 488 select SYS_SUPPORTS_NUMA
>> 489 select SYS_SUPPORTS_64BIT_KERNEL
>> 490 select SYS_SUPPORTS_HIGHMEM
>> 491 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 492 select SYS_SUPPORTS_ZBOOT
>> 493 select SYS_SUPPORTS_RELOCATABLE
>> 494 select ZONE_DMA32
>> 495 select NUMA
>> 496 select SMP
>> 497 select COMMON_CLK
>> 498 select USE_OF
>> 499 select BUILTIN_DTB
>> 500 select PCI_HOST_GENERIC
>> 501 help
>> 502 This enables the support of Loongson-2/3 family of machines.
>> 503
>> 504 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 505 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 506 and Loongson-2F which will be removed), developed by the Institute
>> 507 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 508
>> 509 config MACH_PISTACHIO
>> 510 bool "IMG Pistachio SoC based boards"
>> 511 select BOOT_ELF32
>> 512 select BOOT_RAW
>> 513 select CEVT_R4K
>> 514 select CLKSRC_MIPS_GIC
>> 515 select COMMON_CLK
>> 516 select CSRC_R4K
>> 517 select DMA_NONCOHERENT
>> 518 select GPIOLIB
>> 519 select IRQ_MIPS_CPU
>> 520 select MFD_SYSCON
>> 521 select MIPS_CPU_SCACHE
>> 522 select MIPS_GIC
>> 523 select PINCTRL
>> 524 select REGULATOR
>> 525 select SYS_HAS_CPU_MIPS32_R2
>> 526 select SYS_SUPPORTS_32BIT_KERNEL
>> 527 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 528 select SYS_SUPPORTS_MIPS_CPS
>> 529 select SYS_SUPPORTS_MULTITHREADING
>> 530 select SYS_SUPPORTS_RELOCATABLE
>> 531 select SYS_SUPPORTS_ZBOOT
>> 532 select SYS_HAS_EARLY_PRINTK
>> 533 select USE_GENERIC_EARLY_PRINTK_8250
>> 534 select USE_OF
>> 535 help
>> 536 This enables support for the IMG Pistachio SoC platform.
>> 537
>> 538 config MIPS_MALTA
>> 539 bool "MIPS Malta board"
>> 540 select ARCH_MAY_HAVE_PC_FDC
>> 541 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 542 select ARCH_MIGHT_HAVE_PC_SERIO
>> 543 select BOOT_ELF32
>> 544 select BOOT_RAW
>> 545 select BUILTIN_DTB
>> 546 select CEVT_R4K
>> 547 select CLKSRC_MIPS_GIC
>> 548 select COMMON_CLK
>> 549 select CSRC_R4K
>> 550 select DMA_MAYBE_COHERENT
>> 551 select GENERIC_ISA_DMA
>> 552 select HAVE_PCSPKR_PLATFORM
>> 553 select HAVE_PCI
>> 554 select I8253
>> 555 select I8259
>> 556 select IRQ_MIPS_CPU
>> 557 select MIPS_BONITO64
>> 558 select MIPS_CPU_SCACHE
>> 559 select MIPS_GIC
>> 560 select MIPS_L1_CACHE_SHIFT_6
>> 561 select MIPS_MSC
>> 562 select PCI_GT64XXX_PCI0
>> 563 select SMP_UP if SMP
>> 564 select SWAP_IO_SPACE
>> 565 select SYS_HAS_CPU_MIPS32_R1
>> 566 select SYS_HAS_CPU_MIPS32_R2
>> 567 select SYS_HAS_CPU_MIPS32_R3_5
>> 568 select SYS_HAS_CPU_MIPS32_R5
>> 569 select SYS_HAS_CPU_MIPS32_R6
>> 570 select SYS_HAS_CPU_MIPS64_R1
>> 571 select SYS_HAS_CPU_MIPS64_R2
>> 572 select SYS_HAS_CPU_MIPS64_R6
>> 573 select SYS_HAS_CPU_NEVADA
>> 574 select SYS_HAS_CPU_RM7000
>> 575 select SYS_SUPPORTS_32BIT_KERNEL
>> 576 select SYS_SUPPORTS_64BIT_KERNEL
>> 577 select SYS_SUPPORTS_BIG_ENDIAN
>> 578 select SYS_SUPPORTS_HIGHMEM
>> 579 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 580 select SYS_SUPPORTS_MICROMIPS
>> 581 select SYS_SUPPORTS_MIPS16
>> 582 select SYS_SUPPORTS_MIPS_CMP
>> 583 select SYS_SUPPORTS_MIPS_CPS
>> 584 select SYS_SUPPORTS_MULTITHREADING
>> 585 select SYS_SUPPORTS_RELOCATABLE
>> 586 select SYS_SUPPORTS_SMARTMIPS
>> 587 select SYS_SUPPORTS_VPE_LOADER
>> 588 select SYS_SUPPORTS_ZBOOT
>> 589 select USE_OF
>> 590 select WAR_ICACHE_REFILLS
>> 591 select ZONE_DMA32 if 64BIT
>> 592 help
>> 593 This enables support for the MIPS Technologies Malta evaluation
>> 594 board.
>> 595
>> 596 config MACH_PIC32
>> 597 bool "Microchip PIC32 Family"
>> 598 help
>> 599 This enables support for the Microchip PIC32 family of platforms.
>> 600
>> 601 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 602 microcontrollers.
>> 603
>> 604 config MACH_VR41XX
>> 605 bool "NEC VR4100 series based machines"
>> 606 select CEVT_R4K
>> 607 select CSRC_R4K
>> 608 select SYS_HAS_CPU_VR41XX
>> 609 select SYS_SUPPORTS_MIPS16
>> 610 select GPIOLIB
>> 611
>> 612 config RALINK
>> 613 bool "Ralink based machines"
>> 614 select CEVT_R4K
>> 615 select CSRC_R4K
>> 616 select BOOT_RAW
>> 617 select DMA_NONCOHERENT
>> 618 select IRQ_MIPS_CPU
>> 619 select USE_OF
>> 620 select SYS_HAS_CPU_MIPS32_R1
>> 621 select SYS_HAS_CPU_MIPS32_R2
>> 622 select SYS_SUPPORTS_32BIT_KERNEL
>> 623 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 624 select SYS_SUPPORTS_MIPS16
>> 625 select SYS_SUPPORTS_ZBOOT
>> 626 select SYS_HAS_EARLY_PRINTK
>> 627 select CLKDEV_LOOKUP
>> 628 select ARCH_HAS_RESET_CONTROLLER
>> 629 select RESET_CONTROLLER
>> 630
>> 631 config SGI_IP22
>> 632 bool "SGI IP22 (Indy/Indigo2)"
>> 633 select ARC_MEMORY
>> 634 select ARC_PROMLIB
>> 635 select FW_ARC
>> 636 select FW_ARC32
>> 637 select ARCH_MIGHT_HAVE_PC_SERIO
>> 638 select BOOT_ELF32
>> 639 select CEVT_R4K
>> 640 select CSRC_R4K
>> 641 select DEFAULT_SGI_PARTITION
>> 642 select DMA_NONCOHERENT
>> 643 select HAVE_EISA
>> 644 select I8253
>> 645 select I8259
>> 646 select IP22_CPU_SCACHE
>> 647 select IRQ_MIPS_CPU
>> 648 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 649 select SGI_HAS_I8042
>> 650 select SGI_HAS_INDYDOG
>> 651 select SGI_HAS_HAL2
>> 652 select SGI_HAS_SEEQ
>> 653 select SGI_HAS_WD93
>> 654 select SGI_HAS_ZILOG
>> 655 select SWAP_IO_SPACE
>> 656 select SYS_HAS_CPU_R4X00
>> 657 select SYS_HAS_CPU_R5000
>> 658 select SYS_HAS_EARLY_PRINTK
>> 659 select SYS_SUPPORTS_32BIT_KERNEL
>> 660 select SYS_SUPPORTS_64BIT_KERNEL
>> 661 select SYS_SUPPORTS_BIG_ENDIAN
>> 662 select WAR_R4600_V1_INDEX_ICACHEOP
>> 663 select WAR_R4600_V1_HIT_CACHEOP
>> 664 select WAR_R4600_V2_HIT_CACHEOP
>> 665 select MIPS_L1_CACHE_SHIFT_7
>> 666 help
>> 667 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 668 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 669 that runs on these, say Y here.
>> 670
>> 671 config SGI_IP27
>> 672 bool "SGI IP27 (Origin200/2000)"
>> 673 select ARCH_HAS_PHYS_TO_DMA
>> 674 select ARCH_SPARSEMEM_ENABLE
>> 675 select FW_ARC
>> 676 select FW_ARC64
>> 677 select ARC_CMDLINE_ONLY
>> 678 select BOOT_ELF64
>> 679 select DEFAULT_SGI_PARTITION
>> 680 select SYS_HAS_EARLY_PRINTK
>> 681 select HAVE_PCI
>> 682 select IRQ_MIPS_CPU
>> 683 select IRQ_DOMAIN_HIERARCHY
>> 684 select NR_CPUS_DEFAULT_64
>> 685 select PCI_DRIVERS_GENERIC
>> 686 select PCI_XTALK_BRIDGE
>> 687 select SYS_HAS_CPU_R10000
>> 688 select SYS_SUPPORTS_64BIT_KERNEL
>> 689 select SYS_SUPPORTS_BIG_ENDIAN
>> 690 select SYS_SUPPORTS_NUMA
>> 691 select SYS_SUPPORTS_SMP
>> 692 select WAR_R10000_LLSC
>> 693 select MIPS_L1_CACHE_SHIFT_7
>> 694 select NUMA
>> 695 help
>> 696 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 697 workstations. To compile a Linux kernel that runs on these, say Y
>> 698 here.
>> 699
>> 700 config SGI_IP28
>> 701 bool "SGI IP28 (Indigo2 R10k)"
>> 702 select ARC_MEMORY
>> 703 select ARC_PROMLIB
>> 704 select FW_ARC
>> 705 select FW_ARC64
>> 706 select ARCH_MIGHT_HAVE_PC_SERIO
>> 707 select BOOT_ELF64
>> 708 select CEVT_R4K
>> 709 select CSRC_R4K
>> 710 select DEFAULT_SGI_PARTITION
>> 711 select DMA_NONCOHERENT
>> 712 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 713 select IRQ_MIPS_CPU
>> 714 select HAVE_EISA
>> 715 select I8253
>> 716 select I8259
>> 717 select SGI_HAS_I8042
>> 718 select SGI_HAS_INDYDOG
>> 719 select SGI_HAS_HAL2
>> 720 select SGI_HAS_SEEQ
>> 721 select SGI_HAS_WD93
>> 722 select SGI_HAS_ZILOG
>> 723 select SWAP_IO_SPACE
>> 724 select SYS_HAS_CPU_R10000
>> 725 select SYS_HAS_EARLY_PRINTK
>> 726 select SYS_SUPPORTS_64BIT_KERNEL
>> 727 select SYS_SUPPORTS_BIG_ENDIAN
>> 728 select WAR_R10000_LLSC
>> 729 select MIPS_L1_CACHE_SHIFT_7
>> 730 help
>> 731 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 732 kernel that runs on these, say Y here.
>> 733
>> 734 config SGI_IP30
>> 735 bool "SGI IP30 (Octane/Octane2)"
>> 736 select ARCH_HAS_PHYS_TO_DMA
>> 737 select FW_ARC
>> 738 select FW_ARC64
>> 739 select BOOT_ELF64
>> 740 select CEVT_R4K
>> 741 select CSRC_R4K
>> 742 select SYNC_R4K if SMP
>> 743 select ZONE_DMA32
>> 744 select HAVE_PCI
>> 745 select IRQ_MIPS_CPU
>> 746 select IRQ_DOMAIN_HIERARCHY
>> 747 select NR_CPUS_DEFAULT_2
>> 748 select PCI_DRIVERS_GENERIC
>> 749 select PCI_XTALK_BRIDGE
>> 750 select SYS_HAS_EARLY_PRINTK
>> 751 select SYS_HAS_CPU_R10000
>> 752 select SYS_SUPPORTS_64BIT_KERNEL
>> 753 select SYS_SUPPORTS_BIG_ENDIAN
>> 754 select SYS_SUPPORTS_SMP
>> 755 select WAR_R10000_LLSC
>> 756 select MIPS_L1_CACHE_SHIFT_7
>> 757 select ARC_MEMORY
>> 758 help
>> 759 These are the SGI Octane and Octane2 graphics workstations. To
>> 760 compile a Linux kernel that runs on these, say Y here.
>> 761
>> 762 config SGI_IP32
>> 763 bool "SGI IP32 (O2)"
>> 764 select ARC_MEMORY
>> 765 select ARC_PROMLIB
>> 766 select ARCH_HAS_PHYS_TO_DMA
>> 767 select FW_ARC
>> 768 select FW_ARC32
>> 769 select BOOT_ELF32
>> 770 select CEVT_R4K
>> 771 select CSRC_R4K
>> 772 select DMA_NONCOHERENT
>> 773 select HAVE_PCI
>> 774 select IRQ_MIPS_CPU
>> 775 select R5000_CPU_SCACHE
>> 776 select RM7000_CPU_SCACHE
>> 777 select SYS_HAS_CPU_R5000
>> 778 select SYS_HAS_CPU_R10000 if BROKEN
>> 779 select SYS_HAS_CPU_RM7000
>> 780 select SYS_HAS_CPU_NEVADA
>> 781 select SYS_SUPPORTS_64BIT_KERNEL
>> 782 select SYS_SUPPORTS_BIG_ENDIAN
>> 783 select WAR_ICACHE_REFILLS
>> 784 help
>> 785 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 786
>> 787 config SIBYTE_CRHINE
>> 788 bool "Sibyte BCM91120C-CRhine"
>> 789 select BOOT_ELF32
>> 790 select SIBYTE_BCM1120
>> 791 select SWAP_IO_SPACE
>> 792 select SYS_HAS_CPU_SB1
>> 793 select SYS_SUPPORTS_BIG_ENDIAN
>> 794 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 795
>> 796 config SIBYTE_CARMEL
>> 797 bool "Sibyte BCM91120x-Carmel"
>> 798 select BOOT_ELF32
>> 799 select SIBYTE_BCM1120
>> 800 select SWAP_IO_SPACE
>> 801 select SYS_HAS_CPU_SB1
>> 802 select SYS_SUPPORTS_BIG_ENDIAN
>> 803 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 804
>> 805 config SIBYTE_CRHONE
>> 806 bool "Sibyte BCM91125C-CRhone"
>> 807 select BOOT_ELF32
>> 808 select SIBYTE_BCM1125
>> 809 select SWAP_IO_SPACE
>> 810 select SYS_HAS_CPU_SB1
>> 811 select SYS_SUPPORTS_BIG_ENDIAN
>> 812 select SYS_SUPPORTS_HIGHMEM
>> 813 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 814
>> 815 config SIBYTE_RHONE
>> 816 bool "Sibyte BCM91125E-Rhone"
>> 817 select BOOT_ELF32
>> 818 select SIBYTE_BCM1125H
>> 819 select SWAP_IO_SPACE
>> 820 select SYS_HAS_CPU_SB1
>> 821 select SYS_SUPPORTS_BIG_ENDIAN
>> 822 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 823
>> 824 config SIBYTE_SWARM
>> 825 bool "Sibyte BCM91250A-SWARM"
>> 826 select BOOT_ELF32
>> 827 select HAVE_PATA_PLATFORM
>> 828 select SIBYTE_SB1250
>> 829 select SWAP_IO_SPACE
>> 830 select SYS_HAS_CPU_SB1
>> 831 select SYS_SUPPORTS_BIG_ENDIAN
>> 832 select SYS_SUPPORTS_HIGHMEM
>> 833 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 834 select ZONE_DMA32 if 64BIT
>> 835 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 836
>> 837 config SIBYTE_LITTLESUR
>> 838 bool "Sibyte BCM91250C2-LittleSur"
>> 839 select BOOT_ELF32
>> 840 select HAVE_PATA_PLATFORM
>> 841 select SIBYTE_SB1250
>> 842 select SWAP_IO_SPACE
>> 843 select SYS_HAS_CPU_SB1
>> 844 select SYS_SUPPORTS_BIG_ENDIAN
>> 845 select SYS_SUPPORTS_HIGHMEM
>> 846 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 847 select ZONE_DMA32 if 64BIT
>> 848
>> 849 config SIBYTE_SENTOSA
>> 850 bool "Sibyte BCM91250E-Sentosa"
>> 851 select BOOT_ELF32
>> 852 select SIBYTE_SB1250
>> 853 select SWAP_IO_SPACE
>> 854 select SYS_HAS_CPU_SB1
>> 855 select SYS_SUPPORTS_BIG_ENDIAN
>> 856 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 857 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 858
>> 859 config SIBYTE_BIGSUR
>> 860 bool "Sibyte BCM91480B-BigSur"
>> 861 select BOOT_ELF32
>> 862 select NR_CPUS_DEFAULT_4
>> 863 select SIBYTE_BCM1x80
>> 864 select SWAP_IO_SPACE
>> 865 select SYS_HAS_CPU_SB1
>> 866 select SYS_SUPPORTS_BIG_ENDIAN
>> 867 select SYS_SUPPORTS_HIGHMEM
>> 868 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 869 select ZONE_DMA32 if 64BIT
>> 870 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 871
>> 872 config SNI_RM
>> 873 bool "SNI RM200/300/400"
>> 874 select ARC_MEMORY
>> 875 select ARC_PROMLIB
>> 876 select FW_ARC if CPU_LITTLE_ENDIAN
>> 877 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 878 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 879 select ARCH_MAY_HAVE_PC_FDC
>> 880 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 881 select ARCH_MIGHT_HAVE_PC_SERIO
>> 882 select BOOT_ELF32
>> 883 select CEVT_R4K
>> 884 select CSRC_R4K
>> 885 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 886 select DMA_NONCOHERENT
>> 887 select GENERIC_ISA_DMA
>> 888 select HAVE_EISA
>> 889 select HAVE_PCSPKR_PLATFORM
>> 890 select HAVE_PCI
>> 891 select IRQ_MIPS_CPU
>> 892 select I8253
>> 893 select I8259
>> 894 select ISA
>> 895 select MIPS_L1_CACHE_SHIFT_6
>> 896 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 897 select SYS_HAS_CPU_R4X00
>> 898 select SYS_HAS_CPU_R5000
>> 899 select SYS_HAS_CPU_R10000
>> 900 select R5000_CPU_SCACHE
>> 901 select SYS_HAS_EARLY_PRINTK
>> 902 select SYS_SUPPORTS_32BIT_KERNEL
>> 903 select SYS_SUPPORTS_64BIT_KERNEL
>> 904 select SYS_SUPPORTS_BIG_ENDIAN
>> 905 select SYS_SUPPORTS_HIGHMEM
>> 906 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 907 select WAR_R4600_V2_HIT_CACHEOP
>> 908 help
>> 909 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 910 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 911 Technology and now in turn merged with Fujitsu. Say Y here to
>> 912 support this machine type.
>> 913
>> 914 config MACH_TX39XX
>> 915 bool "Toshiba TX39 series based machines"
>> 916
>> 917 config MACH_TX49XX
>> 918 bool "Toshiba TX49 series based machines"
>> 919 select WAR_TX49XX_ICACHE_INDEX_INV
>> 920
>> 921 config MIKROTIK_RB532
>> 922 bool "Mikrotik RB532 boards"
>> 923 select CEVT_R4K
>> 924 select CSRC_R4K
>> 925 select DMA_NONCOHERENT
>> 926 select HAVE_PCI
>> 927 select IRQ_MIPS_CPU
>> 928 select SYS_HAS_CPU_MIPS32_R1
>> 929 select SYS_SUPPORTS_32BIT_KERNEL
>> 930 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 931 select SWAP_IO_SPACE
>> 932 select BOOT_RAW
>> 933 select GPIOLIB
>> 934 select MIPS_L1_CACHE_SHIFT_4
>> 935 help
>> 936 Support the Mikrotik(tm) RouterBoard 532 series,
>> 937 based on the IDT RC32434 SoC.
>> 938
>> 939 config CAVIUM_OCTEON_SOC
>> 940 bool "Cavium Networks Octeon SoC based boards"
>> 941 select CEVT_R4K
>> 942 select ARCH_HAS_PHYS_TO_DMA
>> 943 select HAVE_RAPIDIO
>> 944 select PHYS_ADDR_T_64BIT
>> 945 select SYS_SUPPORTS_64BIT_KERNEL
>> 946 select SYS_SUPPORTS_BIG_ENDIAN
>> 947 select EDAC_SUPPORT
>> 948 select EDAC_ATOMIC_SCRUB
>> 949 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 950 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 951 select SYS_HAS_EARLY_PRINTK
>> 952 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 953 select HAVE_PCI
>> 954 select HAVE_PLAT_DELAY
>> 955 select HAVE_PLAT_FW_INIT_CMDLINE
>> 956 select HAVE_PLAT_MEMCPY
>> 957 select ZONE_DMA32
>> 958 select HOLES_IN_ZONE
>> 959 select GPIOLIB
>> 960 select USE_OF
>> 961 select ARCH_SPARSEMEM_ENABLE
>> 962 select SYS_SUPPORTS_SMP
>> 963 select NR_CPUS_DEFAULT_64
>> 964 select MIPS_NR_CPU_NR_MAP_1024
>> 965 select BUILTIN_DTB
>> 966 select MTD_COMPLEX_MAPPINGS
>> 967 select SWIOTLB
>> 968 select SYS_SUPPORTS_RELOCATABLE
>> 969 help
>> 970 This option supports all of the Octeon reference boards from Cavium
>> 971 Networks. It builds a kernel that dynamically determines the Octeon
>> 972 CPU type and supports all known board reference implementations.
>> 973 Some of the supported boards are:
>> 974 EBT3000
>> 975 EBH3000
>> 976 EBH3100
>> 977 Thunder
>> 978 Kodama
>> 979 Hikari
>> 980 Say Y here for most Octeon reference boards.
>> 981
>> 982 config NLM_XLR_BOARD
>> 983 bool "Netlogic XLR/XLS based systems"
>> 984 select BOOT_ELF32
>> 985 select NLM_COMMON
>> 986 select SYS_HAS_CPU_XLR
>> 987 select SYS_SUPPORTS_SMP
>> 988 select HAVE_PCI
>> 989 select SWAP_IO_SPACE
>> 990 select SYS_SUPPORTS_32BIT_KERNEL
>> 991 select SYS_SUPPORTS_64BIT_KERNEL
>> 992 select PHYS_ADDR_T_64BIT
>> 993 select SYS_SUPPORTS_BIG_ENDIAN
>> 994 select SYS_SUPPORTS_HIGHMEM
>> 995 select NR_CPUS_DEFAULT_32
>> 996 select CEVT_R4K
>> 997 select CSRC_R4K
>> 998 select IRQ_MIPS_CPU
>> 999 select ZONE_DMA32 if 64BIT
>> 1000 select SYNC_R4K
>> 1001 select SYS_HAS_EARLY_PRINTK
>> 1002 select SYS_SUPPORTS_ZBOOT
>> 1003 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1004 help
>> 1005 Support for systems based on Netlogic XLR and XLS processors.
>> 1006 Say Y here if you have a XLR or XLS based board.
>> 1007
>> 1008 config NLM_XLP_BOARD
>> 1009 bool "Netlogic XLP based systems"
>> 1010 select BOOT_ELF32
>> 1011 select NLM_COMMON
>> 1012 select SYS_HAS_CPU_XLP
>> 1013 select SYS_SUPPORTS_SMP
>> 1014 select HAVE_PCI
>> 1015 select SYS_SUPPORTS_32BIT_KERNEL
>> 1016 select SYS_SUPPORTS_64BIT_KERNEL
>> 1017 select PHYS_ADDR_T_64BIT
>> 1018 select GPIOLIB
>> 1019 select SYS_SUPPORTS_BIG_ENDIAN
>> 1020 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1021 select SYS_SUPPORTS_HIGHMEM
>> 1022 select NR_CPUS_DEFAULT_32
>> 1023 select CEVT_R4K
>> 1024 select CSRC_R4K
>> 1025 select IRQ_MIPS_CPU
>> 1026 select ZONE_DMA32 if 64BIT
>> 1027 select SYNC_R4K
>> 1028 select SYS_HAS_EARLY_PRINTK
>> 1029 select USE_OF
>> 1030 select SYS_SUPPORTS_ZBOOT
>> 1031 select SYS_SUPPORTS_ZBOOT_UART16550
60 help 1032 help
61 Xtensa processors are 32-bit RISC ma !! 1033 This board is based on Netlogic XLP Processor.
62 primarily for embedded systems. The !! 1034 Say Y here if you have a XLP based board.
63 configurable and extensible. The Li !! 1035
64 architecture supports all processor !! 1036 endchoice
65 with reasonable minimum requirements !! 1037
66 a home page at <http://www.linux-xte !! 1038 source "arch/mips/alchemy/Kconfig"
>> 1039 source "arch/mips/ath25/Kconfig"
>> 1040 source "arch/mips/ath79/Kconfig"
>> 1041 source "arch/mips/bcm47xx/Kconfig"
>> 1042 source "arch/mips/bcm63xx/Kconfig"
>> 1043 source "arch/mips/bmips/Kconfig"
>> 1044 source "arch/mips/generic/Kconfig"
>> 1045 source "arch/mips/ingenic/Kconfig"
>> 1046 source "arch/mips/jazz/Kconfig"
>> 1047 source "arch/mips/lantiq/Kconfig"
>> 1048 source "arch/mips/pic32/Kconfig"
>> 1049 source "arch/mips/pistachio/Kconfig"
>> 1050 source "arch/mips/ralink/Kconfig"
>> 1051 source "arch/mips/sgi-ip27/Kconfig"
>> 1052 source "arch/mips/sibyte/Kconfig"
>> 1053 source "arch/mips/txx9/Kconfig"
>> 1054 source "arch/mips/vr41xx/Kconfig"
>> 1055 source "arch/mips/cavium-octeon/Kconfig"
>> 1056 source "arch/mips/loongson2ef/Kconfig"
>> 1057 source "arch/mips/loongson32/Kconfig"
>> 1058 source "arch/mips/loongson64/Kconfig"
>> 1059 source "arch/mips/netlogic/Kconfig"
>> 1060
>> 1061 endmenu
67 1062
68 config GENERIC_HWEIGHT 1063 config GENERIC_HWEIGHT
69 def_bool y !! 1064 bool
>> 1065 default y
70 1066
71 config ARCH_HAS_ILOG2_U32 !! 1067 config GENERIC_CALIBRATE_DELAY
72 def_bool n !! 1068 bool
>> 1069 default y
73 1070
74 config ARCH_HAS_ILOG2_U64 !! 1071 config SCHED_OMIT_FRAME_POINTER
75 def_bool n !! 1072 bool
>> 1073 default y
76 1074
77 config ARCH_MTD_XIP !! 1075 #
78 def_bool y !! 1076 # Select some configuration options automatically based on user selections.
>> 1077 #
>> 1078 config FW_ARC
>> 1079 bool
>> 1080
>> 1081 config ARCH_MAY_HAVE_PC_FDC
>> 1082 bool
>> 1083
>> 1084 config BOOT_RAW
>> 1085 bool
>> 1086
>> 1087 config CEVT_BCM1480
>> 1088 bool
>> 1089
>> 1090 config CEVT_DS1287
>> 1091 bool
>> 1092
>> 1093 config CEVT_GT641XX
>> 1094 bool
>> 1095
>> 1096 config CEVT_R4K
>> 1097 bool
>> 1098
>> 1099 config CEVT_SB1250
>> 1100 bool
>> 1101
>> 1102 config CEVT_TXX9
>> 1103 bool
>> 1104
>> 1105 config CSRC_BCM1480
>> 1106 bool
>> 1107
>> 1108 config CSRC_IOASIC
>> 1109 bool
>> 1110
>> 1111 config CSRC_R4K
>> 1112 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1113 bool
>> 1114
>> 1115 config CSRC_SB1250
>> 1116 bool
>> 1117
>> 1118 config MIPS_CLOCK_VSYSCALL
>> 1119 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1120
>> 1121 config GPIO_TXX9
>> 1122 select GPIOLIB
>> 1123 bool
>> 1124
>> 1125 config FW_CFE
>> 1126 bool
>> 1127
>> 1128 config ARCH_SUPPORTS_UPROBES
>> 1129 bool
>> 1130
>> 1131 config DMA_MAYBE_COHERENT
>> 1132 select ARCH_HAS_DMA_COHERENCE_H
>> 1133 select DMA_NONCOHERENT
>> 1134 bool
>> 1135
>> 1136 config DMA_PERDEV_COHERENT
>> 1137 bool
>> 1138 select ARCH_HAS_SETUP_DMA_OPS
>> 1139 select DMA_NONCOHERENT
>> 1140
>> 1141 config DMA_NONCOHERENT
>> 1142 bool
>> 1143 #
>> 1144 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1145 # Attribute bits. It is believed that the uncached access through
>> 1146 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1147 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1148 # significant advantages.
>> 1149 #
>> 1150 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1151 select ARCH_HAS_DMA_PREP_COHERENT
>> 1152 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1153 select ARCH_HAS_DMA_SET_UNCACHED
>> 1154 select DMA_NONCOHERENT_MMAP
>> 1155 select NEED_DMA_MAP_STATE
>> 1156
>> 1157 config SYS_HAS_EARLY_PRINTK
>> 1158 bool
>> 1159
>> 1160 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1161 bool
>> 1162
>> 1163 config MIPS_BONITO64
>> 1164 bool
>> 1165
>> 1166 config MIPS_MSC
>> 1167 bool
>> 1168
>> 1169 config SYNC_R4K
>> 1170 bool
79 1171
80 config NO_IOPORT_MAP 1172 config NO_IOPORT_MAP
81 def_bool n 1173 def_bool n
82 1174
83 config HZ !! 1175 config GENERIC_CSUM
84 int !! 1176 def_bool CPU_NO_LOAD_STORE_LR
85 default 100 <<
86 1177
87 config LOCKDEP_SUPPORT !! 1178 config GENERIC_ISA_DMA
88 def_bool y !! 1179 bool
>> 1180 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1181 select ISA_DMA_API
89 1182
90 config STACKTRACE_SUPPORT !! 1183 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1184 bool
>> 1185 select GENERIC_ISA_DMA
>> 1186
>> 1187 config HAVE_PLAT_DELAY
>> 1188 bool
>> 1189
>> 1190 config HAVE_PLAT_FW_INIT_CMDLINE
>> 1191 bool
>> 1192
>> 1193 config HAVE_PLAT_MEMCPY
>> 1194 bool
>> 1195
>> 1196 config ISA_DMA_API
>> 1197 bool
>> 1198
>> 1199 config HOLES_IN_ZONE
>> 1200 bool
>> 1201
>> 1202 config SYS_SUPPORTS_RELOCATABLE
>> 1203 bool
>> 1204 help
>> 1205 Selected if the platform supports relocating the kernel.
>> 1206 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1207 to allow access to command line and entropy sources.
>> 1208
>> 1209 config MIPS_CBPF_JIT
91 def_bool y 1210 def_bool y
>> 1211 depends on BPF_JIT && HAVE_CBPF_JIT
92 1212
93 config MMU !! 1213 config MIPS_EBPF_JIT
94 def_bool n !! 1214 def_bool y
95 select PFAULT !! 1215 depends on BPF_JIT && HAVE_EBPF_JIT
96 1216
97 config HAVE_XTENSA_GPIO32 <<
98 def_bool n <<
99 1217
100 config KASAN_SHADOW_OFFSET !! 1218 #
101 hex !! 1219 # Endianness selection. Sufficiently obscure so many users don't know what to
102 default 0x6e400000 !! 1220 # answer,so we try hard to limit the available choices. Also the use of a
>> 1221 # choice statement should be more obvious to the user.
>> 1222 #
>> 1223 choice
>> 1224 prompt "Endianness selection"
>> 1225 help
>> 1226 Some MIPS machines can be configured for either little or big endian
>> 1227 byte order. These modes require different kernels and a different
>> 1228 Linux distribution. In general there is one preferred byteorder for a
>> 1229 particular system but some systems are just as commonly used in the
>> 1230 one or the other endianness.
103 1231
104 config CPU_BIG_ENDIAN 1232 config CPU_BIG_ENDIAN
105 def_bool $(success,test "$(shell,echo !! 1233 bool "Big endian"
>> 1234 depends on SYS_SUPPORTS_BIG_ENDIAN
106 1235
107 config CPU_LITTLE_ENDIAN 1236 config CPU_LITTLE_ENDIAN
108 def_bool !CPU_BIG_ENDIAN !! 1237 bool "Little endian"
>> 1238 depends on SYS_SUPPORTS_LITTLE_ENDIAN
>> 1239
>> 1240 endchoice
>> 1241
>> 1242 config EXPORT_UASM
>> 1243 bool
>> 1244
>> 1245 config SYS_SUPPORTS_APM_EMULATION
>> 1246 bool
>> 1247
>> 1248 config SYS_SUPPORTS_BIG_ENDIAN
>> 1249 bool
>> 1250
>> 1251 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1252 bool
>> 1253
>> 1254 config SYS_SUPPORTS_HUGETLBFS
>> 1255 bool
>> 1256 depends on CPU_SUPPORTS_HUGEPAGES
>> 1257 default y
>> 1258
>> 1259 config MIPS_HUGE_TLB_SUPPORT
>> 1260 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
>> 1261
>> 1262 config IRQ_CPU_RM7K
>> 1263 bool
>> 1264
>> 1265 config IRQ_MSP_SLP
>> 1266 bool
>> 1267
>> 1268 config IRQ_MSP_CIC
>> 1269 bool
>> 1270
>> 1271 config IRQ_TXX9
>> 1272 bool
>> 1273
>> 1274 config IRQ_GT641XX
>> 1275 bool
>> 1276
>> 1277 config PCI_GT64XXX_PCI0
>> 1278 bool
>> 1279
>> 1280 config PCI_XTALK_BRIDGE
>> 1281 bool
>> 1282
>> 1283 config NO_EXCEPT_FILL
>> 1284 bool
>> 1285
>> 1286 config MIPS_SPRAM
>> 1287 bool
>> 1288
>> 1289 config SWAP_IO_SPACE
>> 1290 bool
>> 1291
>> 1292 config SGI_HAS_INDYDOG
>> 1293 bool
>> 1294
>> 1295 config SGI_HAS_HAL2
>> 1296 bool
>> 1297
>> 1298 config SGI_HAS_SEEQ
>> 1299 bool
>> 1300
>> 1301 config SGI_HAS_WD93
>> 1302 bool
>> 1303
>> 1304 config SGI_HAS_ZILOG
>> 1305 bool
>> 1306
>> 1307 config SGI_HAS_I8042
>> 1308 bool
>> 1309
>> 1310 config DEFAULT_SGI_PARTITION
>> 1311 bool
>> 1312
>> 1313 config FW_ARC32
>> 1314 bool
>> 1315
>> 1316 config FW_SNIPROM
>> 1317 bool
>> 1318
>> 1319 config BOOT_ELF32
>> 1320 bool
>> 1321
>> 1322 config MIPS_L1_CACHE_SHIFT_4
>> 1323 bool
>> 1324
>> 1325 config MIPS_L1_CACHE_SHIFT_5
>> 1326 bool
>> 1327
>> 1328 config MIPS_L1_CACHE_SHIFT_6
>> 1329 bool
>> 1330
>> 1331 config MIPS_L1_CACHE_SHIFT_7
>> 1332 bool
>> 1333
>> 1334 config MIPS_L1_CACHE_SHIFT
>> 1335 int
>> 1336 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1337 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1338 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1339 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1340 default "5"
>> 1341
>> 1342 config ARC_CMDLINE_ONLY
>> 1343 bool
>> 1344
>> 1345 config ARC_CONSOLE
>> 1346 bool "ARC console support"
>> 1347 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
>> 1348
>> 1349 config ARC_MEMORY
>> 1350 bool
>> 1351
>> 1352 config ARC_PROMLIB
>> 1353 bool
>> 1354
>> 1355 config FW_ARC64
>> 1356 bool
109 1357
110 config CC_HAVE_CALL0_ABI !! 1358 config BOOT_ELF64
111 def_bool $(success,test "$(shell,echo !! 1359 bool
112 1360
113 menu "Processor type and features" !! 1361 menu "CPU selection"
114 1362
115 choice 1363 choice
116 prompt "Xtensa Processor Configuration !! 1364 prompt "CPU type"
117 default XTENSA_VARIANT_FSF !! 1365 default CPU_R4X00
118 1366
119 config XTENSA_VARIANT_FSF !! 1367 config CPU_LOONGSON64
120 bool "fsf - default (not generic) conf !! 1368 bool "Loongson 64-bit CPU"
121 select MMU !! 1369 depends on SYS_HAS_CPU_LOONGSON64
>> 1370 select ARCH_HAS_PHYS_TO_DMA
>> 1371 select CPU_MIPSR2
>> 1372 select CPU_HAS_PREFETCH
>> 1373 select CPU_SUPPORTS_64BIT_KERNEL
>> 1374 select CPU_SUPPORTS_HIGHMEM
>> 1375 select CPU_SUPPORTS_HUGEPAGES
>> 1376 select CPU_SUPPORTS_MSA
>> 1377 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1378 select CPU_MIPSR2_IRQ_VI
>> 1379 select WEAK_ORDERING
>> 1380 select WEAK_REORDERING_BEYOND_LLSC
>> 1381 select MIPS_ASID_BITS_VARIABLE
>> 1382 select MIPS_PGD_C0_CONTEXT
>> 1383 select MIPS_L1_CACHE_SHIFT_6
>> 1384 select GPIOLIB
>> 1385 select SWIOTLB
>> 1386 select HAVE_KVM
>> 1387 help
>> 1388 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1389 cores implements the MIPS64R2 instruction set with many extensions,
>> 1390 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1391 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1392 Loongson-2E/2F is not covered here and will be removed in future.
122 1393
123 config XTENSA_VARIANT_DC232B !! 1394 config LOONGSON3_ENHANCEMENT
124 bool "dc232b - Diamond 232L Standard C !! 1395 bool "New Loongson-3 CPU Enhancements"
125 select MMU !! 1396 default n
126 select HAVE_XTENSA_GPIO32 !! 1397 depends on CPU_LOONGSON64
127 help 1398 help
128 This variant refers to Tensilica's D !! 1399 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1400 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1401 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1402 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1403 Fast TLB refill support, etc.
>> 1404
>> 1405 This option enable those enhancements which are not probed at run
>> 1406 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1407 please say 'N' here. If you want a high-performance kernel to run on
>> 1408 new Loongson-3 machines only, please say 'Y' here.
>> 1409
>> 1410 config CPU_LOONGSON3_WORKAROUNDS
>> 1411 bool "Old Loongson-3 LLSC Workarounds"
>> 1412 default y if SMP
>> 1413 depends on CPU_LOONGSON64
>> 1414 help
>> 1415 Loongson-3 processors have the llsc issues which require workarounds.
>> 1416 Without workarounds the system may hang unexpectedly.
>> 1417
>> 1418 Newer Loongson-3 will fix these issues and no workarounds are needed.
>> 1419 The workarounds have no significant side effect on them but may
>> 1420 decrease the performance of the system so this option should be
>> 1421 disabled unless the kernel is intended to be run on old systems.
129 1422
130 config XTENSA_VARIANT_DC233C !! 1423 If unsure, please say Y.
131 bool "dc233c - Diamond 233L Standard C <<
132 select MMU <<
133 select HAVE_XTENSA_GPIO32 <<
134 help <<
135 This variant refers to Tensilica's D <<
136 1424
137 config XTENSA_VARIANT_CUSTOM !! 1425 config CPU_LOONGSON3_CPUCFG_EMULATION
138 bool "Custom Xtensa processor configur !! 1426 bool "Emulate the CPUCFG instruction on older Loongson cores"
139 select HAVE_XTENSA_GPIO32 !! 1427 default y
>> 1428 depends on CPU_LOONGSON64
>> 1429 help
>> 1430 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1431 userland to query CPU capabilities, much like CPUID on x86. This
>> 1432 option provides emulation of the instruction on older Loongson
>> 1433 cores, back to Loongson-3A1000.
>> 1434
>> 1435 If unsure, please say Y.
>> 1436
>> 1437 config CPU_LOONGSON2E
>> 1438 bool "Loongson 2E"
>> 1439 depends on SYS_HAS_CPU_LOONGSON2E
>> 1440 select CPU_LOONGSON2EF
>> 1441 help
>> 1442 The Loongson 2E processor implements the MIPS III instruction set
>> 1443 with many extensions.
>> 1444
>> 1445 It has an internal FPGA northbridge, which is compatible to
>> 1446 bonito64.
>> 1447
>> 1448 config CPU_LOONGSON2F
>> 1449 bool "Loongson 2F"
>> 1450 depends on SYS_HAS_CPU_LOONGSON2F
>> 1451 select CPU_LOONGSON2EF
>> 1452 select GPIOLIB
>> 1453 help
>> 1454 The Loongson 2F processor implements the MIPS III instruction set
>> 1455 with many extensions.
>> 1456
>> 1457 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1458 have a similar programming interface with FPGA northbridge used in
>> 1459 Loongson2E.
>> 1460
>> 1461 config CPU_LOONGSON1B
>> 1462 bool "Loongson 1B"
>> 1463 depends on SYS_HAS_CPU_LOONGSON1B
>> 1464 select CPU_LOONGSON32
>> 1465 select LEDS_GPIO_REGISTER
>> 1466 help
>> 1467 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1468 Release 1 instruction set and part of the MIPS32 Release 2
>> 1469 instruction set.
>> 1470
>> 1471 config CPU_LOONGSON1C
>> 1472 bool "Loongson 1C"
>> 1473 depends on SYS_HAS_CPU_LOONGSON1C
>> 1474 select CPU_LOONGSON32
>> 1475 select LEDS_GPIO_REGISTER
>> 1476 help
>> 1477 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1478 Release 1 instruction set and part of the MIPS32 Release 2
>> 1479 instruction set.
>> 1480
>> 1481 config CPU_MIPS32_R1
>> 1482 bool "MIPS32 Release 1"
>> 1483 depends on SYS_HAS_CPU_MIPS32_R1
>> 1484 select CPU_HAS_PREFETCH
>> 1485 select CPU_SUPPORTS_32BIT_KERNEL
>> 1486 select CPU_SUPPORTS_HIGHMEM
>> 1487 help
>> 1488 Choose this option to build a kernel for release 1 or later of the
>> 1489 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1490 MIPS processor are based on a MIPS32 processor. If you know the
>> 1491 specific type of processor in your system, choose those that one
>> 1492 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1493 Release 2 of the MIPS32 architecture is available since several
>> 1494 years so chances are you even have a MIPS32 Release 2 processor
>> 1495 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1496 performance.
>> 1497
>> 1498 config CPU_MIPS32_R2
>> 1499 bool "MIPS32 Release 2"
>> 1500 depends on SYS_HAS_CPU_MIPS32_R2
>> 1501 select CPU_HAS_PREFETCH
>> 1502 select CPU_SUPPORTS_32BIT_KERNEL
>> 1503 select CPU_SUPPORTS_HIGHMEM
>> 1504 select CPU_SUPPORTS_MSA
>> 1505 select HAVE_KVM
>> 1506 help
>> 1507 Choose this option to build a kernel for release 2 or later of the
>> 1508 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1509 MIPS processor are based on a MIPS32 processor. If you know the
>> 1510 specific type of processor in your system, choose those that one
>> 1511 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1512
>> 1513 config CPU_MIPS32_R5
>> 1514 bool "MIPS32 Release 5"
>> 1515 depends on SYS_HAS_CPU_MIPS32_R5
>> 1516 select CPU_HAS_PREFETCH
>> 1517 select CPU_SUPPORTS_32BIT_KERNEL
>> 1518 select CPU_SUPPORTS_HIGHMEM
>> 1519 select CPU_SUPPORTS_MSA
>> 1520 select HAVE_KVM
>> 1521 select MIPS_O32_FP64_SUPPORT
>> 1522 help
>> 1523 Choose this option to build a kernel for release 5 or later of the
>> 1524 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1525 family, are based on a MIPS32r5 processor. If you own an older
>> 1526 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1527
>> 1528 config CPU_MIPS32_R6
>> 1529 bool "MIPS32 Release 6"
>> 1530 depends on SYS_HAS_CPU_MIPS32_R6
>> 1531 select CPU_HAS_PREFETCH
>> 1532 select CPU_NO_LOAD_STORE_LR
>> 1533 select CPU_SUPPORTS_32BIT_KERNEL
>> 1534 select CPU_SUPPORTS_HIGHMEM
>> 1535 select CPU_SUPPORTS_MSA
>> 1536 select HAVE_KVM
>> 1537 select MIPS_O32_FP64_SUPPORT
>> 1538 help
>> 1539 Choose this option to build a kernel for release 6 or later of the
>> 1540 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1541 family, are based on a MIPS32r6 processor. If you own an older
>> 1542 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1543
>> 1544 config CPU_MIPS64_R1
>> 1545 bool "MIPS64 Release 1"
>> 1546 depends on SYS_HAS_CPU_MIPS64_R1
>> 1547 select CPU_HAS_PREFETCH
>> 1548 select CPU_SUPPORTS_32BIT_KERNEL
>> 1549 select CPU_SUPPORTS_64BIT_KERNEL
>> 1550 select CPU_SUPPORTS_HIGHMEM
>> 1551 select CPU_SUPPORTS_HUGEPAGES
>> 1552 help
>> 1553 Choose this option to build a kernel for release 1 or later of the
>> 1554 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1555 MIPS processor are based on a MIPS64 processor. If you know the
>> 1556 specific type of processor in your system, choose those that one
>> 1557 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1558 Release 2 of the MIPS64 architecture is available since several
>> 1559 years so chances are you even have a MIPS64 Release 2 processor
>> 1560 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1561 performance.
>> 1562
>> 1563 config CPU_MIPS64_R2
>> 1564 bool "MIPS64 Release 2"
>> 1565 depends on SYS_HAS_CPU_MIPS64_R2
>> 1566 select CPU_HAS_PREFETCH
>> 1567 select CPU_SUPPORTS_32BIT_KERNEL
>> 1568 select CPU_SUPPORTS_64BIT_KERNEL
>> 1569 select CPU_SUPPORTS_HIGHMEM
>> 1570 select CPU_SUPPORTS_HUGEPAGES
>> 1571 select CPU_SUPPORTS_MSA
>> 1572 select HAVE_KVM
>> 1573 help
>> 1574 Choose this option to build a kernel for release 2 or later of the
>> 1575 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1576 MIPS processor are based on a MIPS64 processor. If you know the
>> 1577 specific type of processor in your system, choose those that one
>> 1578 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1579
>> 1580 config CPU_MIPS64_R5
>> 1581 bool "MIPS64 Release 5"
>> 1582 depends on SYS_HAS_CPU_MIPS64_R5
>> 1583 select CPU_HAS_PREFETCH
>> 1584 select CPU_SUPPORTS_32BIT_KERNEL
>> 1585 select CPU_SUPPORTS_64BIT_KERNEL
>> 1586 select CPU_SUPPORTS_HIGHMEM
>> 1587 select CPU_SUPPORTS_HUGEPAGES
>> 1588 select CPU_SUPPORTS_MSA
>> 1589 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1590 select HAVE_KVM
>> 1591 help
>> 1592 Choose this option to build a kernel for release 5 or later of the
>> 1593 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1594 release partly implementing release 6 features. Though there is no
>> 1595 any hardware known to be based on this release.
>> 1596
>> 1597 config CPU_MIPS64_R6
>> 1598 bool "MIPS64 Release 6"
>> 1599 depends on SYS_HAS_CPU_MIPS64_R6
>> 1600 select CPU_HAS_PREFETCH
>> 1601 select CPU_NO_LOAD_STORE_LR
>> 1602 select CPU_SUPPORTS_32BIT_KERNEL
>> 1603 select CPU_SUPPORTS_64BIT_KERNEL
>> 1604 select CPU_SUPPORTS_HIGHMEM
>> 1605 select CPU_SUPPORTS_HUGEPAGES
>> 1606 select CPU_SUPPORTS_MSA
>> 1607 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1608 select HAVE_KVM
>> 1609 help
>> 1610 Choose this option to build a kernel for release 6 or later of the
>> 1611 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1612 family, are based on a MIPS64r6 processor. If you own an older
>> 1613 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1614
>> 1615 config CPU_P5600
>> 1616 bool "MIPS Warrior P5600"
>> 1617 depends on SYS_HAS_CPU_P5600
>> 1618 select CPU_HAS_PREFETCH
>> 1619 select CPU_SUPPORTS_32BIT_KERNEL
>> 1620 select CPU_SUPPORTS_HIGHMEM
>> 1621 select CPU_SUPPORTS_MSA
>> 1622 select CPU_SUPPORTS_CPUFREQ
>> 1623 select CPU_MIPSR2_IRQ_VI
>> 1624 select CPU_MIPSR2_IRQ_EI
>> 1625 select HAVE_KVM
>> 1626 select MIPS_O32_FP64_SUPPORT
>> 1627 help
>> 1628 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1629 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1630 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1631 level features like up to six P5600 calculation cores, CM2 with L2
>> 1632 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1633 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1634 eJTAG and PDtrace.
>> 1635
>> 1636 config CPU_R3000
>> 1637 bool "R3000"
>> 1638 depends on SYS_HAS_CPU_R3000
>> 1639 select CPU_HAS_WB
>> 1640 select CPU_R3K_TLB
>> 1641 select CPU_SUPPORTS_32BIT_KERNEL
>> 1642 select CPU_SUPPORTS_HIGHMEM
>> 1643 help
>> 1644 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1645 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1646 *not* work on R4000 machines and vice versa. However, since most
>> 1647 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1648 might be a safe bet. If the resulting kernel does not work,
>> 1649 try to recompile with R3000.
>> 1650
>> 1651 config CPU_TX39XX
>> 1652 bool "R39XX"
>> 1653 depends on SYS_HAS_CPU_TX39XX
>> 1654 select CPU_SUPPORTS_32BIT_KERNEL
>> 1655 select CPU_R3K_TLB
>> 1656
>> 1657 config CPU_VR41XX
>> 1658 bool "R41xx"
>> 1659 depends on SYS_HAS_CPU_VR41XX
>> 1660 select CPU_SUPPORTS_32BIT_KERNEL
>> 1661 select CPU_SUPPORTS_64BIT_KERNEL
>> 1662 help
>> 1663 The options selects support for the NEC VR4100 series of processors.
>> 1664 Only choose this option if you have one of these processors as a
>> 1665 kernel built with this option will not run on any other type of
>> 1666 processor or vice versa.
>> 1667
>> 1668 config CPU_R4X00
>> 1669 bool "R4x00"
>> 1670 depends on SYS_HAS_CPU_R4X00
>> 1671 select CPU_SUPPORTS_32BIT_KERNEL
>> 1672 select CPU_SUPPORTS_64BIT_KERNEL
>> 1673 select CPU_SUPPORTS_HUGEPAGES
>> 1674 help
>> 1675 MIPS Technologies R4000-series processors other than 4300, including
>> 1676 the R4000, R4400, R4600, and 4700.
>> 1677
>> 1678 config CPU_TX49XX
>> 1679 bool "R49XX"
>> 1680 depends on SYS_HAS_CPU_TX49XX
>> 1681 select CPU_HAS_PREFETCH
>> 1682 select CPU_SUPPORTS_32BIT_KERNEL
>> 1683 select CPU_SUPPORTS_64BIT_KERNEL
>> 1684 select CPU_SUPPORTS_HUGEPAGES
>> 1685
>> 1686 config CPU_R5000
>> 1687 bool "R5000"
>> 1688 depends on SYS_HAS_CPU_R5000
>> 1689 select CPU_SUPPORTS_32BIT_KERNEL
>> 1690 select CPU_SUPPORTS_64BIT_KERNEL
>> 1691 select CPU_SUPPORTS_HUGEPAGES
>> 1692 help
>> 1693 MIPS Technologies R5000-series processors other than the Nevada.
>> 1694
>> 1695 config CPU_R5500
>> 1696 bool "R5500"
>> 1697 depends on SYS_HAS_CPU_R5500
>> 1698 select CPU_SUPPORTS_32BIT_KERNEL
>> 1699 select CPU_SUPPORTS_64BIT_KERNEL
>> 1700 select CPU_SUPPORTS_HUGEPAGES
>> 1701 help
>> 1702 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1703 instruction set.
>> 1704
>> 1705 config CPU_NEVADA
>> 1706 bool "RM52xx"
>> 1707 depends on SYS_HAS_CPU_NEVADA
>> 1708 select CPU_SUPPORTS_32BIT_KERNEL
>> 1709 select CPU_SUPPORTS_64BIT_KERNEL
>> 1710 select CPU_SUPPORTS_HUGEPAGES
>> 1711 help
>> 1712 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1713
>> 1714 config CPU_R10000
>> 1715 bool "R10000"
>> 1716 depends on SYS_HAS_CPU_R10000
>> 1717 select CPU_HAS_PREFETCH
>> 1718 select CPU_SUPPORTS_32BIT_KERNEL
>> 1719 select CPU_SUPPORTS_64BIT_KERNEL
>> 1720 select CPU_SUPPORTS_HIGHMEM
>> 1721 select CPU_SUPPORTS_HUGEPAGES
>> 1722 help
>> 1723 MIPS Technologies R10000-series processors.
>> 1724
>> 1725 config CPU_RM7000
>> 1726 bool "RM7000"
>> 1727 depends on SYS_HAS_CPU_RM7000
>> 1728 select CPU_HAS_PREFETCH
>> 1729 select CPU_SUPPORTS_32BIT_KERNEL
>> 1730 select CPU_SUPPORTS_64BIT_KERNEL
>> 1731 select CPU_SUPPORTS_HIGHMEM
>> 1732 select CPU_SUPPORTS_HUGEPAGES
>> 1733
>> 1734 config CPU_SB1
>> 1735 bool "SB1"
>> 1736 depends on SYS_HAS_CPU_SB1
>> 1737 select CPU_SUPPORTS_32BIT_KERNEL
>> 1738 select CPU_SUPPORTS_64BIT_KERNEL
>> 1739 select CPU_SUPPORTS_HIGHMEM
>> 1740 select CPU_SUPPORTS_HUGEPAGES
>> 1741 select WEAK_ORDERING
>> 1742
>> 1743 config CPU_CAVIUM_OCTEON
>> 1744 bool "Cavium Octeon processor"
>> 1745 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1746 select CPU_HAS_PREFETCH
>> 1747 select CPU_SUPPORTS_64BIT_KERNEL
>> 1748 select WEAK_ORDERING
>> 1749 select CPU_SUPPORTS_HIGHMEM
>> 1750 select CPU_SUPPORTS_HUGEPAGES
>> 1751 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1752 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1753 select MIPS_L1_CACHE_SHIFT_7
>> 1754 select HAVE_KVM
>> 1755 help
>> 1756 The Cavium Octeon processor is a highly integrated chip containing
>> 1757 many ethernet hardware widgets for networking tasks. The processor
>> 1758 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1759 Full details can be found at http://www.caviumnetworks.com.
>> 1760
>> 1761 config CPU_BMIPS
>> 1762 bool "Broadcom BMIPS"
>> 1763 depends on SYS_HAS_CPU_BMIPS
>> 1764 select CPU_MIPS32
>> 1765 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1766 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1767 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1768 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1769 select CPU_SUPPORTS_32BIT_KERNEL
>> 1770 select DMA_NONCOHERENT
>> 1771 select IRQ_MIPS_CPU
>> 1772 select SWAP_IO_SPACE
>> 1773 select WEAK_ORDERING
>> 1774 select CPU_SUPPORTS_HIGHMEM
>> 1775 select CPU_HAS_PREFETCH
>> 1776 select CPU_SUPPORTS_CPUFREQ
>> 1777 select MIPS_EXTERNAL_TIMER
>> 1778 help
>> 1779 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1780
>> 1781 config CPU_XLR
>> 1782 bool "Netlogic XLR SoC"
>> 1783 depends on SYS_HAS_CPU_XLR
>> 1784 select CPU_SUPPORTS_32BIT_KERNEL
>> 1785 select CPU_SUPPORTS_64BIT_KERNEL
>> 1786 select CPU_SUPPORTS_HIGHMEM
>> 1787 select CPU_SUPPORTS_HUGEPAGES
>> 1788 select WEAK_ORDERING
>> 1789 select WEAK_REORDERING_BEYOND_LLSC
>> 1790 help
>> 1791 Netlogic Microsystems XLR/XLS processors.
>> 1792
>> 1793 config CPU_XLP
>> 1794 bool "Netlogic XLP SoC"
>> 1795 depends on SYS_HAS_CPU_XLP
>> 1796 select CPU_SUPPORTS_32BIT_KERNEL
>> 1797 select CPU_SUPPORTS_64BIT_KERNEL
>> 1798 select CPU_SUPPORTS_HIGHMEM
>> 1799 select WEAK_ORDERING
>> 1800 select WEAK_REORDERING_BEYOND_LLSC
>> 1801 select CPU_HAS_PREFETCH
>> 1802 select CPU_MIPSR2
>> 1803 select CPU_SUPPORTS_HUGEPAGES
>> 1804 select MIPS_ASID_BITS_VARIABLE
140 help 1805 help
141 Select this variant to use a custom !! 1806 Netlogic Microsystems XLP processors.
142 You will be prompted for a processor <<
143 endchoice 1807 endchoice
144 1808
145 config XTENSA_VARIANT_CUSTOM_NAME !! 1809 config CPU_MIPS32_3_5_FEATURES
146 string "Xtensa Processor Custom Core V !! 1810 bool "MIPS32 Release 3.5 Features"
147 depends on XTENSA_VARIANT_CUSTOM !! 1811 depends on SYS_HAS_CPU_MIPS32_R3_5
148 help !! 1812 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
149 Provide the name of a custom Xtensa !! 1813 CPU_P5600
150 This CORENAME selects arch/xtensa/va !! 1814 help
151 Don't forget you have to select MMU !! 1815 Choose this option to build a kernel for release 2 or later of the
152 !! 1816 MIPS32 architecture including features from the 3.5 release such as
153 config XTENSA_VARIANT_NAME !! 1817 support for Enhanced Virtual Addressing (EVA).
154 string !! 1818
155 default "dc232b" !! 1819 config CPU_MIPS32_3_5_EVA
156 default "dc233c" !! 1820 bool "Enhanced Virtual Addressing (EVA)"
157 default "fsf" !! 1821 depends on CPU_MIPS32_3_5_FEATURES
158 default XTENSA_VARIANT_CUSTOM_NAME !! 1822 select EVA
159 !! 1823 default y
160 config XTENSA_VARIANT_MMU !! 1824 help
161 bool "Core variant has a Full MMU (TLB !! 1825 Choose this option if you want to enable the Enhanced Virtual
162 depends on XTENSA_VARIANT_CUSTOM !! 1826 Addressing (EVA) on your MIPS32 core (such as proAptiv).
163 default y !! 1827 One of its primary benefits is an increase in the maximum size
164 select MMU !! 1828 of lowmem (up to 3GB). If unsure, say 'N' here.
165 help !! 1829
166 Build a Conventional Kernel with ful !! 1830 config CPU_MIPS32_R5_FEATURES
167 ie: it supports a TLB with auto-load !! 1831 bool "MIPS32 Release 5 Features"
168 !! 1832 depends on SYS_HAS_CPU_MIPS32_R5
169 config XTENSA_VARIANT_HAVE_PERF_EVENTS !! 1833 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
170 bool "Core variant has Performance Mon !! 1834 help
171 depends on XTENSA_VARIANT_CUSTOM !! 1835 Choose this option to build a kernel for release 2 or later of the
>> 1836 MIPS32 architecture including features from release 5 such as
>> 1837 support for Extended Physical Addressing (XPA).
>> 1838
>> 1839 config CPU_MIPS32_R5_XPA
>> 1840 bool "Extended Physical Addressing (XPA)"
>> 1841 depends on CPU_MIPS32_R5_FEATURES
>> 1842 depends on !EVA
>> 1843 depends on !PAGE_SIZE_4KB
>> 1844 depends on SYS_SUPPORTS_HIGHMEM
>> 1845 select XPA
>> 1846 select HIGHMEM
>> 1847 select PHYS_ADDR_T_64BIT
172 default n 1848 default n
173 help 1849 help
174 Enable if core variant has Performan !! 1850 Choose this option if you want to enable the Extended Physical
175 External Registers Interface. !! 1851 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1852 benefit is to increase physical addressing equal to or greater
>> 1853 than 40 bits. Note that this has the side effect of turning on
>> 1854 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1855 If unsure, say 'N' here.
176 1856
177 If unsure, say N. !! 1857 if CPU_LOONGSON2F
>> 1858 config CPU_NOP_WORKAROUNDS
>> 1859 bool
178 1860
179 config XTENSA_FAKE_NMI !! 1861 config CPU_JUMP_WORKAROUNDS
180 bool "Treat PMM IRQ as NMI" !! 1862 bool
181 depends on XTENSA_VARIANT_HAVE_PERF_EV !! 1863
182 default n !! 1864 config CPU_LOONGSON2F_WORKAROUNDS
>> 1865 bool "Loongson 2F Workarounds"
>> 1866 default y
>> 1867 select CPU_NOP_WORKAROUNDS
>> 1868 select CPU_JUMP_WORKAROUNDS
183 help 1869 help
184 If PMM IRQ is the only IRQ at EXCM l !! 1870 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
185 treat it as NMI, which improves accu !! 1871 require workarounds. Without workarounds the system may hang
>> 1872 unexpectedly. For more information please refer to the gas
>> 1873 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1874
>> 1875 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1876 are needed. The workarounds have no significant side effect on them
>> 1877 but may decrease the performance of the system so this option should
>> 1878 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1879 systems.
186 1880
187 If there are other interrupts at or !! 1881 If unsure, please say Y.
188 but not above the EXCM level, PMM IR !! 1882 endif # CPU_LOONGSON2F
189 but only if these IRQs are not used. <<
190 saying that this is not safe, and a <<
191 actually fire. <<
192 1883
193 If unsure, say N. !! 1884 config SYS_SUPPORTS_ZBOOT
>> 1885 bool
>> 1886 select HAVE_KERNEL_GZIP
>> 1887 select HAVE_KERNEL_BZIP2
>> 1888 select HAVE_KERNEL_LZ4
>> 1889 select HAVE_KERNEL_LZMA
>> 1890 select HAVE_KERNEL_LZO
>> 1891 select HAVE_KERNEL_XZ
>> 1892 select HAVE_KERNEL_ZSTD
194 1893
195 config PFAULT !! 1894 config SYS_SUPPORTS_ZBOOT_UART16550
196 bool "Handle protection faults" if EXP !! 1895 bool
197 default y !! 1896 select SYS_SUPPORTS_ZBOOT
>> 1897
>> 1898 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1899 bool
>> 1900 select SYS_SUPPORTS_ZBOOT
>> 1901
>> 1902 config CPU_LOONGSON2EF
>> 1903 bool
>> 1904 select CPU_SUPPORTS_32BIT_KERNEL
>> 1905 select CPU_SUPPORTS_64BIT_KERNEL
>> 1906 select CPU_SUPPORTS_HIGHMEM
>> 1907 select CPU_SUPPORTS_HUGEPAGES
>> 1908 select ARCH_HAS_PHYS_TO_DMA
>> 1909
>> 1910 config CPU_LOONGSON32
>> 1911 bool
>> 1912 select CPU_MIPS32
>> 1913 select CPU_MIPSR2
>> 1914 select CPU_HAS_PREFETCH
>> 1915 select CPU_SUPPORTS_32BIT_KERNEL
>> 1916 select CPU_SUPPORTS_HIGHMEM
>> 1917 select CPU_SUPPORTS_CPUFREQ
>> 1918
>> 1919 config CPU_BMIPS32_3300
>> 1920 select SMP_UP if SMP
>> 1921 bool
>> 1922
>> 1923 config CPU_BMIPS4350
>> 1924 bool
>> 1925 select SYS_SUPPORTS_SMP
>> 1926 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1927
>> 1928 config CPU_BMIPS4380
>> 1929 bool
>> 1930 select MIPS_L1_CACHE_SHIFT_6
>> 1931 select SYS_SUPPORTS_SMP
>> 1932 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1933 select CPU_HAS_RIXI
>> 1934
>> 1935 config CPU_BMIPS5000
>> 1936 bool
>> 1937 select MIPS_CPU_SCACHE
>> 1938 select MIPS_L1_CACHE_SHIFT_7
>> 1939 select SYS_SUPPORTS_SMP
>> 1940 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1941 select CPU_HAS_RIXI
>> 1942
>> 1943 config SYS_HAS_CPU_LOONGSON64
>> 1944 bool
>> 1945 select CPU_SUPPORTS_CPUFREQ
>> 1946 select CPU_HAS_RIXI
>> 1947
>> 1948 config SYS_HAS_CPU_LOONGSON2E
>> 1949 bool
>> 1950
>> 1951 config SYS_HAS_CPU_LOONGSON2F
>> 1952 bool
>> 1953 select CPU_SUPPORTS_CPUFREQ
>> 1954 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1955
>> 1956 config SYS_HAS_CPU_LOONGSON1B
>> 1957 bool
>> 1958
>> 1959 config SYS_HAS_CPU_LOONGSON1C
>> 1960 bool
>> 1961
>> 1962 config SYS_HAS_CPU_MIPS32_R1
>> 1963 bool
>> 1964
>> 1965 config SYS_HAS_CPU_MIPS32_R2
>> 1966 bool
>> 1967
>> 1968 config SYS_HAS_CPU_MIPS32_R3_5
>> 1969 bool
>> 1970
>> 1971 config SYS_HAS_CPU_MIPS32_R5
>> 1972 bool
>> 1973 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1974
>> 1975 config SYS_HAS_CPU_MIPS32_R6
>> 1976 bool
>> 1977 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1978
>> 1979 config SYS_HAS_CPU_MIPS64_R1
>> 1980 bool
>> 1981
>> 1982 config SYS_HAS_CPU_MIPS64_R2
>> 1983 bool
>> 1984
>> 1985 config SYS_HAS_CPU_MIPS64_R6
>> 1986 bool
>> 1987 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1988
>> 1989 config SYS_HAS_CPU_P5600
>> 1990 bool
>> 1991 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1992
>> 1993 config SYS_HAS_CPU_R3000
>> 1994 bool
>> 1995
>> 1996 config SYS_HAS_CPU_TX39XX
>> 1997 bool
>> 1998
>> 1999 config SYS_HAS_CPU_VR41XX
>> 2000 bool
>> 2001
>> 2002 config SYS_HAS_CPU_R4X00
>> 2003 bool
>> 2004
>> 2005 config SYS_HAS_CPU_TX49XX
>> 2006 bool
>> 2007
>> 2008 config SYS_HAS_CPU_R5000
>> 2009 bool
>> 2010
>> 2011 config SYS_HAS_CPU_R5500
>> 2012 bool
>> 2013
>> 2014 config SYS_HAS_CPU_NEVADA
>> 2015 bool
>> 2016
>> 2017 config SYS_HAS_CPU_R10000
>> 2018 bool
>> 2019 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2020
>> 2021 config SYS_HAS_CPU_RM7000
>> 2022 bool
>> 2023
>> 2024 config SYS_HAS_CPU_SB1
>> 2025 bool
>> 2026
>> 2027 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 2028 bool
>> 2029
>> 2030 config SYS_HAS_CPU_BMIPS
>> 2031 bool
>> 2032
>> 2033 config SYS_HAS_CPU_BMIPS32_3300
>> 2034 bool
>> 2035 select SYS_HAS_CPU_BMIPS
>> 2036
>> 2037 config SYS_HAS_CPU_BMIPS4350
>> 2038 bool
>> 2039 select SYS_HAS_CPU_BMIPS
>> 2040
>> 2041 config SYS_HAS_CPU_BMIPS4380
>> 2042 bool
>> 2043 select SYS_HAS_CPU_BMIPS
>> 2044
>> 2045 config SYS_HAS_CPU_BMIPS5000
>> 2046 bool
>> 2047 select SYS_HAS_CPU_BMIPS
>> 2048 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 2049
>> 2050 config SYS_HAS_CPU_XLR
>> 2051 bool
>> 2052
>> 2053 config SYS_HAS_CPU_XLP
>> 2054 bool
>> 2055
>> 2056 #
>> 2057 # CPU may reorder R->R, R->W, W->R, W->W
>> 2058 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2059 #
>> 2060 config WEAK_ORDERING
>> 2061 bool
>> 2062
>> 2063 #
>> 2064 # CPU may reorder reads and writes beyond LL/SC
>> 2065 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 2066 #
>> 2067 config WEAK_REORDERING_BEYOND_LLSC
>> 2068 bool
>> 2069 endmenu
>> 2070
>> 2071 #
>> 2072 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2073 #
>> 2074 config CPU_MIPS32
>> 2075 bool
>> 2076 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 2077 CPU_MIPS32_R6 || CPU_P5600
>> 2078
>> 2079 config CPU_MIPS64
>> 2080 bool
>> 2081 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 2082 CPU_MIPS64_R6
>> 2083
>> 2084 #
>> 2085 # These indicate the revision of the architecture
>> 2086 #
>> 2087 config CPU_MIPSR1
>> 2088 bool
>> 2089 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 2090
>> 2091 config CPU_MIPSR2
>> 2092 bool
>> 2093 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2094 select CPU_HAS_RIXI
>> 2095 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2096 select MIPS_SPRAM
>> 2097
>> 2098 config CPU_MIPSR5
>> 2099 bool
>> 2100 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2101 select CPU_HAS_RIXI
>> 2102 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2103 select MIPS_SPRAM
>> 2104
>> 2105 config CPU_MIPSR6
>> 2106 bool
>> 2107 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2108 select CPU_HAS_RIXI
>> 2109 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2110 select HAVE_ARCH_BITREVERSE
>> 2111 select MIPS_ASID_BITS_VARIABLE
>> 2112 select MIPS_CRC_SUPPORT
>> 2113 select MIPS_SPRAM
>> 2114
>> 2115 config TARGET_ISA_REV
>> 2116 int
>> 2117 default 1 if CPU_MIPSR1
>> 2118 default 2 if CPU_MIPSR2
>> 2119 default 5 if CPU_MIPSR5
>> 2120 default 6 if CPU_MIPSR6
>> 2121 default 0
198 help 2122 help
199 Handle protection faults. MMU config !! 2123 Reflects the ISA revision being targeted by the kernel build. This
200 noMMU configurations may disable it !! 2124 is effectively the Kconfig equivalent of MIPS_ISA_REV.
201 generates protection faults or fault <<
202 2125
203 If unsure, say Y. !! 2126 config EVA
>> 2127 bool
>> 2128
>> 2129 config XPA
>> 2130 bool
204 2131
205 config XTENSA_UNALIGNED_USER !! 2132 config SYS_SUPPORTS_32BIT_KERNEL
206 bool "Unaligned memory access in user !! 2133 bool
>> 2134 config SYS_SUPPORTS_64BIT_KERNEL
>> 2135 bool
>> 2136 config CPU_SUPPORTS_32BIT_KERNEL
>> 2137 bool
>> 2138 config CPU_SUPPORTS_64BIT_KERNEL
>> 2139 bool
>> 2140 config CPU_SUPPORTS_CPUFREQ
>> 2141 bool
>> 2142 config CPU_SUPPORTS_ADDRWINCFG
>> 2143 bool
>> 2144 config CPU_SUPPORTS_HUGEPAGES
>> 2145 bool
>> 2146 depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
>> 2147 config MIPS_PGD_C0_CONTEXT
>> 2148 bool
>> 2149 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
>> 2150
>> 2151 #
>> 2152 # Set to y for ptrace access to watch registers.
>> 2153 #
>> 2154 config HARDWARE_WATCHPOINTS
>> 2155 bool
>> 2156 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
>> 2157
>> 2158 menu "Kernel type"
>> 2159
>> 2160 choice
>> 2161 prompt "Kernel code model"
207 help 2162 help
208 The Xtensa architecture currently do !! 2163 You should only select this option if you have a workload that
209 memory accesses in hardware but thro !! 2164 actually benefits from 64-bit processing or if your machine has
210 Per default, unaligned memory access !! 2165 large memory. You will only be presented a single option in this
>> 2166 menu if your system does not support both 32-bit and 64-bit kernels.
211 2167
212 Say Y here to enable unaligned memor !! 2168 config 32BIT
>> 2169 bool "32-bit kernel"
>> 2170 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2171 select TRAD_SIGNALS
>> 2172 help
>> 2173 Select this option if you want to build a 32-bit kernel.
213 2174
214 config XTENSA_LOAD_STORE !! 2175 config 64BIT
215 bool "Load/store exception handler for !! 2176 bool "64-bit kernel"
>> 2177 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
216 help 2178 help
217 The Xtensa architecture only allows !! 2179 Select this option if you want to build a 64-bit kernel.
218 instruction bus with l32r and l32i i <<
219 instructions raise an exception with <<
220 This makes it hard to use some confi <<
221 literals in FLASH memory attached to <<
222 2180
223 Say Y here to enable exception handl !! 2181 endchoice
224 byte and 2-byte access to memory att <<
225 2182
226 config HAVE_SMP !! 2183 config KVM_GUEST
227 bool "System Supports SMP (MX)" !! 2184 bool "KVM Guest Kernel"
228 depends on XTENSA_VARIANT_CUSTOM !! 2185 depends on CPU_MIPS32_R2
229 select XTENSA_MX !! 2186 depends on BROKEN_ON_SMP
>> 2187 help
>> 2188 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2189 mode.
>> 2190
>> 2191 config KVM_GUEST_TIMER_FREQ
>> 2192 int "Count/Compare Timer Frequency (MHz)"
>> 2193 depends on KVM_GUEST
>> 2194 default 100
230 help 2195 help
231 This option is used to indicate that !! 2196 Set this to non-zero if building a guest kernel for KVM to skip RTC
232 supports Multiprocessing. Multiproce !! 2197 emulation when determining guest CPU Frequency. Instead, the guest's
233 the CPU core definition and currentl !! 2198 timer frequency is specified directly.
>> 2199
>> 2200 config MIPS_VA_BITS_48
>> 2201 bool "48 bits virtual memory"
>> 2202 depends on 64BIT
>> 2203 help
>> 2204 Support a maximum at least 48 bits of application virtual
>> 2205 memory. Default is 40 bits or less, depending on the CPU.
>> 2206 For page sizes 16k and above, this option results in a small
>> 2207 memory overhead for page tables. For 4k page size, a fourth
>> 2208 level of page tables is added which imposes both a memory
>> 2209 overhead as well as slower TLB fault handling.
234 2210
235 Multiprocessor support is implemente !! 2211 If unsure, say N.
236 interrupt controllers. <<
237 2212
238 The MX interrupt distributer adds In !! 2213 choice
239 and causes the IRQ numbers to be inc !! 2214 prompt "Kernel page size"
240 like the open cores ethernet driver !! 2215 default PAGE_SIZE_4KB
241 2216
242 You still have to select "Enable SMP !! 2217 config PAGE_SIZE_4KB
>> 2218 bool "4kB"
>> 2219 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2220 help
>> 2221 This option select the standard 4kB Linux page size. On some
>> 2222 R3000-family processors this is the only available page size. Using
>> 2223 4kB page size will minimize memory consumption and is therefore
>> 2224 recommended for low memory systems.
>> 2225
>> 2226 config PAGE_SIZE_8KB
>> 2227 bool "8kB"
>> 2228 depends on CPU_CAVIUM_OCTEON
>> 2229 depends on !MIPS_VA_BITS_48
>> 2230 help
>> 2231 Using 8kB page size will result in higher performance kernel at
>> 2232 the price of higher memory consumption. This option is available
>> 2233 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2234 distribution to support this.
>> 2235
>> 2236 config PAGE_SIZE_16KB
>> 2237 bool "16kB"
>> 2238 depends on !CPU_R3000 && !CPU_TX39XX
>> 2239 help
>> 2240 Using 16kB page size will result in higher performance kernel at
>> 2241 the price of higher memory consumption. This option is available on
>> 2242 all non-R3000 family processors. Note that you will need a suitable
>> 2243 Linux distribution to support this.
>> 2244
>> 2245 config PAGE_SIZE_32KB
>> 2246 bool "32kB"
>> 2247 depends on CPU_CAVIUM_OCTEON
>> 2248 depends on !MIPS_VA_BITS_48
>> 2249 help
>> 2250 Using 32kB page size will result in higher performance kernel at
>> 2251 the price of higher memory consumption. This option is available
>> 2252 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2253 distribution to support this.
>> 2254
>> 2255 config PAGE_SIZE_64KB
>> 2256 bool "64kB"
>> 2257 depends on !CPU_R3000 && !CPU_TX39XX
>> 2258 help
>> 2259 Using 64kB page size will result in higher performance kernel at
>> 2260 the price of higher memory consumption. This option is available on
>> 2261 all non-R3000 family processor. Not that at the time of this
>> 2262 writing this option is still high experimental.
243 2263
244 config SMP !! 2264 endchoice
245 bool "Enable Symmetric multi-processin <<
246 depends on HAVE_SMP <<
247 select GENERIC_SMP_IDLE_THREAD <<
248 help <<
249 Enabled SMP Software; allows more th <<
250 to be activated during startup. <<
251 2265
252 config NR_CPUS !! 2266 config FORCE_MAX_ZONEORDER
253 depends on SMP !! 2267 int "Maximum zone order"
254 int "Maximum number of CPUs (2-32)" !! 2268 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
255 range 2 32 !! 2269 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
256 default "4" !! 2270 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2271 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2272 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2273 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2274 range 0 64
>> 2275 default "11"
>> 2276 help
>> 2277 The kernel memory allocator divides physically contiguous memory
>> 2278 blocks into "zones", where each zone is a power of two number of
>> 2279 pages. This option selects the largest power of two that the kernel
>> 2280 keeps in the memory allocator. If you need to allocate very large
>> 2281 blocks of physically contiguous memory, then you may need to
>> 2282 increase this value.
257 2283
258 config HOTPLUG_CPU !! 2284 This config option is actually maximum order plus one. For example,
259 bool "Enable CPU hotplug support" !! 2285 a value of 11 means that the largest free memory block is 2^10 pages.
260 depends on SMP !! 2286
>> 2287 The page size is not necessarily 4KB. Keep this in mind
>> 2288 when choosing a value for this option.
>> 2289
>> 2290 config BOARD_SCACHE
>> 2291 bool
>> 2292
>> 2293 config IP22_CPU_SCACHE
>> 2294 bool
>> 2295 select BOARD_SCACHE
>> 2296
>> 2297 #
>> 2298 # Support for a MIPS32 / MIPS64 style S-caches
>> 2299 #
>> 2300 config MIPS_CPU_SCACHE
>> 2301 bool
>> 2302 select BOARD_SCACHE
>> 2303
>> 2304 config R5000_CPU_SCACHE
>> 2305 bool
>> 2306 select BOARD_SCACHE
>> 2307
>> 2308 config RM7000_CPU_SCACHE
>> 2309 bool
>> 2310 select BOARD_SCACHE
>> 2311
>> 2312 config SIBYTE_DMA_PAGEOPS
>> 2313 bool "Use DMA to clear/copy pages"
>> 2314 depends on CPU_SB1
261 help 2315 help
262 Say Y here to allow turning CPUs off !! 2316 Instead of using the CPU to zero and copy pages, use a Data Mover
263 controlled through /sys/devices/syst !! 2317 channel. These DMA channels are otherwise unused by the standard
>> 2318 SiByte Linux port. Seems to give a small performance benefit.
264 2319
265 Say N if you want to disable CPU hot !! 2320 config CPU_HAS_PREFETCH
>> 2321 bool
>> 2322
>> 2323 config CPU_GENERIC_DUMP_TLB
>> 2324 bool
>> 2325 default y if !(CPU_R3000 || CPU_TX39XX)
266 2326
267 config SECONDARY_RESET_VECTOR !! 2327 config MIPS_FP_SUPPORT
268 bool "Secondary cores use alternative !! 2328 bool "Floating Point support" if EXPERT
269 default y 2329 default y
270 depends on HAVE_SMP <<
271 help 2330 help
272 Secondary cores may be configured to !! 2331 Select y to include support for floating point in the kernel
273 or all cores may use primary reset v !! 2332 including initialization of FPU hardware, FP context save & restore
274 Say Y here to supply handler for the !! 2333 and emulation of an FPU where necessary. Without this support any
>> 2334 userland program attempting to use floating point instructions will
>> 2335 receive a SIGILL.
>> 2336
>> 2337 If you know that your userland will not attempt to use floating point
>> 2338 instructions then you can say n here to shrink the kernel a little.
>> 2339
>> 2340 If unsure, say y.
>> 2341
>> 2342 config CPU_R2300_FPU
>> 2343 bool
>> 2344 depends on MIPS_FP_SUPPORT
>> 2345 default y if CPU_R3000 || CPU_TX39XX
>> 2346
>> 2347 config CPU_R3K_TLB
>> 2348 bool
>> 2349
>> 2350 config CPU_R4K_FPU
>> 2351 bool
>> 2352 depends on MIPS_FP_SUPPORT
>> 2353 default y if !CPU_R2300_FPU
275 2354
276 config FAST_SYSCALL_XTENSA !! 2355 config CPU_R4K_CACHE_TLB
277 bool "Enable fast atomic syscalls" !! 2356 bool
>> 2357 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2358
>> 2359 config MIPS_MT_SMP
>> 2360 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2361 default y
>> 2362 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2363 select CPU_MIPSR2_IRQ_VI
>> 2364 select CPU_MIPSR2_IRQ_EI
>> 2365 select SYNC_R4K
>> 2366 select MIPS_MT
>> 2367 select SMP
>> 2368 select SMP_UP
>> 2369 select SYS_SUPPORTS_SMP
>> 2370 select SYS_SUPPORTS_SCHED_SMT
>> 2371 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2372 help
>> 2373 This is a kernel model which is known as SMVP. This is supported
>> 2374 on cores with the MT ASE and uses the available VPEs to implement
>> 2375 virtual processors which supports SMP. This is equivalent to the
>> 2376 Intel Hyperthreading feature. For further information go to
>> 2377 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2378
>> 2379 config MIPS_MT
>> 2380 bool
>> 2381
>> 2382 config SCHED_SMT
>> 2383 bool "SMT (multithreading) scheduler support"
>> 2384 depends on SYS_SUPPORTS_SCHED_SMT
278 default n 2385 default n
279 help 2386 help
280 fast_syscall_xtensa is a syscall tha !! 2387 SMT scheduler support improves the CPU scheduler's decision making
281 on UP kernel when processor has no s !! 2388 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2389 increased overhead in some places. If unsure say N here.
282 2390
283 This syscall is deprecated. It may h !! 2391 config SYS_SUPPORTS_SCHED_SMT
284 invalid arguments. It is provided on !! 2392 bool
285 Only enable it if your userspace sof <<
286 2393
287 If unsure, say N. !! 2394 config SYS_SUPPORTS_MULTITHREADING
>> 2395 bool
288 2396
289 config FAST_SYSCALL_SPILL_REGISTERS !! 2397 config MIPS_MT_FPAFF
290 bool "Enable spill registers syscall" !! 2398 bool "Dynamic FPU affinity for FP-intensive threads"
291 default n !! 2399 default y
>> 2400 depends on MIPS_MT_SMP
>> 2401
>> 2402 config MIPSR2_TO_R6_EMULATOR
>> 2403 bool "MIPS R2-to-R6 emulator"
>> 2404 depends on CPU_MIPSR6
>> 2405 depends on MIPS_FP_SUPPORT
>> 2406 default y
>> 2407 help
>> 2408 Choose this option if you want to run non-R6 MIPS userland code.
>> 2409 Even if you say 'Y' here, the emulator will still be disabled by
>> 2410 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2411 The only reason this is a build-time option is to save ~14K from the
>> 2412 final kernel image.
>> 2413
>> 2414 config SYS_SUPPORTS_VPE_LOADER
>> 2415 bool
>> 2416 depends on SYS_SUPPORTS_MULTITHREADING
292 help 2417 help
293 fast_syscall_spill_registers is a sy !! 2418 Indicates that the platform supports the VPE loader, and provides
294 register windows of a calling usersp !! 2419 physical_memsize.
295 2420
296 This syscall is deprecated. It may h !! 2421 config MIPS_VPE_LOADER
297 invalid arguments. It is provided on !! 2422 bool "VPE loader support."
298 Only enable it if your userspace sof !! 2423 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2424 select CPU_MIPSR2_IRQ_VI
>> 2425 select CPU_MIPSR2_IRQ_EI
>> 2426 select MIPS_MT
>> 2427 help
>> 2428 Includes a loader for loading an elf relocatable object
>> 2429 onto another VPE and running it.
299 2430
300 If unsure, say N. !! 2431 config MIPS_VPE_LOADER_CMP
>> 2432 bool
>> 2433 default "y"
>> 2434 depends on MIPS_VPE_LOADER && MIPS_CMP
301 2435
302 choice !! 2436 config MIPS_VPE_LOADER_MT
303 prompt "Kernel ABI" !! 2437 bool
304 default KERNEL_ABI_DEFAULT !! 2438 default "y"
>> 2439 depends on MIPS_VPE_LOADER && !MIPS_CMP
>> 2440
>> 2441 config MIPS_VPE_LOADER_TOM
>> 2442 bool "Load VPE program into memory hidden from linux"
>> 2443 depends on MIPS_VPE_LOADER
>> 2444 default y
305 help 2445 help
306 Select ABI for the kernel code. This !! 2446 The loader can use memory that is present but has been hidden from
307 supported userspace ABI and any comb !! 2447 Linux using the kernel command line option "mem=xxMB". It's up to
308 kernel/userspace ABI is possible and !! 2448 you to ensure the amount you put in the option and the space your
309 !! 2449 program requires is less or equal to the amount physically present.
310 In case both kernel and userspace su !! 2450
311 all register windows support code wi !! 2451 config MIPS_VPE_APSP_API
312 build. !! 2452 bool "Enable support for AP/SP API (RTLX)"
313 !! 2453 depends on MIPS_VPE_LOADER
314 If unsure, choose the default ABI. <<
315 <<
316 config KERNEL_ABI_DEFAULT <<
317 bool "Default ABI" <<
318 help <<
319 Select this option to compile kernel <<
320 selected for the toolchain. <<
321 Normally cores with windowed registe <<
322 cores without it use call0 ABI. <<
323 <<
324 config KERNEL_ABI_CALL0 <<
325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI <<
326 help <<
327 Select this option to compile kernel <<
328 toolchain that defaults to windowed <<
329 When this option is not selected the <<
330 be used for the kernel code. <<
331 2454
332 endchoice !! 2455 config MIPS_VPE_APSP_API_CMP
>> 2456 bool
>> 2457 default "y"
>> 2458 depends on MIPS_VPE_APSP_API && MIPS_CMP
333 2459
334 config USER_ABI_CALL0 !! 2460 config MIPS_VPE_APSP_API_MT
335 bool 2461 bool
>> 2462 default "y"
>> 2463 depends on MIPS_VPE_APSP_API && !MIPS_CMP
336 2464
337 choice !! 2465 config MIPS_CMP
338 prompt "Userspace ABI" !! 2466 bool "MIPS CMP framework support (DEPRECATED)"
339 default USER_ABI_DEFAULT !! 2467 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2468 select SMP
>> 2469 select SYNC_R4K
>> 2470 select SYS_SUPPORTS_SMP
>> 2471 select WEAK_ORDERING
>> 2472 default n
340 help 2473 help
341 Select supported userspace ABI. !! 2474 Select this if you are using a bootloader which implements the "CMP
>> 2475 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2476 its ability to start secondary CPUs.
>> 2477
>> 2478 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2479 instead of this.
>> 2480
>> 2481 config MIPS_CPS
>> 2482 bool "MIPS Coherent Processing System support"
>> 2483 depends on SYS_SUPPORTS_MIPS_CPS
>> 2484 select MIPS_CM
>> 2485 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2486 select SMP
>> 2487 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2488 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2489 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2490 select SYS_SUPPORTS_SMP
>> 2491 select WEAK_ORDERING
>> 2492 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2493 help
>> 2494 Select this if you wish to run an SMP kernel across multiple cores
>> 2495 within a MIPS Coherent Processing System. When this option is
>> 2496 enabled the kernel will probe for other cores and boot them with
>> 2497 no external assistance. It is safe to enable this when hardware
>> 2498 support is unavailable.
342 2499
343 If unsure, choose the default ABI. !! 2500 config MIPS_CPS_PM
>> 2501 depends on MIPS_CPS
>> 2502 bool
>> 2503
>> 2504 config MIPS_CM
>> 2505 bool
>> 2506 select MIPS_CPC
344 2507
345 config USER_ABI_DEFAULT !! 2508 config MIPS_CPC
346 bool "Default ABI only" !! 2509 bool
>> 2510
>> 2511 config SB1_PASS_2_WORKAROUNDS
>> 2512 bool
>> 2513 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2514 default y
>> 2515
>> 2516 config SB1_PASS_2_1_WORKAROUNDS
>> 2517 bool
>> 2518 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2519 default y
>> 2520
>> 2521 choice
>> 2522 prompt "SmartMIPS or microMIPS ASE support"
>> 2523
>> 2524 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
>> 2525 bool "None"
347 help 2526 help
348 Assume default userspace ABI. For XE !! 2527 Select this if you want neither microMIPS nor SmartMIPS support
349 call0 ABI binaries may be run on suc <<
350 will not work correctly for them. <<
351 2528
352 config USER_ABI_CALL0_ONLY !! 2529 config CPU_HAS_SMARTMIPS
353 bool "Call0 ABI only" !! 2530 depends on SYS_SUPPORTS_SMARTMIPS
354 select USER_ABI_CALL0 !! 2531 bool "SmartMIPS"
>> 2532 help
>> 2533 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2534 increased security at both hardware and software level for
>> 2535 smartcards. Enabling this option will allow proper use of the
>> 2536 SmartMIPS instructions by Linux applications. However a kernel with
>> 2537 this option will not work on a MIPS core without SmartMIPS core. If
>> 2538 you don't know you probably don't have SmartMIPS and should say N
>> 2539 here.
>> 2540
>> 2541 config CPU_MICROMIPS
>> 2542 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2543 bool "microMIPS"
355 help 2544 help
356 Select this option to support only c !! 2545 When this option is enabled the kernel will be built using the
357 Windowed ABI binaries will crash wit !! 2546 microMIPS ISA
358 an illegal instruction exception on <<
359 2547
360 Choose this option if you're plannin !! 2548 endchoice
361 built with call0 ABI. <<
362 2549
363 config USER_ABI_CALL0_PROBE !! 2550 config CPU_HAS_MSA
364 bool "Support both windowed and call0 !! 2551 bool "Support for the MIPS SIMD Architecture"
365 select USER_ABI_CALL0 !! 2552 depends on CPU_SUPPORTS_MSA
366 help !! 2553 depends on MIPS_FP_SUPPORT
367 Select this option to support both w !! 2554 depends on 64BIT || MIPS_O32_FP64_SUPPORT
368 ABIs. When enabled all processes are !! 2555 help
369 and a fast user exception handler fo !! 2556 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
370 used to turn on PS.WOE bit on the fi !! 2557 and a set of SIMD instructions to operate on them. When this option
371 the userspace. !! 2558 is enabled the kernel will support allocating & switching MSA
>> 2559 vector register contexts. If you know that your kernel will only be
>> 2560 running on CPUs which do not support MSA or that your userland will
>> 2561 not be making use of it then you may wish to say N here to reduce
>> 2562 the size & complexity of your kernel.
372 2563
373 This option should be enabled for th !! 2564 If unsure, say Y.
374 both call0 and windowed ABIs in user <<
375 2565
376 Note that Xtensa ISA does not guaran !! 2566 config CPU_HAS_WB
377 raise an illegal instruction excepti !! 2567 bool
378 PS.WOE is disabled, check whether th <<
379 2568
380 endchoice !! 2569 config XKS01
>> 2570 bool
381 2571
382 endmenu !! 2572 config CPU_HAS_DIEI
>> 2573 depends on !CPU_DIEI_BROKEN
>> 2574 bool
383 2575
384 config XTENSA_CALIBRATE_CCOUNT !! 2576 config CPU_DIEI_BROKEN
385 def_bool n !! 2577 bool
>> 2578
>> 2579 config CPU_HAS_RIXI
>> 2580 bool
>> 2581
>> 2582 config CPU_NO_LOAD_STORE_LR
>> 2583 bool
386 help 2584 help
387 On some platforms (XT2000, for examp !! 2585 CPU lacks support for unaligned load and store instructions:
388 vary. The frequency can be determin !! 2586 LWL, LWR, SWL, SWR (Load/store word left/right).
389 against a well known, fixed frequenc !! 2587 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2588 systems).
>> 2589
>> 2590 #
>> 2591 # Vectored interrupt mode is an R2 feature
>> 2592 #
>> 2593 config CPU_MIPSR2_IRQ_VI
>> 2594 bool
390 2595
391 config SERIAL_CONSOLE !! 2596 #
392 def_bool n !! 2597 # Extended interrupt mode is an R2 feature
>> 2598 #
>> 2599 config CPU_MIPSR2_IRQ_EI
>> 2600 bool
393 2601
394 config PLATFORM_HAVE_XIP !! 2602 config CPU_HAS_SYNC
395 def_bool n !! 2603 bool
>> 2604 depends on !CPU_R3000
>> 2605 default y
396 2606
397 menu "Platform options" !! 2607 #
>> 2608 # CPU non-features
>> 2609 #
>> 2610 config CPU_DADDI_WORKAROUNDS
>> 2611 bool
398 2612
399 choice !! 2613 config CPU_R4000_WORKAROUNDS
400 prompt "Xtensa System Type" !! 2614 bool
401 default XTENSA_PLATFORM_ISS !! 2615 select CPU_R4400_WORKAROUNDS
402 2616
403 config XTENSA_PLATFORM_ISS !! 2617 config CPU_R4400_WORKAROUNDS
404 bool "ISS" !! 2618 bool
405 select XTENSA_CALIBRATE_CCOUNT <<
406 select SERIAL_CONSOLE <<
407 help <<
408 ISS is an acronym for Tensilica's In <<
409 <<
410 config XTENSA_PLATFORM_XT2000 <<
411 bool "XT2000" <<
412 help <<
413 XT2000 is the name of Tensilica's fe <<
414 This hardware is capable of running <<
415 <<
416 config XTENSA_PLATFORM_XTFPGA <<
417 bool "XTFPGA" <<
418 select ETHOC if ETHERNET <<
419 select PLATFORM_WANT_DEFAULT_MEM if !M <<
420 select SERIAL_CONSOLE <<
421 select XTENSA_CALIBRATE_CCOUNT <<
422 select PLATFORM_HAVE_XIP <<
423 help <<
424 XTFPGA is the name of Tensilica boar <<
425 This hardware is capable of running <<
426 2619
427 endchoice !! 2620 config CPU_R4X00_BUGS64
>> 2621 bool
>> 2622 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
428 2623
429 config PLATFORM_NR_IRQS !! 2624 config MIPS_ASID_SHIFT
430 int 2625 int
431 default 3 if XTENSA_PLATFORM_XT2000 !! 2626 default 6 if CPU_R3000 || CPU_TX39XX
432 default 0 2627 default 0
433 2628
434 config XTENSA_CPU_CLOCK !! 2629 config MIPS_ASID_BITS
435 int "CPU clock rate [MHz]" !! 2630 int
436 depends on !XTENSA_CALIBRATE_CCOUNT !! 2631 default 0 if MIPS_ASID_BITS_VARIABLE
437 default 16 !! 2632 default 6 if CPU_R3000 || CPU_TX39XX
>> 2633 default 8
438 2634
439 config GENERIC_CALIBRATE_DELAY !! 2635 config MIPS_ASID_BITS_VARIABLE
440 bool "Auto calibration of the BogoMIPS !! 2636 bool
441 help <<
442 The BogoMIPS value can easily be der <<
443 2637
444 config CMDLINE_BOOL !! 2638 config MIPS_CRC_SUPPORT
445 bool "Default bootloader kernel argume !! 2639 bool
446 2640
447 config CMDLINE !! 2641 # R4600 erratum. Due to the lack of errata information the exact
448 string "Initial kernel command string" !! 2642 # technical details aren't known. I've experimentally found that disabling
449 depends on CMDLINE_BOOL !! 2643 # interrupts during indexed I-cache flushes seems to be sufficient to deal
450 default "console=ttyS0,38400 root=/dev !! 2644 # with the issue.
451 help !! 2645 config WAR_R4600_V1_INDEX_ICACHEOP
452 On some architectures (EBSA110 and C !! 2646 bool
453 for the boot loader to pass argument <<
454 architectures, you should supply som <<
455 time by entering them here. As a min <<
456 memory size and the root device (e.g <<
457 2647
458 config USE_OF !! 2648 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
459 bool "Flattened Device Tree support" !! 2649 #
460 select OF !! 2650 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
461 select OF_EARLY_FLATTREE !! 2651 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
462 help !! 2652 # executed if there is no other dcache activity. If the dcache is
463 Include support for flattened device !! 2653 # accessed for another instruction immediately preceding when these
>> 2654 # cache instructions are executing, it is possible that the dcache
>> 2655 # tag match outputs used by these cache instructions will be
>> 2656 # incorrect. These cache instructions should be preceded by at least
>> 2657 # four instructions that are not any kind of load or store
>> 2658 # instruction.
>> 2659 #
>> 2660 # This is not allowed: lw
>> 2661 # nop
>> 2662 # nop
>> 2663 # nop
>> 2664 # cache Hit_Writeback_Invalidate_D
>> 2665 #
>> 2666 # This is allowed: lw
>> 2667 # nop
>> 2668 # nop
>> 2669 # nop
>> 2670 # nop
>> 2671 # cache Hit_Writeback_Invalidate_D
>> 2672 config WAR_R4600_V1_HIT_CACHEOP
>> 2673 bool
464 2674
465 config BUILTIN_DTB_SOURCE !! 2675 # Writeback and invalidate the primary cache dcache before DMA.
466 string "DTB to build into the kernel i !! 2676 #
467 depends on OF !! 2677 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2678 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2679 # operate correctly if the internal data cache refill buffer is empty. These
>> 2680 # CACHE instructions should be separated from any potential data cache miss
>> 2681 # by a load instruction to an uncached address to empty the response buffer."
>> 2682 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2683 # in .pdf format.)
>> 2684 config WAR_R4600_V2_HIT_CACHEOP
>> 2685 bool
468 2686
469 config PARSE_BOOTPARAM !! 2687 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
470 bool "Parse bootparam block" !! 2688 # the line which this instruction itself exists, the following
471 default y !! 2689 # operation is not guaranteed."
472 help !! 2690 #
473 Parse parameters passed to the kerne !! 2691 # Workaround: do two phase flushing for Index_Invalidate_I
474 be disabled if the kernel is known t !! 2692 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2693 bool
475 2694
476 If unsure, say Y. !! 2695 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2696 # opposes it being called that) where invalid instructions in the same
>> 2697 # I-cache line worth of instructions being fetched may case spurious
>> 2698 # exceptions.
>> 2699 config WAR_ICACHE_REFILLS
>> 2700 bool
477 2701
478 choice !! 2702 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
479 prompt "Semihosting interface" !! 2703 # may cause ll / sc and lld / scd sequences to execute non-atomically.
480 default XTENSA_SIMCALL_ISS !! 2704 config WAR_R10000_LLSC
481 depends on XTENSA_PLATFORM_ISS !! 2705 bool
482 help <<
483 Choose semihosting interface that wi <<
484 block device and networking. <<
485 2706
486 config XTENSA_SIMCALL_ISS !! 2707 # 34K core erratum: "Problems Executing the TLBR Instruction"
487 bool "simcall" !! 2708 config WAR_MIPS34K_MISSED_ITLB
488 help !! 2709 bool
489 Use simcall instruction. simcall is !! 2710
490 it does nothing on hardware. !! 2711 #
>> 2712 # - Highmem only makes sense for the 32-bit kernel.
>> 2713 # - The current highmem code will only work properly on physically indexed
>> 2714 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2715 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2716 # moment we protect the user and offer the highmem option only on machines
>> 2717 # where it's known to be safe. This will not offer highmem on a few systems
>> 2718 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2719 # indexed CPUs but we're playing safe.
>> 2720 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2721 # know they might have memory configurations that could make use of highmem
>> 2722 # support.
>> 2723 #
>> 2724 config HIGHMEM
>> 2725 bool "High Memory Support"
>> 2726 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2727 select KMAP_LOCAL
>> 2728
>> 2729 config CPU_SUPPORTS_HIGHMEM
>> 2730 bool
>> 2731
>> 2732 config SYS_SUPPORTS_HIGHMEM
>> 2733 bool
>> 2734
>> 2735 config SYS_SUPPORTS_SMARTMIPS
>> 2736 bool
>> 2737
>> 2738 config SYS_SUPPORTS_MICROMIPS
>> 2739 bool
491 2740
492 config XTENSA_SIMCALL_GDBIO !! 2741 config SYS_SUPPORTS_MIPS16
493 bool "GDBIO" !! 2742 bool
494 help 2743 help
495 Use break instruction. It is availab !! 2744 This option must be set if a kernel might be executed on a MIPS16-
496 is attached to it via JTAG. !! 2745 enabled CPU even if MIPS16 is not actually being used. In other
>> 2746 words, it makes the kernel MIPS16-tolerant.
497 2747
498 endchoice !! 2748 config CPU_SUPPORTS_MSA
>> 2749 bool
499 2750
500 config BLK_DEV_SIMDISK !! 2751 config ARCH_FLATMEM_ENABLE
501 tristate "Host file-based simulated bl !! 2752 def_bool y
502 default n !! 2753 depends on !NUMA && !CPU_LOONGSON2EF
503 depends on XTENSA_PLATFORM_ISS && BLOC !! 2754
>> 2755 config ARCH_SPARSEMEM_ENABLE
>> 2756 bool
>> 2757 select SPARSEMEM_STATIC if !SGI_IP27
>> 2758
>> 2759 config NUMA
>> 2760 bool "NUMA Support"
>> 2761 depends on SYS_SUPPORTS_NUMA
>> 2762 help
>> 2763 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2764 Access). This option improves performance on systems with more
>> 2765 than two nodes; on two node systems it is generally better to
>> 2766 leave it disabled; on single node systems leave this option
>> 2767 disabled.
>> 2768
>> 2769 config SYS_SUPPORTS_NUMA
>> 2770 bool
>> 2771
>> 2772 config HAVE_SETUP_PER_CPU_AREA
>> 2773 def_bool y
>> 2774 depends on NUMA
>> 2775
>> 2776 config NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2777 def_bool y
>> 2778 depends on NUMA
>> 2779
>> 2780 config RELOCATABLE
>> 2781 bool "Relocatable kernel"
>> 2782 depends on SYS_SUPPORTS_RELOCATABLE
>> 2783 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2784 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2785 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2786 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2787 CPU_LOONGSON64
>> 2788 help
>> 2789 This builds a kernel image that retains relocation information
>> 2790 so it can be loaded someplace besides the default 1MB.
>> 2791 The relocations make the kernel binary about 15% larger,
>> 2792 but are discarded at runtime
>> 2793
>> 2794 config RELOCATION_TABLE_SIZE
>> 2795 hex "Relocation table size"
>> 2796 depends on RELOCATABLE
>> 2797 range 0x0 0x01000000
>> 2798 default "0x00200000" if CPU_LOONGSON64
>> 2799 default "0x00100000"
>> 2800 help
>> 2801 A table of relocation data will be appended to the kernel binary
>> 2802 and parsed at boot to fix up the relocated kernel.
>> 2803
>> 2804 This option allows the amount of space reserved for the table to be
>> 2805 adjusted, although the default of 1Mb should be ok in most cases.
>> 2806
>> 2807 The build will fail and a valid size suggested if this is too small.
>> 2808
>> 2809 If unsure, leave at the default value.
>> 2810
>> 2811 config RANDOMIZE_BASE
>> 2812 bool "Randomize the address of the kernel image"
>> 2813 depends on RELOCATABLE
>> 2814 help
>> 2815 Randomizes the physical and virtual address at which the
>> 2816 kernel image is loaded, as a security feature that
>> 2817 deters exploit attempts relying on knowledge of the location
>> 2818 of kernel internals.
>> 2819
>> 2820 Entropy is generated using any coprocessor 0 registers available.
>> 2821
>> 2822 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2823
>> 2824 If unsure, say N.
>> 2825
>> 2826 config RANDOMIZE_BASE_MAX_OFFSET
>> 2827 hex "Maximum kASLR offset" if EXPERT
>> 2828 depends on RANDOMIZE_BASE
>> 2829 range 0x0 0x40000000 if EVA || 64BIT
>> 2830 range 0x0 0x08000000
>> 2831 default "0x01000000"
>> 2832 help
>> 2833 When kASLR is active, this provides the maximum offset that will
>> 2834 be applied to the kernel image. It should be set according to the
>> 2835 amount of physical RAM available in the target system minus
>> 2836 PHYSICAL_START and must be a power of 2.
>> 2837
>> 2838 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2839 EVA or 64-bit. The default is 16Mb.
>> 2840
>> 2841 config NODES_SHIFT
>> 2842 int
>> 2843 default "6"
>> 2844 depends on NEED_MULTIPLE_NODES
>> 2845
>> 2846 config HW_PERF_EVENTS
>> 2847 bool "Enable hardware performance counter support for perf events"
>> 2848 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
>> 2849 default y
504 help 2850 help
505 Create block devices that map to fil !! 2851 Enable hardware performance counter support for perf events. If
506 Device binding to host file may be c !! 2852 disabled, perf events will use software events only.
507 interface provided the device is not !! 2853
508 !! 2854 config DMI
509 config BLK_DEV_SIMDISK_COUNT !! 2855 bool "Enable DMI scanning"
510 int "Number of host file-based simulat !! 2856 depends on MACH_LOONGSON64
511 range 1 10 !! 2857 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
512 depends on BLK_DEV_SIMDISK !! 2858 default y
513 default 2 <<
514 help 2859 help
515 This is the default minimal number o !! 2860 Enabled scanning of DMI to identify machine quirks. Say Y
516 Kernel/module parameter 'simdisk_cou !! 2861 here unless you have verified that your setup is not
517 value at runtime. More file names (b !! 2862 affected by entries in the DMI blacklist. Required by PNP
518 specified as parameters, simdisk_cou !! 2863 BIOS code.
519 !! 2864
520 config SIMDISK0_FILENAME !! 2865 config SMP
521 string "Host filename for the first si !! 2866 bool "Multi-Processing support"
522 depends on BLK_DEV_SIMDISK = y !! 2867 depends on SYS_SUPPORTS_SMP
523 default "" <<
524 help <<
525 Attach a first simdisk to a host fil <<
526 contains a root file system. <<
527 <<
528 config SIMDISK1_FILENAME <<
529 string "Host filename for the second s <<
530 depends on BLK_DEV_SIMDISK = y && BLK_ <<
531 default "" <<
532 help <<
533 Another simulated disk in a host fil <<
534 storage. <<
535 <<
536 config XTFPGA_LCD <<
537 bool "Enable XTFPGA LCD driver" <<
538 depends on XTENSA_PLATFORM_XTFPGA <<
539 default n <<
540 help 2868 help
541 There's a 2x16 LCD on most of XTFPGA !! 2869 This enables support for systems with more than one CPU. If you have
542 progress messages there during bootu !! 2870 a system with only one CPU, say N. If you have a system with more
543 during board bringup. !! 2871 than one CPU, say Y.
>> 2872
>> 2873 If you say N here, the kernel will run on uni- and multiprocessor
>> 2874 machines, but will use only one CPU of a multiprocessor machine. If
>> 2875 you say Y here, the kernel will run on many, but not all,
>> 2876 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2877 will run faster if you say N here.
544 2878
545 If unsure, say N. !! 2879 People using multiprocessor machines who say Y here should also say
>> 2880 Y to "Enhanced Real Time Clock Support", below.
546 2881
547 config XTFPGA_LCD_BASE_ADDR !! 2882 See also the SMP-HOWTO available at
548 hex "XTFPGA LCD base address" !! 2883 <https://www.tldp.org/docs.html#howto>.
549 depends on XTFPGA_LCD !! 2884
550 default "0x0d0c0000" !! 2885 If you don't know what to do here, say N.
551 help !! 2886
552 Base address of the LCD controller i !! 2887 config HOTPLUG_CPU
553 Different boards from XTFPGA family !! 2888 bool "Support for hot-pluggable CPUs"
554 addresses. Please consult prototypin !! 2889 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
555 the correct address. Wrong address h <<
556 <<
557 config XTFPGA_LCD_8BIT_ACCESS <<
558 bool "Use 8-bit access to XTFPGA LCD" <<
559 depends on XTFPGA_LCD <<
560 default n <<
561 help 2890 help
562 LCD may be connected with 4- or 8-bi !! 2891 Say Y here to allow turning CPUs off and on. CPUs can be
563 only be used with 8-bit interface. P !! 2892 controlled through /sys/devices/system/cpu.
564 guide for your board for the correct !! 2893 (Note: power management support will enable this option
565 !! 2894 automatically on SMP systems. )
566 comment "Kernel memory layout" !! 2895 Say N if you want to disable CPU hotplug.
567 <<
568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX <<
569 bool "Initialize Xtensa MMU inside the <<
570 depends on !XTENSA_VARIANT_FSF && !XTE <<
571 default y if XTENSA_VARIANT_DC233C || <<
572 help <<
573 Earlier version initialized the MMU <<
574 before jumping to _startup in head.S <<
575 it was possible to place a software <<
576 then enter your normal kernel breakp <<
577 to the kernel mappings (0XC0000000). <<
578 <<
579 This unfortunately won't work for U- <<
580 work for using KEXEC to have a hot k <<
581 KDUMP. <<
582 <<
583 So now the MMU is initialized in hea <<
584 use hardware breakpoints (gdb 'hbrea <<
585 xt-gdb can't place a Software Breakp <<
586 to mapping the MMU and after mapping <<
587 was mapped gdb wouldn't remove the b <<
588 PC wouldn't match. Since Hardware Br <<
589 Linux configurations it seems reason <<
590 and leave this older mechanism for u <<
591 not to follow Tensilica's recommenda <<
592 <<
593 Selecting this will cause U-Boot to <<
594 address at 0x00003000 instead of the <<
595 <<
596 If in doubt, say Y. <<
597 <<
598 config XIP_KERNEL <<
599 bool "Kernel Execute-In-Place from ROM <<
600 depends on PLATFORM_HAVE_XIP <<
601 help <<
602 Execute-In-Place allows the kernel t <<
603 directly addressable by the CPU, suc <<
604 space since the text section of the <<
605 to RAM. Read-write sections, such as <<
606 are still copied to RAM. The XIP ker <<
607 it has to run directly from flash, s <<
608 store it. The flash address used to <<
609 and for storing it, is configuration <<
610 say Y here, you must know the proper <<
611 store the kernel image depending on <<
612 <<
613 Also note that the make target becom <<
614 "make Image" or "make uImage". The f <<
615 ROM memory will be arch/xtensa/boot/ <<
616 2896
617 If unsure, say N. !! 2897 config SMP_UP
>> 2898 bool
>> 2899
>> 2900 config SYS_SUPPORTS_MIPS_CMP
>> 2901 bool
>> 2902
>> 2903 config SYS_SUPPORTS_MIPS_CPS
>> 2904 bool
>> 2905
>> 2906 config SYS_SUPPORTS_SMP
>> 2907 bool
>> 2908
>> 2909 config NR_CPUS_DEFAULT_4
>> 2910 bool
>> 2911
>> 2912 config NR_CPUS_DEFAULT_8
>> 2913 bool
618 2914
619 config MEMMAP_CACHEATTR !! 2915 config NR_CPUS_DEFAULT_16
620 hex "Cache attributes for the memory a !! 2916 bool
621 depends on !MMU !! 2917
622 default 0x22222222 !! 2918 config NR_CPUS_DEFAULT_32
623 help !! 2919 bool
624 These cache attributes are set up fo <<
625 specifies cache attributes for the c <<
626 region: bits 0..3 -- for addresses 0 <<
627 bits 4..7 -- for addresses 0x2000000 <<
628 <<
629 Cache attribute values are specific <<
630 For region protection MMUs: <<
631 1: WT cached, <<
632 2: cache bypass, <<
633 4: WB cached, <<
634 f: illegal. <<
635 For full MMU: <<
636 bit 0: executable, <<
637 bit 1: writable, <<
638 bits 2..3: <<
639 0: cache bypass, <<
640 1: WB cache, <<
641 2: WT cache, <<
642 3: special (c and e are illegal, <<
643 For MPU: <<
644 0: illegal, <<
645 1: WB cache, <<
646 2: WB, no-write-allocate cache, <<
647 3: WT cache, <<
648 4: cache bypass. <<
649 <<
650 config KSEG_PADDR <<
651 hex "Physical address of the KSEG mapp <<
652 depends on INITIALIZE_XTENSA_MMU_INSID <<
653 default 0x00000000 <<
654 help <<
655 This is the physical address where K <<
656 the chosen KSEG layout help for the <<
657 Unpacked kernel image (including vec <<
658 within KSEG. <<
659 Physical memory below this address i <<
660 <<
661 If unsure, leave the default value h <<
662 <<
663 config KERNEL_VIRTUAL_ADDRESS <<
664 hex "Kernel virtual address" <<
665 depends on MMU && XIP_KERNEL <<
666 default 0xd0003000 <<
667 help <<
668 This is the virtual address where th <<
669 XIP kernel may be mapped into KSEG o <<
670 provided here must match kernel load <<
671 KERNEL_LOAD_ADDRESS. <<
672 <<
673 config KERNEL_LOAD_ADDRESS <<
674 hex "Kernel load address" <<
675 default 0x60003000 if !MMU <<
676 default 0x00003000 if MMU && INITIALIZ <<
677 default 0xd0003000 if MMU && !INITIALI <<
678 help <<
679 This is the address where the kernel <<
680 It is virtual address for MMUv2 conf <<
681 for all other configurations. <<
682 2920
683 If unsure, leave the default value h !! 2921 config NR_CPUS_DEFAULT_64
>> 2922 bool
>> 2923
>> 2924 config NR_CPUS
>> 2925 int "Maximum number of CPUs (2-256)"
>> 2926 range 2 256
>> 2927 depends on SMP
>> 2928 default "4" if NR_CPUS_DEFAULT_4
>> 2929 default "8" if NR_CPUS_DEFAULT_8
>> 2930 default "16" if NR_CPUS_DEFAULT_16
>> 2931 default "32" if NR_CPUS_DEFAULT_32
>> 2932 default "64" if NR_CPUS_DEFAULT_64
>> 2933 help
>> 2934 This allows you to specify the maximum number of CPUs which this
>> 2935 kernel will support. The maximum supported value is 32 for 32-bit
>> 2936 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2937 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2938 and 2 for all others.
>> 2939
>> 2940 This is purely to save memory - each supported CPU adds
>> 2941 approximately eight kilobytes to the kernel image. For best
>> 2942 performance should round up your number of processors to the next
>> 2943 power of two.
>> 2944
>> 2945 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2946 bool
>> 2947
>> 2948 config MIPS_NR_CPU_NR_MAP_1024
>> 2949 bool
>> 2950
>> 2951 config MIPS_NR_CPU_NR_MAP
>> 2952 int
>> 2953 depends on SMP
>> 2954 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2955 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
>> 2956
>> 2957 #
>> 2958 # Timer Interrupt Frequency Configuration
>> 2959 #
684 2960
685 choice 2961 choice
686 prompt "Relocatable vectors location" !! 2962 prompt "Timer frequency"
687 default XTENSA_VECTORS_IN_TEXT !! 2963 default HZ_250
688 help 2964 help
689 Choose whether relocatable vectors a !! 2965 Allows the configuration of the timer frequency.
690 or placed separately at runtime. Thi !! 2966
691 configurations without VECBASE regis !! 2967 config HZ_24
692 placed at their hardware-defined loc !! 2968 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
693 !! 2969
694 config XTENSA_VECTORS_IN_TEXT !! 2970 config HZ_48
695 bool "Merge relocatable vectors into k !! 2971 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
696 depends on !MTD_XIP !! 2972
697 help !! 2973 config HZ_100
698 This option puts relocatable vectors !! 2974 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
699 with proper alignment. !! 2975
700 This is a safe choice for most confi !! 2976 config HZ_128
701 !! 2977 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
702 config XTENSA_VECTORS_SEPARATE !! 2978
703 bool "Put relocatable vectors at fixed !! 2979 config HZ_250
704 help !! 2980 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
705 This option puts relocatable vectors !! 2981
706 Vectors are merged with the .init da !! 2982 config HZ_256
707 are copied into their designated loc !! 2983 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
708 Use it to put vectors into IRAM or o !! 2984
709 XIP-aware MTD support. !! 2985 config HZ_1000
>> 2986 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2987
>> 2988 config HZ_1024
>> 2989 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
710 2990
711 endchoice 2991 endchoice
712 2992
713 config VECTORS_ADDR !! 2993 config SYS_SUPPORTS_24HZ
714 hex "Kernel vectors virtual address" !! 2994 bool
715 default 0x00000000 <<
716 depends on XTENSA_VECTORS_SEPARATE <<
717 help <<
718 This is the virtual address of the ( <<
719 It must be within KSEG if MMU is use <<
720 <<
721 config XIP_DATA_ADDR <<
722 hex "XIP kernel data virtual address" <<
723 depends on XIP_KERNEL <<
724 default 0x00000000 <<
725 help <<
726 This is the virtual address where XI <<
727 It must be within KSEG if MMU is use <<
728 2995
729 config PLATFORM_WANT_DEFAULT_MEM !! 2996 config SYS_SUPPORTS_48HZ
730 def_bool n !! 2997 bool
731 2998
732 config DEFAULT_MEM_START !! 2999 config SYS_SUPPORTS_100HZ
733 hex !! 3000 bool
734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !M !! 3001
735 default 0x60000000 if PLATFORM_WANT_DE !! 3002 config SYS_SUPPORTS_128HZ
736 default 0x00000000 !! 3003 bool
737 help <<
738 This is the base address used for bo <<
739 in noMMU configurations. <<
740 3004
741 If unsure, leave the default value h !! 3005 config SYS_SUPPORTS_250HZ
>> 3006 bool
>> 3007
>> 3008 config SYS_SUPPORTS_256HZ
>> 3009 bool
>> 3010
>> 3011 config SYS_SUPPORTS_1000HZ
>> 3012 bool
>> 3013
>> 3014 config SYS_SUPPORTS_1024HZ
>> 3015 bool
>> 3016
>> 3017 config SYS_SUPPORTS_ARBIT_HZ
>> 3018 bool
>> 3019 default y if !SYS_SUPPORTS_24HZ && \
>> 3020 !SYS_SUPPORTS_48HZ && \
>> 3021 !SYS_SUPPORTS_100HZ && \
>> 3022 !SYS_SUPPORTS_128HZ && \
>> 3023 !SYS_SUPPORTS_250HZ && \
>> 3024 !SYS_SUPPORTS_256HZ && \
>> 3025 !SYS_SUPPORTS_1000HZ && \
>> 3026 !SYS_SUPPORTS_1024HZ
>> 3027
>> 3028 config HZ
>> 3029 int
>> 3030 default 24 if HZ_24
>> 3031 default 48 if HZ_48
>> 3032 default 100 if HZ_100
>> 3033 default 128 if HZ_128
>> 3034 default 250 if HZ_250
>> 3035 default 256 if HZ_256
>> 3036 default 1000 if HZ_1000
>> 3037 default 1024 if HZ_1024
>> 3038
>> 3039 config SCHED_HRTICK
>> 3040 def_bool HIGH_RES_TIMERS
>> 3041
>> 3042 config KEXEC
>> 3043 bool "Kexec system call"
>> 3044 select KEXEC_CORE
>> 3045 help
>> 3046 kexec is a system call that implements the ability to shutdown your
>> 3047 current kernel, and to start another kernel. It is like a reboot
>> 3048 but it is independent of the system firmware. And like a reboot
>> 3049 you can start any kernel with it, not just Linux.
>> 3050
>> 3051 The name comes from the similarity to the exec system call.
>> 3052
>> 3053 It is an ongoing process to be certain the hardware in a machine
>> 3054 is properly shutdown, so do not be surprised if this code does not
>> 3055 initially work for you. As of this writing the exact hardware
>> 3056 interface is strongly in flux, so no good recommendation can be
>> 3057 made.
>> 3058
>> 3059 config CRASH_DUMP
>> 3060 bool "Kernel crash dumps"
>> 3061 help
>> 3062 Generate crash dump after being started by kexec.
>> 3063 This should be normally only set in special crash dump kernels
>> 3064 which are loaded in the main kernel with kexec-tools into
>> 3065 a specially reserved region and then later executed after
>> 3066 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 3067 to a memory address not used by the main kernel or firmware using
>> 3068 PHYSICAL_START.
>> 3069
>> 3070 config PHYSICAL_START
>> 3071 hex "Physical address where the kernel is loaded"
>> 3072 default "0xffffffff84000000"
>> 3073 depends on CRASH_DUMP
>> 3074 help
>> 3075 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 3076 If you plan to use kernel for capturing the crash dump change
>> 3077 this value to start of the reserved region (the "X" value as
>> 3078 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3079 passed to the panic-ed kernel).
>> 3080
>> 3081 config MIPS_O32_FP64_SUPPORT
>> 3082 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3083 depends on 32BIT || MIPS32_O32
>> 3084 help
>> 3085 When this is enabled, the kernel will support use of 64-bit floating
>> 3086 point registers with binaries using the O32 ABI along with the
>> 3087 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3088 32-bit MIPS systems this support is at the cost of increasing the
>> 3089 size and complexity of the compiled FPU emulator. Thus if you are
>> 3090 running a MIPS32 system and know that none of your userland binaries
>> 3091 will require 64-bit floating point, you may wish to reduce the size
>> 3092 of your kernel & potentially improve FP emulation performance by
>> 3093 saying N here.
>> 3094
>> 3095 Although binutils currently supports use of this flag the details
>> 3096 concerning its effect upon the O32 ABI in userland are still being
>> 3097 worked on. In order to avoid userland becoming dependent upon current
>> 3098 behaviour before the details have been finalised, this option should
>> 3099 be considered experimental and only enabled by those working upon
>> 3100 said details.
>> 3101
>> 3102 If unsure, say N.
>> 3103
>> 3104 config USE_OF
>> 3105 bool
>> 3106 select OF
>> 3107 select OF_EARLY_FLATTREE
>> 3108 select IRQ_DOMAIN
>> 3109
>> 3110 config UHI_BOOT
>> 3111 bool
>> 3112
>> 3113 config BUILTIN_DTB
>> 3114 bool
742 3115
743 choice 3116 choice
744 prompt "KSEG layout" !! 3117 prompt "Kernel appended dtb support" if USE_OF
745 depends on MMU !! 3118 default MIPS_NO_APPENDED_DTB
746 default XTENSA_KSEG_MMU_V2 <<
747 <<
748 config XTENSA_KSEG_MMU_V2 <<
749 bool "MMUv2: 128MB cached + 128MB unca <<
750 help <<
751 MMUv2 compatible kernel memory map: <<
752 at KSEG_PADDR to 0xd0000000 with cac <<
753 without cache. <<
754 KSEG_PADDR must be aligned to 128MB. <<
755 <<
756 config XTENSA_KSEG_256M <<
757 bool "256MB cached + 256MB uncached" <<
758 depends on INITIALIZE_XTENSA_MMU_INSID <<
759 help <<
760 TLB way 6 maps 256MB starting at KSE <<
761 with cache and to 0xc0000000 without <<
762 KSEG_PADDR must be aligned to 256MB. <<
763 <<
764 config XTENSA_KSEG_512M <<
765 bool "512MB cached + 512MB uncached" <<
766 depends on INITIALIZE_XTENSA_MMU_INSID <<
767 help <<
768 TLB way 6 maps 512MB starting at KSE <<
769 with cache and to 0xc0000000 without <<
770 KSEG_PADDR must be aligned to 256MB. <<
771 3119
>> 3120 config MIPS_NO_APPENDED_DTB
>> 3121 bool "None"
>> 3122 help
>> 3123 Do not enable appended dtb support.
>> 3124
>> 3125 config MIPS_ELF_APPENDED_DTB
>> 3126 bool "vmlinux"
>> 3127 help
>> 3128 With this option, the boot code will look for a device tree binary
>> 3129 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3130 it is empty and the DTB can be appended using binutils command
>> 3131 objcopy:
>> 3132
>> 3133 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3134
>> 3135 This is meant as a backward compatibility convenience for those
>> 3136 systems with a bootloader that can't be upgraded to accommodate
>> 3137 the documented boot protocol using a device tree.
>> 3138
>> 3139 config MIPS_RAW_APPENDED_DTB
>> 3140 bool "vmlinux.bin or vmlinuz.bin"
>> 3141 help
>> 3142 With this option, the boot code will look for a device tree binary
>> 3143 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3144 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3145
>> 3146 This is meant as a backward compatibility convenience for those
>> 3147 systems with a bootloader that can't be upgraded to accommodate
>> 3148 the documented boot protocol using a device tree.
>> 3149
>> 3150 Beware that there is very little in terms of protection against
>> 3151 this option being confused by leftover garbage in memory that might
>> 3152 look like a DTB header after a reboot if no actual DTB is appended
>> 3153 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3154 if you don't intend to always append a DTB.
772 endchoice 3155 endchoice
773 3156
774 config HIGHMEM !! 3157 choice
775 bool "High Memory Support" !! 3158 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
776 depends on MMU !! 3159 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
777 select KMAP_LOCAL !! 3160 !MACH_LOONGSON64 && !MIPS_MALTA && \
778 help !! 3161 !CAVIUM_OCTEON_SOC
779 Linux can use the full amount of RAM !! 3162 default MIPS_CMDLINE_FROM_BOOTLOADER
780 default. However, the default MMUv2 !! 3163
781 lowermost 128 MB of memory linearly !! 3164 config MIPS_CMDLINE_FROM_DTB
782 at 0xd0000000 (cached) and 0xd800000 !! 3165 depends on USE_OF
783 When there are more than 128 MB memo !! 3166 bool "Dtb kernel arguments if available"
784 all of it can be "permanently mapped !! 3167
785 The physical memory that's not perma !! 3168 config MIPS_CMDLINE_DTB_EXTEND
786 "high memory". !! 3169 depends on USE_OF
787 !! 3170 bool "Extend dtb kernel arguments with bootloader arguments"
788 If you are compiling a kernel which !! 3171
789 machine with more than 128 MB total !! 3172 config MIPS_CMDLINE_FROM_BOOTLOADER
790 N here. !! 3173 bool "Bootloader kernel arguments if available"
>> 3174
>> 3175 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3176 depends on CMDLINE_BOOL
>> 3177 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3178 endchoice
791 3179
792 If unsure, say Y. !! 3180 endmenu
>> 3181
>> 3182 config LOCKDEP_SUPPORT
>> 3183 bool
>> 3184 default y
>> 3185
>> 3186 config STACKTRACE_SUPPORT
>> 3187 bool
>> 3188 default y
>> 3189
>> 3190 config PGTABLE_LEVELS
>> 3191 int
>> 3192 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3193 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 3194 default 2
>> 3195
>> 3196 config MIPS_AUTO_PFN_OFFSET
>> 3197 bool
>> 3198
>> 3199 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
793 3200
794 config ARCH_FORCE_MAX_ORDER !! 3201 config PCI_DRIVERS_GENERIC
795 int "Order of maximal physically conti !! 3202 select PCI_DOMAINS_GENERIC if PCI
796 default "10" !! 3203 bool
797 help !! 3204
798 The kernel page allocator limits the !! 3205 config PCI_DRIVERS_LEGACY
799 contiguous allocations. The limit is !! 3206 def_bool !PCI_DRIVERS_GENERIC
800 defines the maximal power of two of !! 3207 select NO_GENERIC_PCI_IOPORT_MAP
801 allocated as a single contiguous blo !! 3208 select PCI_DOMAINS if PCI
802 overriding the default setting when !! 3209
803 large blocks of physically contiguou !! 3210 #
>> 3211 # ISA support is now enabled via select. Too many systems still have the one
>> 3212 # or other ISA chip on the board that users don't know about so don't expect
>> 3213 # users to choose the right thing ...
>> 3214 #
>> 3215 config ISA
>> 3216 bool
804 3217
805 Don't change if unsure. !! 3218 config TC
>> 3219 bool "TURBOchannel support"
>> 3220 depends on MACH_DECSTATION
>> 3221 help
>> 3222 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3223 processors. TURBOchannel programming specifications are available
>> 3224 at:
>> 3225 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3226 and:
>> 3227 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3228 Linux driver support status is documented at:
>> 3229 <http://www.linux-mips.org/wiki/DECstation>
>> 3230
>> 3231 config MMU
>> 3232 bool
>> 3233 default y
>> 3234
>> 3235 config ARCH_MMAP_RND_BITS_MIN
>> 3236 default 12 if 64BIT
>> 3237 default 8
>> 3238
>> 3239 config ARCH_MMAP_RND_BITS_MAX
>> 3240 default 18 if 64BIT
>> 3241 default 15
>> 3242
>> 3243 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3244 default 8
>> 3245
>> 3246 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3247 default 15
>> 3248
>> 3249 config I8253
>> 3250 bool
>> 3251 select CLKSRC_I8253
>> 3252 select CLKEVT_I8253
>> 3253 select MIPS_EXTERNAL_TIMER
>> 3254
>> 3255 config ZONE_DMA
>> 3256 bool
>> 3257
>> 3258 config ZONE_DMA32
>> 3259 bool
806 3260
807 endmenu 3261 endmenu
808 3262
>> 3263 config TRAD_SIGNALS
>> 3264 bool
>> 3265
>> 3266 config MIPS32_COMPAT
>> 3267 bool
>> 3268
>> 3269 config COMPAT
>> 3270 bool
>> 3271
>> 3272 config SYSVIPC_COMPAT
>> 3273 bool
>> 3274
>> 3275 config MIPS32_O32
>> 3276 bool "Kernel support for o32 binaries"
>> 3277 depends on 64BIT
>> 3278 select ARCH_WANT_OLD_COMPAT_IPC
>> 3279 select COMPAT
>> 3280 select MIPS32_COMPAT
>> 3281 select SYSVIPC_COMPAT if SYSVIPC
>> 3282 help
>> 3283 Select this option if you want to run o32 binaries. These are pure
>> 3284 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3285 existing binaries are in this format.
>> 3286
>> 3287 If unsure, say Y.
>> 3288
>> 3289 config MIPS32_N32
>> 3290 bool "Kernel support for n32 binaries"
>> 3291 depends on 64BIT
>> 3292 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3293 select COMPAT
>> 3294 select MIPS32_COMPAT
>> 3295 select SYSVIPC_COMPAT if SYSVIPC
>> 3296 help
>> 3297 Select this option if you want to run n32 binaries. These are
>> 3298 64-bit binaries using 32-bit quantities for addressing and certain
>> 3299 data that would normally be 64-bit. They are used in special
>> 3300 cases.
>> 3301
>> 3302 If unsure, say N.
>> 3303
>> 3304 config BINFMT_ELF32
>> 3305 bool
>> 3306 default y if MIPS32_O32 || MIPS32_N32
>> 3307 select ELFCORE
>> 3308
809 menu "Power management options" 3309 menu "Power management options"
810 3310
811 config ARCH_HIBERNATION_POSSIBLE 3311 config ARCH_HIBERNATION_POSSIBLE
812 def_bool y 3312 def_bool y
>> 3313 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3314
>> 3315 config ARCH_SUSPEND_POSSIBLE
>> 3316 def_bool y
>> 3317 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
813 3318
814 source "kernel/power/Kconfig" 3319 source "kernel/power/Kconfig"
815 3320
816 endmenu 3321 endmenu
>> 3322
>> 3323 config MIPS_EXTERNAL_TIMER
>> 3324 bool
>> 3325
>> 3326 menu "CPU Power Management"
>> 3327
>> 3328 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3329 source "drivers/cpufreq/Kconfig"
>> 3330 endif
>> 3331
>> 3332 source "drivers/cpuidle/Kconfig"
>> 3333
>> 3334 endmenu
>> 3335
>> 3336 source "drivers/firmware/Kconfig"
>> 3337
>> 3338 source "arch/mips/kvm/Kconfig"
>> 3339
>> 3340 source "arch/mips/vdso/Kconfig"
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