1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 config XTENSA !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ARCH_32BIT_OFF_T !! 4 default y
5 select ARCH_HAS_CPU_CACHE_ALIASING !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_HAS_BINFMT_FLAT if !MMU !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CURRENT_STACK_POINTER !! 7 select ARCH_HAS_FORTIFY_SOURCE
8 select ARCH_HAS_DEBUG_VM_PGTABLE <<
9 select ARCH_HAS_DMA_PREP_COHERENT if M <<
10 select ARCH_HAS_GCOV_PROFILE_ALL <<
11 select ARCH_HAS_KCOV 8 select ARCH_HAS_KCOV
12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MM !! 9 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if !! 10 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
14 select ARCH_HAS_DMA_SET_UNCACHED if MM !! 11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
15 select ARCH_HAS_STRNCPY_FROM_USER if ! !! 12 select ARCH_HAS_UBSAN_SANITIZE_ALL
16 select ARCH_HAS_STRNLEN_USER !! 13 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_NEED_CMPXCHG_1_EMU !! 14 select ARCH_KEEP_MEMBLOCK if DEBUG_KERNEL
18 select ARCH_USE_MEMTEST !! 15 select ARCH_SUPPORTS_UPROBES
>> 16 select ARCH_USE_BUILTIN_BSWAP
>> 17 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
19 select ARCH_USE_QUEUED_RWLOCKS 18 select ARCH_USE_QUEUED_RWLOCKS
20 select ARCH_USE_QUEUED_SPINLOCKS 19 select ARCH_USE_QUEUED_SPINLOCKS
>> 20 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
21 select ARCH_WANT_IPC_PARSE_VERSION 21 select ARCH_WANT_IPC_PARSE_VERSION
>> 22 select ARCH_WANT_LD_ORPHAN_WARN
22 select BUILDTIME_TABLE_SORT 23 select BUILDTIME_TABLE_SORT
23 select CLONE_BACKWARDS 24 select CLONE_BACKWARDS
24 select COMMON_CLK !! 25 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
25 select DMA_NONCOHERENT_MMAP if MMU !! 26 select CPU_PM if CPU_IDLE
26 select GENERIC_ATOMIC64 !! 27 select GENERIC_ATOMIC64 if !64BIT
>> 28 select GENERIC_CMOS_UPDATE
>> 29 select GENERIC_CPU_AUTOPROBE
>> 30 select GENERIC_GETTIMEOFDAY
>> 31 select GENERIC_IOMAP
>> 32 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW 33 select GENERIC_IRQ_SHOW
>> 34 select GENERIC_ISA_DMA if EISA
>> 35 select GENERIC_LIB_ASHLDI3
>> 36 select GENERIC_LIB_ASHRDI3
28 select GENERIC_LIB_CMPDI2 37 select GENERIC_LIB_CMPDI2
29 select GENERIC_LIB_MULDI3 !! 38 select GENERIC_LIB_LSHRDI3
30 select GENERIC_LIB_UCMPDI2 39 select GENERIC_LIB_UCMPDI2
31 select GENERIC_PCI_IOMAP !! 40 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
32 select GENERIC_SCHED_CLOCK !! 41 select GENERIC_SMP_IDLE_THREAD
33 select GENERIC_IOREMAP if MMU !! 42 select GENERIC_TIME_VSYSCALL
34 select HAVE_ARCH_AUDITSYSCALL !! 43 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
35 select HAVE_ARCH_JUMP_LABEL if !XIP_KE !! 44 select HANDLE_DOMAIN_IRQ
36 select HAVE_ARCH_KASAN if MMU && !XIP_ !! 45 select HAVE_ARCH_COMPILER_H
37 select HAVE_ARCH_KCSAN !! 46 select HAVE_ARCH_JUMP_LABEL
>> 47 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
>> 48 select HAVE_ARCH_MMAP_RND_BITS if MMU
>> 49 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
38 select HAVE_ARCH_SECCOMP_FILTER 50 select HAVE_ARCH_SECCOMP_FILTER
39 select HAVE_ARCH_TRACEHOOK 51 select HAVE_ARCH_TRACEHOOK
>> 52 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
40 select HAVE_ASM_MODVERSIONS 53 select HAVE_ASM_MODVERSIONS
41 select HAVE_CONTEXT_TRACKING_USER !! 54 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 55 select HAVE_CONTEXT_TRACKING
>> 56 select HAVE_TIF_NOHZ
>> 57 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK 58 select HAVE_DEBUG_KMEMLEAK
>> 59 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_DMA_CONTIGUOUS 60 select HAVE_DMA_CONTIGUOUS
>> 61 select HAVE_DYNAMIC_FTRACE
>> 62 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
44 select HAVE_EXIT_THREAD 63 select HAVE_EXIT_THREAD
>> 64 select HAVE_FAST_GUP
>> 65 select HAVE_FTRACE_MCOUNT_RECORD
>> 66 select HAVE_FUNCTION_GRAPH_TRACER
45 select HAVE_FUNCTION_TRACER 67 select HAVE_FUNCTION_TRACER
46 select HAVE_GCC_PLUGINS if GCC_VERSION !! 68 select HAVE_GCC_PLUGINS
47 select HAVE_HW_BREAKPOINT if PERF_EVEN !! 69 select HAVE_GENERIC_VDSO
>> 70 select HAVE_IDE
>> 71 select HAVE_IOREMAP_PROT
>> 72 select HAVE_IRQ_EXIT_ON_IRQ_STACK
48 select HAVE_IRQ_TIME_ACCOUNTING 73 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_PAGE_SIZE_4KB !! 74 select HAVE_KPROBES
50 select HAVE_PCI !! 75 select HAVE_KRETPROBES
>> 76 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 77 select HAVE_MOD_ARCH_SPECIFIC
>> 78 select HAVE_NMI
51 select HAVE_PERF_EVENTS 79 select HAVE_PERF_EVENTS
>> 80 select HAVE_PERF_REGS
>> 81 select HAVE_PERF_USER_STACK_DUMP
>> 82 select HAVE_REGS_AND_STACK_ACCESS_API
>> 83 select HAVE_RSEQ
>> 84 select HAVE_SPARSE_SYSCALL_NR
52 select HAVE_STACKPROTECTOR 85 select HAVE_STACKPROTECTOR
53 select HAVE_SYSCALL_TRACEPOINTS 86 select HAVE_SYSCALL_TRACEPOINTS
54 select HAVE_VIRT_CPU_ACCOUNTING_GEN !! 87 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
55 select IRQ_DOMAIN !! 88 select IRQ_FORCED_THREADING
56 select LOCK_MM_AND_FIND_VMA !! 89 select ISA if EISA
57 select MODULES_USE_ELF_RELA !! 90 select MODULES_USE_ELF_REL if MODULES
>> 91 select MODULES_USE_ELF_RELA if MODULES && 64BIT
58 select PERF_USE_VMALLOC 92 select PERF_USE_VMALLOC
59 select TRACE_IRQFLAGS_SUPPORT !! 93 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
>> 94 select RTC_LIB
>> 95 select SET_FS
>> 96 select SYSCTL_EXCEPTION_TRACE
>> 97 select VIRT_TO_BUS
>> 98 select ARCH_HAS_ELFCORE_COMPAT
>> 99
>> 100 config MIPS_FIXUP_BIGPHYS_ADDR
>> 101 bool
>> 102
>> 103 config MIPS_GENERIC
>> 104 bool
>> 105
>> 106 config MACH_INGENIC
>> 107 bool
>> 108 select SYS_SUPPORTS_32BIT_KERNEL
>> 109 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 110 select SYS_SUPPORTS_ZBOOT
>> 111 select DMA_NONCOHERENT
>> 112 select IRQ_MIPS_CPU
>> 113 select PINCTRL
>> 114 select GPIOLIB
>> 115 select COMMON_CLK
>> 116 select GENERIC_IRQ_CHIP
>> 117 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 118 select USE_OF
>> 119 select CPU_SUPPORTS_CPUFREQ
>> 120 select MIPS_EXTERNAL_TIMER
>> 121
>> 122 menu "Machine selection"
>> 123
>> 124 choice
>> 125 prompt "System type"
>> 126 default MIPS_GENERIC_KERNEL
>> 127
>> 128 config MIPS_GENERIC_KERNEL
>> 129 bool "Generic board-agnostic MIPS kernel"
>> 130 select ARCH_HAS_SETUP_DMA_OPS
>> 131 select MIPS_GENERIC
>> 132 select BOOT_RAW
>> 133 select BUILTIN_DTB
>> 134 select CEVT_R4K
>> 135 select CLKSRC_MIPS_GIC
>> 136 select COMMON_CLK
>> 137 select CPU_MIPSR2_IRQ_EI
>> 138 select CPU_MIPSR2_IRQ_VI
>> 139 select CSRC_R4K
>> 140 select DMA_NONCOHERENT
>> 141 select HAVE_PCI
>> 142 select IRQ_MIPS_CPU
>> 143 select MIPS_AUTO_PFN_OFFSET
>> 144 select MIPS_CPU_SCACHE
>> 145 select MIPS_GIC
>> 146 select MIPS_L1_CACHE_SHIFT_7
>> 147 select NO_EXCEPT_FILL
>> 148 select PCI_DRIVERS_GENERIC
>> 149 select SMP_UP if SMP
>> 150 select SWAP_IO_SPACE
>> 151 select SYS_HAS_CPU_MIPS32_R1
>> 152 select SYS_HAS_CPU_MIPS32_R2
>> 153 select SYS_HAS_CPU_MIPS32_R6
>> 154 select SYS_HAS_CPU_MIPS64_R1
>> 155 select SYS_HAS_CPU_MIPS64_R2
>> 156 select SYS_HAS_CPU_MIPS64_R6
>> 157 select SYS_SUPPORTS_32BIT_KERNEL
>> 158 select SYS_SUPPORTS_64BIT_KERNEL
>> 159 select SYS_SUPPORTS_BIG_ENDIAN
>> 160 select SYS_SUPPORTS_HIGHMEM
>> 161 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 162 select SYS_SUPPORTS_MICROMIPS
>> 163 select SYS_SUPPORTS_MIPS16
>> 164 select SYS_SUPPORTS_MIPS_CPS
>> 165 select SYS_SUPPORTS_MULTITHREADING
>> 166 select SYS_SUPPORTS_RELOCATABLE
>> 167 select SYS_SUPPORTS_SMARTMIPS
>> 168 select SYS_SUPPORTS_ZBOOT
>> 169 select UHI_BOOT
>> 170 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 171 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 172 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 173 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 174 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 175 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 176 select USE_OF
>> 177 help
>> 178 Select this to build a kernel which aims to support multiple boards,
>> 179 generally using a flattened device tree passed from the bootloader
>> 180 using the boot protocol defined in the UHI (Unified Hosting
>> 181 Interface) specification.
>> 182
>> 183 config MIPS_ALCHEMY
>> 184 bool "Alchemy processor based machines"
>> 185 select PHYS_ADDR_T_64BIT
>> 186 select CEVT_R4K
>> 187 select CSRC_R4K
>> 188 select IRQ_MIPS_CPU
>> 189 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 190 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 191 select SYS_HAS_CPU_MIPS32_R1
>> 192 select SYS_SUPPORTS_32BIT_KERNEL
>> 193 select SYS_SUPPORTS_APM_EMULATION
>> 194 select GPIOLIB
>> 195 select SYS_SUPPORTS_ZBOOT
>> 196 select COMMON_CLK
>> 197
>> 198 config AR7
>> 199 bool "Texas Instruments AR7"
>> 200 select BOOT_ELF32
>> 201 select DMA_NONCOHERENT
>> 202 select CEVT_R4K
>> 203 select CSRC_R4K
>> 204 select IRQ_MIPS_CPU
>> 205 select NO_EXCEPT_FILL
>> 206 select SWAP_IO_SPACE
>> 207 select SYS_HAS_CPU_MIPS32_R1
>> 208 select SYS_HAS_EARLY_PRINTK
>> 209 select SYS_SUPPORTS_32BIT_KERNEL
>> 210 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 211 select SYS_SUPPORTS_MIPS16
>> 212 select SYS_SUPPORTS_ZBOOT_UART16550
>> 213 select GPIOLIB
>> 214 select VLYNQ
>> 215 select HAVE_LEGACY_CLK
>> 216 help
>> 217 Support for the Texas Instruments AR7 System-on-a-Chip
>> 218 family: TNETD7100, 7200 and 7300.
>> 219
>> 220 config ATH25
>> 221 bool "Atheros AR231x/AR531x SoC support"
>> 222 select CEVT_R4K
>> 223 select CSRC_R4K
>> 224 select DMA_NONCOHERENT
>> 225 select IRQ_MIPS_CPU
>> 226 select IRQ_DOMAIN
>> 227 select SYS_HAS_CPU_MIPS32_R1
>> 228 select SYS_SUPPORTS_BIG_ENDIAN
>> 229 select SYS_SUPPORTS_32BIT_KERNEL
>> 230 select SYS_HAS_EARLY_PRINTK
>> 231 help
>> 232 Support for Atheros AR231x and Atheros AR531x based boards
>> 233
>> 234 config ATH79
>> 235 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 236 select ARCH_HAS_RESET_CONTROLLER
>> 237 select BOOT_RAW
>> 238 select CEVT_R4K
>> 239 select CSRC_R4K
>> 240 select DMA_NONCOHERENT
>> 241 select GPIOLIB
>> 242 select PINCTRL
>> 243 select COMMON_CLK
>> 244 select IRQ_MIPS_CPU
>> 245 select SYS_HAS_CPU_MIPS32_R2
>> 246 select SYS_HAS_EARLY_PRINTK
>> 247 select SYS_SUPPORTS_32BIT_KERNEL
>> 248 select SYS_SUPPORTS_BIG_ENDIAN
>> 249 select SYS_SUPPORTS_MIPS16
>> 250 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 251 select USE_OF
>> 252 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 253 help
>> 254 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 255
>> 256 config BMIPS_GENERIC
>> 257 bool "Broadcom Generic BMIPS kernel"
>> 258 select ARCH_HAS_RESET_CONTROLLER
>> 259 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 260 select ARCH_HAS_PHYS_TO_DMA
>> 261 select BOOT_RAW
>> 262 select NO_EXCEPT_FILL
>> 263 select USE_OF
>> 264 select CEVT_R4K
>> 265 select CSRC_R4K
>> 266 select SYNC_R4K
>> 267 select COMMON_CLK
>> 268 select BCM6345_L1_IRQ
>> 269 select BCM7038_L1_IRQ
>> 270 select BCM7120_L2_IRQ
>> 271 select BRCMSTB_L2_IRQ
>> 272 select IRQ_MIPS_CPU
>> 273 select DMA_NONCOHERENT
>> 274 select SYS_SUPPORTS_32BIT_KERNEL
>> 275 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 276 select SYS_SUPPORTS_BIG_ENDIAN
>> 277 select SYS_SUPPORTS_HIGHMEM
>> 278 select SYS_HAS_CPU_BMIPS32_3300
>> 279 select SYS_HAS_CPU_BMIPS4350
>> 280 select SYS_HAS_CPU_BMIPS4380
>> 281 select SYS_HAS_CPU_BMIPS5000
>> 282 select SWAP_IO_SPACE
>> 283 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 284 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 285 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 286 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 287 select HARDIRQS_SW_RESEND
>> 288 help
>> 289 Build a generic DT-based kernel image that boots on select
>> 290 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 291 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 292 must be set appropriately for your board.
>> 293
>> 294 config BCM47XX
>> 295 bool "Broadcom BCM47XX based boards"
>> 296 select BOOT_RAW
>> 297 select CEVT_R4K
>> 298 select CSRC_R4K
>> 299 select DMA_NONCOHERENT
>> 300 select HAVE_PCI
>> 301 select IRQ_MIPS_CPU
>> 302 select SYS_HAS_CPU_MIPS32_R1
>> 303 select NO_EXCEPT_FILL
>> 304 select SYS_SUPPORTS_32BIT_KERNEL
>> 305 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 306 select SYS_SUPPORTS_MIPS16
>> 307 select SYS_SUPPORTS_ZBOOT
>> 308 select SYS_HAS_EARLY_PRINTK
>> 309 select USE_GENERIC_EARLY_PRINTK_8250
>> 310 select GPIOLIB
>> 311 select LEDS_GPIO_REGISTER
>> 312 select BCM47XX_NVRAM
>> 313 select BCM47XX_SPROM
>> 314 select BCM47XX_SSB if !BCM47XX_BCMA
>> 315 help
>> 316 Support for BCM47XX based boards
>> 317
>> 318 config BCM63XX
>> 319 bool "Broadcom BCM63XX based boards"
>> 320 select BOOT_RAW
>> 321 select CEVT_R4K
>> 322 select CSRC_R4K
>> 323 select SYNC_R4K
>> 324 select DMA_NONCOHERENT
>> 325 select IRQ_MIPS_CPU
>> 326 select SYS_SUPPORTS_32BIT_KERNEL
>> 327 select SYS_SUPPORTS_BIG_ENDIAN
>> 328 select SYS_HAS_EARLY_PRINTK
>> 329 select SWAP_IO_SPACE
>> 330 select GPIOLIB
>> 331 select MIPS_L1_CACHE_SHIFT_4
>> 332 select CLKDEV_LOOKUP
>> 333 select HAVE_LEGACY_CLK
>> 334 help
>> 335 Support for BCM63XX based boards
>> 336
>> 337 config MIPS_COBALT
>> 338 bool "Cobalt Server"
>> 339 select CEVT_R4K
>> 340 select CSRC_R4K
>> 341 select CEVT_GT641XX
>> 342 select DMA_NONCOHERENT
>> 343 select FORCE_PCI
>> 344 select I8253
>> 345 select I8259
>> 346 select IRQ_MIPS_CPU
>> 347 select IRQ_GT641XX
>> 348 select PCI_GT64XXX_PCI0
>> 349 select SYS_HAS_CPU_NEVADA
>> 350 select SYS_HAS_EARLY_PRINTK
>> 351 select SYS_SUPPORTS_32BIT_KERNEL
>> 352 select SYS_SUPPORTS_64BIT_KERNEL
>> 353 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 354 select USE_GENERIC_EARLY_PRINTK_8250
>> 355
>> 356 config MACH_DECSTATION
>> 357 bool "DECstations"
>> 358 select BOOT_ELF32
>> 359 select CEVT_DS1287
>> 360 select CEVT_R4K if CPU_R4X00
>> 361 select CSRC_IOASIC
>> 362 select CSRC_R4K if CPU_R4X00
>> 363 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 364 select CPU_R4000_WORKAROUNDS if 64BIT
>> 365 select CPU_R4400_WORKAROUNDS if 64BIT
>> 366 select DMA_NONCOHERENT
>> 367 select NO_IOPORT_MAP
>> 368 select IRQ_MIPS_CPU
>> 369 select SYS_HAS_CPU_R3000
>> 370 select SYS_HAS_CPU_R4X00
>> 371 select SYS_SUPPORTS_32BIT_KERNEL
>> 372 select SYS_SUPPORTS_64BIT_KERNEL
>> 373 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 374 select SYS_SUPPORTS_128HZ
>> 375 select SYS_SUPPORTS_256HZ
>> 376 select SYS_SUPPORTS_1024HZ
>> 377 select MIPS_L1_CACHE_SHIFT_4
>> 378 help
>> 379 This enables support for DEC's MIPS based workstations. For details
>> 380 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 381 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 382
>> 383 If you have one of the following DECstation Models you definitely
>> 384 want to choose R4xx0 for the CPU Type:
>> 385
>> 386 DECstation 5000/50
>> 387 DECstation 5000/150
>> 388 DECstation 5000/260
>> 389 DECsystem 5900/260
>> 390
>> 391 otherwise choose R3000.
>> 392
>> 393 config MACH_JAZZ
>> 394 bool "Jazz family of machines"
>> 395 select ARC_MEMORY
>> 396 select ARC_PROMLIB
>> 397 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 398 select ARCH_MIGHT_HAVE_PC_SERIO
>> 399 select DMA_OPS
>> 400 select FW_ARC
>> 401 select FW_ARC32
>> 402 select ARCH_MAY_HAVE_PC_FDC
>> 403 select CEVT_R4K
>> 404 select CSRC_R4K
>> 405 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 406 select GENERIC_ISA_DMA
>> 407 select HAVE_PCSPKR_PLATFORM
>> 408 select IRQ_MIPS_CPU
>> 409 select I8253
>> 410 select I8259
>> 411 select ISA
>> 412 select SYS_HAS_CPU_R4X00
>> 413 select SYS_SUPPORTS_32BIT_KERNEL
>> 414 select SYS_SUPPORTS_64BIT_KERNEL
>> 415 select SYS_SUPPORTS_100HZ
>> 416 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 417 help
>> 418 This a family of machines based on the MIPS R4030 chipset which was
>> 419 used by several vendors to build RISC/os and Windows NT workstations.
>> 420 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 421 Olivetti M700-10 workstations.
>> 422
>> 423 config MACH_INGENIC_SOC
>> 424 bool "Ingenic SoC based machines"
>> 425 select MIPS_GENERIC
>> 426 select MACH_INGENIC
>> 427 select SYS_SUPPORTS_ZBOOT_UART16550
>> 428 select CPU_SUPPORTS_CPUFREQ
>> 429 select MIPS_EXTERNAL_TIMER
>> 430
>> 431 config LANTIQ
>> 432 bool "Lantiq based platforms"
>> 433 select DMA_NONCOHERENT
>> 434 select IRQ_MIPS_CPU
>> 435 select CEVT_R4K
>> 436 select CSRC_R4K
>> 437 select SYS_HAS_CPU_MIPS32_R1
>> 438 select SYS_HAS_CPU_MIPS32_R2
>> 439 select SYS_SUPPORTS_BIG_ENDIAN
>> 440 select SYS_SUPPORTS_32BIT_KERNEL
>> 441 select SYS_SUPPORTS_MIPS16
>> 442 select SYS_SUPPORTS_MULTITHREADING
>> 443 select SYS_SUPPORTS_VPE_LOADER
>> 444 select SYS_HAS_EARLY_PRINTK
>> 445 select GPIOLIB
>> 446 select SWAP_IO_SPACE
>> 447 select BOOT_RAW
>> 448 select CLKDEV_LOOKUP
>> 449 select HAVE_LEGACY_CLK
>> 450 select USE_OF
>> 451 select PINCTRL
>> 452 select PINCTRL_LANTIQ
>> 453 select ARCH_HAS_RESET_CONTROLLER
>> 454 select RESET_CONTROLLER
>> 455
>> 456 config MACH_LOONGSON32
>> 457 bool "Loongson 32-bit family of machines"
>> 458 select SYS_SUPPORTS_ZBOOT
>> 459 help
>> 460 This enables support for the Loongson-1 family of machines.
>> 461
>> 462 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 463 the Institute of Computing Technology (ICT), Chinese Academy of
>> 464 Sciences (CAS).
>> 465
>> 466 config MACH_LOONGSON2EF
>> 467 bool "Loongson-2E/F family of machines"
>> 468 select SYS_SUPPORTS_ZBOOT
>> 469 help
>> 470 This enables the support of early Loongson-2E/F family of machines.
>> 471
>> 472 config MACH_LOONGSON64
>> 473 bool "Loongson 64-bit family of machines"
>> 474 select ARCH_SPARSEMEM_ENABLE
>> 475 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 476 select ARCH_MIGHT_HAVE_PC_SERIO
>> 477 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 478 select BOOT_ELF32
>> 479 select BOARD_SCACHE
>> 480 select CSRC_R4K
>> 481 select CEVT_R4K
>> 482 select CPU_HAS_WB
>> 483 select FORCE_PCI
>> 484 select ISA
>> 485 select I8259
>> 486 select IRQ_MIPS_CPU
>> 487 select NO_EXCEPT_FILL
>> 488 select NR_CPUS_DEFAULT_64
>> 489 select USE_GENERIC_EARLY_PRINTK_8250
>> 490 select PCI_DRIVERS_GENERIC
>> 491 select SYS_HAS_CPU_LOONGSON64
>> 492 select SYS_HAS_EARLY_PRINTK
>> 493 select SYS_SUPPORTS_SMP
>> 494 select SYS_SUPPORTS_HOTPLUG_CPU
>> 495 select SYS_SUPPORTS_NUMA
>> 496 select SYS_SUPPORTS_64BIT_KERNEL
>> 497 select SYS_SUPPORTS_HIGHMEM
>> 498 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 499 select SYS_SUPPORTS_ZBOOT
>> 500 select SYS_SUPPORTS_RELOCATABLE
>> 501 select ZONE_DMA32
>> 502 select COMMON_CLK
>> 503 select USE_OF
>> 504 select BUILTIN_DTB
>> 505 select PCI_HOST_GENERIC
>> 506 help
>> 507 This enables the support of Loongson-2/3 family of machines.
>> 508
>> 509 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 510 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 511 and Loongson-2F which will be removed), developed by the Institute
>> 512 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 513
>> 514 config MACH_PISTACHIO
>> 515 bool "IMG Pistachio SoC based boards"
>> 516 select BOOT_ELF32
>> 517 select BOOT_RAW
>> 518 select CEVT_R4K
>> 519 select CLKSRC_MIPS_GIC
>> 520 select COMMON_CLK
>> 521 select CSRC_R4K
>> 522 select DMA_NONCOHERENT
>> 523 select GPIOLIB
>> 524 select IRQ_MIPS_CPU
>> 525 select MFD_SYSCON
>> 526 select MIPS_CPU_SCACHE
>> 527 select MIPS_GIC
>> 528 select PINCTRL
>> 529 select REGULATOR
>> 530 select SYS_HAS_CPU_MIPS32_R2
>> 531 select SYS_SUPPORTS_32BIT_KERNEL
>> 532 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 533 select SYS_SUPPORTS_MIPS_CPS
>> 534 select SYS_SUPPORTS_MULTITHREADING
>> 535 select SYS_SUPPORTS_RELOCATABLE
>> 536 select SYS_SUPPORTS_ZBOOT
>> 537 select SYS_HAS_EARLY_PRINTK
>> 538 select USE_GENERIC_EARLY_PRINTK_8250
>> 539 select USE_OF
>> 540 help
>> 541 This enables support for the IMG Pistachio SoC platform.
>> 542
>> 543 config MIPS_MALTA
>> 544 bool "MIPS Malta board"
>> 545 select ARCH_MAY_HAVE_PC_FDC
>> 546 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 547 select ARCH_MIGHT_HAVE_PC_SERIO
>> 548 select BOOT_ELF32
>> 549 select BOOT_RAW
>> 550 select BUILTIN_DTB
>> 551 select CEVT_R4K
>> 552 select CLKSRC_MIPS_GIC
>> 553 select COMMON_CLK
>> 554 select CSRC_R4K
>> 555 select DMA_NONCOHERENT
>> 556 select GENERIC_ISA_DMA
>> 557 select HAVE_PCSPKR_PLATFORM
>> 558 select HAVE_PCI
>> 559 select I8253
>> 560 select I8259
>> 561 select IRQ_MIPS_CPU
>> 562 select MIPS_BONITO64
>> 563 select MIPS_CPU_SCACHE
>> 564 select MIPS_GIC
>> 565 select MIPS_L1_CACHE_SHIFT_6
>> 566 select MIPS_MSC
>> 567 select PCI_GT64XXX_PCI0
>> 568 select SMP_UP if SMP
>> 569 select SWAP_IO_SPACE
>> 570 select SYS_HAS_CPU_MIPS32_R1
>> 571 select SYS_HAS_CPU_MIPS32_R2
>> 572 select SYS_HAS_CPU_MIPS32_R3_5
>> 573 select SYS_HAS_CPU_MIPS32_R5
>> 574 select SYS_HAS_CPU_MIPS32_R6
>> 575 select SYS_HAS_CPU_MIPS64_R1
>> 576 select SYS_HAS_CPU_MIPS64_R2
>> 577 select SYS_HAS_CPU_MIPS64_R6
>> 578 select SYS_HAS_CPU_NEVADA
>> 579 select SYS_HAS_CPU_RM7000
>> 580 select SYS_SUPPORTS_32BIT_KERNEL
>> 581 select SYS_SUPPORTS_64BIT_KERNEL
>> 582 select SYS_SUPPORTS_BIG_ENDIAN
>> 583 select SYS_SUPPORTS_HIGHMEM
>> 584 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 585 select SYS_SUPPORTS_MICROMIPS
>> 586 select SYS_SUPPORTS_MIPS16
>> 587 select SYS_SUPPORTS_MIPS_CMP
>> 588 select SYS_SUPPORTS_MIPS_CPS
>> 589 select SYS_SUPPORTS_MULTITHREADING
>> 590 select SYS_SUPPORTS_RELOCATABLE
>> 591 select SYS_SUPPORTS_SMARTMIPS
>> 592 select SYS_SUPPORTS_VPE_LOADER
>> 593 select SYS_SUPPORTS_ZBOOT
>> 594 select USE_OF
>> 595 select WAR_ICACHE_REFILLS
>> 596 select ZONE_DMA32 if 64BIT
>> 597 help
>> 598 This enables support for the MIPS Technologies Malta evaluation
>> 599 board.
>> 600
>> 601 config MACH_PIC32
>> 602 bool "Microchip PIC32 Family"
>> 603 help
>> 604 This enables support for the Microchip PIC32 family of platforms.
>> 605
>> 606 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 607 microcontrollers.
>> 608
>> 609 config MACH_VR41XX
>> 610 bool "NEC VR4100 series based machines"
>> 611 select CEVT_R4K
>> 612 select CSRC_R4K
>> 613 select SYS_HAS_CPU_VR41XX
>> 614 select SYS_SUPPORTS_MIPS16
>> 615 select GPIOLIB
>> 616
>> 617 config MACH_NINTENDO64
>> 618 bool "Nintendo 64 console"
>> 619 select CEVT_R4K
>> 620 select CSRC_R4K
>> 621 select SYS_HAS_CPU_R4300
>> 622 select SYS_SUPPORTS_BIG_ENDIAN
>> 623 select SYS_SUPPORTS_ZBOOT
>> 624 select SYS_SUPPORTS_32BIT_KERNEL
>> 625 select SYS_SUPPORTS_64BIT_KERNEL
>> 626 select DMA_NONCOHERENT
>> 627 select IRQ_MIPS_CPU
>> 628
>> 629 config RALINK
>> 630 bool "Ralink based machines"
>> 631 select CEVT_R4K
>> 632 select CSRC_R4K
>> 633 select BOOT_RAW
>> 634 select DMA_NONCOHERENT
>> 635 select IRQ_MIPS_CPU
>> 636 select USE_OF
>> 637 select SYS_HAS_CPU_MIPS32_R1
>> 638 select SYS_HAS_CPU_MIPS32_R2
>> 639 select SYS_SUPPORTS_32BIT_KERNEL
>> 640 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 641 select SYS_SUPPORTS_MIPS16
>> 642 select SYS_SUPPORTS_ZBOOT
>> 643 select SYS_HAS_EARLY_PRINTK
>> 644 select CLKDEV_LOOKUP
>> 645 select ARCH_HAS_RESET_CONTROLLER
>> 646 select RESET_CONTROLLER
>> 647
>> 648 config MACH_REALTEK_RTL
>> 649 bool "Realtek RTL838x/RTL839x based machines"
>> 650 select MIPS_GENERIC
>> 651 select DMA_NONCOHERENT
>> 652 select IRQ_MIPS_CPU
>> 653 select CSRC_R4K
>> 654 select CEVT_R4K
>> 655 select SYS_HAS_CPU_MIPS32_R1
>> 656 select SYS_HAS_CPU_MIPS32_R2
>> 657 select SYS_SUPPORTS_BIG_ENDIAN
>> 658 select SYS_SUPPORTS_32BIT_KERNEL
>> 659 select SYS_SUPPORTS_MIPS16
>> 660 select SYS_SUPPORTS_MULTITHREADING
>> 661 select SYS_SUPPORTS_VPE_LOADER
>> 662 select SYS_HAS_EARLY_PRINTK
>> 663 select SYS_HAS_EARLY_PRINTK_8250
>> 664 select USE_GENERIC_EARLY_PRINTK_8250
>> 665 select BOOT_RAW
>> 666 select PINCTRL
>> 667 select USE_OF
>> 668
>> 669 config SGI_IP22
>> 670 bool "SGI IP22 (Indy/Indigo2)"
>> 671 select ARC_MEMORY
>> 672 select ARC_PROMLIB
>> 673 select FW_ARC
>> 674 select FW_ARC32
>> 675 select ARCH_MIGHT_HAVE_PC_SERIO
>> 676 select BOOT_ELF32
>> 677 select CEVT_R4K
>> 678 select CSRC_R4K
>> 679 select DEFAULT_SGI_PARTITION
>> 680 select DMA_NONCOHERENT
>> 681 select HAVE_EISA
>> 682 select I8253
>> 683 select I8259
>> 684 select IP22_CPU_SCACHE
>> 685 select IRQ_MIPS_CPU
>> 686 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 687 select SGI_HAS_I8042
>> 688 select SGI_HAS_INDYDOG
>> 689 select SGI_HAS_HAL2
>> 690 select SGI_HAS_SEEQ
>> 691 select SGI_HAS_WD93
>> 692 select SGI_HAS_ZILOG
>> 693 select SWAP_IO_SPACE
>> 694 select SYS_HAS_CPU_R4X00
>> 695 select SYS_HAS_CPU_R5000
>> 696 select SYS_HAS_EARLY_PRINTK
>> 697 select SYS_SUPPORTS_32BIT_KERNEL
>> 698 select SYS_SUPPORTS_64BIT_KERNEL
>> 699 select SYS_SUPPORTS_BIG_ENDIAN
>> 700 select WAR_R4600_V1_INDEX_ICACHEOP
>> 701 select WAR_R4600_V1_HIT_CACHEOP
>> 702 select WAR_R4600_V2_HIT_CACHEOP
>> 703 select MIPS_L1_CACHE_SHIFT_7
>> 704 help
>> 705 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 706 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 707 that runs on these, say Y here.
>> 708
>> 709 config SGI_IP27
>> 710 bool "SGI IP27 (Origin200/2000)"
>> 711 select ARCH_HAS_PHYS_TO_DMA
>> 712 select ARCH_SPARSEMEM_ENABLE
>> 713 select FW_ARC
>> 714 select FW_ARC64
>> 715 select ARC_CMDLINE_ONLY
>> 716 select BOOT_ELF64
>> 717 select DEFAULT_SGI_PARTITION
>> 718 select SYS_HAS_EARLY_PRINTK
>> 719 select HAVE_PCI
>> 720 select IRQ_MIPS_CPU
>> 721 select IRQ_DOMAIN_HIERARCHY
>> 722 select NR_CPUS_DEFAULT_64
>> 723 select PCI_DRIVERS_GENERIC
>> 724 select PCI_XTALK_BRIDGE
>> 725 select SYS_HAS_CPU_R10000
>> 726 select SYS_SUPPORTS_64BIT_KERNEL
>> 727 select SYS_SUPPORTS_BIG_ENDIAN
>> 728 select SYS_SUPPORTS_NUMA
>> 729 select SYS_SUPPORTS_SMP
>> 730 select WAR_R10000_LLSC
>> 731 select MIPS_L1_CACHE_SHIFT_7
>> 732 select NUMA
>> 733 help
>> 734 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 735 workstations. To compile a Linux kernel that runs on these, say Y
>> 736 here.
>> 737
>> 738 config SGI_IP28
>> 739 bool "SGI IP28 (Indigo2 R10k)"
>> 740 select ARC_MEMORY
>> 741 select ARC_PROMLIB
>> 742 select FW_ARC
>> 743 select FW_ARC64
>> 744 select ARCH_MIGHT_HAVE_PC_SERIO
>> 745 select BOOT_ELF64
>> 746 select CEVT_R4K
>> 747 select CSRC_R4K
>> 748 select DEFAULT_SGI_PARTITION
>> 749 select DMA_NONCOHERENT
>> 750 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 751 select IRQ_MIPS_CPU
>> 752 select HAVE_EISA
>> 753 select I8253
>> 754 select I8259
>> 755 select SGI_HAS_I8042
>> 756 select SGI_HAS_INDYDOG
>> 757 select SGI_HAS_HAL2
>> 758 select SGI_HAS_SEEQ
>> 759 select SGI_HAS_WD93
>> 760 select SGI_HAS_ZILOG
>> 761 select SWAP_IO_SPACE
>> 762 select SYS_HAS_CPU_R10000
>> 763 select SYS_HAS_EARLY_PRINTK
>> 764 select SYS_SUPPORTS_64BIT_KERNEL
>> 765 select SYS_SUPPORTS_BIG_ENDIAN
>> 766 select WAR_R10000_LLSC
>> 767 select MIPS_L1_CACHE_SHIFT_7
>> 768 help
>> 769 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 770 kernel that runs on these, say Y here.
>> 771
>> 772 config SGI_IP30
>> 773 bool "SGI IP30 (Octane/Octane2)"
>> 774 select ARCH_HAS_PHYS_TO_DMA
>> 775 select FW_ARC
>> 776 select FW_ARC64
>> 777 select BOOT_ELF64
>> 778 select CEVT_R4K
>> 779 select CSRC_R4K
>> 780 select SYNC_R4K if SMP
>> 781 select ZONE_DMA32
>> 782 select HAVE_PCI
>> 783 select IRQ_MIPS_CPU
>> 784 select IRQ_DOMAIN_HIERARCHY
>> 785 select NR_CPUS_DEFAULT_2
>> 786 select PCI_DRIVERS_GENERIC
>> 787 select PCI_XTALK_BRIDGE
>> 788 select SYS_HAS_EARLY_PRINTK
>> 789 select SYS_HAS_CPU_R10000
>> 790 select SYS_SUPPORTS_64BIT_KERNEL
>> 791 select SYS_SUPPORTS_BIG_ENDIAN
>> 792 select SYS_SUPPORTS_SMP
>> 793 select WAR_R10000_LLSC
>> 794 select MIPS_L1_CACHE_SHIFT_7
>> 795 select ARC_MEMORY
>> 796 help
>> 797 These are the SGI Octane and Octane2 graphics workstations. To
>> 798 compile a Linux kernel that runs on these, say Y here.
>> 799
>> 800 config SGI_IP32
>> 801 bool "SGI IP32 (O2)"
>> 802 select ARC_MEMORY
>> 803 select ARC_PROMLIB
>> 804 select ARCH_HAS_PHYS_TO_DMA
>> 805 select FW_ARC
>> 806 select FW_ARC32
>> 807 select BOOT_ELF32
>> 808 select CEVT_R4K
>> 809 select CSRC_R4K
>> 810 select DMA_NONCOHERENT
>> 811 select HAVE_PCI
>> 812 select IRQ_MIPS_CPU
>> 813 select R5000_CPU_SCACHE
>> 814 select RM7000_CPU_SCACHE
>> 815 select SYS_HAS_CPU_R5000
>> 816 select SYS_HAS_CPU_R10000 if BROKEN
>> 817 select SYS_HAS_CPU_RM7000
>> 818 select SYS_HAS_CPU_NEVADA
>> 819 select SYS_SUPPORTS_64BIT_KERNEL
>> 820 select SYS_SUPPORTS_BIG_ENDIAN
>> 821 select WAR_ICACHE_REFILLS
>> 822 help
>> 823 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 824
>> 825 config SIBYTE_CRHINE
>> 826 bool "Sibyte BCM91120C-CRhine"
>> 827 select BOOT_ELF32
>> 828 select SIBYTE_BCM1120
>> 829 select SWAP_IO_SPACE
>> 830 select SYS_HAS_CPU_SB1
>> 831 select SYS_SUPPORTS_BIG_ENDIAN
>> 832 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 833
>> 834 config SIBYTE_CARMEL
>> 835 bool "Sibyte BCM91120x-Carmel"
>> 836 select BOOT_ELF32
>> 837 select SIBYTE_BCM1120
>> 838 select SWAP_IO_SPACE
>> 839 select SYS_HAS_CPU_SB1
>> 840 select SYS_SUPPORTS_BIG_ENDIAN
>> 841 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 842
>> 843 config SIBYTE_CRHONE
>> 844 bool "Sibyte BCM91125C-CRhone"
>> 845 select BOOT_ELF32
>> 846 select SIBYTE_BCM1125
>> 847 select SWAP_IO_SPACE
>> 848 select SYS_HAS_CPU_SB1
>> 849 select SYS_SUPPORTS_BIG_ENDIAN
>> 850 select SYS_SUPPORTS_HIGHMEM
>> 851 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 852
>> 853 config SIBYTE_RHONE
>> 854 bool "Sibyte BCM91125E-Rhone"
>> 855 select BOOT_ELF32
>> 856 select SIBYTE_BCM1125H
>> 857 select SWAP_IO_SPACE
>> 858 select SYS_HAS_CPU_SB1
>> 859 select SYS_SUPPORTS_BIG_ENDIAN
>> 860 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 861
>> 862 config SIBYTE_SWARM
>> 863 bool "Sibyte BCM91250A-SWARM"
>> 864 select BOOT_ELF32
>> 865 select HAVE_PATA_PLATFORM
>> 866 select SIBYTE_SB1250
>> 867 select SWAP_IO_SPACE
>> 868 select SYS_HAS_CPU_SB1
>> 869 select SYS_SUPPORTS_BIG_ENDIAN
>> 870 select SYS_SUPPORTS_HIGHMEM
>> 871 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 872 select ZONE_DMA32 if 64BIT
>> 873 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 874
>> 875 config SIBYTE_LITTLESUR
>> 876 bool "Sibyte BCM91250C2-LittleSur"
>> 877 select BOOT_ELF32
>> 878 select HAVE_PATA_PLATFORM
>> 879 select SIBYTE_SB1250
>> 880 select SWAP_IO_SPACE
>> 881 select SYS_HAS_CPU_SB1
>> 882 select SYS_SUPPORTS_BIG_ENDIAN
>> 883 select SYS_SUPPORTS_HIGHMEM
>> 884 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 885 select ZONE_DMA32 if 64BIT
>> 886
>> 887 config SIBYTE_SENTOSA
>> 888 bool "Sibyte BCM91250E-Sentosa"
>> 889 select BOOT_ELF32
>> 890 select SIBYTE_SB1250
>> 891 select SWAP_IO_SPACE
>> 892 select SYS_HAS_CPU_SB1
>> 893 select SYS_SUPPORTS_BIG_ENDIAN
>> 894 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 895 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 896
>> 897 config SIBYTE_BIGSUR
>> 898 bool "Sibyte BCM91480B-BigSur"
>> 899 select BOOT_ELF32
>> 900 select NR_CPUS_DEFAULT_4
>> 901 select SIBYTE_BCM1x80
>> 902 select SWAP_IO_SPACE
>> 903 select SYS_HAS_CPU_SB1
>> 904 select SYS_SUPPORTS_BIG_ENDIAN
>> 905 select SYS_SUPPORTS_HIGHMEM
>> 906 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 907 select ZONE_DMA32 if 64BIT
>> 908 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 909
>> 910 config SNI_RM
>> 911 bool "SNI RM200/300/400"
>> 912 select ARC_MEMORY
>> 913 select ARC_PROMLIB
>> 914 select FW_ARC if CPU_LITTLE_ENDIAN
>> 915 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 916 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 917 select ARCH_MAY_HAVE_PC_FDC
>> 918 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 919 select ARCH_MIGHT_HAVE_PC_SERIO
>> 920 select BOOT_ELF32
>> 921 select CEVT_R4K
>> 922 select CSRC_R4K
>> 923 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 924 select DMA_NONCOHERENT
>> 925 select GENERIC_ISA_DMA
>> 926 select HAVE_EISA
>> 927 select HAVE_PCSPKR_PLATFORM
>> 928 select HAVE_PCI
>> 929 select IRQ_MIPS_CPU
>> 930 select I8253
>> 931 select I8259
>> 932 select ISA
>> 933 select MIPS_L1_CACHE_SHIFT_6
>> 934 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 935 select SYS_HAS_CPU_R4X00
>> 936 select SYS_HAS_CPU_R5000
>> 937 select SYS_HAS_CPU_R10000
>> 938 select R5000_CPU_SCACHE
>> 939 select SYS_HAS_EARLY_PRINTK
>> 940 select SYS_SUPPORTS_32BIT_KERNEL
>> 941 select SYS_SUPPORTS_64BIT_KERNEL
>> 942 select SYS_SUPPORTS_BIG_ENDIAN
>> 943 select SYS_SUPPORTS_HIGHMEM
>> 944 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 945 select WAR_R4600_V2_HIT_CACHEOP
>> 946 help
>> 947 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 948 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 949 Technology and now in turn merged with Fujitsu. Say Y here to
>> 950 support this machine type.
>> 951
>> 952 config MACH_TX39XX
>> 953 bool "Toshiba TX39 series based machines"
>> 954
>> 955 config MACH_TX49XX
>> 956 bool "Toshiba TX49 series based machines"
>> 957 select WAR_TX49XX_ICACHE_INDEX_INV
>> 958
>> 959 config MIKROTIK_RB532
>> 960 bool "Mikrotik RB532 boards"
>> 961 select CEVT_R4K
>> 962 select CSRC_R4K
>> 963 select DMA_NONCOHERENT
>> 964 select HAVE_PCI
>> 965 select IRQ_MIPS_CPU
>> 966 select SYS_HAS_CPU_MIPS32_R1
>> 967 select SYS_SUPPORTS_32BIT_KERNEL
>> 968 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 969 select SWAP_IO_SPACE
>> 970 select BOOT_RAW
>> 971 select GPIOLIB
>> 972 select MIPS_L1_CACHE_SHIFT_4
>> 973 help
>> 974 Support the Mikrotik(tm) RouterBoard 532 series,
>> 975 based on the IDT RC32434 SoC.
>> 976
>> 977 config CAVIUM_OCTEON_SOC
>> 978 bool "Cavium Networks Octeon SoC based boards"
>> 979 select CEVT_R4K
>> 980 select ARCH_HAS_PHYS_TO_DMA
>> 981 select HAVE_RAPIDIO
>> 982 select PHYS_ADDR_T_64BIT
>> 983 select SYS_SUPPORTS_64BIT_KERNEL
>> 984 select SYS_SUPPORTS_BIG_ENDIAN
>> 985 select EDAC_SUPPORT
>> 986 select EDAC_ATOMIC_SCRUB
>> 987 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 988 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 989 select SYS_HAS_EARLY_PRINTK
>> 990 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 991 select HAVE_PCI
>> 992 select HAVE_PLAT_DELAY
>> 993 select HAVE_PLAT_FW_INIT_CMDLINE
>> 994 select HAVE_PLAT_MEMCPY
>> 995 select ZONE_DMA32
>> 996 select HOLES_IN_ZONE
>> 997 select GPIOLIB
>> 998 select USE_OF
>> 999 select ARCH_SPARSEMEM_ENABLE
>> 1000 select SYS_SUPPORTS_SMP
>> 1001 select NR_CPUS_DEFAULT_64
>> 1002 select MIPS_NR_CPU_NR_MAP_1024
>> 1003 select BUILTIN_DTB
>> 1004 select MTD_COMPLEX_MAPPINGS
>> 1005 select SWIOTLB
>> 1006 select SYS_SUPPORTS_RELOCATABLE
>> 1007 help
>> 1008 This option supports all of the Octeon reference boards from Cavium
>> 1009 Networks. It builds a kernel that dynamically determines the Octeon
>> 1010 CPU type and supports all known board reference implementations.
>> 1011 Some of the supported boards are:
>> 1012 EBT3000
>> 1013 EBH3000
>> 1014 EBH3100
>> 1015 Thunder
>> 1016 Kodama
>> 1017 Hikari
>> 1018 Say Y here for most Octeon reference boards.
>> 1019
>> 1020 config NLM_XLR_BOARD
>> 1021 bool "Netlogic XLR/XLS based systems"
>> 1022 select BOOT_ELF32
>> 1023 select NLM_COMMON
>> 1024 select SYS_HAS_CPU_XLR
>> 1025 select SYS_SUPPORTS_SMP
>> 1026 select HAVE_PCI
>> 1027 select SWAP_IO_SPACE
>> 1028 select SYS_SUPPORTS_32BIT_KERNEL
>> 1029 select SYS_SUPPORTS_64BIT_KERNEL
>> 1030 select PHYS_ADDR_T_64BIT
>> 1031 select SYS_SUPPORTS_BIG_ENDIAN
>> 1032 select SYS_SUPPORTS_HIGHMEM
>> 1033 select NR_CPUS_DEFAULT_32
>> 1034 select CEVT_R4K
>> 1035 select CSRC_R4K
>> 1036 select IRQ_MIPS_CPU
>> 1037 select ZONE_DMA32 if 64BIT
>> 1038 select SYNC_R4K
>> 1039 select SYS_HAS_EARLY_PRINTK
>> 1040 select SYS_SUPPORTS_ZBOOT
>> 1041 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1042 help
>> 1043 Support for systems based on Netlogic XLR and XLS processors.
>> 1044 Say Y here if you have a XLR or XLS based board.
>> 1045
>> 1046 config NLM_XLP_BOARD
>> 1047 bool "Netlogic XLP based systems"
>> 1048 select BOOT_ELF32
>> 1049 select NLM_COMMON
>> 1050 select SYS_HAS_CPU_XLP
>> 1051 select SYS_SUPPORTS_SMP
>> 1052 select HAVE_PCI
>> 1053 select SYS_SUPPORTS_32BIT_KERNEL
>> 1054 select SYS_SUPPORTS_64BIT_KERNEL
>> 1055 select PHYS_ADDR_T_64BIT
>> 1056 select GPIOLIB
>> 1057 select SYS_SUPPORTS_BIG_ENDIAN
>> 1058 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1059 select SYS_SUPPORTS_HIGHMEM
>> 1060 select NR_CPUS_DEFAULT_32
>> 1061 select CEVT_R4K
>> 1062 select CSRC_R4K
>> 1063 select IRQ_MIPS_CPU
>> 1064 select ZONE_DMA32 if 64BIT
>> 1065 select SYNC_R4K
>> 1066 select SYS_HAS_EARLY_PRINTK
>> 1067 select USE_OF
>> 1068 select SYS_SUPPORTS_ZBOOT
>> 1069 select SYS_SUPPORTS_ZBOOT_UART16550
60 help 1070 help
61 Xtensa processors are 32-bit RISC ma !! 1071 This board is based on Netlogic XLP Processor.
62 primarily for embedded systems. The !! 1072 Say Y here if you have a XLP based board.
63 configurable and extensible. The Li !! 1073
64 architecture supports all processor !! 1074 endchoice
65 with reasonable minimum requirements !! 1075
66 a home page at <http://www.linux-xte !! 1076 source "arch/mips/alchemy/Kconfig"
>> 1077 source "arch/mips/ath25/Kconfig"
>> 1078 source "arch/mips/ath79/Kconfig"
>> 1079 source "arch/mips/bcm47xx/Kconfig"
>> 1080 source "arch/mips/bcm63xx/Kconfig"
>> 1081 source "arch/mips/bmips/Kconfig"
>> 1082 source "arch/mips/generic/Kconfig"
>> 1083 source "arch/mips/ingenic/Kconfig"
>> 1084 source "arch/mips/jazz/Kconfig"
>> 1085 source "arch/mips/lantiq/Kconfig"
>> 1086 source "arch/mips/pic32/Kconfig"
>> 1087 source "arch/mips/pistachio/Kconfig"
>> 1088 source "arch/mips/ralink/Kconfig"
>> 1089 source "arch/mips/sgi-ip27/Kconfig"
>> 1090 source "arch/mips/sibyte/Kconfig"
>> 1091 source "arch/mips/txx9/Kconfig"
>> 1092 source "arch/mips/vr41xx/Kconfig"
>> 1093 source "arch/mips/cavium-octeon/Kconfig"
>> 1094 source "arch/mips/loongson2ef/Kconfig"
>> 1095 source "arch/mips/loongson32/Kconfig"
>> 1096 source "arch/mips/loongson64/Kconfig"
>> 1097 source "arch/mips/netlogic/Kconfig"
>> 1098
>> 1099 endmenu
67 1100
68 config GENERIC_HWEIGHT 1101 config GENERIC_HWEIGHT
69 def_bool y !! 1102 bool
>> 1103 default y
70 1104
71 config ARCH_HAS_ILOG2_U32 !! 1105 config GENERIC_CALIBRATE_DELAY
72 def_bool n !! 1106 bool
>> 1107 default y
73 1108
74 config ARCH_HAS_ILOG2_U64 !! 1109 config SCHED_OMIT_FRAME_POINTER
75 def_bool n !! 1110 bool
>> 1111 default y
76 1112
77 config ARCH_MTD_XIP !! 1113 #
78 def_bool y !! 1114 # Select some configuration options automatically based on user selections.
>> 1115 #
>> 1116 config FW_ARC
>> 1117 bool
>> 1118
>> 1119 config ARCH_MAY_HAVE_PC_FDC
>> 1120 bool
>> 1121
>> 1122 config BOOT_RAW
>> 1123 bool
>> 1124
>> 1125 config CEVT_BCM1480
>> 1126 bool
>> 1127
>> 1128 config CEVT_DS1287
>> 1129 bool
>> 1130
>> 1131 config CEVT_GT641XX
>> 1132 bool
>> 1133
>> 1134 config CEVT_R4K
>> 1135 bool
>> 1136
>> 1137 config CEVT_SB1250
>> 1138 bool
>> 1139
>> 1140 config CEVT_TXX9
>> 1141 bool
>> 1142
>> 1143 config CSRC_BCM1480
>> 1144 bool
>> 1145
>> 1146 config CSRC_IOASIC
>> 1147 bool
>> 1148
>> 1149 config CSRC_R4K
>> 1150 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1151 bool
>> 1152
>> 1153 config CSRC_SB1250
>> 1154 bool
>> 1155
>> 1156 config MIPS_CLOCK_VSYSCALL
>> 1157 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1158
>> 1159 config GPIO_TXX9
>> 1160 select GPIOLIB
>> 1161 bool
>> 1162
>> 1163 config FW_CFE
>> 1164 bool
>> 1165
>> 1166 config ARCH_SUPPORTS_UPROBES
>> 1167 bool
>> 1168
>> 1169 config DMA_PERDEV_COHERENT
>> 1170 bool
>> 1171 select ARCH_HAS_SETUP_DMA_OPS
>> 1172 select DMA_NONCOHERENT
>> 1173
>> 1174 config DMA_NONCOHERENT
>> 1175 bool
>> 1176 #
>> 1177 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1178 # Attribute bits. It is believed that the uncached access through
>> 1179 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1180 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1181 # significant advantages.
>> 1182 #
>> 1183 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1184 select ARCH_HAS_DMA_PREP_COHERENT
>> 1185 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1186 select ARCH_HAS_DMA_SET_UNCACHED
>> 1187 select DMA_NONCOHERENT_MMAP
>> 1188 select NEED_DMA_MAP_STATE
>> 1189
>> 1190 config SYS_HAS_EARLY_PRINTK
>> 1191 bool
>> 1192
>> 1193 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1194 bool
>> 1195
>> 1196 config MIPS_BONITO64
>> 1197 bool
>> 1198
>> 1199 config MIPS_MSC
>> 1200 bool
>> 1201
>> 1202 config SYNC_R4K
>> 1203 bool
79 1204
80 config NO_IOPORT_MAP 1205 config NO_IOPORT_MAP
81 def_bool n 1206 def_bool n
82 1207
83 config HZ !! 1208 config GENERIC_CSUM
84 int !! 1209 def_bool CPU_NO_LOAD_STORE_LR
85 default 100 <<
86 1210
87 config LOCKDEP_SUPPORT !! 1211 config GENERIC_ISA_DMA
88 def_bool y !! 1212 bool
>> 1213 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1214 select ISA_DMA_API
89 1215
90 config STACKTRACE_SUPPORT !! 1216 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1217 bool
>> 1218 select GENERIC_ISA_DMA
>> 1219
>> 1220 config HAVE_PLAT_DELAY
>> 1221 bool
>> 1222
>> 1223 config HAVE_PLAT_FW_INIT_CMDLINE
>> 1224 bool
>> 1225
>> 1226 config HAVE_PLAT_MEMCPY
>> 1227 bool
>> 1228
>> 1229 config ISA_DMA_API
>> 1230 bool
>> 1231
>> 1232 config HOLES_IN_ZONE
>> 1233 bool
>> 1234
>> 1235 config SYS_SUPPORTS_RELOCATABLE
>> 1236 bool
>> 1237 help
>> 1238 Selected if the platform supports relocating the kernel.
>> 1239 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1240 to allow access to command line and entropy sources.
>> 1241
>> 1242 config MIPS_CBPF_JIT
91 def_bool y 1243 def_bool y
>> 1244 depends on BPF_JIT && HAVE_CBPF_JIT
92 1245
93 config MMU !! 1246 config MIPS_EBPF_JIT
94 def_bool n !! 1247 def_bool y
95 select PFAULT !! 1248 depends on BPF_JIT && HAVE_EBPF_JIT
96 1249
97 config HAVE_XTENSA_GPIO32 <<
98 def_bool n <<
99 1250
100 config KASAN_SHADOW_OFFSET !! 1251 #
101 hex !! 1252 # Endianness selection. Sufficiently obscure so many users don't know what to
102 default 0x6e400000 !! 1253 # answer,so we try hard to limit the available choices. Also the use of a
>> 1254 # choice statement should be more obvious to the user.
>> 1255 #
>> 1256 choice
>> 1257 prompt "Endianness selection"
>> 1258 help
>> 1259 Some MIPS machines can be configured for either little or big endian
>> 1260 byte order. These modes require different kernels and a different
>> 1261 Linux distribution. In general there is one preferred byteorder for a
>> 1262 particular system but some systems are just as commonly used in the
>> 1263 one or the other endianness.
103 1264
104 config CPU_BIG_ENDIAN 1265 config CPU_BIG_ENDIAN
105 def_bool $(success,test "$(shell,echo !! 1266 bool "Big endian"
>> 1267 depends on SYS_SUPPORTS_BIG_ENDIAN
106 1268
107 config CPU_LITTLE_ENDIAN 1269 config CPU_LITTLE_ENDIAN
108 def_bool !CPU_BIG_ENDIAN !! 1270 bool "Little endian"
>> 1271 depends on SYS_SUPPORTS_LITTLE_ENDIAN
>> 1272
>> 1273 endchoice
>> 1274
>> 1275 config EXPORT_UASM
>> 1276 bool
>> 1277
>> 1278 config SYS_SUPPORTS_APM_EMULATION
>> 1279 bool
>> 1280
>> 1281 config SYS_SUPPORTS_BIG_ENDIAN
>> 1282 bool
>> 1283
>> 1284 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1285 bool
>> 1286
>> 1287 config SYS_SUPPORTS_HUGETLBFS
>> 1288 bool
>> 1289 depends on CPU_SUPPORTS_HUGEPAGES
>> 1290 default y
>> 1291
>> 1292 config MIPS_HUGE_TLB_SUPPORT
>> 1293 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
>> 1294
>> 1295 config IRQ_MSP_SLP
>> 1296 bool
>> 1297
>> 1298 config IRQ_MSP_CIC
>> 1299 bool
>> 1300
>> 1301 config IRQ_TXX9
>> 1302 bool
>> 1303
>> 1304 config IRQ_GT641XX
>> 1305 bool
>> 1306
>> 1307 config PCI_GT64XXX_PCI0
>> 1308 bool
>> 1309
>> 1310 config PCI_XTALK_BRIDGE
>> 1311 bool
>> 1312
>> 1313 config NO_EXCEPT_FILL
>> 1314 bool
>> 1315
>> 1316 config MIPS_SPRAM
>> 1317 bool
>> 1318
>> 1319 config SWAP_IO_SPACE
>> 1320 bool
109 1321
110 config CC_HAVE_CALL0_ABI !! 1322 config SGI_HAS_INDYDOG
111 def_bool $(success,test "$(shell,echo !! 1323 bool
>> 1324
>> 1325 config SGI_HAS_HAL2
>> 1326 bool
112 1327
113 menu "Processor type and features" !! 1328 config SGI_HAS_SEEQ
>> 1329 bool
>> 1330
>> 1331 config SGI_HAS_WD93
>> 1332 bool
>> 1333
>> 1334 config SGI_HAS_ZILOG
>> 1335 bool
>> 1336
>> 1337 config SGI_HAS_I8042
>> 1338 bool
>> 1339
>> 1340 config DEFAULT_SGI_PARTITION
>> 1341 bool
>> 1342
>> 1343 config FW_ARC32
>> 1344 bool
>> 1345
>> 1346 config FW_SNIPROM
>> 1347 bool
>> 1348
>> 1349 config BOOT_ELF32
>> 1350 bool
>> 1351
>> 1352 config MIPS_L1_CACHE_SHIFT_4
>> 1353 bool
>> 1354
>> 1355 config MIPS_L1_CACHE_SHIFT_5
>> 1356 bool
>> 1357
>> 1358 config MIPS_L1_CACHE_SHIFT_6
>> 1359 bool
>> 1360
>> 1361 config MIPS_L1_CACHE_SHIFT_7
>> 1362 bool
>> 1363
>> 1364 config MIPS_L1_CACHE_SHIFT
>> 1365 int
>> 1366 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1367 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1368 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1369 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1370 default "5"
>> 1371
>> 1372 config ARC_CMDLINE_ONLY
>> 1373 bool
>> 1374
>> 1375 config ARC_CONSOLE
>> 1376 bool "ARC console support"
>> 1377 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
>> 1378
>> 1379 config ARC_MEMORY
>> 1380 bool
>> 1381
>> 1382 config ARC_PROMLIB
>> 1383 bool
>> 1384
>> 1385 config FW_ARC64
>> 1386 bool
>> 1387
>> 1388 config BOOT_ELF64
>> 1389 bool
>> 1390
>> 1391 menu "CPU selection"
114 1392
115 choice 1393 choice
116 prompt "Xtensa Processor Configuration !! 1394 prompt "CPU type"
117 default XTENSA_VARIANT_FSF !! 1395 default CPU_R4X00
118 1396
119 config XTENSA_VARIANT_FSF !! 1397 config CPU_LOONGSON64
120 bool "fsf - default (not generic) conf !! 1398 bool "Loongson 64-bit CPU"
121 select MMU !! 1399 depends on SYS_HAS_CPU_LOONGSON64
>> 1400 select ARCH_HAS_PHYS_TO_DMA
>> 1401 select CPU_MIPSR2
>> 1402 select CPU_HAS_PREFETCH
>> 1403 select CPU_SUPPORTS_64BIT_KERNEL
>> 1404 select CPU_SUPPORTS_HIGHMEM
>> 1405 select CPU_SUPPORTS_HUGEPAGES
>> 1406 select CPU_SUPPORTS_MSA
>> 1407 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1408 select CPU_MIPSR2_IRQ_VI
>> 1409 select WEAK_ORDERING
>> 1410 select WEAK_REORDERING_BEYOND_LLSC
>> 1411 select MIPS_ASID_BITS_VARIABLE
>> 1412 select MIPS_PGD_C0_CONTEXT
>> 1413 select MIPS_L1_CACHE_SHIFT_6
>> 1414 select GPIOLIB
>> 1415 select SWIOTLB
>> 1416 select HAVE_KVM
>> 1417 help
>> 1418 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1419 cores implements the MIPS64R2 instruction set with many extensions,
>> 1420 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1421 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1422 Loongson-2E/2F is not covered here and will be removed in future.
122 1423
123 config XTENSA_VARIANT_DC232B !! 1424 config LOONGSON3_ENHANCEMENT
124 bool "dc232b - Diamond 232L Standard C !! 1425 bool "New Loongson-3 CPU Enhancements"
125 select MMU !! 1426 default n
126 select HAVE_XTENSA_GPIO32 !! 1427 depends on CPU_LOONGSON64
127 help 1428 help
128 This variant refers to Tensilica's D !! 1429 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1430 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1431 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1432 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1433 Fast TLB refill support, etc.
>> 1434
>> 1435 This option enable those enhancements which are not probed at run
>> 1436 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1437 please say 'N' here. If you want a high-performance kernel to run on
>> 1438 new Loongson-3 machines only, please say 'Y' here.
>> 1439
>> 1440 config CPU_LOONGSON3_WORKAROUNDS
>> 1441 bool "Old Loongson-3 LLSC Workarounds"
>> 1442 default y if SMP
>> 1443 depends on CPU_LOONGSON64
>> 1444 help
>> 1445 Loongson-3 processors have the llsc issues which require workarounds.
>> 1446 Without workarounds the system may hang unexpectedly.
>> 1447
>> 1448 Newer Loongson-3 will fix these issues and no workarounds are needed.
>> 1449 The workarounds have no significant side effect on them but may
>> 1450 decrease the performance of the system so this option should be
>> 1451 disabled unless the kernel is intended to be run on old systems.
129 1452
130 config XTENSA_VARIANT_DC233C !! 1453 If unsure, please say Y.
131 bool "dc233c - Diamond 233L Standard C <<
132 select MMU <<
133 select HAVE_XTENSA_GPIO32 <<
134 help <<
135 This variant refers to Tensilica's D <<
136 1454
137 config XTENSA_VARIANT_CUSTOM !! 1455 config CPU_LOONGSON3_CPUCFG_EMULATION
138 bool "Custom Xtensa processor configur !! 1456 bool "Emulate the CPUCFG instruction on older Loongson cores"
139 select HAVE_XTENSA_GPIO32 !! 1457 default y
>> 1458 depends on CPU_LOONGSON64
>> 1459 help
>> 1460 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1461 userland to query CPU capabilities, much like CPUID on x86. This
>> 1462 option provides emulation of the instruction on older Loongson
>> 1463 cores, back to Loongson-3A1000.
>> 1464
>> 1465 If unsure, please say Y.
>> 1466
>> 1467 config CPU_LOONGSON2E
>> 1468 bool "Loongson 2E"
>> 1469 depends on SYS_HAS_CPU_LOONGSON2E
>> 1470 select CPU_LOONGSON2EF
>> 1471 help
>> 1472 The Loongson 2E processor implements the MIPS III instruction set
>> 1473 with many extensions.
>> 1474
>> 1475 It has an internal FPGA northbridge, which is compatible to
>> 1476 bonito64.
>> 1477
>> 1478 config CPU_LOONGSON2F
>> 1479 bool "Loongson 2F"
>> 1480 depends on SYS_HAS_CPU_LOONGSON2F
>> 1481 select CPU_LOONGSON2EF
>> 1482 select GPIOLIB
>> 1483 help
>> 1484 The Loongson 2F processor implements the MIPS III instruction set
>> 1485 with many extensions.
>> 1486
>> 1487 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1488 have a similar programming interface with FPGA northbridge used in
>> 1489 Loongson2E.
>> 1490
>> 1491 config CPU_LOONGSON1B
>> 1492 bool "Loongson 1B"
>> 1493 depends on SYS_HAS_CPU_LOONGSON1B
>> 1494 select CPU_LOONGSON32
>> 1495 select LEDS_GPIO_REGISTER
>> 1496 help
>> 1497 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1498 Release 1 instruction set and part of the MIPS32 Release 2
>> 1499 instruction set.
>> 1500
>> 1501 config CPU_LOONGSON1C
>> 1502 bool "Loongson 1C"
>> 1503 depends on SYS_HAS_CPU_LOONGSON1C
>> 1504 select CPU_LOONGSON32
>> 1505 select LEDS_GPIO_REGISTER
>> 1506 help
>> 1507 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1508 Release 1 instruction set and part of the MIPS32 Release 2
>> 1509 instruction set.
>> 1510
>> 1511 config CPU_MIPS32_R1
>> 1512 bool "MIPS32 Release 1"
>> 1513 depends on SYS_HAS_CPU_MIPS32_R1
>> 1514 select CPU_HAS_PREFETCH
>> 1515 select CPU_SUPPORTS_32BIT_KERNEL
>> 1516 select CPU_SUPPORTS_HIGHMEM
>> 1517 help
>> 1518 Choose this option to build a kernel for release 1 or later of the
>> 1519 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1520 MIPS processor are based on a MIPS32 processor. If you know the
>> 1521 specific type of processor in your system, choose those that one
>> 1522 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1523 Release 2 of the MIPS32 architecture is available since several
>> 1524 years so chances are you even have a MIPS32 Release 2 processor
>> 1525 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1526 performance.
>> 1527
>> 1528 config CPU_MIPS32_R2
>> 1529 bool "MIPS32 Release 2"
>> 1530 depends on SYS_HAS_CPU_MIPS32_R2
>> 1531 select CPU_HAS_PREFETCH
>> 1532 select CPU_SUPPORTS_32BIT_KERNEL
>> 1533 select CPU_SUPPORTS_HIGHMEM
>> 1534 select CPU_SUPPORTS_MSA
>> 1535 select HAVE_KVM
>> 1536 help
>> 1537 Choose this option to build a kernel for release 2 or later of the
>> 1538 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1539 MIPS processor are based on a MIPS32 processor. If you know the
>> 1540 specific type of processor in your system, choose those that one
>> 1541 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1542
>> 1543 config CPU_MIPS32_R5
>> 1544 bool "MIPS32 Release 5"
>> 1545 depends on SYS_HAS_CPU_MIPS32_R5
>> 1546 select CPU_HAS_PREFETCH
>> 1547 select CPU_SUPPORTS_32BIT_KERNEL
>> 1548 select CPU_SUPPORTS_HIGHMEM
>> 1549 select CPU_SUPPORTS_MSA
>> 1550 select HAVE_KVM
>> 1551 select MIPS_O32_FP64_SUPPORT
>> 1552 help
>> 1553 Choose this option to build a kernel for release 5 or later of the
>> 1554 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1555 family, are based on a MIPS32r5 processor. If you own an older
>> 1556 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1557
>> 1558 config CPU_MIPS32_R6
>> 1559 bool "MIPS32 Release 6"
>> 1560 depends on SYS_HAS_CPU_MIPS32_R6
>> 1561 select CPU_HAS_PREFETCH
>> 1562 select CPU_NO_LOAD_STORE_LR
>> 1563 select CPU_SUPPORTS_32BIT_KERNEL
>> 1564 select CPU_SUPPORTS_HIGHMEM
>> 1565 select CPU_SUPPORTS_MSA
>> 1566 select HAVE_KVM
>> 1567 select MIPS_O32_FP64_SUPPORT
>> 1568 help
>> 1569 Choose this option to build a kernel for release 6 or later of the
>> 1570 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1571 family, are based on a MIPS32r6 processor. If you own an older
>> 1572 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1573
>> 1574 config CPU_MIPS64_R1
>> 1575 bool "MIPS64 Release 1"
>> 1576 depends on SYS_HAS_CPU_MIPS64_R1
>> 1577 select CPU_HAS_PREFETCH
>> 1578 select CPU_SUPPORTS_32BIT_KERNEL
>> 1579 select CPU_SUPPORTS_64BIT_KERNEL
>> 1580 select CPU_SUPPORTS_HIGHMEM
>> 1581 select CPU_SUPPORTS_HUGEPAGES
>> 1582 help
>> 1583 Choose this option to build a kernel for release 1 or later of the
>> 1584 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1585 MIPS processor are based on a MIPS64 processor. If you know the
>> 1586 specific type of processor in your system, choose those that one
>> 1587 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1588 Release 2 of the MIPS64 architecture is available since several
>> 1589 years so chances are you even have a MIPS64 Release 2 processor
>> 1590 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1591 performance.
>> 1592
>> 1593 config CPU_MIPS64_R2
>> 1594 bool "MIPS64 Release 2"
>> 1595 depends on SYS_HAS_CPU_MIPS64_R2
>> 1596 select CPU_HAS_PREFETCH
>> 1597 select CPU_SUPPORTS_32BIT_KERNEL
>> 1598 select CPU_SUPPORTS_64BIT_KERNEL
>> 1599 select CPU_SUPPORTS_HIGHMEM
>> 1600 select CPU_SUPPORTS_HUGEPAGES
>> 1601 select CPU_SUPPORTS_MSA
>> 1602 select HAVE_KVM
>> 1603 help
>> 1604 Choose this option to build a kernel for release 2 or later of the
>> 1605 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1606 MIPS processor are based on a MIPS64 processor. If you know the
>> 1607 specific type of processor in your system, choose those that one
>> 1608 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1609
>> 1610 config CPU_MIPS64_R5
>> 1611 bool "MIPS64 Release 5"
>> 1612 depends on SYS_HAS_CPU_MIPS64_R5
>> 1613 select CPU_HAS_PREFETCH
>> 1614 select CPU_SUPPORTS_32BIT_KERNEL
>> 1615 select CPU_SUPPORTS_64BIT_KERNEL
>> 1616 select CPU_SUPPORTS_HIGHMEM
>> 1617 select CPU_SUPPORTS_HUGEPAGES
>> 1618 select CPU_SUPPORTS_MSA
>> 1619 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1620 select HAVE_KVM
>> 1621 help
>> 1622 Choose this option to build a kernel for release 5 or later of the
>> 1623 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1624 release partly implementing release 6 features. Though there is no
>> 1625 any hardware known to be based on this release.
>> 1626
>> 1627 config CPU_MIPS64_R6
>> 1628 bool "MIPS64 Release 6"
>> 1629 depends on SYS_HAS_CPU_MIPS64_R6
>> 1630 select CPU_HAS_PREFETCH
>> 1631 select CPU_NO_LOAD_STORE_LR
>> 1632 select CPU_SUPPORTS_32BIT_KERNEL
>> 1633 select CPU_SUPPORTS_64BIT_KERNEL
>> 1634 select CPU_SUPPORTS_HIGHMEM
>> 1635 select CPU_SUPPORTS_HUGEPAGES
>> 1636 select CPU_SUPPORTS_MSA
>> 1637 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1638 select HAVE_KVM
>> 1639 help
>> 1640 Choose this option to build a kernel for release 6 or later of the
>> 1641 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1642 family, are based on a MIPS64r6 processor. If you own an older
>> 1643 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1644
>> 1645 config CPU_P5600
>> 1646 bool "MIPS Warrior P5600"
>> 1647 depends on SYS_HAS_CPU_P5600
>> 1648 select CPU_HAS_PREFETCH
>> 1649 select CPU_SUPPORTS_32BIT_KERNEL
>> 1650 select CPU_SUPPORTS_HIGHMEM
>> 1651 select CPU_SUPPORTS_MSA
>> 1652 select CPU_SUPPORTS_CPUFREQ
>> 1653 select CPU_MIPSR2_IRQ_VI
>> 1654 select CPU_MIPSR2_IRQ_EI
>> 1655 select HAVE_KVM
>> 1656 select MIPS_O32_FP64_SUPPORT
>> 1657 help
>> 1658 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1659 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1660 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1661 level features like up to six P5600 calculation cores, CM2 with L2
>> 1662 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1663 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1664 eJTAG and PDtrace.
>> 1665
>> 1666 config CPU_R3000
>> 1667 bool "R3000"
>> 1668 depends on SYS_HAS_CPU_R3000
>> 1669 select CPU_HAS_WB
>> 1670 select CPU_R3K_TLB
>> 1671 select CPU_SUPPORTS_32BIT_KERNEL
>> 1672 select CPU_SUPPORTS_HIGHMEM
>> 1673 help
>> 1674 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1675 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1676 *not* work on R4000 machines and vice versa. However, since most
>> 1677 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1678 might be a safe bet. If the resulting kernel does not work,
>> 1679 try to recompile with R3000.
>> 1680
>> 1681 config CPU_TX39XX
>> 1682 bool "R39XX"
>> 1683 depends on SYS_HAS_CPU_TX39XX
>> 1684 select CPU_SUPPORTS_32BIT_KERNEL
>> 1685 select CPU_R3K_TLB
>> 1686
>> 1687 config CPU_VR41XX
>> 1688 bool "R41xx"
>> 1689 depends on SYS_HAS_CPU_VR41XX
>> 1690 select CPU_SUPPORTS_32BIT_KERNEL
>> 1691 select CPU_SUPPORTS_64BIT_KERNEL
>> 1692 help
>> 1693 The options selects support for the NEC VR4100 series of processors.
>> 1694 Only choose this option if you have one of these processors as a
>> 1695 kernel built with this option will not run on any other type of
>> 1696 processor or vice versa.
>> 1697
>> 1698 config CPU_R4300
>> 1699 bool "R4300"
>> 1700 depends on SYS_HAS_CPU_R4300
>> 1701 select CPU_SUPPORTS_32BIT_KERNEL
>> 1702 select CPU_SUPPORTS_64BIT_KERNEL
>> 1703 select CPU_HAS_LOAD_STORE_LR
>> 1704 help
>> 1705 MIPS Technologies R4300-series processors.
>> 1706
>> 1707 config CPU_R4X00
>> 1708 bool "R4x00"
>> 1709 depends on SYS_HAS_CPU_R4X00
>> 1710 select CPU_SUPPORTS_32BIT_KERNEL
>> 1711 select CPU_SUPPORTS_64BIT_KERNEL
>> 1712 select CPU_SUPPORTS_HUGEPAGES
>> 1713 help
>> 1714 MIPS Technologies R4000-series processors other than 4300, including
>> 1715 the R4000, R4400, R4600, and 4700.
>> 1716
>> 1717 config CPU_TX49XX
>> 1718 bool "R49XX"
>> 1719 depends on SYS_HAS_CPU_TX49XX
>> 1720 select CPU_HAS_PREFETCH
>> 1721 select CPU_SUPPORTS_32BIT_KERNEL
>> 1722 select CPU_SUPPORTS_64BIT_KERNEL
>> 1723 select CPU_SUPPORTS_HUGEPAGES
>> 1724
>> 1725 config CPU_R5000
>> 1726 bool "R5000"
>> 1727 depends on SYS_HAS_CPU_R5000
>> 1728 select CPU_SUPPORTS_32BIT_KERNEL
>> 1729 select CPU_SUPPORTS_64BIT_KERNEL
>> 1730 select CPU_SUPPORTS_HUGEPAGES
>> 1731 help
>> 1732 MIPS Technologies R5000-series processors other than the Nevada.
>> 1733
>> 1734 config CPU_R5500
>> 1735 bool "R5500"
>> 1736 depends on SYS_HAS_CPU_R5500
>> 1737 select CPU_SUPPORTS_32BIT_KERNEL
>> 1738 select CPU_SUPPORTS_64BIT_KERNEL
>> 1739 select CPU_SUPPORTS_HUGEPAGES
>> 1740 help
>> 1741 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1742 instruction set.
>> 1743
>> 1744 config CPU_NEVADA
>> 1745 bool "RM52xx"
>> 1746 depends on SYS_HAS_CPU_NEVADA
>> 1747 select CPU_SUPPORTS_32BIT_KERNEL
>> 1748 select CPU_SUPPORTS_64BIT_KERNEL
>> 1749 select CPU_SUPPORTS_HUGEPAGES
>> 1750 help
>> 1751 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1752
>> 1753 config CPU_R10000
>> 1754 bool "R10000"
>> 1755 depends on SYS_HAS_CPU_R10000
>> 1756 select CPU_HAS_PREFETCH
>> 1757 select CPU_SUPPORTS_32BIT_KERNEL
>> 1758 select CPU_SUPPORTS_64BIT_KERNEL
>> 1759 select CPU_SUPPORTS_HIGHMEM
>> 1760 select CPU_SUPPORTS_HUGEPAGES
>> 1761 help
>> 1762 MIPS Technologies R10000-series processors.
>> 1763
>> 1764 config CPU_RM7000
>> 1765 bool "RM7000"
>> 1766 depends on SYS_HAS_CPU_RM7000
>> 1767 select CPU_HAS_PREFETCH
>> 1768 select CPU_SUPPORTS_32BIT_KERNEL
>> 1769 select CPU_SUPPORTS_64BIT_KERNEL
>> 1770 select CPU_SUPPORTS_HIGHMEM
>> 1771 select CPU_SUPPORTS_HUGEPAGES
>> 1772
>> 1773 config CPU_SB1
>> 1774 bool "SB1"
>> 1775 depends on SYS_HAS_CPU_SB1
>> 1776 select CPU_SUPPORTS_32BIT_KERNEL
>> 1777 select CPU_SUPPORTS_64BIT_KERNEL
>> 1778 select CPU_SUPPORTS_HIGHMEM
>> 1779 select CPU_SUPPORTS_HUGEPAGES
>> 1780 select WEAK_ORDERING
>> 1781
>> 1782 config CPU_CAVIUM_OCTEON
>> 1783 bool "Cavium Octeon processor"
>> 1784 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1785 select CPU_HAS_PREFETCH
>> 1786 select CPU_SUPPORTS_64BIT_KERNEL
>> 1787 select WEAK_ORDERING
>> 1788 select CPU_SUPPORTS_HIGHMEM
>> 1789 select CPU_SUPPORTS_HUGEPAGES
>> 1790 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1791 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1792 select MIPS_L1_CACHE_SHIFT_7
>> 1793 select HAVE_KVM
>> 1794 help
>> 1795 The Cavium Octeon processor is a highly integrated chip containing
>> 1796 many ethernet hardware widgets for networking tasks. The processor
>> 1797 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1798 Full details can be found at http://www.caviumnetworks.com.
>> 1799
>> 1800 config CPU_BMIPS
>> 1801 bool "Broadcom BMIPS"
>> 1802 depends on SYS_HAS_CPU_BMIPS
>> 1803 select CPU_MIPS32
>> 1804 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1805 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1806 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1807 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1808 select CPU_SUPPORTS_32BIT_KERNEL
>> 1809 select DMA_NONCOHERENT
>> 1810 select IRQ_MIPS_CPU
>> 1811 select SWAP_IO_SPACE
>> 1812 select WEAK_ORDERING
>> 1813 select CPU_SUPPORTS_HIGHMEM
>> 1814 select CPU_HAS_PREFETCH
>> 1815 select CPU_SUPPORTS_CPUFREQ
>> 1816 select MIPS_EXTERNAL_TIMER
>> 1817 help
>> 1818 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1819
>> 1820 config CPU_XLR
>> 1821 bool "Netlogic XLR SoC"
>> 1822 depends on SYS_HAS_CPU_XLR
>> 1823 select CPU_SUPPORTS_32BIT_KERNEL
>> 1824 select CPU_SUPPORTS_64BIT_KERNEL
>> 1825 select CPU_SUPPORTS_HIGHMEM
>> 1826 select CPU_SUPPORTS_HUGEPAGES
>> 1827 select WEAK_ORDERING
>> 1828 select WEAK_REORDERING_BEYOND_LLSC
>> 1829 help
>> 1830 Netlogic Microsystems XLR/XLS processors.
>> 1831
>> 1832 config CPU_XLP
>> 1833 bool "Netlogic XLP SoC"
>> 1834 depends on SYS_HAS_CPU_XLP
>> 1835 select CPU_SUPPORTS_32BIT_KERNEL
>> 1836 select CPU_SUPPORTS_64BIT_KERNEL
>> 1837 select CPU_SUPPORTS_HIGHMEM
>> 1838 select WEAK_ORDERING
>> 1839 select WEAK_REORDERING_BEYOND_LLSC
>> 1840 select CPU_HAS_PREFETCH
>> 1841 select CPU_MIPSR2
>> 1842 select CPU_SUPPORTS_HUGEPAGES
>> 1843 select MIPS_ASID_BITS_VARIABLE
140 help 1844 help
141 Select this variant to use a custom !! 1845 Netlogic Microsystems XLP processors.
142 You will be prompted for a processor <<
143 endchoice 1846 endchoice
144 1847
145 config XTENSA_VARIANT_CUSTOM_NAME !! 1848 config CPU_MIPS32_3_5_FEATURES
146 string "Xtensa Processor Custom Core V !! 1849 bool "MIPS32 Release 3.5 Features"
147 depends on XTENSA_VARIANT_CUSTOM !! 1850 depends on SYS_HAS_CPU_MIPS32_R3_5
148 help !! 1851 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
149 Provide the name of a custom Xtensa !! 1852 CPU_P5600
150 This CORENAME selects arch/xtensa/va !! 1853 help
151 Don't forget you have to select MMU !! 1854 Choose this option to build a kernel for release 2 or later of the
152 !! 1855 MIPS32 architecture including features from the 3.5 release such as
153 config XTENSA_VARIANT_NAME !! 1856 support for Enhanced Virtual Addressing (EVA).
154 string !! 1857
155 default "dc232b" !! 1858 config CPU_MIPS32_3_5_EVA
156 default "dc233c" !! 1859 bool "Enhanced Virtual Addressing (EVA)"
157 default "fsf" !! 1860 depends on CPU_MIPS32_3_5_FEATURES
158 default XTENSA_VARIANT_CUSTOM_NAME !! 1861 select EVA
159 !! 1862 default y
160 config XTENSA_VARIANT_MMU !! 1863 help
161 bool "Core variant has a Full MMU (TLB !! 1864 Choose this option if you want to enable the Enhanced Virtual
162 depends on XTENSA_VARIANT_CUSTOM !! 1865 Addressing (EVA) on your MIPS32 core (such as proAptiv).
163 default y !! 1866 One of its primary benefits is an increase in the maximum size
164 select MMU !! 1867 of lowmem (up to 3GB). If unsure, say 'N' here.
165 help !! 1868
166 Build a Conventional Kernel with ful !! 1869 config CPU_MIPS32_R5_FEATURES
167 ie: it supports a TLB with auto-load !! 1870 bool "MIPS32 Release 5 Features"
168 !! 1871 depends on SYS_HAS_CPU_MIPS32_R5
169 config XTENSA_VARIANT_HAVE_PERF_EVENTS !! 1872 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
170 bool "Core variant has Performance Mon !! 1873 help
171 depends on XTENSA_VARIANT_CUSTOM !! 1874 Choose this option to build a kernel for release 2 or later of the
>> 1875 MIPS32 architecture including features from release 5 such as
>> 1876 support for Extended Physical Addressing (XPA).
>> 1877
>> 1878 config CPU_MIPS32_R5_XPA
>> 1879 bool "Extended Physical Addressing (XPA)"
>> 1880 depends on CPU_MIPS32_R5_FEATURES
>> 1881 depends on !EVA
>> 1882 depends on !PAGE_SIZE_4KB
>> 1883 depends on SYS_SUPPORTS_HIGHMEM
>> 1884 select XPA
>> 1885 select HIGHMEM
>> 1886 select PHYS_ADDR_T_64BIT
172 default n 1887 default n
173 help 1888 help
174 Enable if core variant has Performan !! 1889 Choose this option if you want to enable the Extended Physical
175 External Registers Interface. !! 1890 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1891 benefit is to increase physical addressing equal to or greater
>> 1892 than 40 bits. Note that this has the side effect of turning on
>> 1893 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1894 If unsure, say 'N' here.
176 1895
177 If unsure, say N. !! 1896 if CPU_LOONGSON2F
>> 1897 config CPU_NOP_WORKAROUNDS
>> 1898 bool
178 1899
179 config XTENSA_FAKE_NMI !! 1900 config CPU_JUMP_WORKAROUNDS
180 bool "Treat PMM IRQ as NMI" !! 1901 bool
181 depends on XTENSA_VARIANT_HAVE_PERF_EV !! 1902
182 default n !! 1903 config CPU_LOONGSON2F_WORKAROUNDS
>> 1904 bool "Loongson 2F Workarounds"
>> 1905 default y
>> 1906 select CPU_NOP_WORKAROUNDS
>> 1907 select CPU_JUMP_WORKAROUNDS
183 help 1908 help
184 If PMM IRQ is the only IRQ at EXCM l !! 1909 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
185 treat it as NMI, which improves accu !! 1910 require workarounds. Without workarounds the system may hang
>> 1911 unexpectedly. For more information please refer to the gas
>> 1912 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1913
>> 1914 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1915 are needed. The workarounds have no significant side effect on them
>> 1916 but may decrease the performance of the system so this option should
>> 1917 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1918 systems.
186 1919
187 If there are other interrupts at or !! 1920 If unsure, please say Y.
188 but not above the EXCM level, PMM IR !! 1921 endif # CPU_LOONGSON2F
189 but only if these IRQs are not used. <<
190 saying that this is not safe, and a <<
191 actually fire. <<
192 1922
193 If unsure, say N. !! 1923 config SYS_SUPPORTS_ZBOOT
>> 1924 bool
>> 1925 select HAVE_KERNEL_GZIP
>> 1926 select HAVE_KERNEL_BZIP2
>> 1927 select HAVE_KERNEL_LZ4
>> 1928 select HAVE_KERNEL_LZMA
>> 1929 select HAVE_KERNEL_LZO
>> 1930 select HAVE_KERNEL_XZ
>> 1931 select HAVE_KERNEL_ZSTD
194 1932
195 config PFAULT !! 1933 config SYS_SUPPORTS_ZBOOT_UART16550
196 bool "Handle protection faults" if EXP !! 1934 bool
197 default y !! 1935 select SYS_SUPPORTS_ZBOOT
>> 1936
>> 1937 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1938 bool
>> 1939 select SYS_SUPPORTS_ZBOOT
>> 1940
>> 1941 config CPU_LOONGSON2EF
>> 1942 bool
>> 1943 select CPU_SUPPORTS_32BIT_KERNEL
>> 1944 select CPU_SUPPORTS_64BIT_KERNEL
>> 1945 select CPU_SUPPORTS_HIGHMEM
>> 1946 select CPU_SUPPORTS_HUGEPAGES
>> 1947 select ARCH_HAS_PHYS_TO_DMA
>> 1948
>> 1949 config CPU_LOONGSON32
>> 1950 bool
>> 1951 select CPU_MIPS32
>> 1952 select CPU_MIPSR2
>> 1953 select CPU_HAS_PREFETCH
>> 1954 select CPU_SUPPORTS_32BIT_KERNEL
>> 1955 select CPU_SUPPORTS_HIGHMEM
>> 1956 select CPU_SUPPORTS_CPUFREQ
>> 1957
>> 1958 config CPU_BMIPS32_3300
>> 1959 select SMP_UP if SMP
>> 1960 bool
>> 1961
>> 1962 config CPU_BMIPS4350
>> 1963 bool
>> 1964 select SYS_SUPPORTS_SMP
>> 1965 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1966
>> 1967 config CPU_BMIPS4380
>> 1968 bool
>> 1969 select MIPS_L1_CACHE_SHIFT_6
>> 1970 select SYS_SUPPORTS_SMP
>> 1971 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1972 select CPU_HAS_RIXI
>> 1973
>> 1974 config CPU_BMIPS5000
>> 1975 bool
>> 1976 select MIPS_CPU_SCACHE
>> 1977 select MIPS_L1_CACHE_SHIFT_7
>> 1978 select SYS_SUPPORTS_SMP
>> 1979 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1980 select CPU_HAS_RIXI
>> 1981
>> 1982 config SYS_HAS_CPU_LOONGSON64
>> 1983 bool
>> 1984 select CPU_SUPPORTS_CPUFREQ
>> 1985 select CPU_HAS_RIXI
>> 1986
>> 1987 config SYS_HAS_CPU_LOONGSON2E
>> 1988 bool
>> 1989
>> 1990 config SYS_HAS_CPU_LOONGSON2F
>> 1991 bool
>> 1992 select CPU_SUPPORTS_CPUFREQ
>> 1993 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1994
>> 1995 config SYS_HAS_CPU_LOONGSON1B
>> 1996 bool
>> 1997
>> 1998 config SYS_HAS_CPU_LOONGSON1C
>> 1999 bool
>> 2000
>> 2001 config SYS_HAS_CPU_MIPS32_R1
>> 2002 bool
>> 2003
>> 2004 config SYS_HAS_CPU_MIPS32_R2
>> 2005 bool
>> 2006
>> 2007 config SYS_HAS_CPU_MIPS32_R3_5
>> 2008 bool
>> 2009
>> 2010 config SYS_HAS_CPU_MIPS32_R5
>> 2011 bool
>> 2012 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2013
>> 2014 config SYS_HAS_CPU_MIPS32_R6
>> 2015 bool
>> 2016 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2017
>> 2018 config SYS_HAS_CPU_MIPS64_R1
>> 2019 bool
>> 2020
>> 2021 config SYS_HAS_CPU_MIPS64_R2
>> 2022 bool
>> 2023
>> 2024 config SYS_HAS_CPU_MIPS64_R6
>> 2025 bool
>> 2026 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2027
>> 2028 config SYS_HAS_CPU_P5600
>> 2029 bool
>> 2030 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2031
>> 2032 config SYS_HAS_CPU_R3000
>> 2033 bool
>> 2034
>> 2035 config SYS_HAS_CPU_TX39XX
>> 2036 bool
>> 2037
>> 2038 config SYS_HAS_CPU_VR41XX
>> 2039 bool
>> 2040
>> 2041 config SYS_HAS_CPU_R4300
>> 2042 bool
>> 2043
>> 2044 config SYS_HAS_CPU_R4X00
>> 2045 bool
>> 2046
>> 2047 config SYS_HAS_CPU_TX49XX
>> 2048 bool
>> 2049
>> 2050 config SYS_HAS_CPU_R5000
>> 2051 bool
>> 2052
>> 2053 config SYS_HAS_CPU_R5500
>> 2054 bool
>> 2055
>> 2056 config SYS_HAS_CPU_NEVADA
>> 2057 bool
>> 2058
>> 2059 config SYS_HAS_CPU_R10000
>> 2060 bool
>> 2061 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2062
>> 2063 config SYS_HAS_CPU_RM7000
>> 2064 bool
>> 2065
>> 2066 config SYS_HAS_CPU_SB1
>> 2067 bool
>> 2068
>> 2069 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 2070 bool
>> 2071
>> 2072 config SYS_HAS_CPU_BMIPS
>> 2073 bool
>> 2074
>> 2075 config SYS_HAS_CPU_BMIPS32_3300
>> 2076 bool
>> 2077 select SYS_HAS_CPU_BMIPS
>> 2078
>> 2079 config SYS_HAS_CPU_BMIPS4350
>> 2080 bool
>> 2081 select SYS_HAS_CPU_BMIPS
>> 2082
>> 2083 config SYS_HAS_CPU_BMIPS4380
>> 2084 bool
>> 2085 select SYS_HAS_CPU_BMIPS
>> 2086
>> 2087 config SYS_HAS_CPU_BMIPS5000
>> 2088 bool
>> 2089 select SYS_HAS_CPU_BMIPS
>> 2090 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 2091
>> 2092 config SYS_HAS_CPU_XLR
>> 2093 bool
>> 2094
>> 2095 config SYS_HAS_CPU_XLP
>> 2096 bool
>> 2097
>> 2098 #
>> 2099 # CPU may reorder R->R, R->W, W->R, W->W
>> 2100 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2101 #
>> 2102 config WEAK_ORDERING
>> 2103 bool
>> 2104
>> 2105 #
>> 2106 # CPU may reorder reads and writes beyond LL/SC
>> 2107 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 2108 #
>> 2109 config WEAK_REORDERING_BEYOND_LLSC
>> 2110 bool
>> 2111 endmenu
>> 2112
>> 2113 #
>> 2114 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2115 #
>> 2116 config CPU_MIPS32
>> 2117 bool
>> 2118 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 2119 CPU_MIPS32_R6 || CPU_P5600
>> 2120
>> 2121 config CPU_MIPS64
>> 2122 bool
>> 2123 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 2124 CPU_MIPS64_R6
>> 2125
>> 2126 #
>> 2127 # These indicate the revision of the architecture
>> 2128 #
>> 2129 config CPU_MIPSR1
>> 2130 bool
>> 2131 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 2132
>> 2133 config CPU_MIPSR2
>> 2134 bool
>> 2135 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2136 select CPU_HAS_RIXI
>> 2137 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2138 select MIPS_SPRAM
>> 2139
>> 2140 config CPU_MIPSR5
>> 2141 bool
>> 2142 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2143 select CPU_HAS_RIXI
>> 2144 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2145 select MIPS_SPRAM
>> 2146
>> 2147 config CPU_MIPSR6
>> 2148 bool
>> 2149 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2150 select CPU_HAS_RIXI
>> 2151 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2152 select HAVE_ARCH_BITREVERSE
>> 2153 select MIPS_ASID_BITS_VARIABLE
>> 2154 select MIPS_CRC_SUPPORT
>> 2155 select MIPS_SPRAM
>> 2156
>> 2157 config TARGET_ISA_REV
>> 2158 int
>> 2159 default 1 if CPU_MIPSR1
>> 2160 default 2 if CPU_MIPSR2
>> 2161 default 5 if CPU_MIPSR5
>> 2162 default 6 if CPU_MIPSR6
>> 2163 default 0
198 help 2164 help
199 Handle protection faults. MMU config !! 2165 Reflects the ISA revision being targeted by the kernel build. This
200 noMMU configurations may disable it !! 2166 is effectively the Kconfig equivalent of MIPS_ISA_REV.
201 generates protection faults or fault <<
202 2167
203 If unsure, say Y. !! 2168 config EVA
>> 2169 bool
>> 2170
>> 2171 config XPA
>> 2172 bool
204 2173
205 config XTENSA_UNALIGNED_USER !! 2174 config SYS_SUPPORTS_32BIT_KERNEL
206 bool "Unaligned memory access in user !! 2175 bool
>> 2176 config SYS_SUPPORTS_64BIT_KERNEL
>> 2177 bool
>> 2178 config CPU_SUPPORTS_32BIT_KERNEL
>> 2179 bool
>> 2180 config CPU_SUPPORTS_64BIT_KERNEL
>> 2181 bool
>> 2182 config CPU_SUPPORTS_CPUFREQ
>> 2183 bool
>> 2184 config CPU_SUPPORTS_ADDRWINCFG
>> 2185 bool
>> 2186 config CPU_SUPPORTS_HUGEPAGES
>> 2187 bool
>> 2188 depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
>> 2189 config MIPS_PGD_C0_CONTEXT
>> 2190 bool
>> 2191 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
>> 2192
>> 2193 #
>> 2194 # Set to y for ptrace access to watch registers.
>> 2195 #
>> 2196 config HARDWARE_WATCHPOINTS
>> 2197 bool
>> 2198 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
>> 2199
>> 2200 menu "Kernel type"
>> 2201
>> 2202 choice
>> 2203 prompt "Kernel code model"
207 help 2204 help
208 The Xtensa architecture currently do !! 2205 You should only select this option if you have a workload that
209 memory accesses in hardware but thro !! 2206 actually benefits from 64-bit processing or if your machine has
210 Per default, unaligned memory access !! 2207 large memory. You will only be presented a single option in this
>> 2208 menu if your system does not support both 32-bit and 64-bit kernels.
211 2209
212 Say Y here to enable unaligned memor !! 2210 config 32BIT
>> 2211 bool "32-bit kernel"
>> 2212 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2213 select TRAD_SIGNALS
>> 2214 help
>> 2215 Select this option if you want to build a 32-bit kernel.
213 2216
214 config XTENSA_LOAD_STORE !! 2217 config 64BIT
215 bool "Load/store exception handler for !! 2218 bool "64-bit kernel"
>> 2219 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
216 help 2220 help
217 The Xtensa architecture only allows !! 2221 Select this option if you want to build a 64-bit kernel.
218 instruction bus with l32r and l32i i <<
219 instructions raise an exception with <<
220 This makes it hard to use some confi <<
221 literals in FLASH memory attached to <<
222 2222
223 Say Y here to enable exception handl !! 2223 endchoice
224 byte and 2-byte access to memory att <<
225 2224
226 config HAVE_SMP !! 2225 config KVM_GUEST
227 bool "System Supports SMP (MX)" !! 2226 bool "KVM Guest Kernel"
228 depends on XTENSA_VARIANT_CUSTOM !! 2227 depends on CPU_MIPS32_R2
229 select XTENSA_MX !! 2228 depends on !64BIT && BROKEN_ON_SMP
>> 2229 help
>> 2230 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2231 mode.
>> 2232
>> 2233 config KVM_GUEST_TIMER_FREQ
>> 2234 int "Count/Compare Timer Frequency (MHz)"
>> 2235 depends on KVM_GUEST
>> 2236 default 100
230 help 2237 help
231 This option is used to indicate that !! 2238 Set this to non-zero if building a guest kernel for KVM to skip RTC
232 supports Multiprocessing. Multiproce !! 2239 emulation when determining guest CPU Frequency. Instead, the guest's
233 the CPU core definition and currentl !! 2240 timer frequency is specified directly.
>> 2241
>> 2242 config MIPS_VA_BITS_48
>> 2243 bool "48 bits virtual memory"
>> 2244 depends on 64BIT
>> 2245 help
>> 2246 Support a maximum at least 48 bits of application virtual
>> 2247 memory. Default is 40 bits or less, depending on the CPU.
>> 2248 For page sizes 16k and above, this option results in a small
>> 2249 memory overhead for page tables. For 4k page size, a fourth
>> 2250 level of page tables is added which imposes both a memory
>> 2251 overhead as well as slower TLB fault handling.
234 2252
235 Multiprocessor support is implemente !! 2253 If unsure, say N.
236 interrupt controllers. <<
237 2254
238 The MX interrupt distributer adds In !! 2255 choice
239 and causes the IRQ numbers to be inc !! 2256 prompt "Kernel page size"
240 like the open cores ethernet driver !! 2257 default PAGE_SIZE_4KB
241 2258
242 You still have to select "Enable SMP !! 2259 config PAGE_SIZE_4KB
>> 2260 bool "4kB"
>> 2261 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2262 help
>> 2263 This option select the standard 4kB Linux page size. On some
>> 2264 R3000-family processors this is the only available page size. Using
>> 2265 4kB page size will minimize memory consumption and is therefore
>> 2266 recommended for low memory systems.
>> 2267
>> 2268 config PAGE_SIZE_8KB
>> 2269 bool "8kB"
>> 2270 depends on CPU_CAVIUM_OCTEON
>> 2271 depends on !MIPS_VA_BITS_48
>> 2272 help
>> 2273 Using 8kB page size will result in higher performance kernel at
>> 2274 the price of higher memory consumption. This option is available
>> 2275 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2276 distribution to support this.
>> 2277
>> 2278 config PAGE_SIZE_16KB
>> 2279 bool "16kB"
>> 2280 depends on !CPU_R3000 && !CPU_TX39XX
>> 2281 help
>> 2282 Using 16kB page size will result in higher performance kernel at
>> 2283 the price of higher memory consumption. This option is available on
>> 2284 all non-R3000 family processors. Note that you will need a suitable
>> 2285 Linux distribution to support this.
>> 2286
>> 2287 config PAGE_SIZE_32KB
>> 2288 bool "32kB"
>> 2289 depends on CPU_CAVIUM_OCTEON
>> 2290 depends on !MIPS_VA_BITS_48
>> 2291 help
>> 2292 Using 32kB page size will result in higher performance kernel at
>> 2293 the price of higher memory consumption. This option is available
>> 2294 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2295 distribution to support this.
>> 2296
>> 2297 config PAGE_SIZE_64KB
>> 2298 bool "64kB"
>> 2299 depends on !CPU_R3000 && !CPU_TX39XX
>> 2300 help
>> 2301 Using 64kB page size will result in higher performance kernel at
>> 2302 the price of higher memory consumption. This option is available on
>> 2303 all non-R3000 family processor. Not that at the time of this
>> 2304 writing this option is still high experimental.
243 2305
244 config SMP !! 2306 endchoice
245 bool "Enable Symmetric multi-processin <<
246 depends on HAVE_SMP <<
247 select GENERIC_SMP_IDLE_THREAD <<
248 help <<
249 Enabled SMP Software; allows more th <<
250 to be activated during startup. <<
251 2307
252 config NR_CPUS !! 2308 config FORCE_MAX_ZONEORDER
253 depends on SMP !! 2309 int "Maximum zone order"
254 int "Maximum number of CPUs (2-32)" !! 2310 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
255 range 2 32 !! 2311 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
256 default "4" !! 2312 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2313 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2314 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2315 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2316 range 0 64
>> 2317 default "11"
>> 2318 help
>> 2319 The kernel memory allocator divides physically contiguous memory
>> 2320 blocks into "zones", where each zone is a power of two number of
>> 2321 pages. This option selects the largest power of two that the kernel
>> 2322 keeps in the memory allocator. If you need to allocate very large
>> 2323 blocks of physically contiguous memory, then you may need to
>> 2324 increase this value.
257 2325
258 config HOTPLUG_CPU !! 2326 This config option is actually maximum order plus one. For example,
259 bool "Enable CPU hotplug support" !! 2327 a value of 11 means that the largest free memory block is 2^10 pages.
260 depends on SMP !! 2328
>> 2329 The page size is not necessarily 4KB. Keep this in mind
>> 2330 when choosing a value for this option.
>> 2331
>> 2332 config BOARD_SCACHE
>> 2333 bool
>> 2334
>> 2335 config IP22_CPU_SCACHE
>> 2336 bool
>> 2337 select BOARD_SCACHE
>> 2338
>> 2339 #
>> 2340 # Support for a MIPS32 / MIPS64 style S-caches
>> 2341 #
>> 2342 config MIPS_CPU_SCACHE
>> 2343 bool
>> 2344 select BOARD_SCACHE
>> 2345
>> 2346 config R5000_CPU_SCACHE
>> 2347 bool
>> 2348 select BOARD_SCACHE
>> 2349
>> 2350 config RM7000_CPU_SCACHE
>> 2351 bool
>> 2352 select BOARD_SCACHE
>> 2353
>> 2354 config SIBYTE_DMA_PAGEOPS
>> 2355 bool "Use DMA to clear/copy pages"
>> 2356 depends on CPU_SB1
261 help 2357 help
262 Say Y here to allow turning CPUs off !! 2358 Instead of using the CPU to zero and copy pages, use a Data Mover
263 controlled through /sys/devices/syst !! 2359 channel. These DMA channels are otherwise unused by the standard
>> 2360 SiByte Linux port. Seems to give a small performance benefit.
264 2361
265 Say N if you want to disable CPU hot !! 2362 config CPU_HAS_PREFETCH
>> 2363 bool
>> 2364
>> 2365 config CPU_GENERIC_DUMP_TLB
>> 2366 bool
>> 2367 default y if !(CPU_R3000 || CPU_TX39XX)
266 2368
267 config SECONDARY_RESET_VECTOR !! 2369 config MIPS_FP_SUPPORT
268 bool "Secondary cores use alternative !! 2370 bool "Floating Point support" if EXPERT
269 default y 2371 default y
270 depends on HAVE_SMP <<
271 help 2372 help
272 Secondary cores may be configured to !! 2373 Select y to include support for floating point in the kernel
273 or all cores may use primary reset v !! 2374 including initialization of FPU hardware, FP context save & restore
274 Say Y here to supply handler for the !! 2375 and emulation of an FPU where necessary. Without this support any
>> 2376 userland program attempting to use floating point instructions will
>> 2377 receive a SIGILL.
>> 2378
>> 2379 If you know that your userland will not attempt to use floating point
>> 2380 instructions then you can say n here to shrink the kernel a little.
>> 2381
>> 2382 If unsure, say y.
>> 2383
>> 2384 config CPU_R2300_FPU
>> 2385 bool
>> 2386 depends on MIPS_FP_SUPPORT
>> 2387 default y if CPU_R3000 || CPU_TX39XX
>> 2388
>> 2389 config CPU_R3K_TLB
>> 2390 bool
>> 2391
>> 2392 config CPU_R4K_FPU
>> 2393 bool
>> 2394 depends on MIPS_FP_SUPPORT
>> 2395 default y if !CPU_R2300_FPU
>> 2396
>> 2397 config CPU_R4K_CACHE_TLB
>> 2398 bool
>> 2399 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2400
>> 2401 config MIPS_MT_SMP
>> 2402 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2403 default y
>> 2404 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2405 select CPU_MIPSR2_IRQ_VI
>> 2406 select CPU_MIPSR2_IRQ_EI
>> 2407 select SYNC_R4K
>> 2408 select MIPS_MT
>> 2409 select SMP
>> 2410 select SMP_UP
>> 2411 select SYS_SUPPORTS_SMP
>> 2412 select SYS_SUPPORTS_SCHED_SMT
>> 2413 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2414 help
>> 2415 This is a kernel model which is known as SMVP. This is supported
>> 2416 on cores with the MT ASE and uses the available VPEs to implement
>> 2417 virtual processors which supports SMP. This is equivalent to the
>> 2418 Intel Hyperthreading feature. For further information go to
>> 2419 <http://www.imgtec.com/mips/mips-multithreading.asp>.
275 2420
276 config FAST_SYSCALL_XTENSA !! 2421 config MIPS_MT
277 bool "Enable fast atomic syscalls" !! 2422 bool
>> 2423
>> 2424 config SCHED_SMT
>> 2425 bool "SMT (multithreading) scheduler support"
>> 2426 depends on SYS_SUPPORTS_SCHED_SMT
278 default n 2427 default n
279 help 2428 help
280 fast_syscall_xtensa is a syscall tha !! 2429 SMT scheduler support improves the CPU scheduler's decision making
281 on UP kernel when processor has no s !! 2430 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2431 increased overhead in some places. If unsure say N here.
282 2432
283 This syscall is deprecated. It may h !! 2433 config SYS_SUPPORTS_SCHED_SMT
284 invalid arguments. It is provided on !! 2434 bool
285 Only enable it if your userspace sof <<
286 2435
287 If unsure, say N. !! 2436 config SYS_SUPPORTS_MULTITHREADING
>> 2437 bool
288 2438
289 config FAST_SYSCALL_SPILL_REGISTERS !! 2439 config MIPS_MT_FPAFF
290 bool "Enable spill registers syscall" !! 2440 bool "Dynamic FPU affinity for FP-intensive threads"
291 default n !! 2441 default y
>> 2442 depends on MIPS_MT_SMP
>> 2443
>> 2444 config MIPSR2_TO_R6_EMULATOR
>> 2445 bool "MIPS R2-to-R6 emulator"
>> 2446 depends on CPU_MIPSR6
>> 2447 depends on MIPS_FP_SUPPORT
>> 2448 default y
292 help 2449 help
293 fast_syscall_spill_registers is a sy !! 2450 Choose this option if you want to run non-R6 MIPS userland code.
294 register windows of a calling usersp !! 2451 Even if you say 'Y' here, the emulator will still be disabled by
>> 2452 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2453 The only reason this is a build-time option is to save ~14K from the
>> 2454 final kernel image.
295 2455
296 This syscall is deprecated. It may h !! 2456 config SYS_SUPPORTS_VPE_LOADER
297 invalid arguments. It is provided on !! 2457 bool
298 Only enable it if your userspace sof !! 2458 depends on SYS_SUPPORTS_MULTITHREADING
>> 2459 help
>> 2460 Indicates that the platform supports the VPE loader, and provides
>> 2461 physical_memsize.
299 2462
300 If unsure, say N. !! 2463 config MIPS_VPE_LOADER
>> 2464 bool "VPE loader support."
>> 2465 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2466 select CPU_MIPSR2_IRQ_VI
>> 2467 select CPU_MIPSR2_IRQ_EI
>> 2468 select MIPS_MT
>> 2469 help
>> 2470 Includes a loader for loading an elf relocatable object
>> 2471 onto another VPE and running it.
301 2472
302 choice !! 2473 config MIPS_VPE_LOADER_CMP
303 prompt "Kernel ABI" !! 2474 bool
304 default KERNEL_ABI_DEFAULT !! 2475 default "y"
>> 2476 depends on MIPS_VPE_LOADER && MIPS_CMP
>> 2477
>> 2478 config MIPS_VPE_LOADER_MT
>> 2479 bool
>> 2480 default "y"
>> 2481 depends on MIPS_VPE_LOADER && !MIPS_CMP
>> 2482
>> 2483 config MIPS_VPE_LOADER_TOM
>> 2484 bool "Load VPE program into memory hidden from linux"
>> 2485 depends on MIPS_VPE_LOADER
>> 2486 default y
305 help 2487 help
306 Select ABI for the kernel code. This !! 2488 The loader can use memory that is present but has been hidden from
307 supported userspace ABI and any comb !! 2489 Linux using the kernel command line option "mem=xxMB". It's up to
308 kernel/userspace ABI is possible and !! 2490 you to ensure the amount you put in the option and the space your
309 !! 2491 program requires is less or equal to the amount physically present.
310 In case both kernel and userspace su !! 2492
311 all register windows support code wi !! 2493 config MIPS_VPE_APSP_API
312 build. !! 2494 bool "Enable support for AP/SP API (RTLX)"
313 !! 2495 depends on MIPS_VPE_LOADER
314 If unsure, choose the default ABI. <<
315 <<
316 config KERNEL_ABI_DEFAULT <<
317 bool "Default ABI" <<
318 help <<
319 Select this option to compile kernel <<
320 selected for the toolchain. <<
321 Normally cores with windowed registe <<
322 cores without it use call0 ABI. <<
323 <<
324 config KERNEL_ABI_CALL0 <<
325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI <<
326 help <<
327 Select this option to compile kernel <<
328 toolchain that defaults to windowed <<
329 When this option is not selected the <<
330 be used for the kernel code. <<
331 2496
332 endchoice !! 2497 config MIPS_VPE_APSP_API_CMP
>> 2498 bool
>> 2499 default "y"
>> 2500 depends on MIPS_VPE_APSP_API && MIPS_CMP
333 2501
334 config USER_ABI_CALL0 !! 2502 config MIPS_VPE_APSP_API_MT
335 bool 2503 bool
>> 2504 default "y"
>> 2505 depends on MIPS_VPE_APSP_API && !MIPS_CMP
336 2506
337 choice !! 2507 config MIPS_CMP
338 prompt "Userspace ABI" !! 2508 bool "MIPS CMP framework support (DEPRECATED)"
339 default USER_ABI_DEFAULT !! 2509 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2510 select SMP
>> 2511 select SYNC_R4K
>> 2512 select SYS_SUPPORTS_SMP
>> 2513 select WEAK_ORDERING
>> 2514 default n
340 help 2515 help
341 Select supported userspace ABI. !! 2516 Select this if you are using a bootloader which implements the "CMP
>> 2517 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2518 its ability to start secondary CPUs.
>> 2519
>> 2520 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2521 instead of this.
>> 2522
>> 2523 config MIPS_CPS
>> 2524 bool "MIPS Coherent Processing System support"
>> 2525 depends on SYS_SUPPORTS_MIPS_CPS
>> 2526 select MIPS_CM
>> 2527 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2528 select SMP
>> 2529 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2530 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2531 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2532 select SYS_SUPPORTS_SMP
>> 2533 select WEAK_ORDERING
>> 2534 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2535 help
>> 2536 Select this if you wish to run an SMP kernel across multiple cores
>> 2537 within a MIPS Coherent Processing System. When this option is
>> 2538 enabled the kernel will probe for other cores and boot them with
>> 2539 no external assistance. It is safe to enable this when hardware
>> 2540 support is unavailable.
>> 2541
>> 2542 config MIPS_CPS_PM
>> 2543 depends on MIPS_CPS
>> 2544 bool
342 2545
343 If unsure, choose the default ABI. !! 2546 config MIPS_CM
>> 2547 bool
>> 2548 select MIPS_CPC
>> 2549
>> 2550 config MIPS_CPC
>> 2551 bool
>> 2552
>> 2553 config SB1_PASS_2_WORKAROUNDS
>> 2554 bool
>> 2555 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2556 default y
>> 2557
>> 2558 config SB1_PASS_2_1_WORKAROUNDS
>> 2559 bool
>> 2560 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2561 default y
>> 2562
>> 2563 choice
>> 2564 prompt "SmartMIPS or microMIPS ASE support"
344 2565
345 config USER_ABI_DEFAULT !! 2566 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
346 bool "Default ABI only" !! 2567 bool "None"
347 help 2568 help
348 Assume default userspace ABI. For XE !! 2569 Select this if you want neither microMIPS nor SmartMIPS support
349 call0 ABI binaries may be run on suc <<
350 will not work correctly for them. <<
351 2570
352 config USER_ABI_CALL0_ONLY !! 2571 config CPU_HAS_SMARTMIPS
353 bool "Call0 ABI only" !! 2572 depends on SYS_SUPPORTS_SMARTMIPS
354 select USER_ABI_CALL0 !! 2573 bool "SmartMIPS"
>> 2574 help
>> 2575 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2576 increased security at both hardware and software level for
>> 2577 smartcards. Enabling this option will allow proper use of the
>> 2578 SmartMIPS instructions by Linux applications. However a kernel with
>> 2579 this option will not work on a MIPS core without SmartMIPS core. If
>> 2580 you don't know you probably don't have SmartMIPS and should say N
>> 2581 here.
>> 2582
>> 2583 config CPU_MICROMIPS
>> 2584 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2585 bool "microMIPS"
355 help 2586 help
356 Select this option to support only c !! 2587 When this option is enabled the kernel will be built using the
357 Windowed ABI binaries will crash wit !! 2588 microMIPS ISA
358 an illegal instruction exception on <<
359 2589
360 Choose this option if you're plannin !! 2590 endchoice
361 built with call0 ABI. <<
362 2591
363 config USER_ABI_CALL0_PROBE !! 2592 config CPU_HAS_MSA
364 bool "Support both windowed and call0 !! 2593 bool "Support for the MIPS SIMD Architecture"
365 select USER_ABI_CALL0 !! 2594 depends on CPU_SUPPORTS_MSA
366 help !! 2595 depends on MIPS_FP_SUPPORT
367 Select this option to support both w !! 2596 depends on 64BIT || MIPS_O32_FP64_SUPPORT
368 ABIs. When enabled all processes are !! 2597 help
369 and a fast user exception handler fo !! 2598 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
370 used to turn on PS.WOE bit on the fi !! 2599 and a set of SIMD instructions to operate on them. When this option
371 the userspace. !! 2600 is enabled the kernel will support allocating & switching MSA
>> 2601 vector register contexts. If you know that your kernel will only be
>> 2602 running on CPUs which do not support MSA or that your userland will
>> 2603 not be making use of it then you may wish to say N here to reduce
>> 2604 the size & complexity of your kernel.
372 2605
373 This option should be enabled for th !! 2606 If unsure, say Y.
374 both call0 and windowed ABIs in user <<
375 2607
376 Note that Xtensa ISA does not guaran !! 2608 config CPU_HAS_WB
377 raise an illegal instruction excepti !! 2609 bool
378 PS.WOE is disabled, check whether th <<
379 2610
380 endchoice !! 2611 config XKS01
>> 2612 bool
381 2613
382 endmenu !! 2614 config CPU_HAS_DIEI
>> 2615 depends on !CPU_DIEI_BROKEN
>> 2616 bool
383 2617
384 config XTENSA_CALIBRATE_CCOUNT !! 2618 config CPU_DIEI_BROKEN
385 def_bool n !! 2619 bool
>> 2620
>> 2621 config CPU_HAS_RIXI
>> 2622 bool
>> 2623
>> 2624 config CPU_NO_LOAD_STORE_LR
>> 2625 bool
386 help 2626 help
387 On some platforms (XT2000, for examp !! 2627 CPU lacks support for unaligned load and store instructions:
388 vary. The frequency can be determin !! 2628 LWL, LWR, SWL, SWR (Load/store word left/right).
389 against a well known, fixed frequenc !! 2629 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2630 systems).
>> 2631
>> 2632 #
>> 2633 # Vectored interrupt mode is an R2 feature
>> 2634 #
>> 2635 config CPU_MIPSR2_IRQ_VI
>> 2636 bool
390 2637
391 config SERIAL_CONSOLE !! 2638 #
392 def_bool n !! 2639 # Extended interrupt mode is an R2 feature
>> 2640 #
>> 2641 config CPU_MIPSR2_IRQ_EI
>> 2642 bool
393 2643
394 config PLATFORM_HAVE_XIP !! 2644 config CPU_HAS_SYNC
395 def_bool n !! 2645 bool
>> 2646 depends on !CPU_R3000
>> 2647 default y
396 2648
397 menu "Platform options" !! 2649 #
>> 2650 # CPU non-features
>> 2651 #
>> 2652 config CPU_DADDI_WORKAROUNDS
>> 2653 bool
398 2654
399 choice !! 2655 config CPU_R4000_WORKAROUNDS
400 prompt "Xtensa System Type" !! 2656 bool
401 default XTENSA_PLATFORM_ISS !! 2657 select CPU_R4400_WORKAROUNDS
402 2658
403 config XTENSA_PLATFORM_ISS !! 2659 config CPU_R4400_WORKAROUNDS
404 bool "ISS" !! 2660 bool
405 select XTENSA_CALIBRATE_CCOUNT <<
406 select SERIAL_CONSOLE <<
407 help <<
408 ISS is an acronym for Tensilica's In <<
409 <<
410 config XTENSA_PLATFORM_XT2000 <<
411 bool "XT2000" <<
412 help <<
413 XT2000 is the name of Tensilica's fe <<
414 This hardware is capable of running <<
415 <<
416 config XTENSA_PLATFORM_XTFPGA <<
417 bool "XTFPGA" <<
418 select ETHOC if ETHERNET <<
419 select PLATFORM_WANT_DEFAULT_MEM if !M <<
420 select SERIAL_CONSOLE <<
421 select XTENSA_CALIBRATE_CCOUNT <<
422 select PLATFORM_HAVE_XIP <<
423 help <<
424 XTFPGA is the name of Tensilica boar <<
425 This hardware is capable of running <<
426 2661
427 endchoice !! 2662 config CPU_R4X00_BUGS64
>> 2663 bool
>> 2664 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
428 2665
429 config PLATFORM_NR_IRQS !! 2666 config MIPS_ASID_SHIFT
430 int 2667 int
431 default 3 if XTENSA_PLATFORM_XT2000 !! 2668 default 6 if CPU_R3000 || CPU_TX39XX
432 default 0 2669 default 0
433 2670
434 config XTENSA_CPU_CLOCK !! 2671 config MIPS_ASID_BITS
435 int "CPU clock rate [MHz]" !! 2672 int
436 depends on !XTENSA_CALIBRATE_CCOUNT !! 2673 default 0 if MIPS_ASID_BITS_VARIABLE
437 default 16 !! 2674 default 6 if CPU_R3000 || CPU_TX39XX
>> 2675 default 8
438 2676
439 config GENERIC_CALIBRATE_DELAY !! 2677 config MIPS_ASID_BITS_VARIABLE
440 bool "Auto calibration of the BogoMIPS !! 2678 bool
441 help <<
442 The BogoMIPS value can easily be der <<
443 2679
444 config CMDLINE_BOOL !! 2680 config MIPS_CRC_SUPPORT
445 bool "Default bootloader kernel argume !! 2681 bool
446 2682
447 config CMDLINE !! 2683 # R4600 erratum. Due to the lack of errata information the exact
448 string "Initial kernel command string" !! 2684 # technical details aren't known. I've experimentally found that disabling
449 depends on CMDLINE_BOOL !! 2685 # interrupts during indexed I-cache flushes seems to be sufficient to deal
450 default "console=ttyS0,38400 root=/dev !! 2686 # with the issue.
451 help !! 2687 config WAR_R4600_V1_INDEX_ICACHEOP
452 On some architectures (EBSA110 and C !! 2688 bool
453 for the boot loader to pass argument <<
454 architectures, you should supply som <<
455 time by entering them here. As a min <<
456 memory size and the root device (e.g <<
457 2689
458 config USE_OF !! 2690 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
459 bool "Flattened Device Tree support" !! 2691 #
460 select OF !! 2692 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
461 select OF_EARLY_FLATTREE !! 2693 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
462 help !! 2694 # executed if there is no other dcache activity. If the dcache is
463 Include support for flattened device !! 2695 # accessed for another instruction immediately preceding when these
>> 2696 # cache instructions are executing, it is possible that the dcache
>> 2697 # tag match outputs used by these cache instructions will be
>> 2698 # incorrect. These cache instructions should be preceded by at least
>> 2699 # four instructions that are not any kind of load or store
>> 2700 # instruction.
>> 2701 #
>> 2702 # This is not allowed: lw
>> 2703 # nop
>> 2704 # nop
>> 2705 # nop
>> 2706 # cache Hit_Writeback_Invalidate_D
>> 2707 #
>> 2708 # This is allowed: lw
>> 2709 # nop
>> 2710 # nop
>> 2711 # nop
>> 2712 # nop
>> 2713 # cache Hit_Writeback_Invalidate_D
>> 2714 config WAR_R4600_V1_HIT_CACHEOP
>> 2715 bool
464 2716
465 config BUILTIN_DTB_SOURCE !! 2717 # Writeback and invalidate the primary cache dcache before DMA.
466 string "DTB to build into the kernel i !! 2718 #
467 depends on OF !! 2719 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2720 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2721 # operate correctly if the internal data cache refill buffer is empty. These
>> 2722 # CACHE instructions should be separated from any potential data cache miss
>> 2723 # by a load instruction to an uncached address to empty the response buffer."
>> 2724 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2725 # in .pdf format.)
>> 2726 config WAR_R4600_V2_HIT_CACHEOP
>> 2727 bool
468 2728
469 config PARSE_BOOTPARAM !! 2729 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
470 bool "Parse bootparam block" !! 2730 # the line which this instruction itself exists, the following
471 default y !! 2731 # operation is not guaranteed."
472 help !! 2732 #
473 Parse parameters passed to the kerne !! 2733 # Workaround: do two phase flushing for Index_Invalidate_I
474 be disabled if the kernel is known t !! 2734 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2735 bool
475 2736
476 If unsure, say Y. !! 2737 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2738 # opposes it being called that) where invalid instructions in the same
>> 2739 # I-cache line worth of instructions being fetched may case spurious
>> 2740 # exceptions.
>> 2741 config WAR_ICACHE_REFILLS
>> 2742 bool
477 2743
478 choice !! 2744 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
479 prompt "Semihosting interface" !! 2745 # may cause ll / sc and lld / scd sequences to execute non-atomically.
480 default XTENSA_SIMCALL_ISS !! 2746 config WAR_R10000_LLSC
481 depends on XTENSA_PLATFORM_ISS !! 2747 bool
482 help <<
483 Choose semihosting interface that wi <<
484 block device and networking. <<
485 2748
486 config XTENSA_SIMCALL_ISS !! 2749 # 34K core erratum: "Problems Executing the TLBR Instruction"
487 bool "simcall" !! 2750 config WAR_MIPS34K_MISSED_ITLB
488 help !! 2751 bool
489 Use simcall instruction. simcall is !! 2752
490 it does nothing on hardware. !! 2753 #
>> 2754 # - Highmem only makes sense for the 32-bit kernel.
>> 2755 # - The current highmem code will only work properly on physically indexed
>> 2756 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2757 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2758 # moment we protect the user and offer the highmem option only on machines
>> 2759 # where it's known to be safe. This will not offer highmem on a few systems
>> 2760 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2761 # indexed CPUs but we're playing safe.
>> 2762 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2763 # know they might have memory configurations that could make use of highmem
>> 2764 # support.
>> 2765 #
>> 2766 config HIGHMEM
>> 2767 bool "High Memory Support"
>> 2768 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2769 select KMAP_LOCAL
>> 2770
>> 2771 config CPU_SUPPORTS_HIGHMEM
>> 2772 bool
>> 2773
>> 2774 config SYS_SUPPORTS_HIGHMEM
>> 2775 bool
>> 2776
>> 2777 config SYS_SUPPORTS_SMARTMIPS
>> 2778 bool
>> 2779
>> 2780 config SYS_SUPPORTS_MICROMIPS
>> 2781 bool
491 2782
492 config XTENSA_SIMCALL_GDBIO !! 2783 config SYS_SUPPORTS_MIPS16
493 bool "GDBIO" !! 2784 bool
494 help 2785 help
495 Use break instruction. It is availab !! 2786 This option must be set if a kernel might be executed on a MIPS16-
496 is attached to it via JTAG. !! 2787 enabled CPU even if MIPS16 is not actually being used. In other
>> 2788 words, it makes the kernel MIPS16-tolerant.
497 2789
498 endchoice !! 2790 config CPU_SUPPORTS_MSA
>> 2791 bool
499 2792
500 config BLK_DEV_SIMDISK !! 2793 config ARCH_FLATMEM_ENABLE
501 tristate "Host file-based simulated bl !! 2794 def_bool y
502 default n !! 2795 depends on !NUMA && !CPU_LOONGSON2EF
503 depends on XTENSA_PLATFORM_ISS && BLOC !! 2796
>> 2797 config ARCH_SPARSEMEM_ENABLE
>> 2798 bool
>> 2799 select SPARSEMEM_STATIC if !SGI_IP27
>> 2800
>> 2801 config NUMA
>> 2802 bool "NUMA Support"
>> 2803 depends on SYS_SUPPORTS_NUMA
>> 2804 select SMP
>> 2805 help
>> 2806 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2807 Access). This option improves performance on systems with more
>> 2808 than two nodes; on two node systems it is generally better to
>> 2809 leave it disabled; on single node systems leave this option
>> 2810 disabled.
>> 2811
>> 2812 config SYS_SUPPORTS_NUMA
>> 2813 bool
>> 2814
>> 2815 config HAVE_SETUP_PER_CPU_AREA
>> 2816 def_bool y
>> 2817 depends on NUMA
>> 2818
>> 2819 config NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2820 def_bool y
>> 2821 depends on NUMA
>> 2822
>> 2823 config RELOCATABLE
>> 2824 bool "Relocatable kernel"
>> 2825 depends on SYS_SUPPORTS_RELOCATABLE
>> 2826 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2827 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2828 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2829 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2830 CPU_LOONGSON64
>> 2831 help
>> 2832 This builds a kernel image that retains relocation information
>> 2833 so it can be loaded someplace besides the default 1MB.
>> 2834 The relocations make the kernel binary about 15% larger,
>> 2835 but are discarded at runtime
>> 2836
>> 2837 config RELOCATION_TABLE_SIZE
>> 2838 hex "Relocation table size"
>> 2839 depends on RELOCATABLE
>> 2840 range 0x0 0x01000000
>> 2841 default "0x00200000" if CPU_LOONGSON64
>> 2842 default "0x00100000"
>> 2843 help
>> 2844 A table of relocation data will be appended to the kernel binary
>> 2845 and parsed at boot to fix up the relocated kernel.
>> 2846
>> 2847 This option allows the amount of space reserved for the table to be
>> 2848 adjusted, although the default of 1Mb should be ok in most cases.
>> 2849
>> 2850 The build will fail and a valid size suggested if this is too small.
>> 2851
>> 2852 If unsure, leave at the default value.
>> 2853
>> 2854 config RANDOMIZE_BASE
>> 2855 bool "Randomize the address of the kernel image"
>> 2856 depends on RELOCATABLE
>> 2857 help
>> 2858 Randomizes the physical and virtual address at which the
>> 2859 kernel image is loaded, as a security feature that
>> 2860 deters exploit attempts relying on knowledge of the location
>> 2861 of kernel internals.
>> 2862
>> 2863 Entropy is generated using any coprocessor 0 registers available.
>> 2864
>> 2865 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2866
>> 2867 If unsure, say N.
>> 2868
>> 2869 config RANDOMIZE_BASE_MAX_OFFSET
>> 2870 hex "Maximum kASLR offset" if EXPERT
>> 2871 depends on RANDOMIZE_BASE
>> 2872 range 0x0 0x40000000 if EVA || 64BIT
>> 2873 range 0x0 0x08000000
>> 2874 default "0x01000000"
>> 2875 help
>> 2876 When kASLR is active, this provides the maximum offset that will
>> 2877 be applied to the kernel image. It should be set according to the
>> 2878 amount of physical RAM available in the target system minus
>> 2879 PHYSICAL_START and must be a power of 2.
>> 2880
>> 2881 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2882 EVA or 64-bit. The default is 16Mb.
>> 2883
>> 2884 config NODES_SHIFT
>> 2885 int
>> 2886 default "6"
>> 2887 depends on NEED_MULTIPLE_NODES
>> 2888
>> 2889 config HW_PERF_EVENTS
>> 2890 bool "Enable hardware performance counter support for perf events"
>> 2891 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
>> 2892 default y
504 help 2893 help
505 Create block devices that map to fil !! 2894 Enable hardware performance counter support for perf events. If
506 Device binding to host file may be c !! 2895 disabled, perf events will use software events only.
507 interface provided the device is not !! 2896
508 !! 2897 config DMI
509 config BLK_DEV_SIMDISK_COUNT !! 2898 bool "Enable DMI scanning"
510 int "Number of host file-based simulat !! 2899 depends on MACH_LOONGSON64
511 range 1 10 !! 2900 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
512 depends on BLK_DEV_SIMDISK !! 2901 default y
513 default 2 <<
514 help 2902 help
515 This is the default minimal number o !! 2903 Enabled scanning of DMI to identify machine quirks. Say Y
516 Kernel/module parameter 'simdisk_cou !! 2904 here unless you have verified that your setup is not
517 value at runtime. More file names (b !! 2905 affected by entries in the DMI blacklist. Required by PNP
518 specified as parameters, simdisk_cou !! 2906 BIOS code.
519 !! 2907
520 config SIMDISK0_FILENAME !! 2908 config SMP
521 string "Host filename for the first si !! 2909 bool "Multi-Processing support"
522 depends on BLK_DEV_SIMDISK = y !! 2910 depends on SYS_SUPPORTS_SMP
523 default "" <<
524 help <<
525 Attach a first simdisk to a host fil <<
526 contains a root file system. <<
527 <<
528 config SIMDISK1_FILENAME <<
529 string "Host filename for the second s <<
530 depends on BLK_DEV_SIMDISK = y && BLK_ <<
531 default "" <<
532 help <<
533 Another simulated disk in a host fil <<
534 storage. <<
535 <<
536 config XTFPGA_LCD <<
537 bool "Enable XTFPGA LCD driver" <<
538 depends on XTENSA_PLATFORM_XTFPGA <<
539 default n <<
540 help 2911 help
541 There's a 2x16 LCD on most of XTFPGA !! 2912 This enables support for systems with more than one CPU. If you have
542 progress messages there during bootu !! 2913 a system with only one CPU, say N. If you have a system with more
543 during board bringup. !! 2914 than one CPU, say Y.
>> 2915
>> 2916 If you say N here, the kernel will run on uni- and multiprocessor
>> 2917 machines, but will use only one CPU of a multiprocessor machine. If
>> 2918 you say Y here, the kernel will run on many, but not all,
>> 2919 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2920 will run faster if you say N here.
544 2921
545 If unsure, say N. !! 2922 People using multiprocessor machines who say Y here should also say
>> 2923 Y to "Enhanced Real Time Clock Support", below.
546 2924
547 config XTFPGA_LCD_BASE_ADDR !! 2925 See also the SMP-HOWTO available at
548 hex "XTFPGA LCD base address" !! 2926 <https://www.tldp.org/docs.html#howto>.
549 depends on XTFPGA_LCD !! 2927
550 default "0x0d0c0000" !! 2928 If you don't know what to do here, say N.
551 help !! 2929
552 Base address of the LCD controller i !! 2930 config HOTPLUG_CPU
553 Different boards from XTFPGA family !! 2931 bool "Support for hot-pluggable CPUs"
554 addresses. Please consult prototypin !! 2932 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
555 the correct address. Wrong address h <<
556 <<
557 config XTFPGA_LCD_8BIT_ACCESS <<
558 bool "Use 8-bit access to XTFPGA LCD" <<
559 depends on XTFPGA_LCD <<
560 default n <<
561 help 2933 help
562 LCD may be connected with 4- or 8-bi !! 2934 Say Y here to allow turning CPUs off and on. CPUs can be
563 only be used with 8-bit interface. P !! 2935 controlled through /sys/devices/system/cpu.
564 guide for your board for the correct !! 2936 (Note: power management support will enable this option
565 !! 2937 automatically on SMP systems. )
566 comment "Kernel memory layout" !! 2938 Say N if you want to disable CPU hotplug.
567 <<
568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX <<
569 bool "Initialize Xtensa MMU inside the <<
570 depends on !XTENSA_VARIANT_FSF && !XTE <<
571 default y if XTENSA_VARIANT_DC233C || <<
572 help <<
573 Earlier version initialized the MMU <<
574 before jumping to _startup in head.S <<
575 it was possible to place a software <<
576 then enter your normal kernel breakp <<
577 to the kernel mappings (0XC0000000). <<
578 <<
579 This unfortunately won't work for U- <<
580 work for using KEXEC to have a hot k <<
581 KDUMP. <<
582 <<
583 So now the MMU is initialized in hea <<
584 use hardware breakpoints (gdb 'hbrea <<
585 xt-gdb can't place a Software Breakp <<
586 to mapping the MMU and after mapping <<
587 was mapped gdb wouldn't remove the b <<
588 PC wouldn't match. Since Hardware Br <<
589 Linux configurations it seems reason <<
590 and leave this older mechanism for u <<
591 not to follow Tensilica's recommenda <<
592 <<
593 Selecting this will cause U-Boot to <<
594 address at 0x00003000 instead of the <<
595 <<
596 If in doubt, say Y. <<
597 <<
598 config XIP_KERNEL <<
599 bool "Kernel Execute-In-Place from ROM <<
600 depends on PLATFORM_HAVE_XIP <<
601 help <<
602 Execute-In-Place allows the kernel t <<
603 directly addressable by the CPU, suc <<
604 space since the text section of the <<
605 to RAM. Read-write sections, such as <<
606 are still copied to RAM. The XIP ker <<
607 it has to run directly from flash, s <<
608 store it. The flash address used to <<
609 and for storing it, is configuration <<
610 say Y here, you must know the proper <<
611 store the kernel image depending on <<
612 <<
613 Also note that the make target becom <<
614 "make Image" or "make uImage". The f <<
615 ROM memory will be arch/xtensa/boot/ <<
616 2939
617 If unsure, say N. !! 2940 config SMP_UP
>> 2941 bool
>> 2942
>> 2943 config SYS_SUPPORTS_MIPS_CMP
>> 2944 bool
>> 2945
>> 2946 config SYS_SUPPORTS_MIPS_CPS
>> 2947 bool
618 2948
619 config MEMMAP_CACHEATTR !! 2949 config SYS_SUPPORTS_SMP
620 hex "Cache attributes for the memory a !! 2950 bool
621 depends on !MMU <<
622 default 0x22222222 <<
623 help <<
624 These cache attributes are set up fo <<
625 specifies cache attributes for the c <<
626 region: bits 0..3 -- for addresses 0 <<
627 bits 4..7 -- for addresses 0x2000000 <<
628 <<
629 Cache attribute values are specific <<
630 For region protection MMUs: <<
631 1: WT cached, <<
632 2: cache bypass, <<
633 4: WB cached, <<
634 f: illegal. <<
635 For full MMU: <<
636 bit 0: executable, <<
637 bit 1: writable, <<
638 bits 2..3: <<
639 0: cache bypass, <<
640 1: WB cache, <<
641 2: WT cache, <<
642 3: special (c and e are illegal, <<
643 For MPU: <<
644 0: illegal, <<
645 1: WB cache, <<
646 2: WB, no-write-allocate cache, <<
647 3: WT cache, <<
648 4: cache bypass. <<
649 <<
650 config KSEG_PADDR <<
651 hex "Physical address of the KSEG mapp <<
652 depends on INITIALIZE_XTENSA_MMU_INSID <<
653 default 0x00000000 <<
654 help <<
655 This is the physical address where K <<
656 the chosen KSEG layout help for the <<
657 Unpacked kernel image (including vec <<
658 within KSEG. <<
659 Physical memory below this address i <<
660 <<
661 If unsure, leave the default value h <<
662 <<
663 config KERNEL_VIRTUAL_ADDRESS <<
664 hex "Kernel virtual address" <<
665 depends on MMU && XIP_KERNEL <<
666 default 0xd0003000 <<
667 help <<
668 This is the virtual address where th <<
669 XIP kernel may be mapped into KSEG o <<
670 provided here must match kernel load <<
671 KERNEL_LOAD_ADDRESS. <<
672 <<
673 config KERNEL_LOAD_ADDRESS <<
674 hex "Kernel load address" <<
675 default 0x60003000 if !MMU <<
676 default 0x00003000 if MMU && INITIALIZ <<
677 default 0xd0003000 if MMU && !INITIALI <<
678 help <<
679 This is the address where the kernel <<
680 It is virtual address for MMUv2 conf <<
681 for all other configurations. <<
682 2951
683 If unsure, leave the default value h !! 2952 config NR_CPUS_DEFAULT_4
>> 2953 bool
>> 2954
>> 2955 config NR_CPUS_DEFAULT_8
>> 2956 bool
>> 2957
>> 2958 config NR_CPUS_DEFAULT_16
>> 2959 bool
>> 2960
>> 2961 config NR_CPUS_DEFAULT_32
>> 2962 bool
>> 2963
>> 2964 config NR_CPUS_DEFAULT_64
>> 2965 bool
>> 2966
>> 2967 config NR_CPUS
>> 2968 int "Maximum number of CPUs (2-256)"
>> 2969 range 2 256
>> 2970 depends on SMP
>> 2971 default "4" if NR_CPUS_DEFAULT_4
>> 2972 default "8" if NR_CPUS_DEFAULT_8
>> 2973 default "16" if NR_CPUS_DEFAULT_16
>> 2974 default "32" if NR_CPUS_DEFAULT_32
>> 2975 default "64" if NR_CPUS_DEFAULT_64
>> 2976 help
>> 2977 This allows you to specify the maximum number of CPUs which this
>> 2978 kernel will support. The maximum supported value is 32 for 32-bit
>> 2979 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2980 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2981 and 2 for all others.
>> 2982
>> 2983 This is purely to save memory - each supported CPU adds
>> 2984 approximately eight kilobytes to the kernel image. For best
>> 2985 performance should round up your number of processors to the next
>> 2986 power of two.
>> 2987
>> 2988 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2989 bool
>> 2990
>> 2991 config MIPS_NR_CPU_NR_MAP_1024
>> 2992 bool
>> 2993
>> 2994 config MIPS_NR_CPU_NR_MAP
>> 2995 int
>> 2996 depends on SMP
>> 2997 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2998 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
>> 2999
>> 3000 #
>> 3001 # Timer Interrupt Frequency Configuration
>> 3002 #
684 3003
685 choice 3004 choice
686 prompt "Relocatable vectors location" !! 3005 prompt "Timer frequency"
687 default XTENSA_VECTORS_IN_TEXT !! 3006 default HZ_250
688 help 3007 help
689 Choose whether relocatable vectors a !! 3008 Allows the configuration of the timer frequency.
690 or placed separately at runtime. Thi !! 3009
691 configurations without VECBASE regis !! 3010 config HZ_24
692 placed at their hardware-defined loc !! 3011 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
693 !! 3012
694 config XTENSA_VECTORS_IN_TEXT !! 3013 config HZ_48
695 bool "Merge relocatable vectors into k !! 3014 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
696 depends on !MTD_XIP !! 3015
697 help !! 3016 config HZ_100
698 This option puts relocatable vectors !! 3017 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
699 with proper alignment. !! 3018
700 This is a safe choice for most confi !! 3019 config HZ_128
701 !! 3020 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
702 config XTENSA_VECTORS_SEPARATE !! 3021
703 bool "Put relocatable vectors at fixed !! 3022 config HZ_250
704 help !! 3023 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
705 This option puts relocatable vectors !! 3024
706 Vectors are merged with the .init da !! 3025 config HZ_256
707 are copied into their designated loc !! 3026 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
708 Use it to put vectors into IRAM or o !! 3027
709 XIP-aware MTD support. !! 3028 config HZ_1000
>> 3029 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 3030
>> 3031 config HZ_1024
>> 3032 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
710 3033
711 endchoice 3034 endchoice
712 3035
713 config VECTORS_ADDR !! 3036 config SYS_SUPPORTS_24HZ
714 hex "Kernel vectors virtual address" !! 3037 bool
715 default 0x00000000 <<
716 depends on XTENSA_VECTORS_SEPARATE <<
717 help <<
718 This is the virtual address of the ( <<
719 It must be within KSEG if MMU is use <<
720 <<
721 config XIP_DATA_ADDR <<
722 hex "XIP kernel data virtual address" <<
723 depends on XIP_KERNEL <<
724 default 0x00000000 <<
725 help <<
726 This is the virtual address where XI <<
727 It must be within KSEG if MMU is use <<
728 3038
729 config PLATFORM_WANT_DEFAULT_MEM !! 3039 config SYS_SUPPORTS_48HZ
730 def_bool n !! 3040 bool
731 3041
732 config DEFAULT_MEM_START !! 3042 config SYS_SUPPORTS_100HZ
733 hex !! 3043 bool
734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !M !! 3044
735 default 0x60000000 if PLATFORM_WANT_DE !! 3045 config SYS_SUPPORTS_128HZ
736 default 0x00000000 !! 3046 bool
737 help !! 3047
738 This is the base address used for bo !! 3048 config SYS_SUPPORTS_250HZ
739 in noMMU configurations. !! 3049 bool
>> 3050
>> 3051 config SYS_SUPPORTS_256HZ
>> 3052 bool
>> 3053
>> 3054 config SYS_SUPPORTS_1000HZ
>> 3055 bool
>> 3056
>> 3057 config SYS_SUPPORTS_1024HZ
>> 3058 bool
740 3059
741 If unsure, leave the default value h !! 3060 config SYS_SUPPORTS_ARBIT_HZ
>> 3061 bool
>> 3062 default y if !SYS_SUPPORTS_24HZ && \
>> 3063 !SYS_SUPPORTS_48HZ && \
>> 3064 !SYS_SUPPORTS_100HZ && \
>> 3065 !SYS_SUPPORTS_128HZ && \
>> 3066 !SYS_SUPPORTS_250HZ && \
>> 3067 !SYS_SUPPORTS_256HZ && \
>> 3068 !SYS_SUPPORTS_1000HZ && \
>> 3069 !SYS_SUPPORTS_1024HZ
>> 3070
>> 3071 config HZ
>> 3072 int
>> 3073 default 24 if HZ_24
>> 3074 default 48 if HZ_48
>> 3075 default 100 if HZ_100
>> 3076 default 128 if HZ_128
>> 3077 default 250 if HZ_250
>> 3078 default 256 if HZ_256
>> 3079 default 1000 if HZ_1000
>> 3080 default 1024 if HZ_1024
>> 3081
>> 3082 config SCHED_HRTICK
>> 3083 def_bool HIGH_RES_TIMERS
>> 3084
>> 3085 config KEXEC
>> 3086 bool "Kexec system call"
>> 3087 select KEXEC_CORE
>> 3088 help
>> 3089 kexec is a system call that implements the ability to shutdown your
>> 3090 current kernel, and to start another kernel. It is like a reboot
>> 3091 but it is independent of the system firmware. And like a reboot
>> 3092 you can start any kernel with it, not just Linux.
>> 3093
>> 3094 The name comes from the similarity to the exec system call.
>> 3095
>> 3096 It is an ongoing process to be certain the hardware in a machine
>> 3097 is properly shutdown, so do not be surprised if this code does not
>> 3098 initially work for you. As of this writing the exact hardware
>> 3099 interface is strongly in flux, so no good recommendation can be
>> 3100 made.
>> 3101
>> 3102 config CRASH_DUMP
>> 3103 bool "Kernel crash dumps"
>> 3104 help
>> 3105 Generate crash dump after being started by kexec.
>> 3106 This should be normally only set in special crash dump kernels
>> 3107 which are loaded in the main kernel with kexec-tools into
>> 3108 a specially reserved region and then later executed after
>> 3109 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 3110 to a memory address not used by the main kernel or firmware using
>> 3111 PHYSICAL_START.
>> 3112
>> 3113 config PHYSICAL_START
>> 3114 hex "Physical address where the kernel is loaded"
>> 3115 default "0xffffffff84000000"
>> 3116 depends on CRASH_DUMP
>> 3117 help
>> 3118 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 3119 If you plan to use kernel for capturing the crash dump change
>> 3120 this value to start of the reserved region (the "X" value as
>> 3121 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3122 passed to the panic-ed kernel).
>> 3123
>> 3124 config MIPS_O32_FP64_SUPPORT
>> 3125 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3126 depends on 32BIT || MIPS32_O32
>> 3127 help
>> 3128 When this is enabled, the kernel will support use of 64-bit floating
>> 3129 point registers with binaries using the O32 ABI along with the
>> 3130 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3131 32-bit MIPS systems this support is at the cost of increasing the
>> 3132 size and complexity of the compiled FPU emulator. Thus if you are
>> 3133 running a MIPS32 system and know that none of your userland binaries
>> 3134 will require 64-bit floating point, you may wish to reduce the size
>> 3135 of your kernel & potentially improve FP emulation performance by
>> 3136 saying N here.
>> 3137
>> 3138 Although binutils currently supports use of this flag the details
>> 3139 concerning its effect upon the O32 ABI in userland are still being
>> 3140 worked on. In order to avoid userland becoming dependent upon current
>> 3141 behaviour before the details have been finalised, this option should
>> 3142 be considered experimental and only enabled by those working upon
>> 3143 said details.
>> 3144
>> 3145 If unsure, say N.
>> 3146
>> 3147 config USE_OF
>> 3148 bool
>> 3149 select OF
>> 3150 select OF_EARLY_FLATTREE
>> 3151 select IRQ_DOMAIN
>> 3152
>> 3153 config UHI_BOOT
>> 3154 bool
>> 3155
>> 3156 config BUILTIN_DTB
>> 3157 bool
742 3158
743 choice 3159 choice
744 prompt "KSEG layout" !! 3160 prompt "Kernel appended dtb support" if USE_OF
745 depends on MMU !! 3161 default MIPS_NO_APPENDED_DTB
746 default XTENSA_KSEG_MMU_V2 <<
747 <<
748 config XTENSA_KSEG_MMU_V2 <<
749 bool "MMUv2: 128MB cached + 128MB unca <<
750 help <<
751 MMUv2 compatible kernel memory map: <<
752 at KSEG_PADDR to 0xd0000000 with cac <<
753 without cache. <<
754 KSEG_PADDR must be aligned to 128MB. <<
755 <<
756 config XTENSA_KSEG_256M <<
757 bool "256MB cached + 256MB uncached" <<
758 depends on INITIALIZE_XTENSA_MMU_INSID <<
759 help <<
760 TLB way 6 maps 256MB starting at KSE <<
761 with cache and to 0xc0000000 without <<
762 KSEG_PADDR must be aligned to 256MB. <<
763 <<
764 config XTENSA_KSEG_512M <<
765 bool "512MB cached + 512MB uncached" <<
766 depends on INITIALIZE_XTENSA_MMU_INSID <<
767 help <<
768 TLB way 6 maps 512MB starting at KSE <<
769 with cache and to 0xc0000000 without <<
770 KSEG_PADDR must be aligned to 256MB. <<
771 3162
>> 3163 config MIPS_NO_APPENDED_DTB
>> 3164 bool "None"
>> 3165 help
>> 3166 Do not enable appended dtb support.
>> 3167
>> 3168 config MIPS_ELF_APPENDED_DTB
>> 3169 bool "vmlinux"
>> 3170 help
>> 3171 With this option, the boot code will look for a device tree binary
>> 3172 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3173 it is empty and the DTB can be appended using binutils command
>> 3174 objcopy:
>> 3175
>> 3176 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3177
>> 3178 This is meant as a backward compatibility convenience for those
>> 3179 systems with a bootloader that can't be upgraded to accommodate
>> 3180 the documented boot protocol using a device tree.
>> 3181
>> 3182 config MIPS_RAW_APPENDED_DTB
>> 3183 bool "vmlinux.bin or vmlinuz.bin"
>> 3184 help
>> 3185 With this option, the boot code will look for a device tree binary
>> 3186 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3187 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3188
>> 3189 This is meant as a backward compatibility convenience for those
>> 3190 systems with a bootloader that can't be upgraded to accommodate
>> 3191 the documented boot protocol using a device tree.
>> 3192
>> 3193 Beware that there is very little in terms of protection against
>> 3194 this option being confused by leftover garbage in memory that might
>> 3195 look like a DTB header after a reboot if no actual DTB is appended
>> 3196 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3197 if you don't intend to always append a DTB.
772 endchoice 3198 endchoice
773 3199
774 config HIGHMEM !! 3200 choice
775 bool "High Memory Support" !! 3201 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
776 depends on MMU !! 3202 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
777 select KMAP_LOCAL !! 3203 !MACH_LOONGSON64 && !MIPS_MALTA && \
778 help !! 3204 !CAVIUM_OCTEON_SOC
779 Linux can use the full amount of RAM !! 3205 default MIPS_CMDLINE_FROM_BOOTLOADER
780 default. However, the default MMUv2 !! 3206
781 lowermost 128 MB of memory linearly !! 3207 config MIPS_CMDLINE_FROM_DTB
782 at 0xd0000000 (cached) and 0xd800000 !! 3208 depends on USE_OF
783 When there are more than 128 MB memo !! 3209 bool "Dtb kernel arguments if available"
784 all of it can be "permanently mapped !! 3210
785 The physical memory that's not perma !! 3211 config MIPS_CMDLINE_DTB_EXTEND
786 "high memory". !! 3212 depends on USE_OF
787 !! 3213 bool "Extend dtb kernel arguments with bootloader arguments"
788 If you are compiling a kernel which !! 3214
789 machine with more than 128 MB total !! 3215 config MIPS_CMDLINE_FROM_BOOTLOADER
790 N here. !! 3216 bool "Bootloader kernel arguments if available"
>> 3217
>> 3218 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3219 depends on CMDLINE_BOOL
>> 3220 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3221 endchoice
791 3222
792 If unsure, say Y. !! 3223 endmenu
>> 3224
>> 3225 config LOCKDEP_SUPPORT
>> 3226 bool
>> 3227 default y
>> 3228
>> 3229 config STACKTRACE_SUPPORT
>> 3230 bool
>> 3231 default y
>> 3232
>> 3233 config PGTABLE_LEVELS
>> 3234 int
>> 3235 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3236 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 3237 default 2
>> 3238
>> 3239 config MIPS_AUTO_PFN_OFFSET
>> 3240 bool
>> 3241
>> 3242 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
793 3243
794 config ARCH_FORCE_MAX_ORDER !! 3244 config PCI_DRIVERS_GENERIC
795 int "Order of maximal physically conti !! 3245 select PCI_DOMAINS_GENERIC if PCI
796 default "10" !! 3246 bool
797 help !! 3247
798 The kernel page allocator limits the !! 3248 config PCI_DRIVERS_LEGACY
799 contiguous allocations. The limit is !! 3249 def_bool !PCI_DRIVERS_GENERIC
800 defines the maximal power of two of !! 3250 select NO_GENERIC_PCI_IOPORT_MAP
801 allocated as a single contiguous blo !! 3251 select PCI_DOMAINS if PCI
802 overriding the default setting when !! 3252
803 large blocks of physically contiguou !! 3253 #
>> 3254 # ISA support is now enabled via select. Too many systems still have the one
>> 3255 # or other ISA chip on the board that users don't know about so don't expect
>> 3256 # users to choose the right thing ...
>> 3257 #
>> 3258 config ISA
>> 3259 bool
804 3260
805 Don't change if unsure. !! 3261 config TC
>> 3262 bool "TURBOchannel support"
>> 3263 depends on MACH_DECSTATION
>> 3264 help
>> 3265 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3266 processors. TURBOchannel programming specifications are available
>> 3267 at:
>> 3268 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3269 and:
>> 3270 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3271 Linux driver support status is documented at:
>> 3272 <http://www.linux-mips.org/wiki/DECstation>
>> 3273
>> 3274 config MMU
>> 3275 bool
>> 3276 default y
>> 3277
>> 3278 config ARCH_MMAP_RND_BITS_MIN
>> 3279 default 12 if 64BIT
>> 3280 default 8
>> 3281
>> 3282 config ARCH_MMAP_RND_BITS_MAX
>> 3283 default 18 if 64BIT
>> 3284 default 15
>> 3285
>> 3286 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3287 default 8
>> 3288
>> 3289 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3290 default 15
>> 3291
>> 3292 config I8253
>> 3293 bool
>> 3294 select CLKSRC_I8253
>> 3295 select CLKEVT_I8253
>> 3296 select MIPS_EXTERNAL_TIMER
>> 3297
>> 3298 config ZONE_DMA
>> 3299 bool
>> 3300
>> 3301 config ZONE_DMA32
>> 3302 bool
806 3303
807 endmenu 3304 endmenu
808 3305
>> 3306 config TRAD_SIGNALS
>> 3307 bool
>> 3308
>> 3309 config MIPS32_COMPAT
>> 3310 bool
>> 3311
>> 3312 config COMPAT
>> 3313 bool
>> 3314
>> 3315 config SYSVIPC_COMPAT
>> 3316 bool
>> 3317
>> 3318 config MIPS32_O32
>> 3319 bool "Kernel support for o32 binaries"
>> 3320 depends on 64BIT
>> 3321 select ARCH_WANT_OLD_COMPAT_IPC
>> 3322 select COMPAT
>> 3323 select MIPS32_COMPAT
>> 3324 select SYSVIPC_COMPAT if SYSVIPC
>> 3325 help
>> 3326 Select this option if you want to run o32 binaries. These are pure
>> 3327 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3328 existing binaries are in this format.
>> 3329
>> 3330 If unsure, say Y.
>> 3331
>> 3332 config MIPS32_N32
>> 3333 bool "Kernel support for n32 binaries"
>> 3334 depends on 64BIT
>> 3335 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3336 select COMPAT
>> 3337 select MIPS32_COMPAT
>> 3338 select SYSVIPC_COMPAT if SYSVIPC
>> 3339 help
>> 3340 Select this option if you want to run n32 binaries. These are
>> 3341 64-bit binaries using 32-bit quantities for addressing and certain
>> 3342 data that would normally be 64-bit. They are used in special
>> 3343 cases.
>> 3344
>> 3345 If unsure, say N.
>> 3346
809 menu "Power management options" 3347 menu "Power management options"
810 3348
811 config ARCH_HIBERNATION_POSSIBLE 3349 config ARCH_HIBERNATION_POSSIBLE
812 def_bool y 3350 def_bool y
>> 3351 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3352
>> 3353 config ARCH_SUSPEND_POSSIBLE
>> 3354 def_bool y
>> 3355 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
813 3356
814 source "kernel/power/Kconfig" 3357 source "kernel/power/Kconfig"
815 3358
816 endmenu 3359 endmenu
>> 3360
>> 3361 config MIPS_EXTERNAL_TIMER
>> 3362 bool
>> 3363
>> 3364 menu "CPU Power Management"
>> 3365
>> 3366 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3367 source "drivers/cpufreq/Kconfig"
>> 3368 endif
>> 3369
>> 3370 source "drivers/cpuidle/Kconfig"
>> 3371
>> 3372 endmenu
>> 3373
>> 3374 source "drivers/firmware/Kconfig"
>> 3375
>> 3376 source "arch/mips/kvm/Kconfig"
>> 3377
>> 3378 source "arch/mips/vdso/Kconfig"
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