1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 config XTENSA !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ARCH_32BIT_OFF_T !! 4 default y
5 select ARCH_HAS_CPU_CACHE_ALIASING !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_HAS_BINFMT_FLAT if !MMU !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CURRENT_STACK_POINTER !! 7 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
8 select ARCH_HAS_DEBUG_VM_PGTABLE !! 8 select ARCH_HAS_FORTIFY_SOURCE
9 select ARCH_HAS_DMA_PREP_COHERENT if M <<
10 select ARCH_HAS_GCOV_PROFILE_ALL <<
11 select ARCH_HAS_KCOV 9 select ARCH_HAS_KCOV
12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MM !! 10 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if !! 11 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
14 select ARCH_HAS_DMA_SET_UNCACHED if MM !! 12 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
15 select ARCH_HAS_STRNCPY_FROM_USER if ! !! 13 select ARCH_HAS_UBSAN_SANITIZE_ALL
16 select ARCH_HAS_STRNLEN_USER !! 14 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_NEED_CMPXCHG_1_EMU !! 15 select ARCH_KEEP_MEMBLOCK
>> 16 select ARCH_SUPPORTS_UPROBES
>> 17 select ARCH_USE_BUILTIN_BSWAP
>> 18 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
18 select ARCH_USE_MEMTEST 19 select ARCH_USE_MEMTEST
19 select ARCH_USE_QUEUED_RWLOCKS 20 select ARCH_USE_QUEUED_RWLOCKS
20 select ARCH_USE_QUEUED_SPINLOCKS 21 select ARCH_USE_QUEUED_SPINLOCKS
>> 22 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
>> 23 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
21 select ARCH_WANT_IPC_PARSE_VERSION 24 select ARCH_WANT_IPC_PARSE_VERSION
>> 25 select ARCH_WANT_LD_ORPHAN_WARN
22 select BUILDTIME_TABLE_SORT 26 select BUILDTIME_TABLE_SORT
23 select CLONE_BACKWARDS 27 select CLONE_BACKWARDS
24 select COMMON_CLK !! 28 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
25 select DMA_NONCOHERENT_MMAP if MMU !! 29 select CPU_PM if CPU_IDLE
26 select GENERIC_ATOMIC64 !! 30 select GENERIC_ATOMIC64 if !64BIT
>> 31 select GENERIC_CMOS_UPDATE
>> 32 select GENERIC_CPU_AUTOPROBE
>> 33 select GENERIC_FIND_FIRST_BIT
>> 34 select GENERIC_GETTIMEOFDAY
>> 35 select GENERIC_IOMAP
>> 36 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW 37 select GENERIC_IRQ_SHOW
>> 38 select GENERIC_ISA_DMA if EISA
>> 39 select GENERIC_LIB_ASHLDI3
>> 40 select GENERIC_LIB_ASHRDI3
28 select GENERIC_LIB_CMPDI2 41 select GENERIC_LIB_CMPDI2
29 select GENERIC_LIB_MULDI3 !! 42 select GENERIC_LIB_LSHRDI3
30 select GENERIC_LIB_UCMPDI2 43 select GENERIC_LIB_UCMPDI2
31 select GENERIC_PCI_IOMAP !! 44 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
32 select GENERIC_SCHED_CLOCK !! 45 select GENERIC_SMP_IDLE_THREAD
33 select GENERIC_IOREMAP if MMU !! 46 select GENERIC_TIME_VSYSCALL
34 select HAVE_ARCH_AUDITSYSCALL !! 47 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
35 select HAVE_ARCH_JUMP_LABEL if !XIP_KE !! 48 select HANDLE_DOMAIN_IRQ
36 select HAVE_ARCH_KASAN if MMU && !XIP_ !! 49 select HAVE_ARCH_COMPILER_H
37 select HAVE_ARCH_KCSAN !! 50 select HAVE_ARCH_JUMP_LABEL
>> 51 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
>> 52 select HAVE_ARCH_MMAP_RND_BITS if MMU
>> 53 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
38 select HAVE_ARCH_SECCOMP_FILTER 54 select HAVE_ARCH_SECCOMP_FILTER
39 select HAVE_ARCH_TRACEHOOK 55 select HAVE_ARCH_TRACEHOOK
>> 56 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
40 select HAVE_ASM_MODVERSIONS 57 select HAVE_ASM_MODVERSIONS
41 select HAVE_CONTEXT_TRACKING_USER !! 58 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 59 select HAVE_CONTEXT_TRACKING
>> 60 select HAVE_TIF_NOHZ
>> 61 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK 62 select HAVE_DEBUG_KMEMLEAK
>> 63 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_DMA_CONTIGUOUS 64 select HAVE_DMA_CONTIGUOUS
>> 65 select HAVE_DYNAMIC_FTRACE
>> 66 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
44 select HAVE_EXIT_THREAD 67 select HAVE_EXIT_THREAD
>> 68 select HAVE_FAST_GUP
>> 69 select HAVE_FTRACE_MCOUNT_RECORD
>> 70 select HAVE_FUNCTION_GRAPH_TRACER
45 select HAVE_FUNCTION_TRACER 71 select HAVE_FUNCTION_TRACER
46 select HAVE_GCC_PLUGINS if GCC_VERSION !! 72 select HAVE_GCC_PLUGINS
47 select HAVE_HW_BREAKPOINT if PERF_EVEN !! 73 select HAVE_GENERIC_VDSO
>> 74 select HAVE_IDE
>> 75 select HAVE_IOREMAP_PROT
>> 76 select HAVE_IRQ_EXIT_ON_IRQ_STACK
48 select HAVE_IRQ_TIME_ACCOUNTING 77 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_PAGE_SIZE_4KB !! 78 select HAVE_KPROBES
50 select HAVE_PCI !! 79 select HAVE_KRETPROBES
>> 80 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 81 select HAVE_MOD_ARCH_SPECIFIC
>> 82 select HAVE_NMI
51 select HAVE_PERF_EVENTS 83 select HAVE_PERF_EVENTS
>> 84 select HAVE_PERF_REGS
>> 85 select HAVE_PERF_USER_STACK_DUMP
>> 86 select HAVE_REGS_AND_STACK_ACCESS_API
>> 87 select HAVE_RSEQ
>> 88 select HAVE_SPARSE_SYSCALL_NR
52 select HAVE_STACKPROTECTOR 89 select HAVE_STACKPROTECTOR
53 select HAVE_SYSCALL_TRACEPOINTS 90 select HAVE_SYSCALL_TRACEPOINTS
54 select HAVE_VIRT_CPU_ACCOUNTING_GEN !! 91 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
55 select IRQ_DOMAIN !! 92 select IRQ_FORCED_THREADING
56 select LOCK_MM_AND_FIND_VMA !! 93 select ISA if EISA
57 select MODULES_USE_ELF_RELA !! 94 select MODULES_USE_ELF_REL if MODULES
>> 95 select MODULES_USE_ELF_RELA if MODULES && 64BIT
58 select PERF_USE_VMALLOC 96 select PERF_USE_VMALLOC
59 select TRACE_IRQFLAGS_SUPPORT !! 97 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
>> 98 select RTC_LIB
>> 99 select SYSCTL_EXCEPTION_TRACE
>> 100 select VIRT_TO_BUS
>> 101 select ARCH_HAS_ELFCORE_COMPAT
>> 102
>> 103 config MIPS_FIXUP_BIGPHYS_ADDR
>> 104 bool
>> 105
>> 106 config MIPS_GENERIC
>> 107 bool
>> 108
>> 109 config MACH_INGENIC
>> 110 bool
>> 111 select SYS_SUPPORTS_32BIT_KERNEL
>> 112 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 113 select SYS_SUPPORTS_ZBOOT
>> 114 select DMA_NONCOHERENT
>> 115 select IRQ_MIPS_CPU
>> 116 select PINCTRL
>> 117 select GPIOLIB
>> 118 select COMMON_CLK
>> 119 select GENERIC_IRQ_CHIP
>> 120 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 121 select USE_OF
>> 122 select CPU_SUPPORTS_CPUFREQ
>> 123 select MIPS_EXTERNAL_TIMER
>> 124
>> 125 menu "Machine selection"
>> 126
>> 127 choice
>> 128 prompt "System type"
>> 129 default MIPS_GENERIC_KERNEL
>> 130
>> 131 config MIPS_GENERIC_KERNEL
>> 132 bool "Generic board-agnostic MIPS kernel"
>> 133 select ARCH_HAS_SETUP_DMA_OPS
>> 134 select MIPS_GENERIC
>> 135 select BOOT_RAW
>> 136 select BUILTIN_DTB
>> 137 select CEVT_R4K
>> 138 select CLKSRC_MIPS_GIC
>> 139 select COMMON_CLK
>> 140 select CPU_MIPSR2_IRQ_EI
>> 141 select CPU_MIPSR2_IRQ_VI
>> 142 select CSRC_R4K
>> 143 select DMA_NONCOHERENT
>> 144 select HAVE_PCI
>> 145 select IRQ_MIPS_CPU
>> 146 select MIPS_AUTO_PFN_OFFSET
>> 147 select MIPS_CPU_SCACHE
>> 148 select MIPS_GIC
>> 149 select MIPS_L1_CACHE_SHIFT_7
>> 150 select NO_EXCEPT_FILL
>> 151 select PCI_DRIVERS_GENERIC
>> 152 select SMP_UP if SMP
>> 153 select SWAP_IO_SPACE
>> 154 select SYS_HAS_CPU_MIPS32_R1
>> 155 select SYS_HAS_CPU_MIPS32_R2
>> 156 select SYS_HAS_CPU_MIPS32_R6
>> 157 select SYS_HAS_CPU_MIPS64_R1
>> 158 select SYS_HAS_CPU_MIPS64_R2
>> 159 select SYS_HAS_CPU_MIPS64_R6
>> 160 select SYS_SUPPORTS_32BIT_KERNEL
>> 161 select SYS_SUPPORTS_64BIT_KERNEL
>> 162 select SYS_SUPPORTS_BIG_ENDIAN
>> 163 select SYS_SUPPORTS_HIGHMEM
>> 164 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 165 select SYS_SUPPORTS_MICROMIPS
>> 166 select SYS_SUPPORTS_MIPS16
>> 167 select SYS_SUPPORTS_MIPS_CPS
>> 168 select SYS_SUPPORTS_MULTITHREADING
>> 169 select SYS_SUPPORTS_RELOCATABLE
>> 170 select SYS_SUPPORTS_SMARTMIPS
>> 171 select SYS_SUPPORTS_ZBOOT
>> 172 select UHI_BOOT
>> 173 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 174 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 175 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 176 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 177 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 178 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 179 select USE_OF
>> 180 help
>> 181 Select this to build a kernel which aims to support multiple boards,
>> 182 generally using a flattened device tree passed from the bootloader
>> 183 using the boot protocol defined in the UHI (Unified Hosting
>> 184 Interface) specification.
>> 185
>> 186 config MIPS_ALCHEMY
>> 187 bool "Alchemy processor based machines"
>> 188 select PHYS_ADDR_T_64BIT
>> 189 select CEVT_R4K
>> 190 select CSRC_R4K
>> 191 select IRQ_MIPS_CPU
>> 192 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 193 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 194 select SYS_HAS_CPU_MIPS32_R1
>> 195 select SYS_SUPPORTS_32BIT_KERNEL
>> 196 select SYS_SUPPORTS_APM_EMULATION
>> 197 select GPIOLIB
>> 198 select SYS_SUPPORTS_ZBOOT
>> 199 select COMMON_CLK
>> 200
>> 201 config AR7
>> 202 bool "Texas Instruments AR7"
>> 203 select BOOT_ELF32
>> 204 select DMA_NONCOHERENT
>> 205 select CEVT_R4K
>> 206 select CSRC_R4K
>> 207 select IRQ_MIPS_CPU
>> 208 select NO_EXCEPT_FILL
>> 209 select SWAP_IO_SPACE
>> 210 select SYS_HAS_CPU_MIPS32_R1
>> 211 select SYS_HAS_EARLY_PRINTK
>> 212 select SYS_SUPPORTS_32BIT_KERNEL
>> 213 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 214 select SYS_SUPPORTS_MIPS16
>> 215 select SYS_SUPPORTS_ZBOOT_UART16550
>> 216 select GPIOLIB
>> 217 select VLYNQ
>> 218 select HAVE_LEGACY_CLK
>> 219 help
>> 220 Support for the Texas Instruments AR7 System-on-a-Chip
>> 221 family: TNETD7100, 7200 and 7300.
>> 222
>> 223 config ATH25
>> 224 bool "Atheros AR231x/AR531x SoC support"
>> 225 select CEVT_R4K
>> 226 select CSRC_R4K
>> 227 select DMA_NONCOHERENT
>> 228 select IRQ_MIPS_CPU
>> 229 select IRQ_DOMAIN
>> 230 select SYS_HAS_CPU_MIPS32_R1
>> 231 select SYS_SUPPORTS_BIG_ENDIAN
>> 232 select SYS_SUPPORTS_32BIT_KERNEL
>> 233 select SYS_HAS_EARLY_PRINTK
>> 234 help
>> 235 Support for Atheros AR231x and Atheros AR531x based boards
>> 236
>> 237 config ATH79
>> 238 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 239 select ARCH_HAS_RESET_CONTROLLER
>> 240 select BOOT_RAW
>> 241 select CEVT_R4K
>> 242 select CSRC_R4K
>> 243 select DMA_NONCOHERENT
>> 244 select GPIOLIB
>> 245 select PINCTRL
>> 246 select COMMON_CLK
>> 247 select IRQ_MIPS_CPU
>> 248 select SYS_HAS_CPU_MIPS32_R2
>> 249 select SYS_HAS_EARLY_PRINTK
>> 250 select SYS_SUPPORTS_32BIT_KERNEL
>> 251 select SYS_SUPPORTS_BIG_ENDIAN
>> 252 select SYS_SUPPORTS_MIPS16
>> 253 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 254 select USE_OF
>> 255 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 256 help
>> 257 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 258
>> 259 config BMIPS_GENERIC
>> 260 bool "Broadcom Generic BMIPS kernel"
>> 261 select ARCH_HAS_RESET_CONTROLLER
>> 262 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 263 select ARCH_HAS_PHYS_TO_DMA
>> 264 select BOOT_RAW
>> 265 select NO_EXCEPT_FILL
>> 266 select USE_OF
>> 267 select CEVT_R4K
>> 268 select CSRC_R4K
>> 269 select SYNC_R4K
>> 270 select COMMON_CLK
>> 271 select BCM6345_L1_IRQ
>> 272 select BCM7038_L1_IRQ
>> 273 select BCM7120_L2_IRQ
>> 274 select BRCMSTB_L2_IRQ
>> 275 select IRQ_MIPS_CPU
>> 276 select DMA_NONCOHERENT
>> 277 select SYS_SUPPORTS_32BIT_KERNEL
>> 278 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 279 select SYS_SUPPORTS_BIG_ENDIAN
>> 280 select SYS_SUPPORTS_HIGHMEM
>> 281 select SYS_HAS_CPU_BMIPS32_3300
>> 282 select SYS_HAS_CPU_BMIPS4350
>> 283 select SYS_HAS_CPU_BMIPS4380
>> 284 select SYS_HAS_CPU_BMIPS5000
>> 285 select SWAP_IO_SPACE
>> 286 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 287 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 288 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 289 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 290 select HARDIRQS_SW_RESEND
>> 291 help
>> 292 Build a generic DT-based kernel image that boots on select
>> 293 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 294 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 295 must be set appropriately for your board.
>> 296
>> 297 config BCM47XX
>> 298 bool "Broadcom BCM47XX based boards"
>> 299 select BOOT_RAW
>> 300 select CEVT_R4K
>> 301 select CSRC_R4K
>> 302 select DMA_NONCOHERENT
>> 303 select HAVE_PCI
>> 304 select IRQ_MIPS_CPU
>> 305 select SYS_HAS_CPU_MIPS32_R1
>> 306 select NO_EXCEPT_FILL
>> 307 select SYS_SUPPORTS_32BIT_KERNEL
>> 308 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 309 select SYS_SUPPORTS_MIPS16
>> 310 select SYS_SUPPORTS_ZBOOT
>> 311 select SYS_HAS_EARLY_PRINTK
>> 312 select USE_GENERIC_EARLY_PRINTK_8250
>> 313 select GPIOLIB
>> 314 select LEDS_GPIO_REGISTER
>> 315 select BCM47XX_NVRAM
>> 316 select BCM47XX_SPROM
>> 317 select BCM47XX_SSB if !BCM47XX_BCMA
>> 318 help
>> 319 Support for BCM47XX based boards
>> 320
>> 321 config BCM63XX
>> 322 bool "Broadcom BCM63XX based boards"
>> 323 select BOOT_RAW
>> 324 select CEVT_R4K
>> 325 select CSRC_R4K
>> 326 select SYNC_R4K
>> 327 select DMA_NONCOHERENT
>> 328 select IRQ_MIPS_CPU
>> 329 select SYS_SUPPORTS_32BIT_KERNEL
>> 330 select SYS_SUPPORTS_BIG_ENDIAN
>> 331 select SYS_HAS_EARLY_PRINTK
>> 332 select SWAP_IO_SPACE
>> 333 select GPIOLIB
>> 334 select MIPS_L1_CACHE_SHIFT_4
>> 335 select CLKDEV_LOOKUP
>> 336 select HAVE_LEGACY_CLK
>> 337 help
>> 338 Support for BCM63XX based boards
>> 339
>> 340 config MIPS_COBALT
>> 341 bool "Cobalt Server"
>> 342 select CEVT_R4K
>> 343 select CSRC_R4K
>> 344 select CEVT_GT641XX
>> 345 select DMA_NONCOHERENT
>> 346 select FORCE_PCI
>> 347 select I8253
>> 348 select I8259
>> 349 select IRQ_MIPS_CPU
>> 350 select IRQ_GT641XX
>> 351 select PCI_GT64XXX_PCI0
>> 352 select SYS_HAS_CPU_NEVADA
>> 353 select SYS_HAS_EARLY_PRINTK
>> 354 select SYS_SUPPORTS_32BIT_KERNEL
>> 355 select SYS_SUPPORTS_64BIT_KERNEL
>> 356 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 357 select USE_GENERIC_EARLY_PRINTK_8250
>> 358
>> 359 config MACH_DECSTATION
>> 360 bool "DECstations"
>> 361 select BOOT_ELF32
>> 362 select CEVT_DS1287
>> 363 select CEVT_R4K if CPU_R4X00
>> 364 select CSRC_IOASIC
>> 365 select CSRC_R4K if CPU_R4X00
>> 366 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 367 select CPU_R4000_WORKAROUNDS if 64BIT
>> 368 select CPU_R4400_WORKAROUNDS if 64BIT
>> 369 select DMA_NONCOHERENT
>> 370 select NO_IOPORT_MAP
>> 371 select IRQ_MIPS_CPU
>> 372 select SYS_HAS_CPU_R3000
>> 373 select SYS_HAS_CPU_R4X00
>> 374 select SYS_SUPPORTS_32BIT_KERNEL
>> 375 select SYS_SUPPORTS_64BIT_KERNEL
>> 376 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 377 select SYS_SUPPORTS_128HZ
>> 378 select SYS_SUPPORTS_256HZ
>> 379 select SYS_SUPPORTS_1024HZ
>> 380 select MIPS_L1_CACHE_SHIFT_4
>> 381 help
>> 382 This enables support for DEC's MIPS based workstations. For details
>> 383 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 384 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 385
>> 386 If you have one of the following DECstation Models you definitely
>> 387 want to choose R4xx0 for the CPU Type:
>> 388
>> 389 DECstation 5000/50
>> 390 DECstation 5000/150
>> 391 DECstation 5000/260
>> 392 DECsystem 5900/260
>> 393
>> 394 otherwise choose R3000.
>> 395
>> 396 config MACH_JAZZ
>> 397 bool "Jazz family of machines"
>> 398 select ARC_MEMORY
>> 399 select ARC_PROMLIB
>> 400 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 401 select ARCH_MIGHT_HAVE_PC_SERIO
>> 402 select DMA_OPS
>> 403 select FW_ARC
>> 404 select FW_ARC32
>> 405 select ARCH_MAY_HAVE_PC_FDC
>> 406 select CEVT_R4K
>> 407 select CSRC_R4K
>> 408 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 409 select GENERIC_ISA_DMA
>> 410 select HAVE_PCSPKR_PLATFORM
>> 411 select IRQ_MIPS_CPU
>> 412 select I8253
>> 413 select I8259
>> 414 select ISA
>> 415 select SYS_HAS_CPU_R4X00
>> 416 select SYS_SUPPORTS_32BIT_KERNEL
>> 417 select SYS_SUPPORTS_64BIT_KERNEL
>> 418 select SYS_SUPPORTS_100HZ
>> 419 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 420 help
>> 421 This a family of machines based on the MIPS R4030 chipset which was
>> 422 used by several vendors to build RISC/os and Windows NT workstations.
>> 423 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 424 Olivetti M700-10 workstations.
>> 425
>> 426 config MACH_INGENIC_SOC
>> 427 bool "Ingenic SoC based machines"
>> 428 select MIPS_GENERIC
>> 429 select MACH_INGENIC
>> 430 select SYS_SUPPORTS_ZBOOT_UART16550
>> 431 select CPU_SUPPORTS_CPUFREQ
>> 432 select MIPS_EXTERNAL_TIMER
>> 433
>> 434 config LANTIQ
>> 435 bool "Lantiq based platforms"
>> 436 select DMA_NONCOHERENT
>> 437 select IRQ_MIPS_CPU
>> 438 select CEVT_R4K
>> 439 select CSRC_R4K
>> 440 select SYS_HAS_CPU_MIPS32_R1
>> 441 select SYS_HAS_CPU_MIPS32_R2
>> 442 select SYS_SUPPORTS_BIG_ENDIAN
>> 443 select SYS_SUPPORTS_32BIT_KERNEL
>> 444 select SYS_SUPPORTS_MIPS16
>> 445 select SYS_SUPPORTS_MULTITHREADING
>> 446 select SYS_SUPPORTS_VPE_LOADER
>> 447 select SYS_HAS_EARLY_PRINTK
>> 448 select GPIOLIB
>> 449 select SWAP_IO_SPACE
>> 450 select BOOT_RAW
>> 451 select CLKDEV_LOOKUP
>> 452 select HAVE_LEGACY_CLK
>> 453 select USE_OF
>> 454 select PINCTRL
>> 455 select PINCTRL_LANTIQ
>> 456 select ARCH_HAS_RESET_CONTROLLER
>> 457 select RESET_CONTROLLER
>> 458
>> 459 config MACH_LOONGSON32
>> 460 bool "Loongson 32-bit family of machines"
>> 461 select SYS_SUPPORTS_ZBOOT
>> 462 help
>> 463 This enables support for the Loongson-1 family of machines.
>> 464
>> 465 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 466 the Institute of Computing Technology (ICT), Chinese Academy of
>> 467 Sciences (CAS).
>> 468
>> 469 config MACH_LOONGSON2EF
>> 470 bool "Loongson-2E/F family of machines"
>> 471 select SYS_SUPPORTS_ZBOOT
>> 472 help
>> 473 This enables the support of early Loongson-2E/F family of machines.
>> 474
>> 475 config MACH_LOONGSON64
>> 476 bool "Loongson 64-bit family of machines"
>> 477 select ARCH_SPARSEMEM_ENABLE
>> 478 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 479 select ARCH_MIGHT_HAVE_PC_SERIO
>> 480 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 481 select BOOT_ELF32
>> 482 select BOARD_SCACHE
>> 483 select CSRC_R4K
>> 484 select CEVT_R4K
>> 485 select CPU_HAS_WB
>> 486 select FORCE_PCI
>> 487 select ISA
>> 488 select I8259
>> 489 select IRQ_MIPS_CPU
>> 490 select NO_EXCEPT_FILL
>> 491 select NR_CPUS_DEFAULT_64
>> 492 select USE_GENERIC_EARLY_PRINTK_8250
>> 493 select PCI_DRIVERS_GENERIC
>> 494 select SYS_HAS_CPU_LOONGSON64
>> 495 select SYS_HAS_EARLY_PRINTK
>> 496 select SYS_SUPPORTS_SMP
>> 497 select SYS_SUPPORTS_HOTPLUG_CPU
>> 498 select SYS_SUPPORTS_NUMA
>> 499 select SYS_SUPPORTS_64BIT_KERNEL
>> 500 select SYS_SUPPORTS_HIGHMEM
>> 501 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 502 select SYS_SUPPORTS_ZBOOT
>> 503 select SYS_SUPPORTS_RELOCATABLE
>> 504 select ZONE_DMA32
>> 505 select COMMON_CLK
>> 506 select USE_OF
>> 507 select BUILTIN_DTB
>> 508 select PCI_HOST_GENERIC
>> 509 help
>> 510 This enables the support of Loongson-2/3 family of machines.
>> 511
>> 512 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 513 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 514 and Loongson-2F which will be removed), developed by the Institute
>> 515 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 516
>> 517 config MACH_PISTACHIO
>> 518 bool "IMG Pistachio SoC based boards"
>> 519 select BOOT_ELF32
>> 520 select BOOT_RAW
>> 521 select CEVT_R4K
>> 522 select CLKSRC_MIPS_GIC
>> 523 select COMMON_CLK
>> 524 select CSRC_R4K
>> 525 select DMA_NONCOHERENT
>> 526 select GPIOLIB
>> 527 select IRQ_MIPS_CPU
>> 528 select MFD_SYSCON
>> 529 select MIPS_CPU_SCACHE
>> 530 select MIPS_GIC
>> 531 select PINCTRL
>> 532 select REGULATOR
>> 533 select SYS_HAS_CPU_MIPS32_R2
>> 534 select SYS_SUPPORTS_32BIT_KERNEL
>> 535 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 536 select SYS_SUPPORTS_MIPS_CPS
>> 537 select SYS_SUPPORTS_MULTITHREADING
>> 538 select SYS_SUPPORTS_RELOCATABLE
>> 539 select SYS_SUPPORTS_ZBOOT
>> 540 select SYS_HAS_EARLY_PRINTK
>> 541 select USE_GENERIC_EARLY_PRINTK_8250
>> 542 select USE_OF
>> 543 help
>> 544 This enables support for the IMG Pistachio SoC platform.
>> 545
>> 546 config MIPS_MALTA
>> 547 bool "MIPS Malta board"
>> 548 select ARCH_MAY_HAVE_PC_FDC
>> 549 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 550 select ARCH_MIGHT_HAVE_PC_SERIO
>> 551 select BOOT_ELF32
>> 552 select BOOT_RAW
>> 553 select BUILTIN_DTB
>> 554 select CEVT_R4K
>> 555 select CLKSRC_MIPS_GIC
>> 556 select COMMON_CLK
>> 557 select CSRC_R4K
>> 558 select DMA_NONCOHERENT
>> 559 select GENERIC_ISA_DMA
>> 560 select HAVE_PCSPKR_PLATFORM
>> 561 select HAVE_PCI
>> 562 select I8253
>> 563 select I8259
>> 564 select IRQ_MIPS_CPU
>> 565 select MIPS_BONITO64
>> 566 select MIPS_CPU_SCACHE
>> 567 select MIPS_GIC
>> 568 select MIPS_L1_CACHE_SHIFT_6
>> 569 select MIPS_MSC
>> 570 select PCI_GT64XXX_PCI0
>> 571 select SMP_UP if SMP
>> 572 select SWAP_IO_SPACE
>> 573 select SYS_HAS_CPU_MIPS32_R1
>> 574 select SYS_HAS_CPU_MIPS32_R2
>> 575 select SYS_HAS_CPU_MIPS32_R3_5
>> 576 select SYS_HAS_CPU_MIPS32_R5
>> 577 select SYS_HAS_CPU_MIPS32_R6
>> 578 select SYS_HAS_CPU_MIPS64_R1
>> 579 select SYS_HAS_CPU_MIPS64_R2
>> 580 select SYS_HAS_CPU_MIPS64_R6
>> 581 select SYS_HAS_CPU_NEVADA
>> 582 select SYS_HAS_CPU_RM7000
>> 583 select SYS_SUPPORTS_32BIT_KERNEL
>> 584 select SYS_SUPPORTS_64BIT_KERNEL
>> 585 select SYS_SUPPORTS_BIG_ENDIAN
>> 586 select SYS_SUPPORTS_HIGHMEM
>> 587 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 588 select SYS_SUPPORTS_MICROMIPS
>> 589 select SYS_SUPPORTS_MIPS16
>> 590 select SYS_SUPPORTS_MIPS_CMP
>> 591 select SYS_SUPPORTS_MIPS_CPS
>> 592 select SYS_SUPPORTS_MULTITHREADING
>> 593 select SYS_SUPPORTS_RELOCATABLE
>> 594 select SYS_SUPPORTS_SMARTMIPS
>> 595 select SYS_SUPPORTS_VPE_LOADER
>> 596 select SYS_SUPPORTS_ZBOOT
>> 597 select USE_OF
>> 598 select WAR_ICACHE_REFILLS
>> 599 select ZONE_DMA32 if 64BIT
>> 600 help
>> 601 This enables support for the MIPS Technologies Malta evaluation
>> 602 board.
>> 603
>> 604 config MACH_PIC32
>> 605 bool "Microchip PIC32 Family"
>> 606 help
>> 607 This enables support for the Microchip PIC32 family of platforms.
>> 608
>> 609 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 610 microcontrollers.
>> 611
>> 612 config MACH_VR41XX
>> 613 bool "NEC VR4100 series based machines"
>> 614 select CEVT_R4K
>> 615 select CSRC_R4K
>> 616 select SYS_HAS_CPU_VR41XX
>> 617 select SYS_SUPPORTS_MIPS16
>> 618 select GPIOLIB
>> 619
>> 620 config MACH_NINTENDO64
>> 621 bool "Nintendo 64 console"
>> 622 select CEVT_R4K
>> 623 select CSRC_R4K
>> 624 select SYS_HAS_CPU_R4300
>> 625 select SYS_SUPPORTS_BIG_ENDIAN
>> 626 select SYS_SUPPORTS_ZBOOT
>> 627 select SYS_SUPPORTS_32BIT_KERNEL
>> 628 select SYS_SUPPORTS_64BIT_KERNEL
>> 629 select DMA_NONCOHERENT
>> 630 select IRQ_MIPS_CPU
>> 631
>> 632 config RALINK
>> 633 bool "Ralink based machines"
>> 634 select CEVT_R4K
>> 635 select CSRC_R4K
>> 636 select BOOT_RAW
>> 637 select DMA_NONCOHERENT
>> 638 select IRQ_MIPS_CPU
>> 639 select USE_OF
>> 640 select SYS_HAS_CPU_MIPS32_R1
>> 641 select SYS_HAS_CPU_MIPS32_R2
>> 642 select SYS_SUPPORTS_32BIT_KERNEL
>> 643 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 644 select SYS_SUPPORTS_MIPS16
>> 645 select SYS_SUPPORTS_ZBOOT
>> 646 select SYS_HAS_EARLY_PRINTK
>> 647 select CLKDEV_LOOKUP
>> 648 select ARCH_HAS_RESET_CONTROLLER
>> 649 select RESET_CONTROLLER
>> 650
>> 651 config MACH_REALTEK_RTL
>> 652 bool "Realtek RTL838x/RTL839x based machines"
>> 653 select MIPS_GENERIC
>> 654 select DMA_NONCOHERENT
>> 655 select IRQ_MIPS_CPU
>> 656 select CSRC_R4K
>> 657 select CEVT_R4K
>> 658 select SYS_HAS_CPU_MIPS32_R1
>> 659 select SYS_HAS_CPU_MIPS32_R2
>> 660 select SYS_SUPPORTS_BIG_ENDIAN
>> 661 select SYS_SUPPORTS_32BIT_KERNEL
>> 662 select SYS_SUPPORTS_MIPS16
>> 663 select SYS_SUPPORTS_MULTITHREADING
>> 664 select SYS_SUPPORTS_VPE_LOADER
>> 665 select SYS_HAS_EARLY_PRINTK
>> 666 select SYS_HAS_EARLY_PRINTK_8250
>> 667 select USE_GENERIC_EARLY_PRINTK_8250
>> 668 select BOOT_RAW
>> 669 select PINCTRL
>> 670 select USE_OF
>> 671
>> 672 config SGI_IP22
>> 673 bool "SGI IP22 (Indy/Indigo2)"
>> 674 select ARC_MEMORY
>> 675 select ARC_PROMLIB
>> 676 select FW_ARC
>> 677 select FW_ARC32
>> 678 select ARCH_MIGHT_HAVE_PC_SERIO
>> 679 select BOOT_ELF32
>> 680 select CEVT_R4K
>> 681 select CSRC_R4K
>> 682 select DEFAULT_SGI_PARTITION
>> 683 select DMA_NONCOHERENT
>> 684 select HAVE_EISA
>> 685 select I8253
>> 686 select I8259
>> 687 select IP22_CPU_SCACHE
>> 688 select IRQ_MIPS_CPU
>> 689 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 690 select SGI_HAS_I8042
>> 691 select SGI_HAS_INDYDOG
>> 692 select SGI_HAS_HAL2
>> 693 select SGI_HAS_SEEQ
>> 694 select SGI_HAS_WD93
>> 695 select SGI_HAS_ZILOG
>> 696 select SWAP_IO_SPACE
>> 697 select SYS_HAS_CPU_R4X00
>> 698 select SYS_HAS_CPU_R5000
>> 699 select SYS_HAS_EARLY_PRINTK
>> 700 select SYS_SUPPORTS_32BIT_KERNEL
>> 701 select SYS_SUPPORTS_64BIT_KERNEL
>> 702 select SYS_SUPPORTS_BIG_ENDIAN
>> 703 select WAR_R4600_V1_INDEX_ICACHEOP
>> 704 select WAR_R4600_V1_HIT_CACHEOP
>> 705 select WAR_R4600_V2_HIT_CACHEOP
>> 706 select MIPS_L1_CACHE_SHIFT_7
>> 707 help
>> 708 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 709 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 710 that runs on these, say Y here.
>> 711
>> 712 config SGI_IP27
>> 713 bool "SGI IP27 (Origin200/2000)"
>> 714 select ARCH_HAS_PHYS_TO_DMA
>> 715 select ARCH_SPARSEMEM_ENABLE
>> 716 select FW_ARC
>> 717 select FW_ARC64
>> 718 select ARC_CMDLINE_ONLY
>> 719 select BOOT_ELF64
>> 720 select DEFAULT_SGI_PARTITION
>> 721 select FORCE_PCI
>> 722 select SYS_HAS_EARLY_PRINTK
>> 723 select HAVE_PCI
>> 724 select IRQ_MIPS_CPU
>> 725 select IRQ_DOMAIN_HIERARCHY
>> 726 select NR_CPUS_DEFAULT_64
>> 727 select PCI_DRIVERS_GENERIC
>> 728 select PCI_XTALK_BRIDGE
>> 729 select SYS_HAS_CPU_R10000
>> 730 select SYS_SUPPORTS_64BIT_KERNEL
>> 731 select SYS_SUPPORTS_BIG_ENDIAN
>> 732 select SYS_SUPPORTS_NUMA
>> 733 select SYS_SUPPORTS_SMP
>> 734 select WAR_R10000_LLSC
>> 735 select MIPS_L1_CACHE_SHIFT_7
>> 736 select NUMA
>> 737 help
>> 738 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 739 workstations. To compile a Linux kernel that runs on these, say Y
>> 740 here.
>> 741
>> 742 config SGI_IP28
>> 743 bool "SGI IP28 (Indigo2 R10k)"
>> 744 select ARC_MEMORY
>> 745 select ARC_PROMLIB
>> 746 select FW_ARC
>> 747 select FW_ARC64
>> 748 select ARCH_MIGHT_HAVE_PC_SERIO
>> 749 select BOOT_ELF64
>> 750 select CEVT_R4K
>> 751 select CSRC_R4K
>> 752 select DEFAULT_SGI_PARTITION
>> 753 select DMA_NONCOHERENT
>> 754 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 755 select IRQ_MIPS_CPU
>> 756 select HAVE_EISA
>> 757 select I8253
>> 758 select I8259
>> 759 select SGI_HAS_I8042
>> 760 select SGI_HAS_INDYDOG
>> 761 select SGI_HAS_HAL2
>> 762 select SGI_HAS_SEEQ
>> 763 select SGI_HAS_WD93
>> 764 select SGI_HAS_ZILOG
>> 765 select SWAP_IO_SPACE
>> 766 select SYS_HAS_CPU_R10000
>> 767 select SYS_HAS_EARLY_PRINTK
>> 768 select SYS_SUPPORTS_64BIT_KERNEL
>> 769 select SYS_SUPPORTS_BIG_ENDIAN
>> 770 select WAR_R10000_LLSC
>> 771 select MIPS_L1_CACHE_SHIFT_7
>> 772 help
>> 773 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 774 kernel that runs on these, say Y here.
>> 775
>> 776 config SGI_IP30
>> 777 bool "SGI IP30 (Octane/Octane2)"
>> 778 select ARCH_HAS_PHYS_TO_DMA
>> 779 select FW_ARC
>> 780 select FW_ARC64
>> 781 select BOOT_ELF64
>> 782 select CEVT_R4K
>> 783 select CSRC_R4K
>> 784 select FORCE_PCI
>> 785 select SYNC_R4K if SMP
>> 786 select ZONE_DMA32
>> 787 select HAVE_PCI
>> 788 select IRQ_MIPS_CPU
>> 789 select IRQ_DOMAIN_HIERARCHY
>> 790 select NR_CPUS_DEFAULT_2
>> 791 select PCI_DRIVERS_GENERIC
>> 792 select PCI_XTALK_BRIDGE
>> 793 select SYS_HAS_EARLY_PRINTK
>> 794 select SYS_HAS_CPU_R10000
>> 795 select SYS_SUPPORTS_64BIT_KERNEL
>> 796 select SYS_SUPPORTS_BIG_ENDIAN
>> 797 select SYS_SUPPORTS_SMP
>> 798 select WAR_R10000_LLSC
>> 799 select MIPS_L1_CACHE_SHIFT_7
>> 800 select ARC_MEMORY
>> 801 help
>> 802 These are the SGI Octane and Octane2 graphics workstations. To
>> 803 compile a Linux kernel that runs on these, say Y here.
>> 804
>> 805 config SGI_IP32
>> 806 bool "SGI IP32 (O2)"
>> 807 select ARC_MEMORY
>> 808 select ARC_PROMLIB
>> 809 select ARCH_HAS_PHYS_TO_DMA
>> 810 select FW_ARC
>> 811 select FW_ARC32
>> 812 select BOOT_ELF32
>> 813 select CEVT_R4K
>> 814 select CSRC_R4K
>> 815 select DMA_NONCOHERENT
>> 816 select HAVE_PCI
>> 817 select IRQ_MIPS_CPU
>> 818 select R5000_CPU_SCACHE
>> 819 select RM7000_CPU_SCACHE
>> 820 select SYS_HAS_CPU_R5000
>> 821 select SYS_HAS_CPU_R10000 if BROKEN
>> 822 select SYS_HAS_CPU_RM7000
>> 823 select SYS_HAS_CPU_NEVADA
>> 824 select SYS_SUPPORTS_64BIT_KERNEL
>> 825 select SYS_SUPPORTS_BIG_ENDIAN
>> 826 select WAR_ICACHE_REFILLS
>> 827 help
>> 828 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 829
>> 830 config SIBYTE_CRHINE
>> 831 bool "Sibyte BCM91120C-CRhine"
>> 832 select BOOT_ELF32
>> 833 select SIBYTE_BCM1120
>> 834 select SWAP_IO_SPACE
>> 835 select SYS_HAS_CPU_SB1
>> 836 select SYS_SUPPORTS_BIG_ENDIAN
>> 837 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 838
>> 839 config SIBYTE_CARMEL
>> 840 bool "Sibyte BCM91120x-Carmel"
>> 841 select BOOT_ELF32
>> 842 select SIBYTE_BCM1120
>> 843 select SWAP_IO_SPACE
>> 844 select SYS_HAS_CPU_SB1
>> 845 select SYS_SUPPORTS_BIG_ENDIAN
>> 846 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 847
>> 848 config SIBYTE_CRHONE
>> 849 bool "Sibyte BCM91125C-CRhone"
>> 850 select BOOT_ELF32
>> 851 select SIBYTE_BCM1125
>> 852 select SWAP_IO_SPACE
>> 853 select SYS_HAS_CPU_SB1
>> 854 select SYS_SUPPORTS_BIG_ENDIAN
>> 855 select SYS_SUPPORTS_HIGHMEM
>> 856 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 857
>> 858 config SIBYTE_RHONE
>> 859 bool "Sibyte BCM91125E-Rhone"
>> 860 select BOOT_ELF32
>> 861 select SIBYTE_BCM1125H
>> 862 select SWAP_IO_SPACE
>> 863 select SYS_HAS_CPU_SB1
>> 864 select SYS_SUPPORTS_BIG_ENDIAN
>> 865 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 866
>> 867 config SIBYTE_SWARM
>> 868 bool "Sibyte BCM91250A-SWARM"
>> 869 select BOOT_ELF32
>> 870 select HAVE_PATA_PLATFORM
>> 871 select SIBYTE_SB1250
>> 872 select SWAP_IO_SPACE
>> 873 select SYS_HAS_CPU_SB1
>> 874 select SYS_SUPPORTS_BIG_ENDIAN
>> 875 select SYS_SUPPORTS_HIGHMEM
>> 876 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 877 select ZONE_DMA32 if 64BIT
>> 878 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 879
>> 880 config SIBYTE_LITTLESUR
>> 881 bool "Sibyte BCM91250C2-LittleSur"
>> 882 select BOOT_ELF32
>> 883 select HAVE_PATA_PLATFORM
>> 884 select SIBYTE_SB1250
>> 885 select SWAP_IO_SPACE
>> 886 select SYS_HAS_CPU_SB1
>> 887 select SYS_SUPPORTS_BIG_ENDIAN
>> 888 select SYS_SUPPORTS_HIGHMEM
>> 889 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 890 select ZONE_DMA32 if 64BIT
>> 891
>> 892 config SIBYTE_SENTOSA
>> 893 bool "Sibyte BCM91250E-Sentosa"
>> 894 select BOOT_ELF32
>> 895 select SIBYTE_SB1250
>> 896 select SWAP_IO_SPACE
>> 897 select SYS_HAS_CPU_SB1
>> 898 select SYS_SUPPORTS_BIG_ENDIAN
>> 899 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 900 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 901
>> 902 config SIBYTE_BIGSUR
>> 903 bool "Sibyte BCM91480B-BigSur"
>> 904 select BOOT_ELF32
>> 905 select NR_CPUS_DEFAULT_4
>> 906 select SIBYTE_BCM1x80
>> 907 select SWAP_IO_SPACE
>> 908 select SYS_HAS_CPU_SB1
>> 909 select SYS_SUPPORTS_BIG_ENDIAN
>> 910 select SYS_SUPPORTS_HIGHMEM
>> 911 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 912 select ZONE_DMA32 if 64BIT
>> 913 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 914
>> 915 config SNI_RM
>> 916 bool "SNI RM200/300/400"
>> 917 select ARC_MEMORY
>> 918 select ARC_PROMLIB
>> 919 select FW_ARC if CPU_LITTLE_ENDIAN
>> 920 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 921 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 922 select ARCH_MAY_HAVE_PC_FDC
>> 923 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 924 select ARCH_MIGHT_HAVE_PC_SERIO
>> 925 select BOOT_ELF32
>> 926 select CEVT_R4K
>> 927 select CSRC_R4K
>> 928 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 929 select DMA_NONCOHERENT
>> 930 select GENERIC_ISA_DMA
>> 931 select HAVE_EISA
>> 932 select HAVE_PCSPKR_PLATFORM
>> 933 select HAVE_PCI
>> 934 select IRQ_MIPS_CPU
>> 935 select I8253
>> 936 select I8259
>> 937 select ISA
>> 938 select MIPS_L1_CACHE_SHIFT_6
>> 939 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 940 select SYS_HAS_CPU_R4X00
>> 941 select SYS_HAS_CPU_R5000
>> 942 select SYS_HAS_CPU_R10000
>> 943 select R5000_CPU_SCACHE
>> 944 select SYS_HAS_EARLY_PRINTK
>> 945 select SYS_SUPPORTS_32BIT_KERNEL
>> 946 select SYS_SUPPORTS_64BIT_KERNEL
>> 947 select SYS_SUPPORTS_BIG_ENDIAN
>> 948 select SYS_SUPPORTS_HIGHMEM
>> 949 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 950 select WAR_R4600_V2_HIT_CACHEOP
>> 951 help
>> 952 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 953 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 954 Technology and now in turn merged with Fujitsu. Say Y here to
>> 955 support this machine type.
>> 956
>> 957 config MACH_TX39XX
>> 958 bool "Toshiba TX39 series based machines"
>> 959
>> 960 config MACH_TX49XX
>> 961 bool "Toshiba TX49 series based machines"
>> 962 select WAR_TX49XX_ICACHE_INDEX_INV
>> 963
>> 964 config MIKROTIK_RB532
>> 965 bool "Mikrotik RB532 boards"
>> 966 select CEVT_R4K
>> 967 select CSRC_R4K
>> 968 select DMA_NONCOHERENT
>> 969 select HAVE_PCI
>> 970 select IRQ_MIPS_CPU
>> 971 select SYS_HAS_CPU_MIPS32_R1
>> 972 select SYS_SUPPORTS_32BIT_KERNEL
>> 973 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 974 select SWAP_IO_SPACE
>> 975 select BOOT_RAW
>> 976 select GPIOLIB
>> 977 select MIPS_L1_CACHE_SHIFT_4
>> 978 help
>> 979 Support the Mikrotik(tm) RouterBoard 532 series,
>> 980 based on the IDT RC32434 SoC.
>> 981
>> 982 config CAVIUM_OCTEON_SOC
>> 983 bool "Cavium Networks Octeon SoC based boards"
>> 984 select CEVT_R4K
>> 985 select ARCH_HAS_PHYS_TO_DMA
>> 986 select HAVE_RAPIDIO
>> 987 select PHYS_ADDR_T_64BIT
>> 988 select SYS_SUPPORTS_64BIT_KERNEL
>> 989 select SYS_SUPPORTS_BIG_ENDIAN
>> 990 select EDAC_SUPPORT
>> 991 select EDAC_ATOMIC_SCRUB
>> 992 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 993 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 994 select SYS_HAS_EARLY_PRINTK
>> 995 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 996 select HAVE_PCI
>> 997 select HAVE_PLAT_DELAY
>> 998 select HAVE_PLAT_FW_INIT_CMDLINE
>> 999 select HAVE_PLAT_MEMCPY
>> 1000 select ZONE_DMA32
>> 1001 select HOLES_IN_ZONE
>> 1002 select GPIOLIB
>> 1003 select USE_OF
>> 1004 select ARCH_SPARSEMEM_ENABLE
>> 1005 select SYS_SUPPORTS_SMP
>> 1006 select NR_CPUS_DEFAULT_64
>> 1007 select MIPS_NR_CPU_NR_MAP_1024
>> 1008 select BUILTIN_DTB
>> 1009 select MTD
>> 1010 select MTD_COMPLEX_MAPPINGS
>> 1011 select SWIOTLB
>> 1012 select SYS_SUPPORTS_RELOCATABLE
>> 1013 help
>> 1014 This option supports all of the Octeon reference boards from Cavium
>> 1015 Networks. It builds a kernel that dynamically determines the Octeon
>> 1016 CPU type and supports all known board reference implementations.
>> 1017 Some of the supported boards are:
>> 1018 EBT3000
>> 1019 EBH3000
>> 1020 EBH3100
>> 1021 Thunder
>> 1022 Kodama
>> 1023 Hikari
>> 1024 Say Y here for most Octeon reference boards.
>> 1025
>> 1026 config NLM_XLR_BOARD
>> 1027 bool "Netlogic XLR/XLS based systems"
>> 1028 select BOOT_ELF32
>> 1029 select NLM_COMMON
>> 1030 select SYS_HAS_CPU_XLR
>> 1031 select SYS_SUPPORTS_SMP
>> 1032 select HAVE_PCI
>> 1033 select SWAP_IO_SPACE
>> 1034 select SYS_SUPPORTS_32BIT_KERNEL
>> 1035 select SYS_SUPPORTS_64BIT_KERNEL
>> 1036 select PHYS_ADDR_T_64BIT
>> 1037 select SYS_SUPPORTS_BIG_ENDIAN
>> 1038 select SYS_SUPPORTS_HIGHMEM
>> 1039 select NR_CPUS_DEFAULT_32
>> 1040 select CEVT_R4K
>> 1041 select CSRC_R4K
>> 1042 select IRQ_MIPS_CPU
>> 1043 select ZONE_DMA32 if 64BIT
>> 1044 select SYNC_R4K
>> 1045 select SYS_HAS_EARLY_PRINTK
>> 1046 select SYS_SUPPORTS_ZBOOT
>> 1047 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1048 help
>> 1049 Support for systems based on Netlogic XLR and XLS processors.
>> 1050 Say Y here if you have a XLR or XLS based board.
>> 1051
>> 1052 config NLM_XLP_BOARD
>> 1053 bool "Netlogic XLP based systems"
>> 1054 select BOOT_ELF32
>> 1055 select NLM_COMMON
>> 1056 select SYS_HAS_CPU_XLP
>> 1057 select SYS_SUPPORTS_SMP
>> 1058 select HAVE_PCI
>> 1059 select SYS_SUPPORTS_32BIT_KERNEL
>> 1060 select SYS_SUPPORTS_64BIT_KERNEL
>> 1061 select PHYS_ADDR_T_64BIT
>> 1062 select GPIOLIB
>> 1063 select SYS_SUPPORTS_BIG_ENDIAN
>> 1064 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1065 select SYS_SUPPORTS_HIGHMEM
>> 1066 select NR_CPUS_DEFAULT_32
>> 1067 select CEVT_R4K
>> 1068 select CSRC_R4K
>> 1069 select IRQ_MIPS_CPU
>> 1070 select ZONE_DMA32 if 64BIT
>> 1071 select SYNC_R4K
>> 1072 select SYS_HAS_EARLY_PRINTK
>> 1073 select USE_OF
>> 1074 select SYS_SUPPORTS_ZBOOT
>> 1075 select SYS_SUPPORTS_ZBOOT_UART16550
60 help 1076 help
61 Xtensa processors are 32-bit RISC ma !! 1077 This board is based on Netlogic XLP Processor.
62 primarily for embedded systems. The !! 1078 Say Y here if you have a XLP based board.
63 configurable and extensible. The Li !! 1079
64 architecture supports all processor !! 1080 endchoice
65 with reasonable minimum requirements !! 1081
66 a home page at <http://www.linux-xte !! 1082 source "arch/mips/alchemy/Kconfig"
>> 1083 source "arch/mips/ath25/Kconfig"
>> 1084 source "arch/mips/ath79/Kconfig"
>> 1085 source "arch/mips/bcm47xx/Kconfig"
>> 1086 source "arch/mips/bcm63xx/Kconfig"
>> 1087 source "arch/mips/bmips/Kconfig"
>> 1088 source "arch/mips/generic/Kconfig"
>> 1089 source "arch/mips/ingenic/Kconfig"
>> 1090 source "arch/mips/jazz/Kconfig"
>> 1091 source "arch/mips/lantiq/Kconfig"
>> 1092 source "arch/mips/pic32/Kconfig"
>> 1093 source "arch/mips/pistachio/Kconfig"
>> 1094 source "arch/mips/ralink/Kconfig"
>> 1095 source "arch/mips/sgi-ip27/Kconfig"
>> 1096 source "arch/mips/sibyte/Kconfig"
>> 1097 source "arch/mips/txx9/Kconfig"
>> 1098 source "arch/mips/vr41xx/Kconfig"
>> 1099 source "arch/mips/cavium-octeon/Kconfig"
>> 1100 source "arch/mips/loongson2ef/Kconfig"
>> 1101 source "arch/mips/loongson32/Kconfig"
>> 1102 source "arch/mips/loongson64/Kconfig"
>> 1103 source "arch/mips/netlogic/Kconfig"
>> 1104
>> 1105 endmenu
67 1106
68 config GENERIC_HWEIGHT 1107 config GENERIC_HWEIGHT
69 def_bool y !! 1108 bool
>> 1109 default y
70 1110
71 config ARCH_HAS_ILOG2_U32 !! 1111 config GENERIC_CALIBRATE_DELAY
72 def_bool n !! 1112 bool
>> 1113 default y
73 1114
74 config ARCH_HAS_ILOG2_U64 !! 1115 config SCHED_OMIT_FRAME_POINTER
75 def_bool n !! 1116 bool
>> 1117 default y
76 1118
77 config ARCH_MTD_XIP !! 1119 #
78 def_bool y !! 1120 # Select some configuration options automatically based on user selections.
>> 1121 #
>> 1122 config FW_ARC
>> 1123 bool
>> 1124
>> 1125 config ARCH_MAY_HAVE_PC_FDC
>> 1126 bool
>> 1127
>> 1128 config BOOT_RAW
>> 1129 bool
>> 1130
>> 1131 config CEVT_BCM1480
>> 1132 bool
>> 1133
>> 1134 config CEVT_DS1287
>> 1135 bool
>> 1136
>> 1137 config CEVT_GT641XX
>> 1138 bool
>> 1139
>> 1140 config CEVT_R4K
>> 1141 bool
>> 1142
>> 1143 config CEVT_SB1250
>> 1144 bool
>> 1145
>> 1146 config CEVT_TXX9
>> 1147 bool
>> 1148
>> 1149 config CSRC_BCM1480
>> 1150 bool
>> 1151
>> 1152 config CSRC_IOASIC
>> 1153 bool
>> 1154
>> 1155 config CSRC_R4K
>> 1156 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1157 bool
>> 1158
>> 1159 config CSRC_SB1250
>> 1160 bool
>> 1161
>> 1162 config MIPS_CLOCK_VSYSCALL
>> 1163 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1164
>> 1165 config GPIO_TXX9
>> 1166 select GPIOLIB
>> 1167 bool
>> 1168
>> 1169 config FW_CFE
>> 1170 bool
>> 1171
>> 1172 config ARCH_SUPPORTS_UPROBES
>> 1173 bool
>> 1174
>> 1175 config DMA_PERDEV_COHERENT
>> 1176 bool
>> 1177 select ARCH_HAS_SETUP_DMA_OPS
>> 1178 select DMA_NONCOHERENT
>> 1179
>> 1180 config DMA_NONCOHERENT
>> 1181 bool
>> 1182 #
>> 1183 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1184 # Attribute bits. It is believed that the uncached access through
>> 1185 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1186 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1187 # significant advantages.
>> 1188 #
>> 1189 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1190 select ARCH_HAS_DMA_PREP_COHERENT
>> 1191 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1192 select ARCH_HAS_DMA_SET_UNCACHED
>> 1193 select DMA_NONCOHERENT_MMAP
>> 1194 select NEED_DMA_MAP_STATE
>> 1195
>> 1196 config SYS_HAS_EARLY_PRINTK
>> 1197 bool
>> 1198
>> 1199 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1200 bool
>> 1201
>> 1202 config MIPS_BONITO64
>> 1203 bool
>> 1204
>> 1205 config MIPS_MSC
>> 1206 bool
>> 1207
>> 1208 config SYNC_R4K
>> 1209 bool
79 1210
80 config NO_IOPORT_MAP 1211 config NO_IOPORT_MAP
81 def_bool n 1212 def_bool n
82 1213
83 config HZ !! 1214 config GENERIC_CSUM
84 int !! 1215 def_bool CPU_NO_LOAD_STORE_LR
85 default 100 <<
86 1216
87 config LOCKDEP_SUPPORT !! 1217 config GENERIC_ISA_DMA
88 def_bool y !! 1218 bool
>> 1219 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1220 select ISA_DMA_API
89 1221
90 config STACKTRACE_SUPPORT !! 1222 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1223 bool
>> 1224 select GENERIC_ISA_DMA
>> 1225
>> 1226 config HAVE_PLAT_DELAY
>> 1227 bool
>> 1228
>> 1229 config HAVE_PLAT_FW_INIT_CMDLINE
>> 1230 bool
>> 1231
>> 1232 config HAVE_PLAT_MEMCPY
>> 1233 bool
>> 1234
>> 1235 config ISA_DMA_API
>> 1236 bool
>> 1237
>> 1238 config HOLES_IN_ZONE
>> 1239 bool
>> 1240
>> 1241 config SYS_SUPPORTS_RELOCATABLE
>> 1242 bool
>> 1243 help
>> 1244 Selected if the platform supports relocating the kernel.
>> 1245 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1246 to allow access to command line and entropy sources.
>> 1247
>> 1248 config MIPS_CBPF_JIT
91 def_bool y 1249 def_bool y
>> 1250 depends on BPF_JIT && HAVE_CBPF_JIT
92 1251
93 config MMU !! 1252 config MIPS_EBPF_JIT
94 def_bool n !! 1253 def_bool y
95 select PFAULT !! 1254 depends on BPF_JIT && HAVE_EBPF_JIT
96 1255
97 config HAVE_XTENSA_GPIO32 <<
98 def_bool n <<
99 1256
100 config KASAN_SHADOW_OFFSET !! 1257 #
101 hex !! 1258 # Endianness selection. Sufficiently obscure so many users don't know what to
102 default 0x6e400000 !! 1259 # answer,so we try hard to limit the available choices. Also the use of a
>> 1260 # choice statement should be more obvious to the user.
>> 1261 #
>> 1262 choice
>> 1263 prompt "Endianness selection"
>> 1264 help
>> 1265 Some MIPS machines can be configured for either little or big endian
>> 1266 byte order. These modes require different kernels and a different
>> 1267 Linux distribution. In general there is one preferred byteorder for a
>> 1268 particular system but some systems are just as commonly used in the
>> 1269 one or the other endianness.
103 1270
104 config CPU_BIG_ENDIAN 1271 config CPU_BIG_ENDIAN
105 def_bool $(success,test "$(shell,echo !! 1272 bool "Big endian"
>> 1273 depends on SYS_SUPPORTS_BIG_ENDIAN
106 1274
107 config CPU_LITTLE_ENDIAN 1275 config CPU_LITTLE_ENDIAN
108 def_bool !CPU_BIG_ENDIAN !! 1276 bool "Little endian"
>> 1277 depends on SYS_SUPPORTS_LITTLE_ENDIAN
>> 1278
>> 1279 endchoice
>> 1280
>> 1281 config EXPORT_UASM
>> 1282 bool
>> 1283
>> 1284 config SYS_SUPPORTS_APM_EMULATION
>> 1285 bool
>> 1286
>> 1287 config SYS_SUPPORTS_BIG_ENDIAN
>> 1288 bool
>> 1289
>> 1290 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1291 bool
>> 1292
>> 1293 config MIPS_HUGE_TLB_SUPPORT
>> 1294 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
>> 1295
>> 1296 config IRQ_MSP_SLP
>> 1297 bool
>> 1298
>> 1299 config IRQ_MSP_CIC
>> 1300 bool
>> 1301
>> 1302 config IRQ_TXX9
>> 1303 bool
>> 1304
>> 1305 config IRQ_GT641XX
>> 1306 bool
>> 1307
>> 1308 config PCI_GT64XXX_PCI0
>> 1309 bool
>> 1310
>> 1311 config PCI_XTALK_BRIDGE
>> 1312 bool
>> 1313
>> 1314 config NO_EXCEPT_FILL
>> 1315 bool
>> 1316
>> 1317 config MIPS_SPRAM
>> 1318 bool
>> 1319
>> 1320 config SWAP_IO_SPACE
>> 1321 bool
>> 1322
>> 1323 config SGI_HAS_INDYDOG
>> 1324 bool
>> 1325
>> 1326 config SGI_HAS_HAL2
>> 1327 bool
>> 1328
>> 1329 config SGI_HAS_SEEQ
>> 1330 bool
109 1331
110 config CC_HAVE_CALL0_ABI !! 1332 config SGI_HAS_WD93
111 def_bool $(success,test "$(shell,echo !! 1333 bool
>> 1334
>> 1335 config SGI_HAS_ZILOG
>> 1336 bool
112 1337
113 menu "Processor type and features" !! 1338 config SGI_HAS_I8042
>> 1339 bool
>> 1340
>> 1341 config DEFAULT_SGI_PARTITION
>> 1342 bool
>> 1343
>> 1344 config FW_ARC32
>> 1345 bool
>> 1346
>> 1347 config FW_SNIPROM
>> 1348 bool
>> 1349
>> 1350 config BOOT_ELF32
>> 1351 bool
>> 1352
>> 1353 config MIPS_L1_CACHE_SHIFT_4
>> 1354 bool
>> 1355
>> 1356 config MIPS_L1_CACHE_SHIFT_5
>> 1357 bool
>> 1358
>> 1359 config MIPS_L1_CACHE_SHIFT_6
>> 1360 bool
>> 1361
>> 1362 config MIPS_L1_CACHE_SHIFT_7
>> 1363 bool
>> 1364
>> 1365 config MIPS_L1_CACHE_SHIFT
>> 1366 int
>> 1367 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1368 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1369 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1370 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1371 default "5"
>> 1372
>> 1373 config ARC_CMDLINE_ONLY
>> 1374 bool
>> 1375
>> 1376 config ARC_CONSOLE
>> 1377 bool "ARC console support"
>> 1378 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
>> 1379
>> 1380 config ARC_MEMORY
>> 1381 bool
>> 1382
>> 1383 config ARC_PROMLIB
>> 1384 bool
>> 1385
>> 1386 config FW_ARC64
>> 1387 bool
>> 1388
>> 1389 config BOOT_ELF64
>> 1390 bool
>> 1391
>> 1392 menu "CPU selection"
114 1393
115 choice 1394 choice
116 prompt "Xtensa Processor Configuration !! 1395 prompt "CPU type"
117 default XTENSA_VARIANT_FSF !! 1396 default CPU_R4X00
118 1397
119 config XTENSA_VARIANT_FSF !! 1398 config CPU_LOONGSON64
120 bool "fsf - default (not generic) conf !! 1399 bool "Loongson 64-bit CPU"
121 select MMU !! 1400 depends on SYS_HAS_CPU_LOONGSON64
>> 1401 select ARCH_HAS_PHYS_TO_DMA
>> 1402 select CPU_MIPSR2
>> 1403 select CPU_HAS_PREFETCH
>> 1404 select CPU_SUPPORTS_64BIT_KERNEL
>> 1405 select CPU_SUPPORTS_HIGHMEM
>> 1406 select CPU_SUPPORTS_HUGEPAGES
>> 1407 select CPU_SUPPORTS_MSA
>> 1408 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1409 select CPU_MIPSR2_IRQ_VI
>> 1410 select WEAK_ORDERING
>> 1411 select WEAK_REORDERING_BEYOND_LLSC
>> 1412 select MIPS_ASID_BITS_VARIABLE
>> 1413 select MIPS_PGD_C0_CONTEXT
>> 1414 select MIPS_L1_CACHE_SHIFT_6
>> 1415 select GPIOLIB
>> 1416 select SWIOTLB
>> 1417 select HAVE_KVM
>> 1418 help
>> 1419 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1420 cores implements the MIPS64R2 instruction set with many extensions,
>> 1421 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1422 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1423 Loongson-2E/2F is not covered here and will be removed in future.
122 1424
123 config XTENSA_VARIANT_DC232B !! 1425 config LOONGSON3_ENHANCEMENT
124 bool "dc232b - Diamond 232L Standard C !! 1426 bool "New Loongson-3 CPU Enhancements"
125 select MMU !! 1427 default n
126 select HAVE_XTENSA_GPIO32 !! 1428 depends on CPU_LOONGSON64
127 help 1429 help
128 This variant refers to Tensilica's D !! 1430 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1431 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1432 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1433 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1434 Fast TLB refill support, etc.
>> 1435
>> 1436 This option enable those enhancements which are not probed at run
>> 1437 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1438 please say 'N' here. If you want a high-performance kernel to run on
>> 1439 new Loongson-3 machines only, please say 'Y' here.
>> 1440
>> 1441 config CPU_LOONGSON3_WORKAROUNDS
>> 1442 bool "Old Loongson-3 LLSC Workarounds"
>> 1443 default y if SMP
>> 1444 depends on CPU_LOONGSON64
>> 1445 help
>> 1446 Loongson-3 processors have the llsc issues which require workarounds.
>> 1447 Without workarounds the system may hang unexpectedly.
>> 1448
>> 1449 Newer Loongson-3 will fix these issues and no workarounds are needed.
>> 1450 The workarounds have no significant side effect on them but may
>> 1451 decrease the performance of the system so this option should be
>> 1452 disabled unless the kernel is intended to be run on old systems.
129 1453
130 config XTENSA_VARIANT_DC233C !! 1454 If unsure, please say Y.
131 bool "dc233c - Diamond 233L Standard C <<
132 select MMU <<
133 select HAVE_XTENSA_GPIO32 <<
134 help <<
135 This variant refers to Tensilica's D <<
136 1455
137 config XTENSA_VARIANT_CUSTOM !! 1456 config CPU_LOONGSON3_CPUCFG_EMULATION
138 bool "Custom Xtensa processor configur !! 1457 bool "Emulate the CPUCFG instruction on older Loongson cores"
139 select HAVE_XTENSA_GPIO32 !! 1458 default y
>> 1459 depends on CPU_LOONGSON64
>> 1460 help
>> 1461 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1462 userland to query CPU capabilities, much like CPUID on x86. This
>> 1463 option provides emulation of the instruction on older Loongson
>> 1464 cores, back to Loongson-3A1000.
>> 1465
>> 1466 If unsure, please say Y.
>> 1467
>> 1468 config CPU_LOONGSON2E
>> 1469 bool "Loongson 2E"
>> 1470 depends on SYS_HAS_CPU_LOONGSON2E
>> 1471 select CPU_LOONGSON2EF
>> 1472 help
>> 1473 The Loongson 2E processor implements the MIPS III instruction set
>> 1474 with many extensions.
>> 1475
>> 1476 It has an internal FPGA northbridge, which is compatible to
>> 1477 bonito64.
>> 1478
>> 1479 config CPU_LOONGSON2F
>> 1480 bool "Loongson 2F"
>> 1481 depends on SYS_HAS_CPU_LOONGSON2F
>> 1482 select CPU_LOONGSON2EF
>> 1483 select GPIOLIB
>> 1484 help
>> 1485 The Loongson 2F processor implements the MIPS III instruction set
>> 1486 with many extensions.
>> 1487
>> 1488 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1489 have a similar programming interface with FPGA northbridge used in
>> 1490 Loongson2E.
>> 1491
>> 1492 config CPU_LOONGSON1B
>> 1493 bool "Loongson 1B"
>> 1494 depends on SYS_HAS_CPU_LOONGSON1B
>> 1495 select CPU_LOONGSON32
>> 1496 select LEDS_GPIO_REGISTER
>> 1497 help
>> 1498 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1499 Release 1 instruction set and part of the MIPS32 Release 2
>> 1500 instruction set.
>> 1501
>> 1502 config CPU_LOONGSON1C
>> 1503 bool "Loongson 1C"
>> 1504 depends on SYS_HAS_CPU_LOONGSON1C
>> 1505 select CPU_LOONGSON32
>> 1506 select LEDS_GPIO_REGISTER
>> 1507 help
>> 1508 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1509 Release 1 instruction set and part of the MIPS32 Release 2
>> 1510 instruction set.
>> 1511
>> 1512 config CPU_MIPS32_R1
>> 1513 bool "MIPS32 Release 1"
>> 1514 depends on SYS_HAS_CPU_MIPS32_R1
>> 1515 select CPU_HAS_PREFETCH
>> 1516 select CPU_SUPPORTS_32BIT_KERNEL
>> 1517 select CPU_SUPPORTS_HIGHMEM
>> 1518 help
>> 1519 Choose this option to build a kernel for release 1 or later of the
>> 1520 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1521 MIPS processor are based on a MIPS32 processor. If you know the
>> 1522 specific type of processor in your system, choose those that one
>> 1523 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1524 Release 2 of the MIPS32 architecture is available since several
>> 1525 years so chances are you even have a MIPS32 Release 2 processor
>> 1526 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1527 performance.
>> 1528
>> 1529 config CPU_MIPS32_R2
>> 1530 bool "MIPS32 Release 2"
>> 1531 depends on SYS_HAS_CPU_MIPS32_R2
>> 1532 select CPU_HAS_PREFETCH
>> 1533 select CPU_SUPPORTS_32BIT_KERNEL
>> 1534 select CPU_SUPPORTS_HIGHMEM
>> 1535 select CPU_SUPPORTS_MSA
>> 1536 select HAVE_KVM
>> 1537 help
>> 1538 Choose this option to build a kernel for release 2 or later of the
>> 1539 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1540 MIPS processor are based on a MIPS32 processor. If you know the
>> 1541 specific type of processor in your system, choose those that one
>> 1542 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1543
>> 1544 config CPU_MIPS32_R5
>> 1545 bool "MIPS32 Release 5"
>> 1546 depends on SYS_HAS_CPU_MIPS32_R5
>> 1547 select CPU_HAS_PREFETCH
>> 1548 select CPU_SUPPORTS_32BIT_KERNEL
>> 1549 select CPU_SUPPORTS_HIGHMEM
>> 1550 select CPU_SUPPORTS_MSA
>> 1551 select HAVE_KVM
>> 1552 select MIPS_O32_FP64_SUPPORT
>> 1553 help
>> 1554 Choose this option to build a kernel for release 5 or later of the
>> 1555 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1556 family, are based on a MIPS32r5 processor. If you own an older
>> 1557 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1558
>> 1559 config CPU_MIPS32_R6
>> 1560 bool "MIPS32 Release 6"
>> 1561 depends on SYS_HAS_CPU_MIPS32_R6
>> 1562 select CPU_HAS_PREFETCH
>> 1563 select CPU_NO_LOAD_STORE_LR
>> 1564 select CPU_SUPPORTS_32BIT_KERNEL
>> 1565 select CPU_SUPPORTS_HIGHMEM
>> 1566 select CPU_SUPPORTS_MSA
>> 1567 select HAVE_KVM
>> 1568 select MIPS_O32_FP64_SUPPORT
>> 1569 help
>> 1570 Choose this option to build a kernel for release 6 or later of the
>> 1571 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1572 family, are based on a MIPS32r6 processor. If you own an older
>> 1573 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1574
>> 1575 config CPU_MIPS64_R1
>> 1576 bool "MIPS64 Release 1"
>> 1577 depends on SYS_HAS_CPU_MIPS64_R1
>> 1578 select CPU_HAS_PREFETCH
>> 1579 select CPU_SUPPORTS_32BIT_KERNEL
>> 1580 select CPU_SUPPORTS_64BIT_KERNEL
>> 1581 select CPU_SUPPORTS_HIGHMEM
>> 1582 select CPU_SUPPORTS_HUGEPAGES
>> 1583 help
>> 1584 Choose this option to build a kernel for release 1 or later of the
>> 1585 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1586 MIPS processor are based on a MIPS64 processor. If you know the
>> 1587 specific type of processor in your system, choose those that one
>> 1588 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1589 Release 2 of the MIPS64 architecture is available since several
>> 1590 years so chances are you even have a MIPS64 Release 2 processor
>> 1591 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1592 performance.
>> 1593
>> 1594 config CPU_MIPS64_R2
>> 1595 bool "MIPS64 Release 2"
>> 1596 depends on SYS_HAS_CPU_MIPS64_R2
>> 1597 select CPU_HAS_PREFETCH
>> 1598 select CPU_SUPPORTS_32BIT_KERNEL
>> 1599 select CPU_SUPPORTS_64BIT_KERNEL
>> 1600 select CPU_SUPPORTS_HIGHMEM
>> 1601 select CPU_SUPPORTS_HUGEPAGES
>> 1602 select CPU_SUPPORTS_MSA
>> 1603 select HAVE_KVM
>> 1604 help
>> 1605 Choose this option to build a kernel for release 2 or later of the
>> 1606 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1607 MIPS processor are based on a MIPS64 processor. If you know the
>> 1608 specific type of processor in your system, choose those that one
>> 1609 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1610
>> 1611 config CPU_MIPS64_R5
>> 1612 bool "MIPS64 Release 5"
>> 1613 depends on SYS_HAS_CPU_MIPS64_R5
>> 1614 select CPU_HAS_PREFETCH
>> 1615 select CPU_SUPPORTS_32BIT_KERNEL
>> 1616 select CPU_SUPPORTS_64BIT_KERNEL
>> 1617 select CPU_SUPPORTS_HIGHMEM
>> 1618 select CPU_SUPPORTS_HUGEPAGES
>> 1619 select CPU_SUPPORTS_MSA
>> 1620 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1621 select HAVE_KVM
>> 1622 help
>> 1623 Choose this option to build a kernel for release 5 or later of the
>> 1624 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1625 release partly implementing release 6 features. Though there is no
>> 1626 any hardware known to be based on this release.
>> 1627
>> 1628 config CPU_MIPS64_R6
>> 1629 bool "MIPS64 Release 6"
>> 1630 depends on SYS_HAS_CPU_MIPS64_R6
>> 1631 select CPU_HAS_PREFETCH
>> 1632 select CPU_NO_LOAD_STORE_LR
>> 1633 select CPU_SUPPORTS_32BIT_KERNEL
>> 1634 select CPU_SUPPORTS_64BIT_KERNEL
>> 1635 select CPU_SUPPORTS_HIGHMEM
>> 1636 select CPU_SUPPORTS_HUGEPAGES
>> 1637 select CPU_SUPPORTS_MSA
>> 1638 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1639 select HAVE_KVM
>> 1640 help
>> 1641 Choose this option to build a kernel for release 6 or later of the
>> 1642 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1643 family, are based on a MIPS64r6 processor. If you own an older
>> 1644 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1645
>> 1646 config CPU_P5600
>> 1647 bool "MIPS Warrior P5600"
>> 1648 depends on SYS_HAS_CPU_P5600
>> 1649 select CPU_HAS_PREFETCH
>> 1650 select CPU_SUPPORTS_32BIT_KERNEL
>> 1651 select CPU_SUPPORTS_HIGHMEM
>> 1652 select CPU_SUPPORTS_MSA
>> 1653 select CPU_SUPPORTS_CPUFREQ
>> 1654 select CPU_MIPSR2_IRQ_VI
>> 1655 select CPU_MIPSR2_IRQ_EI
>> 1656 select HAVE_KVM
>> 1657 select MIPS_O32_FP64_SUPPORT
>> 1658 help
>> 1659 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1660 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1661 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1662 level features like up to six P5600 calculation cores, CM2 with L2
>> 1663 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1664 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1665 eJTAG and PDtrace.
>> 1666
>> 1667 config CPU_R3000
>> 1668 bool "R3000"
>> 1669 depends on SYS_HAS_CPU_R3000
>> 1670 select CPU_HAS_WB
>> 1671 select CPU_R3K_TLB
>> 1672 select CPU_SUPPORTS_32BIT_KERNEL
>> 1673 select CPU_SUPPORTS_HIGHMEM
>> 1674 help
>> 1675 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1676 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1677 *not* work on R4000 machines and vice versa. However, since most
>> 1678 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1679 might be a safe bet. If the resulting kernel does not work,
>> 1680 try to recompile with R3000.
>> 1681
>> 1682 config CPU_TX39XX
>> 1683 bool "R39XX"
>> 1684 depends on SYS_HAS_CPU_TX39XX
>> 1685 select CPU_SUPPORTS_32BIT_KERNEL
>> 1686 select CPU_R3K_TLB
>> 1687
>> 1688 config CPU_VR41XX
>> 1689 bool "R41xx"
>> 1690 depends on SYS_HAS_CPU_VR41XX
>> 1691 select CPU_SUPPORTS_32BIT_KERNEL
>> 1692 select CPU_SUPPORTS_64BIT_KERNEL
>> 1693 help
>> 1694 The options selects support for the NEC VR4100 series of processors.
>> 1695 Only choose this option if you have one of these processors as a
>> 1696 kernel built with this option will not run on any other type of
>> 1697 processor or vice versa.
>> 1698
>> 1699 config CPU_R4300
>> 1700 bool "R4300"
>> 1701 depends on SYS_HAS_CPU_R4300
>> 1702 select CPU_SUPPORTS_32BIT_KERNEL
>> 1703 select CPU_SUPPORTS_64BIT_KERNEL
>> 1704 select CPU_HAS_LOAD_STORE_LR
>> 1705 help
>> 1706 MIPS Technologies R4300-series processors.
>> 1707
>> 1708 config CPU_R4X00
>> 1709 bool "R4x00"
>> 1710 depends on SYS_HAS_CPU_R4X00
>> 1711 select CPU_SUPPORTS_32BIT_KERNEL
>> 1712 select CPU_SUPPORTS_64BIT_KERNEL
>> 1713 select CPU_SUPPORTS_HUGEPAGES
>> 1714 help
>> 1715 MIPS Technologies R4000-series processors other than 4300, including
>> 1716 the R4000, R4400, R4600, and 4700.
>> 1717
>> 1718 config CPU_TX49XX
>> 1719 bool "R49XX"
>> 1720 depends on SYS_HAS_CPU_TX49XX
>> 1721 select CPU_HAS_PREFETCH
>> 1722 select CPU_SUPPORTS_32BIT_KERNEL
>> 1723 select CPU_SUPPORTS_64BIT_KERNEL
>> 1724 select CPU_SUPPORTS_HUGEPAGES
>> 1725
>> 1726 config CPU_R5000
>> 1727 bool "R5000"
>> 1728 depends on SYS_HAS_CPU_R5000
>> 1729 select CPU_SUPPORTS_32BIT_KERNEL
>> 1730 select CPU_SUPPORTS_64BIT_KERNEL
>> 1731 select CPU_SUPPORTS_HUGEPAGES
>> 1732 help
>> 1733 MIPS Technologies R5000-series processors other than the Nevada.
>> 1734
>> 1735 config CPU_R5500
>> 1736 bool "R5500"
>> 1737 depends on SYS_HAS_CPU_R5500
>> 1738 select CPU_SUPPORTS_32BIT_KERNEL
>> 1739 select CPU_SUPPORTS_64BIT_KERNEL
>> 1740 select CPU_SUPPORTS_HUGEPAGES
>> 1741 help
>> 1742 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1743 instruction set.
>> 1744
>> 1745 config CPU_NEVADA
>> 1746 bool "RM52xx"
>> 1747 depends on SYS_HAS_CPU_NEVADA
>> 1748 select CPU_SUPPORTS_32BIT_KERNEL
>> 1749 select CPU_SUPPORTS_64BIT_KERNEL
>> 1750 select CPU_SUPPORTS_HUGEPAGES
>> 1751 help
>> 1752 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1753
>> 1754 config CPU_R10000
>> 1755 bool "R10000"
>> 1756 depends on SYS_HAS_CPU_R10000
>> 1757 select CPU_HAS_PREFETCH
>> 1758 select CPU_SUPPORTS_32BIT_KERNEL
>> 1759 select CPU_SUPPORTS_64BIT_KERNEL
>> 1760 select CPU_SUPPORTS_HIGHMEM
>> 1761 select CPU_SUPPORTS_HUGEPAGES
>> 1762 help
>> 1763 MIPS Technologies R10000-series processors.
>> 1764
>> 1765 config CPU_RM7000
>> 1766 bool "RM7000"
>> 1767 depends on SYS_HAS_CPU_RM7000
>> 1768 select CPU_HAS_PREFETCH
>> 1769 select CPU_SUPPORTS_32BIT_KERNEL
>> 1770 select CPU_SUPPORTS_64BIT_KERNEL
>> 1771 select CPU_SUPPORTS_HIGHMEM
>> 1772 select CPU_SUPPORTS_HUGEPAGES
>> 1773
>> 1774 config CPU_SB1
>> 1775 bool "SB1"
>> 1776 depends on SYS_HAS_CPU_SB1
>> 1777 select CPU_SUPPORTS_32BIT_KERNEL
>> 1778 select CPU_SUPPORTS_64BIT_KERNEL
>> 1779 select CPU_SUPPORTS_HIGHMEM
>> 1780 select CPU_SUPPORTS_HUGEPAGES
>> 1781 select WEAK_ORDERING
>> 1782
>> 1783 config CPU_CAVIUM_OCTEON
>> 1784 bool "Cavium Octeon processor"
>> 1785 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1786 select CPU_HAS_PREFETCH
>> 1787 select CPU_SUPPORTS_64BIT_KERNEL
>> 1788 select WEAK_ORDERING
>> 1789 select CPU_SUPPORTS_HIGHMEM
>> 1790 select CPU_SUPPORTS_HUGEPAGES
>> 1791 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1792 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1793 select MIPS_L1_CACHE_SHIFT_7
>> 1794 select HAVE_KVM
>> 1795 help
>> 1796 The Cavium Octeon processor is a highly integrated chip containing
>> 1797 many ethernet hardware widgets for networking tasks. The processor
>> 1798 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1799 Full details can be found at http://www.caviumnetworks.com.
>> 1800
>> 1801 config CPU_BMIPS
>> 1802 bool "Broadcom BMIPS"
>> 1803 depends on SYS_HAS_CPU_BMIPS
>> 1804 select CPU_MIPS32
>> 1805 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1806 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1807 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1808 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1809 select CPU_SUPPORTS_32BIT_KERNEL
>> 1810 select DMA_NONCOHERENT
>> 1811 select IRQ_MIPS_CPU
>> 1812 select SWAP_IO_SPACE
>> 1813 select WEAK_ORDERING
>> 1814 select CPU_SUPPORTS_HIGHMEM
>> 1815 select CPU_HAS_PREFETCH
>> 1816 select CPU_SUPPORTS_CPUFREQ
>> 1817 select MIPS_EXTERNAL_TIMER
>> 1818 help
>> 1819 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1820
>> 1821 config CPU_XLR
>> 1822 bool "Netlogic XLR SoC"
>> 1823 depends on SYS_HAS_CPU_XLR
>> 1824 select CPU_SUPPORTS_32BIT_KERNEL
>> 1825 select CPU_SUPPORTS_64BIT_KERNEL
>> 1826 select CPU_SUPPORTS_HIGHMEM
>> 1827 select CPU_SUPPORTS_HUGEPAGES
>> 1828 select WEAK_ORDERING
>> 1829 select WEAK_REORDERING_BEYOND_LLSC
>> 1830 help
>> 1831 Netlogic Microsystems XLR/XLS processors.
>> 1832
>> 1833 config CPU_XLP
>> 1834 bool "Netlogic XLP SoC"
>> 1835 depends on SYS_HAS_CPU_XLP
>> 1836 select CPU_SUPPORTS_32BIT_KERNEL
>> 1837 select CPU_SUPPORTS_64BIT_KERNEL
>> 1838 select CPU_SUPPORTS_HIGHMEM
>> 1839 select WEAK_ORDERING
>> 1840 select WEAK_REORDERING_BEYOND_LLSC
>> 1841 select CPU_HAS_PREFETCH
>> 1842 select CPU_MIPSR2
>> 1843 select CPU_SUPPORTS_HUGEPAGES
>> 1844 select MIPS_ASID_BITS_VARIABLE
140 help 1845 help
141 Select this variant to use a custom !! 1846 Netlogic Microsystems XLP processors.
142 You will be prompted for a processor <<
143 endchoice 1847 endchoice
144 1848
145 config XTENSA_VARIANT_CUSTOM_NAME !! 1849 config CPU_MIPS32_3_5_FEATURES
146 string "Xtensa Processor Custom Core V !! 1850 bool "MIPS32 Release 3.5 Features"
147 depends on XTENSA_VARIANT_CUSTOM !! 1851 depends on SYS_HAS_CPU_MIPS32_R3_5
148 help !! 1852 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
149 Provide the name of a custom Xtensa !! 1853 CPU_P5600
150 This CORENAME selects arch/xtensa/va !! 1854 help
151 Don't forget you have to select MMU !! 1855 Choose this option to build a kernel for release 2 or later of the
152 !! 1856 MIPS32 architecture including features from the 3.5 release such as
153 config XTENSA_VARIANT_NAME !! 1857 support for Enhanced Virtual Addressing (EVA).
154 string !! 1858
155 default "dc232b" !! 1859 config CPU_MIPS32_3_5_EVA
156 default "dc233c" !! 1860 bool "Enhanced Virtual Addressing (EVA)"
157 default "fsf" !! 1861 depends on CPU_MIPS32_3_5_FEATURES
158 default XTENSA_VARIANT_CUSTOM_NAME !! 1862 select EVA
159 !! 1863 default y
160 config XTENSA_VARIANT_MMU <<
161 bool "Core variant has a Full MMU (TLB <<
162 depends on XTENSA_VARIANT_CUSTOM <<
163 default y <<
164 select MMU <<
165 help <<
166 Build a Conventional Kernel with ful <<
167 ie: it supports a TLB with auto-load <<
168 <<
169 config XTENSA_VARIANT_HAVE_PERF_EVENTS <<
170 bool "Core variant has Performance Mon <<
171 depends on XTENSA_VARIANT_CUSTOM <<
172 default n <<
173 help 1864 help
174 Enable if core variant has Performan !! 1865 Choose this option if you want to enable the Enhanced Virtual
175 External Registers Interface. !! 1866 Addressing (EVA) on your MIPS32 core (such as proAptiv).
176 !! 1867 One of its primary benefits is an increase in the maximum size
177 If unsure, say N. !! 1868 of lowmem (up to 3GB). If unsure, say 'N' here.
178 !! 1869
179 config XTENSA_FAKE_NMI !! 1870 config CPU_MIPS32_R5_FEATURES
180 bool "Treat PMM IRQ as NMI" !! 1871 bool "MIPS32 Release 5 Features"
181 depends on XTENSA_VARIANT_HAVE_PERF_EV !! 1872 depends on SYS_HAS_CPU_MIPS32_R5
>> 1873 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1874 help
>> 1875 Choose this option to build a kernel for release 2 or later of the
>> 1876 MIPS32 architecture including features from release 5 such as
>> 1877 support for Extended Physical Addressing (XPA).
>> 1878
>> 1879 config CPU_MIPS32_R5_XPA
>> 1880 bool "Extended Physical Addressing (XPA)"
>> 1881 depends on CPU_MIPS32_R5_FEATURES
>> 1882 depends on !EVA
>> 1883 depends on !PAGE_SIZE_4KB
>> 1884 depends on SYS_SUPPORTS_HIGHMEM
>> 1885 select XPA
>> 1886 select HIGHMEM
>> 1887 select PHYS_ADDR_T_64BIT
182 default n 1888 default n
183 help 1889 help
184 If PMM IRQ is the only IRQ at EXCM l !! 1890 Choose this option if you want to enable the Extended Physical
185 treat it as NMI, which improves accu !! 1891 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1892 benefit is to increase physical addressing equal to or greater
>> 1893 than 40 bits. Note that this has the side effect of turning on
>> 1894 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1895 If unsure, say 'N' here.
186 1896
187 If there are other interrupts at or !! 1897 if CPU_LOONGSON2F
188 but not above the EXCM level, PMM IR !! 1898 config CPU_NOP_WORKAROUNDS
189 but only if these IRQs are not used. !! 1899 bool
190 saying that this is not safe, and a <<
191 actually fire. <<
192 1900
193 If unsure, say N. !! 1901 config CPU_JUMP_WORKAROUNDS
>> 1902 bool
194 1903
195 config PFAULT !! 1904 config CPU_LOONGSON2F_WORKAROUNDS
196 bool "Handle protection faults" if EXP !! 1905 bool "Loongson 2F Workarounds"
197 default y 1906 default y
>> 1907 select CPU_NOP_WORKAROUNDS
>> 1908 select CPU_JUMP_WORKAROUNDS
198 help 1909 help
199 Handle protection faults. MMU config !! 1910 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
200 noMMU configurations may disable it !! 1911 require workarounds. Without workarounds the system may hang
201 generates protection faults or fault !! 1912 unexpectedly. For more information please refer to the gas
>> 1913 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1914
>> 1915 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1916 are needed. The workarounds have no significant side effect on them
>> 1917 but may decrease the performance of the system so this option should
>> 1918 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1919 systems.
202 1920
203 If unsure, say Y. !! 1921 If unsure, please say Y.
>> 1922 endif # CPU_LOONGSON2F
>> 1923
>> 1924 config SYS_SUPPORTS_ZBOOT
>> 1925 bool
>> 1926 select HAVE_KERNEL_GZIP
>> 1927 select HAVE_KERNEL_BZIP2
>> 1928 select HAVE_KERNEL_LZ4
>> 1929 select HAVE_KERNEL_LZMA
>> 1930 select HAVE_KERNEL_LZO
>> 1931 select HAVE_KERNEL_XZ
>> 1932 select HAVE_KERNEL_ZSTD
>> 1933
>> 1934 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1935 bool
>> 1936 select SYS_SUPPORTS_ZBOOT
>> 1937
>> 1938 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1939 bool
>> 1940 select SYS_SUPPORTS_ZBOOT
>> 1941
>> 1942 config CPU_LOONGSON2EF
>> 1943 bool
>> 1944 select CPU_SUPPORTS_32BIT_KERNEL
>> 1945 select CPU_SUPPORTS_64BIT_KERNEL
>> 1946 select CPU_SUPPORTS_HIGHMEM
>> 1947 select CPU_SUPPORTS_HUGEPAGES
>> 1948 select ARCH_HAS_PHYS_TO_DMA
>> 1949
>> 1950 config CPU_LOONGSON32
>> 1951 bool
>> 1952 select CPU_MIPS32
>> 1953 select CPU_MIPSR2
>> 1954 select CPU_HAS_PREFETCH
>> 1955 select CPU_SUPPORTS_32BIT_KERNEL
>> 1956 select CPU_SUPPORTS_HIGHMEM
>> 1957 select CPU_SUPPORTS_CPUFREQ
>> 1958
>> 1959 config CPU_BMIPS32_3300
>> 1960 select SMP_UP if SMP
>> 1961 bool
>> 1962
>> 1963 config CPU_BMIPS4350
>> 1964 bool
>> 1965 select SYS_SUPPORTS_SMP
>> 1966 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1967
>> 1968 config CPU_BMIPS4380
>> 1969 bool
>> 1970 select MIPS_L1_CACHE_SHIFT_6
>> 1971 select SYS_SUPPORTS_SMP
>> 1972 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1973 select CPU_HAS_RIXI
>> 1974
>> 1975 config CPU_BMIPS5000
>> 1976 bool
>> 1977 select MIPS_CPU_SCACHE
>> 1978 select MIPS_L1_CACHE_SHIFT_7
>> 1979 select SYS_SUPPORTS_SMP
>> 1980 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1981 select CPU_HAS_RIXI
>> 1982
>> 1983 config SYS_HAS_CPU_LOONGSON64
>> 1984 bool
>> 1985 select CPU_SUPPORTS_CPUFREQ
>> 1986 select CPU_HAS_RIXI
>> 1987
>> 1988 config SYS_HAS_CPU_LOONGSON2E
>> 1989 bool
>> 1990
>> 1991 config SYS_HAS_CPU_LOONGSON2F
>> 1992 bool
>> 1993 select CPU_SUPPORTS_CPUFREQ
>> 1994 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1995
>> 1996 config SYS_HAS_CPU_LOONGSON1B
>> 1997 bool
204 1998
205 config XTENSA_UNALIGNED_USER !! 1999 config SYS_HAS_CPU_LOONGSON1C
206 bool "Unaligned memory access in user !! 2000 bool
>> 2001
>> 2002 config SYS_HAS_CPU_MIPS32_R1
>> 2003 bool
>> 2004
>> 2005 config SYS_HAS_CPU_MIPS32_R2
>> 2006 bool
>> 2007
>> 2008 config SYS_HAS_CPU_MIPS32_R3_5
>> 2009 bool
>> 2010
>> 2011 config SYS_HAS_CPU_MIPS32_R5
>> 2012 bool
>> 2013 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2014
>> 2015 config SYS_HAS_CPU_MIPS32_R6
>> 2016 bool
>> 2017 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2018
>> 2019 config SYS_HAS_CPU_MIPS64_R1
>> 2020 bool
>> 2021
>> 2022 config SYS_HAS_CPU_MIPS64_R2
>> 2023 bool
>> 2024
>> 2025 config SYS_HAS_CPU_MIPS64_R6
>> 2026 bool
>> 2027 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2028
>> 2029 config SYS_HAS_CPU_P5600
>> 2030 bool
>> 2031 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2032
>> 2033 config SYS_HAS_CPU_R3000
>> 2034 bool
>> 2035
>> 2036 config SYS_HAS_CPU_TX39XX
>> 2037 bool
>> 2038
>> 2039 config SYS_HAS_CPU_VR41XX
>> 2040 bool
>> 2041
>> 2042 config SYS_HAS_CPU_R4300
>> 2043 bool
>> 2044
>> 2045 config SYS_HAS_CPU_R4X00
>> 2046 bool
>> 2047
>> 2048 config SYS_HAS_CPU_TX49XX
>> 2049 bool
>> 2050
>> 2051 config SYS_HAS_CPU_R5000
>> 2052 bool
>> 2053
>> 2054 config SYS_HAS_CPU_R5500
>> 2055 bool
>> 2056
>> 2057 config SYS_HAS_CPU_NEVADA
>> 2058 bool
>> 2059
>> 2060 config SYS_HAS_CPU_R10000
>> 2061 bool
>> 2062 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2063
>> 2064 config SYS_HAS_CPU_RM7000
>> 2065 bool
>> 2066
>> 2067 config SYS_HAS_CPU_SB1
>> 2068 bool
>> 2069
>> 2070 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 2071 bool
>> 2072
>> 2073 config SYS_HAS_CPU_BMIPS
>> 2074 bool
>> 2075
>> 2076 config SYS_HAS_CPU_BMIPS32_3300
>> 2077 bool
>> 2078 select SYS_HAS_CPU_BMIPS
>> 2079
>> 2080 config SYS_HAS_CPU_BMIPS4350
>> 2081 bool
>> 2082 select SYS_HAS_CPU_BMIPS
>> 2083
>> 2084 config SYS_HAS_CPU_BMIPS4380
>> 2085 bool
>> 2086 select SYS_HAS_CPU_BMIPS
>> 2087
>> 2088 config SYS_HAS_CPU_BMIPS5000
>> 2089 bool
>> 2090 select SYS_HAS_CPU_BMIPS
>> 2091 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 2092
>> 2093 config SYS_HAS_CPU_XLR
>> 2094 bool
>> 2095
>> 2096 config SYS_HAS_CPU_XLP
>> 2097 bool
>> 2098
>> 2099 #
>> 2100 # CPU may reorder R->R, R->W, W->R, W->W
>> 2101 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2102 #
>> 2103 config WEAK_ORDERING
>> 2104 bool
>> 2105
>> 2106 #
>> 2107 # CPU may reorder reads and writes beyond LL/SC
>> 2108 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 2109 #
>> 2110 config WEAK_REORDERING_BEYOND_LLSC
>> 2111 bool
>> 2112 endmenu
>> 2113
>> 2114 #
>> 2115 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2116 #
>> 2117 config CPU_MIPS32
>> 2118 bool
>> 2119 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 2120 CPU_MIPS32_R6 || CPU_P5600
>> 2121
>> 2122 config CPU_MIPS64
>> 2123 bool
>> 2124 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 2125 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
>> 2126
>> 2127 #
>> 2128 # These indicate the revision of the architecture
>> 2129 #
>> 2130 config CPU_MIPSR1
>> 2131 bool
>> 2132 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 2133
>> 2134 config CPU_MIPSR2
>> 2135 bool
>> 2136 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2137 select CPU_HAS_RIXI
>> 2138 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2139 select MIPS_SPRAM
>> 2140
>> 2141 config CPU_MIPSR5
>> 2142 bool
>> 2143 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2144 select CPU_HAS_RIXI
>> 2145 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2146 select MIPS_SPRAM
>> 2147
>> 2148 config CPU_MIPSR6
>> 2149 bool
>> 2150 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2151 select CPU_HAS_RIXI
>> 2152 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2153 select HAVE_ARCH_BITREVERSE
>> 2154 select MIPS_ASID_BITS_VARIABLE
>> 2155 select MIPS_CRC_SUPPORT
>> 2156 select MIPS_SPRAM
>> 2157
>> 2158 config TARGET_ISA_REV
>> 2159 int
>> 2160 default 1 if CPU_MIPSR1
>> 2161 default 2 if CPU_MIPSR2
>> 2162 default 5 if CPU_MIPSR5
>> 2163 default 6 if CPU_MIPSR6
>> 2164 default 0
207 help 2165 help
208 The Xtensa architecture currently do !! 2166 Reflects the ISA revision being targeted by the kernel build. This
209 memory accesses in hardware but thro !! 2167 is effectively the Kconfig equivalent of MIPS_ISA_REV.
210 Per default, unaligned memory access !! 2168
>> 2169 config EVA
>> 2170 bool
>> 2171
>> 2172 config XPA
>> 2173 bool
>> 2174
>> 2175 config SYS_SUPPORTS_32BIT_KERNEL
>> 2176 bool
>> 2177 config SYS_SUPPORTS_64BIT_KERNEL
>> 2178 bool
>> 2179 config CPU_SUPPORTS_32BIT_KERNEL
>> 2180 bool
>> 2181 config CPU_SUPPORTS_64BIT_KERNEL
>> 2182 bool
>> 2183 config CPU_SUPPORTS_CPUFREQ
>> 2184 bool
>> 2185 config CPU_SUPPORTS_ADDRWINCFG
>> 2186 bool
>> 2187 config CPU_SUPPORTS_HUGEPAGES
>> 2188 bool
>> 2189 depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
>> 2190 config MIPS_PGD_C0_CONTEXT
>> 2191 bool
>> 2192 depends on 64BIT
>> 2193 default y if (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
>> 2194
>> 2195 #
>> 2196 # Set to y for ptrace access to watch registers.
>> 2197 #
>> 2198 config HARDWARE_WATCHPOINTS
>> 2199 bool
>> 2200 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
211 2201
212 Say Y here to enable unaligned memor !! 2202 menu "Kernel type"
213 2203
214 config XTENSA_LOAD_STORE !! 2204 choice
215 bool "Load/store exception handler for !! 2205 prompt "Kernel code model"
216 help 2206 help
217 The Xtensa architecture only allows !! 2207 You should only select this option if you have a workload that
218 instruction bus with l32r and l32i i !! 2208 actually benefits from 64-bit processing or if your machine has
219 instructions raise an exception with !! 2209 large memory. You will only be presented a single option in this
220 This makes it hard to use some confi !! 2210 menu if your system does not support both 32-bit and 64-bit kernels.
221 literals in FLASH memory attached to <<
222 2211
223 Say Y here to enable exception handl !! 2212 config 32BIT
224 byte and 2-byte access to memory att !! 2213 bool "32-bit kernel"
>> 2214 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2215 select TRAD_SIGNALS
>> 2216 help
>> 2217 Select this option if you want to build a 32-bit kernel.
225 2218
226 config HAVE_SMP !! 2219 config 64BIT
227 bool "System Supports SMP (MX)" !! 2220 bool "64-bit kernel"
228 depends on XTENSA_VARIANT_CUSTOM !! 2221 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
229 select XTENSA_MX <<
230 help 2222 help
231 This option is used to indicate that !! 2223 Select this option if you want to build a 64-bit kernel.
232 supports Multiprocessing. Multiproce <<
233 the CPU core definition and currentl <<
234 2224
235 Multiprocessor support is implemente !! 2225 endchoice
236 interrupt controllers. <<
237 2226
238 The MX interrupt distributer adds In !! 2227 config MIPS_VA_BITS_48
239 and causes the IRQ numbers to be inc !! 2228 bool "48 bits virtual memory"
240 like the open cores ethernet driver !! 2229 depends on 64BIT
>> 2230 help
>> 2231 Support a maximum at least 48 bits of application virtual
>> 2232 memory. Default is 40 bits or less, depending on the CPU.
>> 2233 For page sizes 16k and above, this option results in a small
>> 2234 memory overhead for page tables. For 4k page size, a fourth
>> 2235 level of page tables is added which imposes both a memory
>> 2236 overhead as well as slower TLB fault handling.
241 2237
242 You still have to select "Enable SMP !! 2238 If unsure, say N.
243 2239
244 config SMP !! 2240 choice
245 bool "Enable Symmetric multi-processin !! 2241 prompt "Kernel page size"
246 depends on HAVE_SMP !! 2242 default PAGE_SIZE_4KB
247 select GENERIC_SMP_IDLE_THREAD <<
248 help <<
249 Enabled SMP Software; allows more th <<
250 to be activated during startup. <<
251 2243
252 config NR_CPUS !! 2244 config PAGE_SIZE_4KB
253 depends on SMP !! 2245 bool "4kB"
254 int "Maximum number of CPUs (2-32)" !! 2246 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
255 range 2 32 !! 2247 help
256 default "4" !! 2248 This option select the standard 4kB Linux page size. On some
>> 2249 R3000-family processors this is the only available page size. Using
>> 2250 4kB page size will minimize memory consumption and is therefore
>> 2251 recommended for low memory systems.
>> 2252
>> 2253 config PAGE_SIZE_8KB
>> 2254 bool "8kB"
>> 2255 depends on CPU_CAVIUM_OCTEON
>> 2256 depends on !MIPS_VA_BITS_48
>> 2257 help
>> 2258 Using 8kB page size will result in higher performance kernel at
>> 2259 the price of higher memory consumption. This option is available
>> 2260 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2261 distribution to support this.
>> 2262
>> 2263 config PAGE_SIZE_16KB
>> 2264 bool "16kB"
>> 2265 depends on !CPU_R3000 && !CPU_TX39XX
>> 2266 help
>> 2267 Using 16kB page size will result in higher performance kernel at
>> 2268 the price of higher memory consumption. This option is available on
>> 2269 all non-R3000 family processors. Note that you will need a suitable
>> 2270 Linux distribution to support this.
>> 2271
>> 2272 config PAGE_SIZE_32KB
>> 2273 bool "32kB"
>> 2274 depends on CPU_CAVIUM_OCTEON
>> 2275 depends on !MIPS_VA_BITS_48
>> 2276 help
>> 2277 Using 32kB page size will result in higher performance kernel at
>> 2278 the price of higher memory consumption. This option is available
>> 2279 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2280 distribution to support this.
>> 2281
>> 2282 config PAGE_SIZE_64KB
>> 2283 bool "64kB"
>> 2284 depends on !CPU_R3000 && !CPU_TX39XX
>> 2285 help
>> 2286 Using 64kB page size will result in higher performance kernel at
>> 2287 the price of higher memory consumption. This option is available on
>> 2288 all non-R3000 family processor. Not that at the time of this
>> 2289 writing this option is still high experimental.
257 2290
258 config HOTPLUG_CPU !! 2291 endchoice
259 bool "Enable CPU hotplug support" !! 2292
260 depends on SMP !! 2293 config FORCE_MAX_ZONEORDER
>> 2294 int "Maximum zone order"
>> 2295 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2296 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2297 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2298 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2299 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2300 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2301 range 0 64
>> 2302 default "11"
>> 2303 help
>> 2304 The kernel memory allocator divides physically contiguous memory
>> 2305 blocks into "zones", where each zone is a power of two number of
>> 2306 pages. This option selects the largest power of two that the kernel
>> 2307 keeps in the memory allocator. If you need to allocate very large
>> 2308 blocks of physically contiguous memory, then you may need to
>> 2309 increase this value.
>> 2310
>> 2311 This config option is actually maximum order plus one. For example,
>> 2312 a value of 11 means that the largest free memory block is 2^10 pages.
>> 2313
>> 2314 The page size is not necessarily 4KB. Keep this in mind
>> 2315 when choosing a value for this option.
>> 2316
>> 2317 config BOARD_SCACHE
>> 2318 bool
>> 2319
>> 2320 config IP22_CPU_SCACHE
>> 2321 bool
>> 2322 select BOARD_SCACHE
>> 2323
>> 2324 #
>> 2325 # Support for a MIPS32 / MIPS64 style S-caches
>> 2326 #
>> 2327 config MIPS_CPU_SCACHE
>> 2328 bool
>> 2329 select BOARD_SCACHE
>> 2330
>> 2331 config R5000_CPU_SCACHE
>> 2332 bool
>> 2333 select BOARD_SCACHE
>> 2334
>> 2335 config RM7000_CPU_SCACHE
>> 2336 bool
>> 2337 select BOARD_SCACHE
>> 2338
>> 2339 config SIBYTE_DMA_PAGEOPS
>> 2340 bool "Use DMA to clear/copy pages"
>> 2341 depends on CPU_SB1
261 help 2342 help
262 Say Y here to allow turning CPUs off !! 2343 Instead of using the CPU to zero and copy pages, use a Data Mover
263 controlled through /sys/devices/syst !! 2344 channel. These DMA channels are otherwise unused by the standard
>> 2345 SiByte Linux port. Seems to give a small performance benefit.
264 2346
265 Say N if you want to disable CPU hot !! 2347 config CPU_HAS_PREFETCH
>> 2348 bool
266 2349
267 config SECONDARY_RESET_VECTOR !! 2350 config CPU_GENERIC_DUMP_TLB
268 bool "Secondary cores use alternative !! 2351 bool
>> 2352 default y if !(CPU_R3000 || CPU_TX39XX)
>> 2353
>> 2354 config MIPS_FP_SUPPORT
>> 2355 bool "Floating Point support" if EXPERT
269 default y 2356 default y
270 depends on HAVE_SMP <<
271 help 2357 help
272 Secondary cores may be configured to !! 2358 Select y to include support for floating point in the kernel
273 or all cores may use primary reset v !! 2359 including initialization of FPU hardware, FP context save & restore
274 Say Y here to supply handler for the !! 2360 and emulation of an FPU where necessary. Without this support any
>> 2361 userland program attempting to use floating point instructions will
>> 2362 receive a SIGILL.
>> 2363
>> 2364 If you know that your userland will not attempt to use floating point
>> 2365 instructions then you can say n here to shrink the kernel a little.
>> 2366
>> 2367 If unsure, say y.
>> 2368
>> 2369 config CPU_R2300_FPU
>> 2370 bool
>> 2371 depends on MIPS_FP_SUPPORT
>> 2372 default y if CPU_R3000 || CPU_TX39XX
>> 2373
>> 2374 config CPU_R3K_TLB
>> 2375 bool
>> 2376
>> 2377 config CPU_R4K_FPU
>> 2378 bool
>> 2379 depends on MIPS_FP_SUPPORT
>> 2380 default y if !CPU_R2300_FPU
>> 2381
>> 2382 config CPU_R4K_CACHE_TLB
>> 2383 bool
>> 2384 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2385
>> 2386 config MIPS_MT_SMP
>> 2387 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2388 default y
>> 2389 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2390 select CPU_MIPSR2_IRQ_VI
>> 2391 select CPU_MIPSR2_IRQ_EI
>> 2392 select SYNC_R4K
>> 2393 select MIPS_MT
>> 2394 select SMP
>> 2395 select SMP_UP
>> 2396 select SYS_SUPPORTS_SMP
>> 2397 select SYS_SUPPORTS_SCHED_SMT
>> 2398 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2399 help
>> 2400 This is a kernel model which is known as SMVP. This is supported
>> 2401 on cores with the MT ASE and uses the available VPEs to implement
>> 2402 virtual processors which supports SMP. This is equivalent to the
>> 2403 Intel Hyperthreading feature. For further information go to
>> 2404 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2405
>> 2406 config MIPS_MT
>> 2407 bool
275 2408
276 config FAST_SYSCALL_XTENSA !! 2409 config SCHED_SMT
277 bool "Enable fast atomic syscalls" !! 2410 bool "SMT (multithreading) scheduler support"
>> 2411 depends on SYS_SUPPORTS_SCHED_SMT
278 default n 2412 default n
279 help 2413 help
280 fast_syscall_xtensa is a syscall tha !! 2414 SMT scheduler support improves the CPU scheduler's decision making
281 on UP kernel when processor has no s !! 2415 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2416 increased overhead in some places. If unsure say N here.
282 2417
283 This syscall is deprecated. It may h !! 2418 config SYS_SUPPORTS_SCHED_SMT
284 invalid arguments. It is provided on !! 2419 bool
285 Only enable it if your userspace sof <<
286 2420
287 If unsure, say N. !! 2421 config SYS_SUPPORTS_MULTITHREADING
>> 2422 bool
288 2423
289 config FAST_SYSCALL_SPILL_REGISTERS !! 2424 config MIPS_MT_FPAFF
290 bool "Enable spill registers syscall" !! 2425 bool "Dynamic FPU affinity for FP-intensive threads"
291 default n !! 2426 default y
>> 2427 depends on MIPS_MT_SMP
>> 2428
>> 2429 config MIPSR2_TO_R6_EMULATOR
>> 2430 bool "MIPS R2-to-R6 emulator"
>> 2431 depends on CPU_MIPSR6
>> 2432 depends on MIPS_FP_SUPPORT
>> 2433 default y
292 help 2434 help
293 fast_syscall_spill_registers is a sy !! 2435 Choose this option if you want to run non-R6 MIPS userland code.
294 register windows of a calling usersp !! 2436 Even if you say 'Y' here, the emulator will still be disabled by
>> 2437 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2438 The only reason this is a build-time option is to save ~14K from the
>> 2439 final kernel image.
295 2440
296 This syscall is deprecated. It may h !! 2441 config SYS_SUPPORTS_VPE_LOADER
297 invalid arguments. It is provided on !! 2442 bool
298 Only enable it if your userspace sof !! 2443 depends on SYS_SUPPORTS_MULTITHREADING
>> 2444 help
>> 2445 Indicates that the platform supports the VPE loader, and provides
>> 2446 physical_memsize.
299 2447
300 If unsure, say N. !! 2448 config MIPS_VPE_LOADER
>> 2449 bool "VPE loader support."
>> 2450 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2451 select CPU_MIPSR2_IRQ_VI
>> 2452 select CPU_MIPSR2_IRQ_EI
>> 2453 select MIPS_MT
>> 2454 help
>> 2455 Includes a loader for loading an elf relocatable object
>> 2456 onto another VPE and running it.
301 2457
302 choice !! 2458 config MIPS_VPE_LOADER_CMP
303 prompt "Kernel ABI" !! 2459 bool
304 default KERNEL_ABI_DEFAULT !! 2460 default "y"
>> 2461 depends on MIPS_VPE_LOADER && MIPS_CMP
>> 2462
>> 2463 config MIPS_VPE_LOADER_MT
>> 2464 bool
>> 2465 default "y"
>> 2466 depends on MIPS_VPE_LOADER && !MIPS_CMP
>> 2467
>> 2468 config MIPS_VPE_LOADER_TOM
>> 2469 bool "Load VPE program into memory hidden from linux"
>> 2470 depends on MIPS_VPE_LOADER
>> 2471 default y
305 help 2472 help
306 Select ABI for the kernel code. This !! 2473 The loader can use memory that is present but has been hidden from
307 supported userspace ABI and any comb !! 2474 Linux using the kernel command line option "mem=xxMB". It's up to
308 kernel/userspace ABI is possible and !! 2475 you to ensure the amount you put in the option and the space your
309 !! 2476 program requires is less or equal to the amount physically present.
310 In case both kernel and userspace su !! 2477
311 all register windows support code wi !! 2478 config MIPS_VPE_APSP_API
312 build. !! 2479 bool "Enable support for AP/SP API (RTLX)"
313 !! 2480 depends on MIPS_VPE_LOADER
314 If unsure, choose the default ABI. <<
315 <<
316 config KERNEL_ABI_DEFAULT <<
317 bool "Default ABI" <<
318 help <<
319 Select this option to compile kernel <<
320 selected for the toolchain. <<
321 Normally cores with windowed registe <<
322 cores without it use call0 ABI. <<
323 <<
324 config KERNEL_ABI_CALL0 <<
325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI <<
326 help <<
327 Select this option to compile kernel <<
328 toolchain that defaults to windowed <<
329 When this option is not selected the <<
330 be used for the kernel code. <<
331 2481
332 endchoice !! 2482 config MIPS_VPE_APSP_API_CMP
>> 2483 bool
>> 2484 default "y"
>> 2485 depends on MIPS_VPE_APSP_API && MIPS_CMP
333 2486
334 config USER_ABI_CALL0 !! 2487 config MIPS_VPE_APSP_API_MT
335 bool 2488 bool
>> 2489 default "y"
>> 2490 depends on MIPS_VPE_APSP_API && !MIPS_CMP
336 2491
337 choice !! 2492 config MIPS_CMP
338 prompt "Userspace ABI" !! 2493 bool "MIPS CMP framework support (DEPRECATED)"
339 default USER_ABI_DEFAULT !! 2494 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2495 select SMP
>> 2496 select SYNC_R4K
>> 2497 select SYS_SUPPORTS_SMP
>> 2498 select WEAK_ORDERING
>> 2499 default n
340 help 2500 help
341 Select supported userspace ABI. !! 2501 Select this if you are using a bootloader which implements the "CMP
>> 2502 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2503 its ability to start secondary CPUs.
>> 2504
>> 2505 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2506 instead of this.
>> 2507
>> 2508 config MIPS_CPS
>> 2509 bool "MIPS Coherent Processing System support"
>> 2510 depends on SYS_SUPPORTS_MIPS_CPS
>> 2511 select MIPS_CM
>> 2512 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2513 select SMP
>> 2514 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2515 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2516 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2517 select SYS_SUPPORTS_SMP
>> 2518 select WEAK_ORDERING
>> 2519 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2520 help
>> 2521 Select this if you wish to run an SMP kernel across multiple cores
>> 2522 within a MIPS Coherent Processing System. When this option is
>> 2523 enabled the kernel will probe for other cores and boot them with
>> 2524 no external assistance. It is safe to enable this when hardware
>> 2525 support is unavailable.
342 2526
343 If unsure, choose the default ABI. !! 2527 config MIPS_CPS_PM
>> 2528 depends on MIPS_CPS
>> 2529 bool
344 2530
345 config USER_ABI_DEFAULT !! 2531 config MIPS_CM
346 bool "Default ABI only" !! 2532 bool
>> 2533 select MIPS_CPC
>> 2534
>> 2535 config MIPS_CPC
>> 2536 bool
>> 2537
>> 2538 config SB1_PASS_2_WORKAROUNDS
>> 2539 bool
>> 2540 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2541 default y
>> 2542
>> 2543 config SB1_PASS_2_1_WORKAROUNDS
>> 2544 bool
>> 2545 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2546 default y
>> 2547
>> 2548 choice
>> 2549 prompt "SmartMIPS or microMIPS ASE support"
>> 2550
>> 2551 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
>> 2552 bool "None"
347 help 2553 help
348 Assume default userspace ABI. For XE !! 2554 Select this if you want neither microMIPS nor SmartMIPS support
349 call0 ABI binaries may be run on suc <<
350 will not work correctly for them. <<
351 2555
352 config USER_ABI_CALL0_ONLY !! 2556 config CPU_HAS_SMARTMIPS
353 bool "Call0 ABI only" !! 2557 depends on SYS_SUPPORTS_SMARTMIPS
354 select USER_ABI_CALL0 !! 2558 bool "SmartMIPS"
>> 2559 help
>> 2560 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2561 increased security at both hardware and software level for
>> 2562 smartcards. Enabling this option will allow proper use of the
>> 2563 SmartMIPS instructions by Linux applications. However a kernel with
>> 2564 this option will not work on a MIPS core without SmartMIPS core. If
>> 2565 you don't know you probably don't have SmartMIPS and should say N
>> 2566 here.
>> 2567
>> 2568 config CPU_MICROMIPS
>> 2569 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2570 bool "microMIPS"
355 help 2571 help
356 Select this option to support only c !! 2572 When this option is enabled the kernel will be built using the
357 Windowed ABI binaries will crash wit !! 2573 microMIPS ISA
358 an illegal instruction exception on !! 2574
>> 2575 endchoice
359 2576
360 Choose this option if you're plannin !! 2577 config CPU_HAS_MSA
361 built with call0 ABI. !! 2578 bool "Support for the MIPS SIMD Architecture"
>> 2579 depends on CPU_SUPPORTS_MSA
>> 2580 depends on MIPS_FP_SUPPORT
>> 2581 depends on 64BIT || MIPS_O32_FP64_SUPPORT
>> 2582 help
>> 2583 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
>> 2584 and a set of SIMD instructions to operate on them. When this option
>> 2585 is enabled the kernel will support allocating & switching MSA
>> 2586 vector register contexts. If you know that your kernel will only be
>> 2587 running on CPUs which do not support MSA or that your userland will
>> 2588 not be making use of it then you may wish to say N here to reduce
>> 2589 the size & complexity of your kernel.
362 2590
363 config USER_ABI_CALL0_PROBE !! 2591 If unsure, say Y.
364 bool "Support both windowed and call0 <<
365 select USER_ABI_CALL0 <<
366 help <<
367 Select this option to support both w <<
368 ABIs. When enabled all processes are <<
369 and a fast user exception handler fo <<
370 used to turn on PS.WOE bit on the fi <<
371 the userspace. <<
372 2592
373 This option should be enabled for th !! 2593 config CPU_HAS_WB
374 both call0 and windowed ABIs in user !! 2594 bool
375 2595
376 Note that Xtensa ISA does not guaran !! 2596 config XKS01
377 raise an illegal instruction excepti !! 2597 bool
378 PS.WOE is disabled, check whether th <<
379 2598
380 endchoice !! 2599 config CPU_HAS_DIEI
>> 2600 depends on !CPU_DIEI_BROKEN
>> 2601 bool
381 2602
382 endmenu !! 2603 config CPU_DIEI_BROKEN
>> 2604 bool
383 2605
384 config XTENSA_CALIBRATE_CCOUNT !! 2606 config CPU_HAS_RIXI
385 def_bool n !! 2607 bool
>> 2608
>> 2609 config CPU_NO_LOAD_STORE_LR
>> 2610 bool
386 help 2611 help
387 On some platforms (XT2000, for examp !! 2612 CPU lacks support for unaligned load and store instructions:
388 vary. The frequency can be determin !! 2613 LWL, LWR, SWL, SWR (Load/store word left/right).
389 against a well known, fixed frequenc !! 2614 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2615 systems).
>> 2616
>> 2617 #
>> 2618 # Vectored interrupt mode is an R2 feature
>> 2619 #
>> 2620 config CPU_MIPSR2_IRQ_VI
>> 2621 bool
390 2622
391 config SERIAL_CONSOLE !! 2623 #
392 def_bool n !! 2624 # Extended interrupt mode is an R2 feature
>> 2625 #
>> 2626 config CPU_MIPSR2_IRQ_EI
>> 2627 bool
393 2628
394 config PLATFORM_HAVE_XIP !! 2629 config CPU_HAS_SYNC
395 def_bool n !! 2630 bool
>> 2631 depends on !CPU_R3000
>> 2632 default y
396 2633
397 menu "Platform options" !! 2634 #
>> 2635 # CPU non-features
>> 2636 #
>> 2637 config CPU_DADDI_WORKAROUNDS
>> 2638 bool
398 2639
399 choice !! 2640 config CPU_R4000_WORKAROUNDS
400 prompt "Xtensa System Type" !! 2641 bool
401 default XTENSA_PLATFORM_ISS !! 2642 select CPU_R4400_WORKAROUNDS
402 2643
403 config XTENSA_PLATFORM_ISS !! 2644 config CPU_R4400_WORKAROUNDS
404 bool "ISS" !! 2645 bool
405 select XTENSA_CALIBRATE_CCOUNT <<
406 select SERIAL_CONSOLE <<
407 help <<
408 ISS is an acronym for Tensilica's In <<
409 <<
410 config XTENSA_PLATFORM_XT2000 <<
411 bool "XT2000" <<
412 help <<
413 XT2000 is the name of Tensilica's fe <<
414 This hardware is capable of running <<
415 <<
416 config XTENSA_PLATFORM_XTFPGA <<
417 bool "XTFPGA" <<
418 select ETHOC if ETHERNET <<
419 select PLATFORM_WANT_DEFAULT_MEM if !M <<
420 select SERIAL_CONSOLE <<
421 select XTENSA_CALIBRATE_CCOUNT <<
422 select PLATFORM_HAVE_XIP <<
423 help <<
424 XTFPGA is the name of Tensilica boar <<
425 This hardware is capable of running <<
426 2646
427 endchoice !! 2647 config CPU_R4X00_BUGS64
>> 2648 bool
>> 2649 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
428 2650
429 config PLATFORM_NR_IRQS !! 2651 config MIPS_ASID_SHIFT
430 int 2652 int
431 default 3 if XTENSA_PLATFORM_XT2000 !! 2653 default 6 if CPU_R3000 || CPU_TX39XX
432 default 0 2654 default 0
433 2655
434 config XTENSA_CPU_CLOCK !! 2656 config MIPS_ASID_BITS
435 int "CPU clock rate [MHz]" !! 2657 int
436 depends on !XTENSA_CALIBRATE_CCOUNT !! 2658 default 0 if MIPS_ASID_BITS_VARIABLE
437 default 16 !! 2659 default 6 if CPU_R3000 || CPU_TX39XX
>> 2660 default 8
438 2661
439 config GENERIC_CALIBRATE_DELAY !! 2662 config MIPS_ASID_BITS_VARIABLE
440 bool "Auto calibration of the BogoMIPS !! 2663 bool
441 help <<
442 The BogoMIPS value can easily be der <<
443 2664
444 config CMDLINE_BOOL !! 2665 config MIPS_CRC_SUPPORT
445 bool "Default bootloader kernel argume !! 2666 bool
446 2667
447 config CMDLINE !! 2668 # R4600 erratum. Due to the lack of errata information the exact
448 string "Initial kernel command string" !! 2669 # technical details aren't known. I've experimentally found that disabling
449 depends on CMDLINE_BOOL !! 2670 # interrupts during indexed I-cache flushes seems to be sufficient to deal
450 default "console=ttyS0,38400 root=/dev !! 2671 # with the issue.
451 help !! 2672 config WAR_R4600_V1_INDEX_ICACHEOP
452 On some architectures (EBSA110 and C !! 2673 bool
453 for the boot loader to pass argument <<
454 architectures, you should supply som <<
455 time by entering them here. As a min <<
456 memory size and the root device (e.g <<
457 2674
458 config USE_OF !! 2675 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
459 bool "Flattened Device Tree support" !! 2676 #
460 select OF !! 2677 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
461 select OF_EARLY_FLATTREE !! 2678 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
462 help !! 2679 # executed if there is no other dcache activity. If the dcache is
463 Include support for flattened device !! 2680 # accessed for another instruction immediately preceding when these
>> 2681 # cache instructions are executing, it is possible that the dcache
>> 2682 # tag match outputs used by these cache instructions will be
>> 2683 # incorrect. These cache instructions should be preceded by at least
>> 2684 # four instructions that are not any kind of load or store
>> 2685 # instruction.
>> 2686 #
>> 2687 # This is not allowed: lw
>> 2688 # nop
>> 2689 # nop
>> 2690 # nop
>> 2691 # cache Hit_Writeback_Invalidate_D
>> 2692 #
>> 2693 # This is allowed: lw
>> 2694 # nop
>> 2695 # nop
>> 2696 # nop
>> 2697 # nop
>> 2698 # cache Hit_Writeback_Invalidate_D
>> 2699 config WAR_R4600_V1_HIT_CACHEOP
>> 2700 bool
464 2701
465 config BUILTIN_DTB_SOURCE !! 2702 # Writeback and invalidate the primary cache dcache before DMA.
466 string "DTB to build into the kernel i !! 2703 #
467 depends on OF !! 2704 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2705 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2706 # operate correctly if the internal data cache refill buffer is empty. These
>> 2707 # CACHE instructions should be separated from any potential data cache miss
>> 2708 # by a load instruction to an uncached address to empty the response buffer."
>> 2709 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2710 # in .pdf format.)
>> 2711 config WAR_R4600_V2_HIT_CACHEOP
>> 2712 bool
468 2713
469 config PARSE_BOOTPARAM !! 2714 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
470 bool "Parse bootparam block" !! 2715 # the line which this instruction itself exists, the following
471 default y !! 2716 # operation is not guaranteed."
472 help !! 2717 #
473 Parse parameters passed to the kerne !! 2718 # Workaround: do two phase flushing for Index_Invalidate_I
474 be disabled if the kernel is known t !! 2719 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2720 bool
475 2721
476 If unsure, say Y. !! 2722 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2723 # opposes it being called that) where invalid instructions in the same
>> 2724 # I-cache line worth of instructions being fetched may case spurious
>> 2725 # exceptions.
>> 2726 config WAR_ICACHE_REFILLS
>> 2727 bool
477 2728
478 choice !! 2729 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
479 prompt "Semihosting interface" !! 2730 # may cause ll / sc and lld / scd sequences to execute non-atomically.
480 default XTENSA_SIMCALL_ISS !! 2731 config WAR_R10000_LLSC
481 depends on XTENSA_PLATFORM_ISS !! 2732 bool
482 help <<
483 Choose semihosting interface that wi <<
484 block device and networking. <<
485 2733
486 config XTENSA_SIMCALL_ISS !! 2734 # 34K core erratum: "Problems Executing the TLBR Instruction"
487 bool "simcall" !! 2735 config WAR_MIPS34K_MISSED_ITLB
488 help !! 2736 bool
489 Use simcall instruction. simcall is !! 2737
490 it does nothing on hardware. !! 2738 #
>> 2739 # - Highmem only makes sense for the 32-bit kernel.
>> 2740 # - The current highmem code will only work properly on physically indexed
>> 2741 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2742 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2743 # moment we protect the user and offer the highmem option only on machines
>> 2744 # where it's known to be safe. This will not offer highmem on a few systems
>> 2745 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2746 # indexed CPUs but we're playing safe.
>> 2747 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2748 # know they might have memory configurations that could make use of highmem
>> 2749 # support.
>> 2750 #
>> 2751 config HIGHMEM
>> 2752 bool "High Memory Support"
>> 2753 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2754 select KMAP_LOCAL
>> 2755
>> 2756 config CPU_SUPPORTS_HIGHMEM
>> 2757 bool
>> 2758
>> 2759 config SYS_SUPPORTS_HIGHMEM
>> 2760 bool
>> 2761
>> 2762 config SYS_SUPPORTS_SMARTMIPS
>> 2763 bool
>> 2764
>> 2765 config SYS_SUPPORTS_MICROMIPS
>> 2766 bool
491 2767
492 config XTENSA_SIMCALL_GDBIO !! 2768 config SYS_SUPPORTS_MIPS16
493 bool "GDBIO" !! 2769 bool
494 help 2770 help
495 Use break instruction. It is availab !! 2771 This option must be set if a kernel might be executed on a MIPS16-
496 is attached to it via JTAG. !! 2772 enabled CPU even if MIPS16 is not actually being used. In other
>> 2773 words, it makes the kernel MIPS16-tolerant.
497 2774
498 endchoice !! 2775 config CPU_SUPPORTS_MSA
>> 2776 bool
499 2777
500 config BLK_DEV_SIMDISK !! 2778 config ARCH_FLATMEM_ENABLE
501 tristate "Host file-based simulated bl !! 2779 def_bool y
502 default n !! 2780 depends on !NUMA && !CPU_LOONGSON2EF
503 depends on XTENSA_PLATFORM_ISS && BLOC !! 2781
>> 2782 config ARCH_SPARSEMEM_ENABLE
>> 2783 bool
>> 2784 select SPARSEMEM_STATIC if !SGI_IP27
>> 2785
>> 2786 config NUMA
>> 2787 bool "NUMA Support"
>> 2788 depends on SYS_SUPPORTS_NUMA
>> 2789 select SMP
>> 2790 help
>> 2791 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2792 Access). This option improves performance on systems with more
>> 2793 than two nodes; on two node systems it is generally better to
>> 2794 leave it disabled; on single node systems leave this option
>> 2795 disabled.
>> 2796
>> 2797 config SYS_SUPPORTS_NUMA
>> 2798 bool
>> 2799
>> 2800 config HAVE_SETUP_PER_CPU_AREA
>> 2801 def_bool y
>> 2802 depends on NUMA
>> 2803
>> 2804 config NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2805 def_bool y
>> 2806 depends on NUMA
>> 2807
>> 2808 config RELOCATABLE
>> 2809 bool "Relocatable kernel"
>> 2810 depends on SYS_SUPPORTS_RELOCATABLE
>> 2811 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2812 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2813 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2814 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2815 CPU_LOONGSON64
>> 2816 help
>> 2817 This builds a kernel image that retains relocation information
>> 2818 so it can be loaded someplace besides the default 1MB.
>> 2819 The relocations make the kernel binary about 15% larger,
>> 2820 but are discarded at runtime
>> 2821
>> 2822 config RELOCATION_TABLE_SIZE
>> 2823 hex "Relocation table size"
>> 2824 depends on RELOCATABLE
>> 2825 range 0x0 0x01000000
>> 2826 default "0x00200000" if CPU_LOONGSON64
>> 2827 default "0x00100000"
>> 2828 help
>> 2829 A table of relocation data will be appended to the kernel binary
>> 2830 and parsed at boot to fix up the relocated kernel.
>> 2831
>> 2832 This option allows the amount of space reserved for the table to be
>> 2833 adjusted, although the default of 1Mb should be ok in most cases.
>> 2834
>> 2835 The build will fail and a valid size suggested if this is too small.
>> 2836
>> 2837 If unsure, leave at the default value.
>> 2838
>> 2839 config RANDOMIZE_BASE
>> 2840 bool "Randomize the address of the kernel image"
>> 2841 depends on RELOCATABLE
>> 2842 help
>> 2843 Randomizes the physical and virtual address at which the
>> 2844 kernel image is loaded, as a security feature that
>> 2845 deters exploit attempts relying on knowledge of the location
>> 2846 of kernel internals.
>> 2847
>> 2848 Entropy is generated using any coprocessor 0 registers available.
>> 2849
>> 2850 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2851
>> 2852 If unsure, say N.
>> 2853
>> 2854 config RANDOMIZE_BASE_MAX_OFFSET
>> 2855 hex "Maximum kASLR offset" if EXPERT
>> 2856 depends on RANDOMIZE_BASE
>> 2857 range 0x0 0x40000000 if EVA || 64BIT
>> 2858 range 0x0 0x08000000
>> 2859 default "0x01000000"
>> 2860 help
>> 2861 When kASLR is active, this provides the maximum offset that will
>> 2862 be applied to the kernel image. It should be set according to the
>> 2863 amount of physical RAM available in the target system minus
>> 2864 PHYSICAL_START and must be a power of 2.
>> 2865
>> 2866 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2867 EVA or 64-bit. The default is 16Mb.
>> 2868
>> 2869 config NODES_SHIFT
>> 2870 int
>> 2871 default "6"
>> 2872 depends on NEED_MULTIPLE_NODES
>> 2873
>> 2874 config HW_PERF_EVENTS
>> 2875 bool "Enable hardware performance counter support for perf events"
>> 2876 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
>> 2877 default y
504 help 2878 help
505 Create block devices that map to fil !! 2879 Enable hardware performance counter support for perf events. If
506 Device binding to host file may be c !! 2880 disabled, perf events will use software events only.
507 interface provided the device is not !! 2881
508 !! 2882 config DMI
509 config BLK_DEV_SIMDISK_COUNT !! 2883 bool "Enable DMI scanning"
510 int "Number of host file-based simulat !! 2884 depends on MACH_LOONGSON64
511 range 1 10 !! 2885 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
512 depends on BLK_DEV_SIMDISK !! 2886 default y
513 default 2 <<
514 help 2887 help
515 This is the default minimal number o !! 2888 Enabled scanning of DMI to identify machine quirks. Say Y
516 Kernel/module parameter 'simdisk_cou !! 2889 here unless you have verified that your setup is not
517 value at runtime. More file names (b !! 2890 affected by entries in the DMI blacklist. Required by PNP
518 specified as parameters, simdisk_cou !! 2891 BIOS code.
519 !! 2892
520 config SIMDISK0_FILENAME !! 2893 config SMP
521 string "Host filename for the first si !! 2894 bool "Multi-Processing support"
522 depends on BLK_DEV_SIMDISK = y !! 2895 depends on SYS_SUPPORTS_SMP
523 default "" <<
524 help <<
525 Attach a first simdisk to a host fil <<
526 contains a root file system. <<
527 <<
528 config SIMDISK1_FILENAME <<
529 string "Host filename for the second s <<
530 depends on BLK_DEV_SIMDISK = y && BLK_ <<
531 default "" <<
532 help <<
533 Another simulated disk in a host fil <<
534 storage. <<
535 <<
536 config XTFPGA_LCD <<
537 bool "Enable XTFPGA LCD driver" <<
538 depends on XTENSA_PLATFORM_XTFPGA <<
539 default n <<
540 help 2896 help
541 There's a 2x16 LCD on most of XTFPGA !! 2897 This enables support for systems with more than one CPU. If you have
542 progress messages there during bootu !! 2898 a system with only one CPU, say N. If you have a system with more
543 during board bringup. !! 2899 than one CPU, say Y.
>> 2900
>> 2901 If you say N here, the kernel will run on uni- and multiprocessor
>> 2902 machines, but will use only one CPU of a multiprocessor machine. If
>> 2903 you say Y here, the kernel will run on many, but not all,
>> 2904 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2905 will run faster if you say N here.
544 2906
545 If unsure, say N. !! 2907 People using multiprocessor machines who say Y here should also say
>> 2908 Y to "Enhanced Real Time Clock Support", below.
546 2909
547 config XTFPGA_LCD_BASE_ADDR !! 2910 See also the SMP-HOWTO available at
548 hex "XTFPGA LCD base address" !! 2911 <https://www.tldp.org/docs.html#howto>.
549 depends on XTFPGA_LCD !! 2912
550 default "0x0d0c0000" !! 2913 If you don't know what to do here, say N.
551 help !! 2914
552 Base address of the LCD controller i !! 2915 config HOTPLUG_CPU
553 Different boards from XTFPGA family !! 2916 bool "Support for hot-pluggable CPUs"
554 addresses. Please consult prototypin !! 2917 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
555 the correct address. Wrong address h <<
556 <<
557 config XTFPGA_LCD_8BIT_ACCESS <<
558 bool "Use 8-bit access to XTFPGA LCD" <<
559 depends on XTFPGA_LCD <<
560 default n <<
561 help 2918 help
562 LCD may be connected with 4- or 8-bi !! 2919 Say Y here to allow turning CPUs off and on. CPUs can be
563 only be used with 8-bit interface. P !! 2920 controlled through /sys/devices/system/cpu.
564 guide for your board for the correct !! 2921 (Note: power management support will enable this option
565 !! 2922 automatically on SMP systems. )
566 comment "Kernel memory layout" !! 2923 Say N if you want to disable CPU hotplug.
567 <<
568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX <<
569 bool "Initialize Xtensa MMU inside the <<
570 depends on !XTENSA_VARIANT_FSF && !XTE <<
571 default y if XTENSA_VARIANT_DC233C || <<
572 help <<
573 Earlier version initialized the MMU <<
574 before jumping to _startup in head.S <<
575 it was possible to place a software <<
576 then enter your normal kernel breakp <<
577 to the kernel mappings (0XC0000000). <<
578 <<
579 This unfortunately won't work for U- <<
580 work for using KEXEC to have a hot k <<
581 KDUMP. <<
582 <<
583 So now the MMU is initialized in hea <<
584 use hardware breakpoints (gdb 'hbrea <<
585 xt-gdb can't place a Software Breakp <<
586 to mapping the MMU and after mapping <<
587 was mapped gdb wouldn't remove the b <<
588 PC wouldn't match. Since Hardware Br <<
589 Linux configurations it seems reason <<
590 and leave this older mechanism for u <<
591 not to follow Tensilica's recommenda <<
592 <<
593 Selecting this will cause U-Boot to <<
594 address at 0x00003000 instead of the <<
595 <<
596 If in doubt, say Y. <<
597 <<
598 config XIP_KERNEL <<
599 bool "Kernel Execute-In-Place from ROM <<
600 depends on PLATFORM_HAVE_XIP <<
601 help <<
602 Execute-In-Place allows the kernel t <<
603 directly addressable by the CPU, suc <<
604 space since the text section of the <<
605 to RAM. Read-write sections, such as <<
606 are still copied to RAM. The XIP ker <<
607 it has to run directly from flash, s <<
608 store it. The flash address used to <<
609 and for storing it, is configuration <<
610 say Y here, you must know the proper <<
611 store the kernel image depending on <<
612 <<
613 Also note that the make target becom <<
614 "make Image" or "make uImage". The f <<
615 ROM memory will be arch/xtensa/boot/ <<
616 2924
617 If unsure, say N. !! 2925 config SMP_UP
>> 2926 bool
618 2927
619 config MEMMAP_CACHEATTR !! 2928 config SYS_SUPPORTS_MIPS_CMP
620 hex "Cache attributes for the memory a !! 2929 bool
621 depends on !MMU !! 2930
622 default 0x22222222 !! 2931 config SYS_SUPPORTS_MIPS_CPS
623 help !! 2932 bool
624 These cache attributes are set up fo !! 2933
625 specifies cache attributes for the c !! 2934 config SYS_SUPPORTS_SMP
626 region: bits 0..3 -- for addresses 0 !! 2935 bool
627 bits 4..7 -- for addresses 0x2000000 <<
628 <<
629 Cache attribute values are specific <<
630 For region protection MMUs: <<
631 1: WT cached, <<
632 2: cache bypass, <<
633 4: WB cached, <<
634 f: illegal. <<
635 For full MMU: <<
636 bit 0: executable, <<
637 bit 1: writable, <<
638 bits 2..3: <<
639 0: cache bypass, <<
640 1: WB cache, <<
641 2: WT cache, <<
642 3: special (c and e are illegal, <<
643 For MPU: <<
644 0: illegal, <<
645 1: WB cache, <<
646 2: WB, no-write-allocate cache, <<
647 3: WT cache, <<
648 4: cache bypass. <<
649 <<
650 config KSEG_PADDR <<
651 hex "Physical address of the KSEG mapp <<
652 depends on INITIALIZE_XTENSA_MMU_INSID <<
653 default 0x00000000 <<
654 help <<
655 This is the physical address where K <<
656 the chosen KSEG layout help for the <<
657 Unpacked kernel image (including vec <<
658 within KSEG. <<
659 Physical memory below this address i <<
660 <<
661 If unsure, leave the default value h <<
662 <<
663 config KERNEL_VIRTUAL_ADDRESS <<
664 hex "Kernel virtual address" <<
665 depends on MMU && XIP_KERNEL <<
666 default 0xd0003000 <<
667 help <<
668 This is the virtual address where th <<
669 XIP kernel may be mapped into KSEG o <<
670 provided here must match kernel load <<
671 KERNEL_LOAD_ADDRESS. <<
672 <<
673 config KERNEL_LOAD_ADDRESS <<
674 hex "Kernel load address" <<
675 default 0x60003000 if !MMU <<
676 default 0x00003000 if MMU && INITIALIZ <<
677 default 0xd0003000 if MMU && !INITIALI <<
678 help <<
679 This is the address where the kernel <<
680 It is virtual address for MMUv2 conf <<
681 for all other configurations. <<
682 2936
683 If unsure, leave the default value h !! 2937 config NR_CPUS_DEFAULT_4
>> 2938 bool
>> 2939
>> 2940 config NR_CPUS_DEFAULT_8
>> 2941 bool
>> 2942
>> 2943 config NR_CPUS_DEFAULT_16
>> 2944 bool
>> 2945
>> 2946 config NR_CPUS_DEFAULT_32
>> 2947 bool
>> 2948
>> 2949 config NR_CPUS_DEFAULT_64
>> 2950 bool
>> 2951
>> 2952 config NR_CPUS
>> 2953 int "Maximum number of CPUs (2-256)"
>> 2954 range 2 256
>> 2955 depends on SMP
>> 2956 default "4" if NR_CPUS_DEFAULT_4
>> 2957 default "8" if NR_CPUS_DEFAULT_8
>> 2958 default "16" if NR_CPUS_DEFAULT_16
>> 2959 default "32" if NR_CPUS_DEFAULT_32
>> 2960 default "64" if NR_CPUS_DEFAULT_64
>> 2961 help
>> 2962 This allows you to specify the maximum number of CPUs which this
>> 2963 kernel will support. The maximum supported value is 32 for 32-bit
>> 2964 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2965 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2966 and 2 for all others.
>> 2967
>> 2968 This is purely to save memory - each supported CPU adds
>> 2969 approximately eight kilobytes to the kernel image. For best
>> 2970 performance should round up your number of processors to the next
>> 2971 power of two.
>> 2972
>> 2973 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2974 bool
>> 2975
>> 2976 config MIPS_NR_CPU_NR_MAP_1024
>> 2977 bool
>> 2978
>> 2979 config MIPS_NR_CPU_NR_MAP
>> 2980 int
>> 2981 depends on SMP
>> 2982 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2983 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
>> 2984
>> 2985 #
>> 2986 # Timer Interrupt Frequency Configuration
>> 2987 #
684 2988
685 choice 2989 choice
686 prompt "Relocatable vectors location" !! 2990 prompt "Timer frequency"
687 default XTENSA_VECTORS_IN_TEXT !! 2991 default HZ_250
688 help 2992 help
689 Choose whether relocatable vectors a !! 2993 Allows the configuration of the timer frequency.
690 or placed separately at runtime. Thi !! 2994
691 configurations without VECBASE regis !! 2995 config HZ_24
692 placed at their hardware-defined loc !! 2996 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
693 !! 2997
694 config XTENSA_VECTORS_IN_TEXT !! 2998 config HZ_48
695 bool "Merge relocatable vectors into k !! 2999 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
696 depends on !MTD_XIP !! 3000
697 help !! 3001 config HZ_100
698 This option puts relocatable vectors !! 3002 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
699 with proper alignment. !! 3003
700 This is a safe choice for most confi !! 3004 config HZ_128
701 !! 3005 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
702 config XTENSA_VECTORS_SEPARATE !! 3006
703 bool "Put relocatable vectors at fixed !! 3007 config HZ_250
704 help !! 3008 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
705 This option puts relocatable vectors !! 3009
706 Vectors are merged with the .init da !! 3010 config HZ_256
707 are copied into their designated loc !! 3011 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
708 Use it to put vectors into IRAM or o !! 3012
709 XIP-aware MTD support. !! 3013 config HZ_1000
>> 3014 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 3015
>> 3016 config HZ_1024
>> 3017 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
710 3018
711 endchoice 3019 endchoice
712 3020
713 config VECTORS_ADDR !! 3021 config SYS_SUPPORTS_24HZ
714 hex "Kernel vectors virtual address" !! 3022 bool
715 default 0x00000000 <<
716 depends on XTENSA_VECTORS_SEPARATE <<
717 help <<
718 This is the virtual address of the ( <<
719 It must be within KSEG if MMU is use <<
720 <<
721 config XIP_DATA_ADDR <<
722 hex "XIP kernel data virtual address" <<
723 depends on XIP_KERNEL <<
724 default 0x00000000 <<
725 help <<
726 This is the virtual address where XI <<
727 It must be within KSEG if MMU is use <<
728 3023
729 config PLATFORM_WANT_DEFAULT_MEM !! 3024 config SYS_SUPPORTS_48HZ
730 def_bool n !! 3025 bool
731 3026
732 config DEFAULT_MEM_START !! 3027 config SYS_SUPPORTS_100HZ
733 hex !! 3028 bool
734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !M !! 3029
735 default 0x60000000 if PLATFORM_WANT_DE !! 3030 config SYS_SUPPORTS_128HZ
736 default 0x00000000 !! 3031 bool
737 help !! 3032
738 This is the base address used for bo !! 3033 config SYS_SUPPORTS_250HZ
739 in noMMU configurations. !! 3034 bool
>> 3035
>> 3036 config SYS_SUPPORTS_256HZ
>> 3037 bool
740 3038
741 If unsure, leave the default value h !! 3039 config SYS_SUPPORTS_1000HZ
>> 3040 bool
>> 3041
>> 3042 config SYS_SUPPORTS_1024HZ
>> 3043 bool
>> 3044
>> 3045 config SYS_SUPPORTS_ARBIT_HZ
>> 3046 bool
>> 3047 default y if !SYS_SUPPORTS_24HZ && \
>> 3048 !SYS_SUPPORTS_48HZ && \
>> 3049 !SYS_SUPPORTS_100HZ && \
>> 3050 !SYS_SUPPORTS_128HZ && \
>> 3051 !SYS_SUPPORTS_250HZ && \
>> 3052 !SYS_SUPPORTS_256HZ && \
>> 3053 !SYS_SUPPORTS_1000HZ && \
>> 3054 !SYS_SUPPORTS_1024HZ
>> 3055
>> 3056 config HZ
>> 3057 int
>> 3058 default 24 if HZ_24
>> 3059 default 48 if HZ_48
>> 3060 default 100 if HZ_100
>> 3061 default 128 if HZ_128
>> 3062 default 250 if HZ_250
>> 3063 default 256 if HZ_256
>> 3064 default 1000 if HZ_1000
>> 3065 default 1024 if HZ_1024
>> 3066
>> 3067 config SCHED_HRTICK
>> 3068 def_bool HIGH_RES_TIMERS
>> 3069
>> 3070 config KEXEC
>> 3071 bool "Kexec system call"
>> 3072 select KEXEC_CORE
>> 3073 help
>> 3074 kexec is a system call that implements the ability to shutdown your
>> 3075 current kernel, and to start another kernel. It is like a reboot
>> 3076 but it is independent of the system firmware. And like a reboot
>> 3077 you can start any kernel with it, not just Linux.
>> 3078
>> 3079 The name comes from the similarity to the exec system call.
>> 3080
>> 3081 It is an ongoing process to be certain the hardware in a machine
>> 3082 is properly shutdown, so do not be surprised if this code does not
>> 3083 initially work for you. As of this writing the exact hardware
>> 3084 interface is strongly in flux, so no good recommendation can be
>> 3085 made.
>> 3086
>> 3087 config CRASH_DUMP
>> 3088 bool "Kernel crash dumps"
>> 3089 help
>> 3090 Generate crash dump after being started by kexec.
>> 3091 This should be normally only set in special crash dump kernels
>> 3092 which are loaded in the main kernel with kexec-tools into
>> 3093 a specially reserved region and then later executed after
>> 3094 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 3095 to a memory address not used by the main kernel or firmware using
>> 3096 PHYSICAL_START.
>> 3097
>> 3098 config PHYSICAL_START
>> 3099 hex "Physical address where the kernel is loaded"
>> 3100 default "0xffffffff84000000"
>> 3101 depends on CRASH_DUMP
>> 3102 help
>> 3103 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 3104 If you plan to use kernel for capturing the crash dump change
>> 3105 this value to start of the reserved region (the "X" value as
>> 3106 specified in the "crashkernel=YM@XM" command line boot parameter
>> 3107 passed to the panic-ed kernel).
>> 3108
>> 3109 config MIPS_O32_FP64_SUPPORT
>> 3110 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 3111 depends on 32BIT || MIPS32_O32
>> 3112 help
>> 3113 When this is enabled, the kernel will support use of 64-bit floating
>> 3114 point registers with binaries using the O32 ABI along with the
>> 3115 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3116 32-bit MIPS systems this support is at the cost of increasing the
>> 3117 size and complexity of the compiled FPU emulator. Thus if you are
>> 3118 running a MIPS32 system and know that none of your userland binaries
>> 3119 will require 64-bit floating point, you may wish to reduce the size
>> 3120 of your kernel & potentially improve FP emulation performance by
>> 3121 saying N here.
>> 3122
>> 3123 Although binutils currently supports use of this flag the details
>> 3124 concerning its effect upon the O32 ABI in userland are still being
>> 3125 worked on. In order to avoid userland becoming dependent upon current
>> 3126 behaviour before the details have been finalised, this option should
>> 3127 be considered experimental and only enabled by those working upon
>> 3128 said details.
>> 3129
>> 3130 If unsure, say N.
>> 3131
>> 3132 config USE_OF
>> 3133 bool
>> 3134 select OF
>> 3135 select OF_EARLY_FLATTREE
>> 3136 select IRQ_DOMAIN
>> 3137
>> 3138 config UHI_BOOT
>> 3139 bool
>> 3140
>> 3141 config BUILTIN_DTB
>> 3142 bool
742 3143
743 choice 3144 choice
744 prompt "KSEG layout" !! 3145 prompt "Kernel appended dtb support" if USE_OF
745 depends on MMU !! 3146 default MIPS_NO_APPENDED_DTB
746 default XTENSA_KSEG_MMU_V2 <<
747 <<
748 config XTENSA_KSEG_MMU_V2 <<
749 bool "MMUv2: 128MB cached + 128MB unca <<
750 help <<
751 MMUv2 compatible kernel memory map: <<
752 at KSEG_PADDR to 0xd0000000 with cac <<
753 without cache. <<
754 KSEG_PADDR must be aligned to 128MB. <<
755 <<
756 config XTENSA_KSEG_256M <<
757 bool "256MB cached + 256MB uncached" <<
758 depends on INITIALIZE_XTENSA_MMU_INSID <<
759 help <<
760 TLB way 6 maps 256MB starting at KSE <<
761 with cache and to 0xc0000000 without <<
762 KSEG_PADDR must be aligned to 256MB. <<
763 <<
764 config XTENSA_KSEG_512M <<
765 bool "512MB cached + 512MB uncached" <<
766 depends on INITIALIZE_XTENSA_MMU_INSID <<
767 help <<
768 TLB way 6 maps 512MB starting at KSE <<
769 with cache and to 0xc0000000 without <<
770 KSEG_PADDR must be aligned to 256MB. <<
771 3147
>> 3148 config MIPS_NO_APPENDED_DTB
>> 3149 bool "None"
>> 3150 help
>> 3151 Do not enable appended dtb support.
>> 3152
>> 3153 config MIPS_ELF_APPENDED_DTB
>> 3154 bool "vmlinux"
>> 3155 help
>> 3156 With this option, the boot code will look for a device tree binary
>> 3157 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3158 it is empty and the DTB can be appended using binutils command
>> 3159 objcopy:
>> 3160
>> 3161 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3162
>> 3163 This is meant as a backward compatibility convenience for those
>> 3164 systems with a bootloader that can't be upgraded to accommodate
>> 3165 the documented boot protocol using a device tree.
>> 3166
>> 3167 config MIPS_RAW_APPENDED_DTB
>> 3168 bool "vmlinux.bin or vmlinuz.bin"
>> 3169 help
>> 3170 With this option, the boot code will look for a device tree binary
>> 3171 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3172 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3173
>> 3174 This is meant as a backward compatibility convenience for those
>> 3175 systems with a bootloader that can't be upgraded to accommodate
>> 3176 the documented boot protocol using a device tree.
>> 3177
>> 3178 Beware that there is very little in terms of protection against
>> 3179 this option being confused by leftover garbage in memory that might
>> 3180 look like a DTB header after a reboot if no actual DTB is appended
>> 3181 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3182 if you don't intend to always append a DTB.
772 endchoice 3183 endchoice
773 3184
774 config HIGHMEM !! 3185 choice
775 bool "High Memory Support" !! 3186 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
776 depends on MMU !! 3187 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
777 select KMAP_LOCAL !! 3188 !MACH_LOONGSON64 && !MIPS_MALTA && \
778 help !! 3189 !CAVIUM_OCTEON_SOC
779 Linux can use the full amount of RAM !! 3190 default MIPS_CMDLINE_FROM_BOOTLOADER
780 default. However, the default MMUv2 !! 3191
781 lowermost 128 MB of memory linearly !! 3192 config MIPS_CMDLINE_FROM_DTB
782 at 0xd0000000 (cached) and 0xd800000 !! 3193 depends on USE_OF
783 When there are more than 128 MB memo !! 3194 bool "Dtb kernel arguments if available"
784 all of it can be "permanently mapped !! 3195
785 The physical memory that's not perma !! 3196 config MIPS_CMDLINE_DTB_EXTEND
786 "high memory". !! 3197 depends on USE_OF
787 !! 3198 bool "Extend dtb kernel arguments with bootloader arguments"
788 If you are compiling a kernel which !! 3199
789 machine with more than 128 MB total !! 3200 config MIPS_CMDLINE_FROM_BOOTLOADER
790 N here. !! 3201 bool "Bootloader kernel arguments if available"
>> 3202
>> 3203 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3204 depends on CMDLINE_BOOL
>> 3205 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3206 endchoice
791 3207
792 If unsure, say Y. !! 3208 endmenu
>> 3209
>> 3210 config LOCKDEP_SUPPORT
>> 3211 bool
>> 3212 default y
>> 3213
>> 3214 config STACKTRACE_SUPPORT
>> 3215 bool
>> 3216 default y
>> 3217
>> 3218 config PGTABLE_LEVELS
>> 3219 int
>> 3220 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3221 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 3222 default 2
>> 3223
>> 3224 config MIPS_AUTO_PFN_OFFSET
>> 3225 bool
>> 3226
>> 3227 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
>> 3228
>> 3229 config PCI_DRIVERS_GENERIC
>> 3230 select PCI_DOMAINS_GENERIC if PCI
>> 3231 bool
>> 3232
>> 3233 config PCI_DRIVERS_LEGACY
>> 3234 def_bool !PCI_DRIVERS_GENERIC
>> 3235 select NO_GENERIC_PCI_IOPORT_MAP
>> 3236 select PCI_DOMAINS if PCI
>> 3237
>> 3238 #
>> 3239 # ISA support is now enabled via select. Too many systems still have the one
>> 3240 # or other ISA chip on the board that users don't know about so don't expect
>> 3241 # users to choose the right thing ...
>> 3242 #
>> 3243 config ISA
>> 3244 bool
>> 3245
>> 3246 config TC
>> 3247 bool "TURBOchannel support"
>> 3248 depends on MACH_DECSTATION
>> 3249 help
>> 3250 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3251 processors. TURBOchannel programming specifications are available
>> 3252 at:
>> 3253 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3254 and:
>> 3255 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3256 Linux driver support status is documented at:
>> 3257 <http://www.linux-mips.org/wiki/DECstation>
>> 3258
>> 3259 config MMU
>> 3260 bool
>> 3261 default y
>> 3262
>> 3263 config ARCH_MMAP_RND_BITS_MIN
>> 3264 default 12 if 64BIT
>> 3265 default 8
>> 3266
>> 3267 config ARCH_MMAP_RND_BITS_MAX
>> 3268 default 18 if 64BIT
>> 3269 default 15
>> 3270
>> 3271 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3272 default 8
>> 3273
>> 3274 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3275 default 15
793 3276
794 config ARCH_FORCE_MAX_ORDER !! 3277 config I8253
795 int "Order of maximal physically conti !! 3278 bool
796 default "10" !! 3279 select CLKSRC_I8253
797 help !! 3280 select CLKEVT_I8253
798 The kernel page allocator limits the !! 3281 select MIPS_EXTERNAL_TIMER
799 contiguous allocations. The limit is <<
800 defines the maximal power of two of <<
801 allocated as a single contiguous blo <<
802 overriding the default setting when <<
803 large blocks of physically contiguou <<
804 3282
805 Don't change if unsure. !! 3283 config ZONE_DMA
>> 3284 bool
>> 3285
>> 3286 config ZONE_DMA32
>> 3287 bool
806 3288
807 endmenu 3289 endmenu
808 3290
>> 3291 config TRAD_SIGNALS
>> 3292 bool
>> 3293
>> 3294 config MIPS32_COMPAT
>> 3295 bool
>> 3296
>> 3297 config COMPAT
>> 3298 bool
>> 3299
>> 3300 config SYSVIPC_COMPAT
>> 3301 bool
>> 3302
>> 3303 config MIPS32_O32
>> 3304 bool "Kernel support for o32 binaries"
>> 3305 depends on 64BIT
>> 3306 select ARCH_WANT_OLD_COMPAT_IPC
>> 3307 select COMPAT
>> 3308 select MIPS32_COMPAT
>> 3309 select SYSVIPC_COMPAT if SYSVIPC
>> 3310 help
>> 3311 Select this option if you want to run o32 binaries. These are pure
>> 3312 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3313 existing binaries are in this format.
>> 3314
>> 3315 If unsure, say Y.
>> 3316
>> 3317 config MIPS32_N32
>> 3318 bool "Kernel support for n32 binaries"
>> 3319 depends on 64BIT
>> 3320 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3321 select COMPAT
>> 3322 select MIPS32_COMPAT
>> 3323 select SYSVIPC_COMPAT if SYSVIPC
>> 3324 help
>> 3325 Select this option if you want to run n32 binaries. These are
>> 3326 64-bit binaries using 32-bit quantities for addressing and certain
>> 3327 data that would normally be 64-bit. They are used in special
>> 3328 cases.
>> 3329
>> 3330 If unsure, say N.
>> 3331
809 menu "Power management options" 3332 menu "Power management options"
810 3333
811 config ARCH_HIBERNATION_POSSIBLE 3334 config ARCH_HIBERNATION_POSSIBLE
812 def_bool y 3335 def_bool y
>> 3336 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3337
>> 3338 config ARCH_SUSPEND_POSSIBLE
>> 3339 def_bool y
>> 3340 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
813 3341
814 source "kernel/power/Kconfig" 3342 source "kernel/power/Kconfig"
815 3343
816 endmenu 3344 endmenu
>> 3345
>> 3346 config MIPS_EXTERNAL_TIMER
>> 3347 bool
>> 3348
>> 3349 menu "CPU Power Management"
>> 3350
>> 3351 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3352 source "drivers/cpufreq/Kconfig"
>> 3353 endif
>> 3354
>> 3355 source "drivers/cpuidle/Kconfig"
>> 3356
>> 3357 endmenu
>> 3358
>> 3359 source "drivers/firmware/Kconfig"
>> 3360
>> 3361 source "arch/mips/kvm/Kconfig"
>> 3362
>> 3363 source "arch/mips/vdso/Kconfig"
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