1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 config XTENSA !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ARCH_32BIT_OFF_T !! 4 default y
5 select ARCH_HAS_CPU_CACHE_ALIASING !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_HAS_BINFMT_FLAT if !MMU !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CURRENT_STACK_POINTER !! 7 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
8 select ARCH_HAS_DEBUG_VM_PGTABLE !! 8 select ARCH_HAS_FORTIFY_SOURCE
9 select ARCH_HAS_DMA_PREP_COHERENT if M <<
10 select ARCH_HAS_GCOV_PROFILE_ALL <<
11 select ARCH_HAS_KCOV 9 select ARCH_HAS_KCOV
12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MM !! 10 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if !! 11 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
14 select ARCH_HAS_DMA_SET_UNCACHED if MM !! 12 select ARCH_HAS_STRNCPY_FROM_USER
15 select ARCH_HAS_STRNCPY_FROM_USER if ! <<
16 select ARCH_HAS_STRNLEN_USER 13 select ARCH_HAS_STRNLEN_USER
17 select ARCH_NEED_CMPXCHG_1_EMU !! 14 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 15 select ARCH_HAS_UBSAN_SANITIZE_ALL
>> 16 select ARCH_HAS_GCOV_PROFILE_ALL
>> 17 select ARCH_KEEP_MEMBLOCK
>> 18 select ARCH_SUPPORTS_UPROBES
>> 19 select ARCH_USE_BUILTIN_BSWAP
>> 20 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
18 select ARCH_USE_MEMTEST 21 select ARCH_USE_MEMTEST
19 select ARCH_USE_QUEUED_RWLOCKS 22 select ARCH_USE_QUEUED_RWLOCKS
20 select ARCH_USE_QUEUED_SPINLOCKS 23 select ARCH_USE_QUEUED_SPINLOCKS
>> 24 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
>> 25 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
21 select ARCH_WANT_IPC_PARSE_VERSION 26 select ARCH_WANT_IPC_PARSE_VERSION
>> 27 select ARCH_WANT_LD_ORPHAN_WARN
22 select BUILDTIME_TABLE_SORT 28 select BUILDTIME_TABLE_SORT
23 select CLONE_BACKWARDS 29 select CLONE_BACKWARDS
24 select COMMON_CLK !! 30 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
25 select DMA_NONCOHERENT_MMAP if MMU !! 31 select CPU_PM if CPU_IDLE
26 select GENERIC_ATOMIC64 !! 32 select GENERIC_ATOMIC64 if !64BIT
>> 33 select GENERIC_CMOS_UPDATE
>> 34 select GENERIC_CPU_AUTOPROBE
>> 35 select GENERIC_FIND_FIRST_BIT
>> 36 select GENERIC_GETTIMEOFDAY
>> 37 select GENERIC_IOMAP
>> 38 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW 39 select GENERIC_IRQ_SHOW
>> 40 select GENERIC_ISA_DMA if EISA
>> 41 select GENERIC_LIB_ASHLDI3
>> 42 select GENERIC_LIB_ASHRDI3
28 select GENERIC_LIB_CMPDI2 43 select GENERIC_LIB_CMPDI2
29 select GENERIC_LIB_MULDI3 !! 44 select GENERIC_LIB_LSHRDI3
30 select GENERIC_LIB_UCMPDI2 45 select GENERIC_LIB_UCMPDI2
31 select GENERIC_PCI_IOMAP !! 46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
32 select GENERIC_SCHED_CLOCK !! 47 select GENERIC_SMP_IDLE_THREAD
33 select GENERIC_IOREMAP if MMU !! 48 select GENERIC_TIME_VSYSCALL
34 select HAVE_ARCH_AUDITSYSCALL !! 49 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
35 select HAVE_ARCH_JUMP_LABEL if !XIP_KE !! 50 select HAVE_ARCH_COMPILER_H
36 select HAVE_ARCH_KASAN if MMU && !XIP_ !! 51 select HAVE_ARCH_JUMP_LABEL
37 select HAVE_ARCH_KCSAN !! 52 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
>> 53 select HAVE_ARCH_MMAP_RND_BITS if MMU
>> 54 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
38 select HAVE_ARCH_SECCOMP_FILTER 55 select HAVE_ARCH_SECCOMP_FILTER
39 select HAVE_ARCH_TRACEHOOK 56 select HAVE_ARCH_TRACEHOOK
>> 57 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
40 select HAVE_ASM_MODVERSIONS 58 select HAVE_ASM_MODVERSIONS
41 select HAVE_CONTEXT_TRACKING_USER !! 59 select HAVE_CONTEXT_TRACKING
>> 60 select HAVE_TIF_NOHZ
>> 61 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK 62 select HAVE_DEBUG_KMEMLEAK
>> 63 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_DMA_CONTIGUOUS 64 select HAVE_DMA_CONTIGUOUS
>> 65 select HAVE_DYNAMIC_FTRACE
>> 66 select HAVE_EBPF_JIT if !CPU_MICROMIPS && \
>> 67 !CPU_DADDI_WORKAROUNDS && \
>> 68 !CPU_R4000_WORKAROUNDS && \
>> 69 !CPU_R4400_WORKAROUNDS
44 select HAVE_EXIT_THREAD 70 select HAVE_EXIT_THREAD
>> 71 select HAVE_FAST_GUP
>> 72 select HAVE_FTRACE_MCOUNT_RECORD
>> 73 select HAVE_FUNCTION_GRAPH_TRACER
45 select HAVE_FUNCTION_TRACER 74 select HAVE_FUNCTION_TRACER
46 select HAVE_GCC_PLUGINS if GCC_VERSION !! 75 select HAVE_GCC_PLUGINS
47 select HAVE_HW_BREAKPOINT if PERF_EVEN !! 76 select HAVE_GENERIC_VDSO
>> 77 select HAVE_IOREMAP_PROT
>> 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
48 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_PAGE_SIZE_4KB !! 80 select HAVE_KPROBES
50 select HAVE_PCI !! 81 select HAVE_KRETPROBES
>> 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 83 select HAVE_MOD_ARCH_SPECIFIC
>> 84 select HAVE_NMI
51 select HAVE_PERF_EVENTS 85 select HAVE_PERF_EVENTS
>> 86 select HAVE_PERF_REGS
>> 87 select HAVE_PERF_USER_STACK_DUMP
>> 88 select HAVE_REGS_AND_STACK_ACCESS_API
>> 89 select HAVE_RSEQ
>> 90 select HAVE_SPARSE_SYSCALL_NR
52 select HAVE_STACKPROTECTOR 91 select HAVE_STACKPROTECTOR
53 select HAVE_SYSCALL_TRACEPOINTS 92 select HAVE_SYSCALL_TRACEPOINTS
54 select HAVE_VIRT_CPU_ACCOUNTING_GEN !! 93 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
55 select IRQ_DOMAIN !! 94 select IRQ_FORCED_THREADING
56 select LOCK_MM_AND_FIND_VMA !! 95 select ISA if EISA
57 select MODULES_USE_ELF_RELA !! 96 select MODULES_USE_ELF_REL if MODULES
>> 97 select MODULES_USE_ELF_RELA if MODULES && 64BIT
58 select PERF_USE_VMALLOC 98 select PERF_USE_VMALLOC
>> 99 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
>> 100 select RTC_LIB
>> 101 select SYSCTL_EXCEPTION_TRACE
59 select TRACE_IRQFLAGS_SUPPORT 102 select TRACE_IRQFLAGS_SUPPORT
>> 103 select VIRT_TO_BUS
>> 104 select ARCH_HAS_ELFCORE_COMPAT
>> 105
>> 106 config MIPS_FIXUP_BIGPHYS_ADDR
>> 107 bool
>> 108
>> 109 config MIPS_GENERIC
>> 110 bool
>> 111
>> 112 config MACH_INGENIC
>> 113 bool
>> 114 select SYS_SUPPORTS_32BIT_KERNEL
>> 115 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 116 select SYS_SUPPORTS_ZBOOT
>> 117 select DMA_NONCOHERENT
>> 118 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 119 select IRQ_MIPS_CPU
>> 120 select PINCTRL
>> 121 select GPIOLIB
>> 122 select COMMON_CLK
>> 123 select GENERIC_IRQ_CHIP
>> 124 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 125 select USE_OF
>> 126 select CPU_SUPPORTS_CPUFREQ
>> 127 select MIPS_EXTERNAL_TIMER
>> 128
>> 129 menu "Machine selection"
>> 130
>> 131 choice
>> 132 prompt "System type"
>> 133 default MIPS_GENERIC_KERNEL
>> 134
>> 135 config MIPS_GENERIC_KERNEL
>> 136 bool "Generic board-agnostic MIPS kernel"
>> 137 select ARCH_HAS_SETUP_DMA_OPS
>> 138 select MIPS_GENERIC
>> 139 select BOOT_RAW
>> 140 select BUILTIN_DTB
>> 141 select CEVT_R4K
>> 142 select CLKSRC_MIPS_GIC
>> 143 select COMMON_CLK
>> 144 select CPU_MIPSR2_IRQ_EI
>> 145 select CPU_MIPSR2_IRQ_VI
>> 146 select CSRC_R4K
>> 147 select DMA_NONCOHERENT
>> 148 select HAVE_PCI
>> 149 select IRQ_MIPS_CPU
>> 150 select MIPS_AUTO_PFN_OFFSET
>> 151 select MIPS_CPU_SCACHE
>> 152 select MIPS_GIC
>> 153 select MIPS_L1_CACHE_SHIFT_7
>> 154 select NO_EXCEPT_FILL
>> 155 select PCI_DRIVERS_GENERIC
>> 156 select SMP_UP if SMP
>> 157 select SWAP_IO_SPACE
>> 158 select SYS_HAS_CPU_MIPS32_R1
>> 159 select SYS_HAS_CPU_MIPS32_R2
>> 160 select SYS_HAS_CPU_MIPS32_R6
>> 161 select SYS_HAS_CPU_MIPS64_R1
>> 162 select SYS_HAS_CPU_MIPS64_R2
>> 163 select SYS_HAS_CPU_MIPS64_R6
>> 164 select SYS_SUPPORTS_32BIT_KERNEL
>> 165 select SYS_SUPPORTS_64BIT_KERNEL
>> 166 select SYS_SUPPORTS_BIG_ENDIAN
>> 167 select SYS_SUPPORTS_HIGHMEM
>> 168 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 169 select SYS_SUPPORTS_MICROMIPS
>> 170 select SYS_SUPPORTS_MIPS16
>> 171 select SYS_SUPPORTS_MIPS_CPS
>> 172 select SYS_SUPPORTS_MULTITHREADING
>> 173 select SYS_SUPPORTS_RELOCATABLE
>> 174 select SYS_SUPPORTS_SMARTMIPS
>> 175 select SYS_SUPPORTS_ZBOOT
>> 176 select UHI_BOOT
>> 177 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 178 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 179 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 180 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 181 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 182 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 183 select USE_OF
>> 184 help
>> 185 Select this to build a kernel which aims to support multiple boards,
>> 186 generally using a flattened device tree passed from the bootloader
>> 187 using the boot protocol defined in the UHI (Unified Hosting
>> 188 Interface) specification.
>> 189
>> 190 config MIPS_ALCHEMY
>> 191 bool "Alchemy processor based machines"
>> 192 select PHYS_ADDR_T_64BIT
>> 193 select CEVT_R4K
>> 194 select CSRC_R4K
>> 195 select IRQ_MIPS_CPU
>> 196 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 197 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 198 select SYS_HAS_CPU_MIPS32_R1
>> 199 select SYS_SUPPORTS_32BIT_KERNEL
>> 200 select SYS_SUPPORTS_APM_EMULATION
>> 201 select GPIOLIB
>> 202 select SYS_SUPPORTS_ZBOOT
>> 203 select COMMON_CLK
>> 204
>> 205 config AR7
>> 206 bool "Texas Instruments AR7"
>> 207 select BOOT_ELF32
>> 208 select COMMON_CLK
>> 209 select DMA_NONCOHERENT
>> 210 select CEVT_R4K
>> 211 select CSRC_R4K
>> 212 select IRQ_MIPS_CPU
>> 213 select NO_EXCEPT_FILL
>> 214 select SWAP_IO_SPACE
>> 215 select SYS_HAS_CPU_MIPS32_R1
>> 216 select SYS_HAS_EARLY_PRINTK
>> 217 select SYS_SUPPORTS_32BIT_KERNEL
>> 218 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 219 select SYS_SUPPORTS_MIPS16
>> 220 select SYS_SUPPORTS_ZBOOT_UART16550
>> 221 select GPIOLIB
>> 222 select VLYNQ
>> 223 help
>> 224 Support for the Texas Instruments AR7 System-on-a-Chip
>> 225 family: TNETD7100, 7200 and 7300.
>> 226
>> 227 config ATH25
>> 228 bool "Atheros AR231x/AR531x SoC support"
>> 229 select CEVT_R4K
>> 230 select CSRC_R4K
>> 231 select DMA_NONCOHERENT
>> 232 select IRQ_MIPS_CPU
>> 233 select IRQ_DOMAIN
>> 234 select SYS_HAS_CPU_MIPS32_R1
>> 235 select SYS_SUPPORTS_BIG_ENDIAN
>> 236 select SYS_SUPPORTS_32BIT_KERNEL
>> 237 select SYS_HAS_EARLY_PRINTK
>> 238 help
>> 239 Support for Atheros AR231x and Atheros AR531x based boards
>> 240
>> 241 config ATH79
>> 242 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 243 select ARCH_HAS_RESET_CONTROLLER
>> 244 select BOOT_RAW
>> 245 select CEVT_R4K
>> 246 select CSRC_R4K
>> 247 select DMA_NONCOHERENT
>> 248 select GPIOLIB
>> 249 select PINCTRL
>> 250 select COMMON_CLK
>> 251 select IRQ_MIPS_CPU
>> 252 select SYS_HAS_CPU_MIPS32_R2
>> 253 select SYS_HAS_EARLY_PRINTK
>> 254 select SYS_SUPPORTS_32BIT_KERNEL
>> 255 select SYS_SUPPORTS_BIG_ENDIAN
>> 256 select SYS_SUPPORTS_MIPS16
>> 257 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 258 select USE_OF
>> 259 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 260 help
>> 261 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 262
>> 263 config BMIPS_GENERIC
>> 264 bool "Broadcom Generic BMIPS kernel"
>> 265 select ARCH_HAS_RESET_CONTROLLER
>> 266 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 267 select ARCH_HAS_PHYS_TO_DMA
>> 268 select BOOT_RAW
>> 269 select NO_EXCEPT_FILL
>> 270 select USE_OF
>> 271 select CEVT_R4K
>> 272 select CSRC_R4K
>> 273 select SYNC_R4K
>> 274 select COMMON_CLK
>> 275 select BCM6345_L1_IRQ
>> 276 select BCM7038_L1_IRQ
>> 277 select BCM7120_L2_IRQ
>> 278 select BRCMSTB_L2_IRQ
>> 279 select IRQ_MIPS_CPU
>> 280 select DMA_NONCOHERENT
>> 281 select SYS_SUPPORTS_32BIT_KERNEL
>> 282 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 283 select SYS_SUPPORTS_BIG_ENDIAN
>> 284 select SYS_SUPPORTS_HIGHMEM
>> 285 select SYS_HAS_CPU_BMIPS32_3300
>> 286 select SYS_HAS_CPU_BMIPS4350
>> 287 select SYS_HAS_CPU_BMIPS4380
>> 288 select SYS_HAS_CPU_BMIPS5000
>> 289 select SWAP_IO_SPACE
>> 290 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 291 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 292 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 293 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 294 select HARDIRQS_SW_RESEND
>> 295 select HAVE_PCI
>> 296 select PCI_DRIVERS_GENERIC
60 help 297 help
61 Xtensa processors are 32-bit RISC ma !! 298 Build a generic DT-based kernel image that boots on select
62 primarily for embedded systems. The !! 299 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
63 configurable and extensible. The Li !! 300 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
64 architecture supports all processor !! 301 must be set appropriately for your board.
65 with reasonable minimum requirements !! 302
66 a home page at <http://www.linux-xte !! 303 config BCM47XX
>> 304 bool "Broadcom BCM47XX based boards"
>> 305 select BOOT_RAW
>> 306 select CEVT_R4K
>> 307 select CSRC_R4K
>> 308 select DMA_NONCOHERENT
>> 309 select HAVE_PCI
>> 310 select IRQ_MIPS_CPU
>> 311 select SYS_HAS_CPU_MIPS32_R1
>> 312 select NO_EXCEPT_FILL
>> 313 select SYS_SUPPORTS_32BIT_KERNEL
>> 314 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 315 select SYS_SUPPORTS_MIPS16
>> 316 select SYS_SUPPORTS_ZBOOT
>> 317 select SYS_HAS_EARLY_PRINTK
>> 318 select USE_GENERIC_EARLY_PRINTK_8250
>> 319 select GPIOLIB
>> 320 select LEDS_GPIO_REGISTER
>> 321 select BCM47XX_NVRAM
>> 322 select BCM47XX_SPROM
>> 323 select BCM47XX_SSB if !BCM47XX_BCMA
>> 324 help
>> 325 Support for BCM47XX based boards
>> 326
>> 327 config BCM63XX
>> 328 bool "Broadcom BCM63XX based boards"
>> 329 select BOOT_RAW
>> 330 select CEVT_R4K
>> 331 select CSRC_R4K
>> 332 select SYNC_R4K
>> 333 select DMA_NONCOHERENT
>> 334 select IRQ_MIPS_CPU
>> 335 select SYS_SUPPORTS_32BIT_KERNEL
>> 336 select SYS_SUPPORTS_BIG_ENDIAN
>> 337 select SYS_HAS_EARLY_PRINTK
>> 338 select SYS_HAS_CPU_BMIPS32_3300
>> 339 select SYS_HAS_CPU_BMIPS4350
>> 340 select SYS_HAS_CPU_BMIPS4380
>> 341 select SWAP_IO_SPACE
>> 342 select GPIOLIB
>> 343 select MIPS_L1_CACHE_SHIFT_4
>> 344 select HAVE_LEGACY_CLK
>> 345 help
>> 346 Support for BCM63XX based boards
>> 347
>> 348 config MIPS_COBALT
>> 349 bool "Cobalt Server"
>> 350 select CEVT_R4K
>> 351 select CSRC_R4K
>> 352 select CEVT_GT641XX
>> 353 select DMA_NONCOHERENT
>> 354 select FORCE_PCI
>> 355 select I8253
>> 356 select I8259
>> 357 select IRQ_MIPS_CPU
>> 358 select IRQ_GT641XX
>> 359 select PCI_GT64XXX_PCI0
>> 360 select SYS_HAS_CPU_NEVADA
>> 361 select SYS_HAS_EARLY_PRINTK
>> 362 select SYS_SUPPORTS_32BIT_KERNEL
>> 363 select SYS_SUPPORTS_64BIT_KERNEL
>> 364 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 365 select USE_GENERIC_EARLY_PRINTK_8250
>> 366
>> 367 config MACH_DECSTATION
>> 368 bool "DECstations"
>> 369 select BOOT_ELF32
>> 370 select CEVT_DS1287
>> 371 select CEVT_R4K if CPU_R4X00
>> 372 select CSRC_IOASIC
>> 373 select CSRC_R4K if CPU_R4X00
>> 374 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 375 select CPU_R4000_WORKAROUNDS if 64BIT
>> 376 select CPU_R4400_WORKAROUNDS if 64BIT
>> 377 select DMA_NONCOHERENT
>> 378 select NO_IOPORT_MAP
>> 379 select IRQ_MIPS_CPU
>> 380 select SYS_HAS_CPU_R3000
>> 381 select SYS_HAS_CPU_R4X00
>> 382 select SYS_SUPPORTS_32BIT_KERNEL
>> 383 select SYS_SUPPORTS_64BIT_KERNEL
>> 384 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 385 select SYS_SUPPORTS_128HZ
>> 386 select SYS_SUPPORTS_256HZ
>> 387 select SYS_SUPPORTS_1024HZ
>> 388 select MIPS_L1_CACHE_SHIFT_4
>> 389 help
>> 390 This enables support for DEC's MIPS based workstations. For details
>> 391 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 392 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 393
>> 394 If you have one of the following DECstation Models you definitely
>> 395 want to choose R4xx0 for the CPU Type:
>> 396
>> 397 DECstation 5000/50
>> 398 DECstation 5000/150
>> 399 DECstation 5000/260
>> 400 DECsystem 5900/260
>> 401
>> 402 otherwise choose R3000.
>> 403
>> 404 config MACH_JAZZ
>> 405 bool "Jazz family of machines"
>> 406 select ARC_MEMORY
>> 407 select ARC_PROMLIB
>> 408 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 409 select ARCH_MIGHT_HAVE_PC_SERIO
>> 410 select DMA_OPS
>> 411 select FW_ARC
>> 412 select FW_ARC32
>> 413 select ARCH_MAY_HAVE_PC_FDC
>> 414 select CEVT_R4K
>> 415 select CSRC_R4K
>> 416 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 417 select GENERIC_ISA_DMA
>> 418 select HAVE_PCSPKR_PLATFORM
>> 419 select IRQ_MIPS_CPU
>> 420 select I8253
>> 421 select I8259
>> 422 select ISA
>> 423 select SYS_HAS_CPU_R4X00
>> 424 select SYS_SUPPORTS_32BIT_KERNEL
>> 425 select SYS_SUPPORTS_64BIT_KERNEL
>> 426 select SYS_SUPPORTS_100HZ
>> 427 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 428 help
>> 429 This a family of machines based on the MIPS R4030 chipset which was
>> 430 used by several vendors to build RISC/os and Windows NT workstations.
>> 431 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 432 Olivetti M700-10 workstations.
>> 433
>> 434 config MACH_INGENIC_SOC
>> 435 bool "Ingenic SoC based machines"
>> 436 select MIPS_GENERIC
>> 437 select MACH_INGENIC
>> 438 select SYS_SUPPORTS_ZBOOT_UART16550
>> 439 select CPU_SUPPORTS_CPUFREQ
>> 440 select MIPS_EXTERNAL_TIMER
>> 441
>> 442 config LANTIQ
>> 443 bool "Lantiq based platforms"
>> 444 select DMA_NONCOHERENT
>> 445 select IRQ_MIPS_CPU
>> 446 select CEVT_R4K
>> 447 select CSRC_R4K
>> 448 select SYS_HAS_CPU_MIPS32_R1
>> 449 select SYS_HAS_CPU_MIPS32_R2
>> 450 select SYS_SUPPORTS_BIG_ENDIAN
>> 451 select SYS_SUPPORTS_32BIT_KERNEL
>> 452 select SYS_SUPPORTS_MIPS16
>> 453 select SYS_SUPPORTS_MULTITHREADING
>> 454 select SYS_SUPPORTS_VPE_LOADER
>> 455 select SYS_HAS_EARLY_PRINTK
>> 456 select GPIOLIB
>> 457 select SWAP_IO_SPACE
>> 458 select BOOT_RAW
>> 459 select HAVE_LEGACY_CLK
>> 460 select USE_OF
>> 461 select PINCTRL
>> 462 select PINCTRL_LANTIQ
>> 463 select ARCH_HAS_RESET_CONTROLLER
>> 464 select RESET_CONTROLLER
>> 465
>> 466 config MACH_LOONGSON32
>> 467 bool "Loongson 32-bit family of machines"
>> 468 select SYS_SUPPORTS_ZBOOT
>> 469 help
>> 470 This enables support for the Loongson-1 family of machines.
>> 471
>> 472 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 473 the Institute of Computing Technology (ICT), Chinese Academy of
>> 474 Sciences (CAS).
>> 475
>> 476 config MACH_LOONGSON2EF
>> 477 bool "Loongson-2E/F family of machines"
>> 478 select SYS_SUPPORTS_ZBOOT
>> 479 help
>> 480 This enables the support of early Loongson-2E/F family of machines.
>> 481
>> 482 config MACH_LOONGSON64
>> 483 bool "Loongson 64-bit family of machines"
>> 484 select ARCH_SPARSEMEM_ENABLE
>> 485 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 486 select ARCH_MIGHT_HAVE_PC_SERIO
>> 487 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 488 select BOOT_ELF32
>> 489 select BOARD_SCACHE
>> 490 select CSRC_R4K
>> 491 select CEVT_R4K
>> 492 select CPU_HAS_WB
>> 493 select FORCE_PCI
>> 494 select ISA
>> 495 select I8259
>> 496 select IRQ_MIPS_CPU
>> 497 select NO_EXCEPT_FILL
>> 498 select NR_CPUS_DEFAULT_64
>> 499 select USE_GENERIC_EARLY_PRINTK_8250
>> 500 select PCI_DRIVERS_GENERIC
>> 501 select SYS_HAS_CPU_LOONGSON64
>> 502 select SYS_HAS_EARLY_PRINTK
>> 503 select SYS_SUPPORTS_SMP
>> 504 select SYS_SUPPORTS_HOTPLUG_CPU
>> 505 select SYS_SUPPORTS_NUMA
>> 506 select SYS_SUPPORTS_64BIT_KERNEL
>> 507 select SYS_SUPPORTS_HIGHMEM
>> 508 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 509 select SYS_SUPPORTS_ZBOOT
>> 510 select SYS_SUPPORTS_RELOCATABLE
>> 511 select ZONE_DMA32
>> 512 select COMMON_CLK
>> 513 select USE_OF
>> 514 select BUILTIN_DTB
>> 515 select PCI_HOST_GENERIC
>> 516 help
>> 517 This enables the support of Loongson-2/3 family of machines.
>> 518
>> 519 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 520 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 521 and Loongson-2F which will be removed), developed by the Institute
>> 522 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 523
>> 524 config MIPS_MALTA
>> 525 bool "MIPS Malta board"
>> 526 select ARCH_MAY_HAVE_PC_FDC
>> 527 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 528 select ARCH_MIGHT_HAVE_PC_SERIO
>> 529 select BOOT_ELF32
>> 530 select BOOT_RAW
>> 531 select BUILTIN_DTB
>> 532 select CEVT_R4K
>> 533 select CLKSRC_MIPS_GIC
>> 534 select COMMON_CLK
>> 535 select CSRC_R4K
>> 536 select DMA_NONCOHERENT
>> 537 select GENERIC_ISA_DMA
>> 538 select HAVE_PCSPKR_PLATFORM
>> 539 select HAVE_PCI
>> 540 select I8253
>> 541 select I8259
>> 542 select IRQ_MIPS_CPU
>> 543 select MIPS_BONITO64
>> 544 select MIPS_CPU_SCACHE
>> 545 select MIPS_GIC
>> 546 select MIPS_L1_CACHE_SHIFT_6
>> 547 select MIPS_MSC
>> 548 select PCI_GT64XXX_PCI0
>> 549 select SMP_UP if SMP
>> 550 select SWAP_IO_SPACE
>> 551 select SYS_HAS_CPU_MIPS32_R1
>> 552 select SYS_HAS_CPU_MIPS32_R2
>> 553 select SYS_HAS_CPU_MIPS32_R3_5
>> 554 select SYS_HAS_CPU_MIPS32_R5
>> 555 select SYS_HAS_CPU_MIPS32_R6
>> 556 select SYS_HAS_CPU_MIPS64_R1
>> 557 select SYS_HAS_CPU_MIPS64_R2
>> 558 select SYS_HAS_CPU_MIPS64_R6
>> 559 select SYS_HAS_CPU_NEVADA
>> 560 select SYS_HAS_CPU_RM7000
>> 561 select SYS_SUPPORTS_32BIT_KERNEL
>> 562 select SYS_SUPPORTS_64BIT_KERNEL
>> 563 select SYS_SUPPORTS_BIG_ENDIAN
>> 564 select SYS_SUPPORTS_HIGHMEM
>> 565 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 566 select SYS_SUPPORTS_MICROMIPS
>> 567 select SYS_SUPPORTS_MIPS16
>> 568 select SYS_SUPPORTS_MIPS_CMP
>> 569 select SYS_SUPPORTS_MIPS_CPS
>> 570 select SYS_SUPPORTS_MULTITHREADING
>> 571 select SYS_SUPPORTS_RELOCATABLE
>> 572 select SYS_SUPPORTS_SMARTMIPS
>> 573 select SYS_SUPPORTS_VPE_LOADER
>> 574 select SYS_SUPPORTS_ZBOOT
>> 575 select USE_OF
>> 576 select WAR_ICACHE_REFILLS
>> 577 select ZONE_DMA32 if 64BIT
>> 578 help
>> 579 This enables support for the MIPS Technologies Malta evaluation
>> 580 board.
>> 581
>> 582 config MACH_PIC32
>> 583 bool "Microchip PIC32 Family"
>> 584 help
>> 585 This enables support for the Microchip PIC32 family of platforms.
>> 586
>> 587 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 588 microcontrollers.
>> 589
>> 590 config MACH_VR41XX
>> 591 bool "NEC VR4100 series based machines"
>> 592 select CEVT_R4K
>> 593 select CSRC_R4K
>> 594 select SYS_HAS_CPU_VR41XX
>> 595 select SYS_SUPPORTS_MIPS16
>> 596 select GPIOLIB
>> 597
>> 598 config MACH_NINTENDO64
>> 599 bool "Nintendo 64 console"
>> 600 select CEVT_R4K
>> 601 select CSRC_R4K
>> 602 select SYS_HAS_CPU_R4300
>> 603 select SYS_SUPPORTS_BIG_ENDIAN
>> 604 select SYS_SUPPORTS_ZBOOT
>> 605 select SYS_SUPPORTS_32BIT_KERNEL
>> 606 select SYS_SUPPORTS_64BIT_KERNEL
>> 607 select DMA_NONCOHERENT
>> 608 select IRQ_MIPS_CPU
>> 609
>> 610 config RALINK
>> 611 bool "Ralink based machines"
>> 612 select CEVT_R4K
>> 613 select COMMON_CLK
>> 614 select CSRC_R4K
>> 615 select BOOT_RAW
>> 616 select DMA_NONCOHERENT
>> 617 select IRQ_MIPS_CPU
>> 618 select USE_OF
>> 619 select SYS_HAS_CPU_MIPS32_R1
>> 620 select SYS_HAS_CPU_MIPS32_R2
>> 621 select SYS_SUPPORTS_32BIT_KERNEL
>> 622 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 623 select SYS_SUPPORTS_MIPS16
>> 624 select SYS_SUPPORTS_ZBOOT
>> 625 select SYS_HAS_EARLY_PRINTK
>> 626 select ARCH_HAS_RESET_CONTROLLER
>> 627 select RESET_CONTROLLER
>> 628
>> 629 config MACH_REALTEK_RTL
>> 630 bool "Realtek RTL838x/RTL839x based machines"
>> 631 select MIPS_GENERIC
>> 632 select DMA_NONCOHERENT
>> 633 select IRQ_MIPS_CPU
>> 634 select CSRC_R4K
>> 635 select CEVT_R4K
>> 636 select SYS_HAS_CPU_MIPS32_R1
>> 637 select SYS_HAS_CPU_MIPS32_R2
>> 638 select SYS_SUPPORTS_BIG_ENDIAN
>> 639 select SYS_SUPPORTS_32BIT_KERNEL
>> 640 select SYS_SUPPORTS_MIPS16
>> 641 select SYS_SUPPORTS_MULTITHREADING
>> 642 select SYS_SUPPORTS_VPE_LOADER
>> 643 select SYS_HAS_EARLY_PRINTK
>> 644 select SYS_HAS_EARLY_PRINTK_8250
>> 645 select USE_GENERIC_EARLY_PRINTK_8250
>> 646 select BOOT_RAW
>> 647 select PINCTRL
>> 648 select USE_OF
>> 649
>> 650 config SGI_IP22
>> 651 bool "SGI IP22 (Indy/Indigo2)"
>> 652 select ARC_MEMORY
>> 653 select ARC_PROMLIB
>> 654 select FW_ARC
>> 655 select FW_ARC32
>> 656 select ARCH_MIGHT_HAVE_PC_SERIO
>> 657 select BOOT_ELF32
>> 658 select CEVT_R4K
>> 659 select CSRC_R4K
>> 660 select DEFAULT_SGI_PARTITION
>> 661 select DMA_NONCOHERENT
>> 662 select HAVE_EISA
>> 663 select I8253
>> 664 select I8259
>> 665 select IP22_CPU_SCACHE
>> 666 select IRQ_MIPS_CPU
>> 667 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 668 select SGI_HAS_I8042
>> 669 select SGI_HAS_INDYDOG
>> 670 select SGI_HAS_HAL2
>> 671 select SGI_HAS_SEEQ
>> 672 select SGI_HAS_WD93
>> 673 select SGI_HAS_ZILOG
>> 674 select SWAP_IO_SPACE
>> 675 select SYS_HAS_CPU_R4X00
>> 676 select SYS_HAS_CPU_R5000
>> 677 select SYS_HAS_EARLY_PRINTK
>> 678 select SYS_SUPPORTS_32BIT_KERNEL
>> 679 select SYS_SUPPORTS_64BIT_KERNEL
>> 680 select SYS_SUPPORTS_BIG_ENDIAN
>> 681 select WAR_R4600_V1_INDEX_ICACHEOP
>> 682 select WAR_R4600_V1_HIT_CACHEOP
>> 683 select WAR_R4600_V2_HIT_CACHEOP
>> 684 select MIPS_L1_CACHE_SHIFT_7
>> 685 help
>> 686 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 687 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 688 that runs on these, say Y here.
>> 689
>> 690 config SGI_IP27
>> 691 bool "SGI IP27 (Origin200/2000)"
>> 692 select ARCH_HAS_PHYS_TO_DMA
>> 693 select ARCH_SPARSEMEM_ENABLE
>> 694 select FW_ARC
>> 695 select FW_ARC64
>> 696 select ARC_CMDLINE_ONLY
>> 697 select BOOT_ELF64
>> 698 select DEFAULT_SGI_PARTITION
>> 699 select FORCE_PCI
>> 700 select SYS_HAS_EARLY_PRINTK
>> 701 select HAVE_PCI
>> 702 select IRQ_MIPS_CPU
>> 703 select IRQ_DOMAIN_HIERARCHY
>> 704 select NR_CPUS_DEFAULT_64
>> 705 select PCI_DRIVERS_GENERIC
>> 706 select PCI_XTALK_BRIDGE
>> 707 select SYS_HAS_CPU_R10000
>> 708 select SYS_SUPPORTS_64BIT_KERNEL
>> 709 select SYS_SUPPORTS_BIG_ENDIAN
>> 710 select SYS_SUPPORTS_NUMA
>> 711 select SYS_SUPPORTS_SMP
>> 712 select WAR_R10000_LLSC
>> 713 select MIPS_L1_CACHE_SHIFT_7
>> 714 select NUMA
>> 715 help
>> 716 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 717 workstations. To compile a Linux kernel that runs on these, say Y
>> 718 here.
>> 719
>> 720 config SGI_IP28
>> 721 bool "SGI IP28 (Indigo2 R10k)"
>> 722 select ARC_MEMORY
>> 723 select ARC_PROMLIB
>> 724 select FW_ARC
>> 725 select FW_ARC64
>> 726 select ARCH_MIGHT_HAVE_PC_SERIO
>> 727 select BOOT_ELF64
>> 728 select CEVT_R4K
>> 729 select CSRC_R4K
>> 730 select DEFAULT_SGI_PARTITION
>> 731 select DMA_NONCOHERENT
>> 732 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 733 select IRQ_MIPS_CPU
>> 734 select HAVE_EISA
>> 735 select I8253
>> 736 select I8259
>> 737 select SGI_HAS_I8042
>> 738 select SGI_HAS_INDYDOG
>> 739 select SGI_HAS_HAL2
>> 740 select SGI_HAS_SEEQ
>> 741 select SGI_HAS_WD93
>> 742 select SGI_HAS_ZILOG
>> 743 select SWAP_IO_SPACE
>> 744 select SYS_HAS_CPU_R10000
>> 745 select SYS_HAS_EARLY_PRINTK
>> 746 select SYS_SUPPORTS_64BIT_KERNEL
>> 747 select SYS_SUPPORTS_BIG_ENDIAN
>> 748 select WAR_R10000_LLSC
>> 749 select MIPS_L1_CACHE_SHIFT_7
>> 750 help
>> 751 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 752 kernel that runs on these, say Y here.
>> 753
>> 754 config SGI_IP30
>> 755 bool "SGI IP30 (Octane/Octane2)"
>> 756 select ARCH_HAS_PHYS_TO_DMA
>> 757 select FW_ARC
>> 758 select FW_ARC64
>> 759 select BOOT_ELF64
>> 760 select CEVT_R4K
>> 761 select CSRC_R4K
>> 762 select FORCE_PCI
>> 763 select SYNC_R4K if SMP
>> 764 select ZONE_DMA32
>> 765 select HAVE_PCI
>> 766 select IRQ_MIPS_CPU
>> 767 select IRQ_DOMAIN_HIERARCHY
>> 768 select NR_CPUS_DEFAULT_2
>> 769 select PCI_DRIVERS_GENERIC
>> 770 select PCI_XTALK_BRIDGE
>> 771 select SYS_HAS_EARLY_PRINTK
>> 772 select SYS_HAS_CPU_R10000
>> 773 select SYS_SUPPORTS_64BIT_KERNEL
>> 774 select SYS_SUPPORTS_BIG_ENDIAN
>> 775 select SYS_SUPPORTS_SMP
>> 776 select WAR_R10000_LLSC
>> 777 select MIPS_L1_CACHE_SHIFT_7
>> 778 select ARC_MEMORY
>> 779 help
>> 780 These are the SGI Octane and Octane2 graphics workstations. To
>> 781 compile a Linux kernel that runs on these, say Y here.
>> 782
>> 783 config SGI_IP32
>> 784 bool "SGI IP32 (O2)"
>> 785 select ARC_MEMORY
>> 786 select ARC_PROMLIB
>> 787 select ARCH_HAS_PHYS_TO_DMA
>> 788 select FW_ARC
>> 789 select FW_ARC32
>> 790 select BOOT_ELF32
>> 791 select CEVT_R4K
>> 792 select CSRC_R4K
>> 793 select DMA_NONCOHERENT
>> 794 select HAVE_PCI
>> 795 select IRQ_MIPS_CPU
>> 796 select R5000_CPU_SCACHE
>> 797 select RM7000_CPU_SCACHE
>> 798 select SYS_HAS_CPU_R5000
>> 799 select SYS_HAS_CPU_R10000 if BROKEN
>> 800 select SYS_HAS_CPU_RM7000
>> 801 select SYS_HAS_CPU_NEVADA
>> 802 select SYS_SUPPORTS_64BIT_KERNEL
>> 803 select SYS_SUPPORTS_BIG_ENDIAN
>> 804 select WAR_ICACHE_REFILLS
>> 805 help
>> 806 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 807
>> 808 config SIBYTE_CRHINE
>> 809 bool "Sibyte BCM91120C-CRhine"
>> 810 select BOOT_ELF32
>> 811 select SIBYTE_BCM1120
>> 812 select SWAP_IO_SPACE
>> 813 select SYS_HAS_CPU_SB1
>> 814 select SYS_SUPPORTS_BIG_ENDIAN
>> 815 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 816
>> 817 config SIBYTE_CARMEL
>> 818 bool "Sibyte BCM91120x-Carmel"
>> 819 select BOOT_ELF32
>> 820 select SIBYTE_BCM1120
>> 821 select SWAP_IO_SPACE
>> 822 select SYS_HAS_CPU_SB1
>> 823 select SYS_SUPPORTS_BIG_ENDIAN
>> 824 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 825
>> 826 config SIBYTE_CRHONE
>> 827 bool "Sibyte BCM91125C-CRhone"
>> 828 select BOOT_ELF32
>> 829 select SIBYTE_BCM1125
>> 830 select SWAP_IO_SPACE
>> 831 select SYS_HAS_CPU_SB1
>> 832 select SYS_SUPPORTS_BIG_ENDIAN
>> 833 select SYS_SUPPORTS_HIGHMEM
>> 834 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 835
>> 836 config SIBYTE_RHONE
>> 837 bool "Sibyte BCM91125E-Rhone"
>> 838 select BOOT_ELF32
>> 839 select SIBYTE_BCM1125H
>> 840 select SWAP_IO_SPACE
>> 841 select SYS_HAS_CPU_SB1
>> 842 select SYS_SUPPORTS_BIG_ENDIAN
>> 843 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 844
>> 845 config SIBYTE_SWARM
>> 846 bool "Sibyte BCM91250A-SWARM"
>> 847 select BOOT_ELF32
>> 848 select HAVE_PATA_PLATFORM
>> 849 select SIBYTE_SB1250
>> 850 select SWAP_IO_SPACE
>> 851 select SYS_HAS_CPU_SB1
>> 852 select SYS_SUPPORTS_BIG_ENDIAN
>> 853 select SYS_SUPPORTS_HIGHMEM
>> 854 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 855 select ZONE_DMA32 if 64BIT
>> 856 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 857
>> 858 config SIBYTE_LITTLESUR
>> 859 bool "Sibyte BCM91250C2-LittleSur"
>> 860 select BOOT_ELF32
>> 861 select HAVE_PATA_PLATFORM
>> 862 select SIBYTE_SB1250
>> 863 select SWAP_IO_SPACE
>> 864 select SYS_HAS_CPU_SB1
>> 865 select SYS_SUPPORTS_BIG_ENDIAN
>> 866 select SYS_SUPPORTS_HIGHMEM
>> 867 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 868 select ZONE_DMA32 if 64BIT
>> 869
>> 870 config SIBYTE_SENTOSA
>> 871 bool "Sibyte BCM91250E-Sentosa"
>> 872 select BOOT_ELF32
>> 873 select SIBYTE_SB1250
>> 874 select SWAP_IO_SPACE
>> 875 select SYS_HAS_CPU_SB1
>> 876 select SYS_SUPPORTS_BIG_ENDIAN
>> 877 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 878 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 879
>> 880 config SIBYTE_BIGSUR
>> 881 bool "Sibyte BCM91480B-BigSur"
>> 882 select BOOT_ELF32
>> 883 select NR_CPUS_DEFAULT_4
>> 884 select SIBYTE_BCM1x80
>> 885 select SWAP_IO_SPACE
>> 886 select SYS_HAS_CPU_SB1
>> 887 select SYS_SUPPORTS_BIG_ENDIAN
>> 888 select SYS_SUPPORTS_HIGHMEM
>> 889 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 890 select ZONE_DMA32 if 64BIT
>> 891 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 892
>> 893 config SNI_RM
>> 894 bool "SNI RM200/300/400"
>> 895 select ARC_MEMORY
>> 896 select ARC_PROMLIB
>> 897 select FW_ARC if CPU_LITTLE_ENDIAN
>> 898 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 899 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 900 select ARCH_MAY_HAVE_PC_FDC
>> 901 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 902 select ARCH_MIGHT_HAVE_PC_SERIO
>> 903 select BOOT_ELF32
>> 904 select CEVT_R4K
>> 905 select CSRC_R4K
>> 906 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 907 select DMA_NONCOHERENT
>> 908 select GENERIC_ISA_DMA
>> 909 select HAVE_EISA
>> 910 select HAVE_PCSPKR_PLATFORM
>> 911 select HAVE_PCI
>> 912 select IRQ_MIPS_CPU
>> 913 select I8253
>> 914 select I8259
>> 915 select ISA
>> 916 select MIPS_L1_CACHE_SHIFT_6
>> 917 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 918 select SYS_HAS_CPU_R4X00
>> 919 select SYS_HAS_CPU_R5000
>> 920 select SYS_HAS_CPU_R10000
>> 921 select R5000_CPU_SCACHE
>> 922 select SYS_HAS_EARLY_PRINTK
>> 923 select SYS_SUPPORTS_32BIT_KERNEL
>> 924 select SYS_SUPPORTS_64BIT_KERNEL
>> 925 select SYS_SUPPORTS_BIG_ENDIAN
>> 926 select SYS_SUPPORTS_HIGHMEM
>> 927 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 928 select WAR_R4600_V2_HIT_CACHEOP
>> 929 help
>> 930 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 931 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 932 Technology and now in turn merged with Fujitsu. Say Y here to
>> 933 support this machine type.
>> 934
>> 935 config MACH_TX39XX
>> 936 bool "Toshiba TX39 series based machines"
>> 937
>> 938 config MACH_TX49XX
>> 939 bool "Toshiba TX49 series based machines"
>> 940 select WAR_TX49XX_ICACHE_INDEX_INV
>> 941
>> 942 config MIKROTIK_RB532
>> 943 bool "Mikrotik RB532 boards"
>> 944 select CEVT_R4K
>> 945 select CSRC_R4K
>> 946 select DMA_NONCOHERENT
>> 947 select HAVE_PCI
>> 948 select IRQ_MIPS_CPU
>> 949 select SYS_HAS_CPU_MIPS32_R1
>> 950 select SYS_SUPPORTS_32BIT_KERNEL
>> 951 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 952 select SWAP_IO_SPACE
>> 953 select BOOT_RAW
>> 954 select GPIOLIB
>> 955 select MIPS_L1_CACHE_SHIFT_4
>> 956 help
>> 957 Support the Mikrotik(tm) RouterBoard 532 series,
>> 958 based on the IDT RC32434 SoC.
>> 959
>> 960 config CAVIUM_OCTEON_SOC
>> 961 bool "Cavium Networks Octeon SoC based boards"
>> 962 select CEVT_R4K
>> 963 select ARCH_HAS_PHYS_TO_DMA
>> 964 select HAVE_RAPIDIO
>> 965 select PHYS_ADDR_T_64BIT
>> 966 select SYS_SUPPORTS_64BIT_KERNEL
>> 967 select SYS_SUPPORTS_BIG_ENDIAN
>> 968 select EDAC_SUPPORT
>> 969 select EDAC_ATOMIC_SCRUB
>> 970 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 971 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 972 select SYS_HAS_EARLY_PRINTK
>> 973 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 974 select HAVE_PCI
>> 975 select HAVE_PLAT_DELAY
>> 976 select HAVE_PLAT_FW_INIT_CMDLINE
>> 977 select HAVE_PLAT_MEMCPY
>> 978 select ZONE_DMA32
>> 979 select GPIOLIB
>> 980 select USE_OF
>> 981 select ARCH_SPARSEMEM_ENABLE
>> 982 select SYS_SUPPORTS_SMP
>> 983 select NR_CPUS_DEFAULT_64
>> 984 select MIPS_NR_CPU_NR_MAP_1024
>> 985 select BUILTIN_DTB
>> 986 select MTD
>> 987 select MTD_COMPLEX_MAPPINGS
>> 988 select SWIOTLB
>> 989 select SYS_SUPPORTS_RELOCATABLE
>> 990 help
>> 991 This option supports all of the Octeon reference boards from Cavium
>> 992 Networks. It builds a kernel that dynamically determines the Octeon
>> 993 CPU type and supports all known board reference implementations.
>> 994 Some of the supported boards are:
>> 995 EBT3000
>> 996 EBH3000
>> 997 EBH3100
>> 998 Thunder
>> 999 Kodama
>> 1000 Hikari
>> 1001 Say Y here for most Octeon reference boards.
>> 1002
>> 1003 endchoice
>> 1004
>> 1005 source "arch/mips/alchemy/Kconfig"
>> 1006 source "arch/mips/ath25/Kconfig"
>> 1007 source "arch/mips/ath79/Kconfig"
>> 1008 source "arch/mips/bcm47xx/Kconfig"
>> 1009 source "arch/mips/bcm63xx/Kconfig"
>> 1010 source "arch/mips/bmips/Kconfig"
>> 1011 source "arch/mips/generic/Kconfig"
>> 1012 source "arch/mips/ingenic/Kconfig"
>> 1013 source "arch/mips/jazz/Kconfig"
>> 1014 source "arch/mips/lantiq/Kconfig"
>> 1015 source "arch/mips/pic32/Kconfig"
>> 1016 source "arch/mips/ralink/Kconfig"
>> 1017 source "arch/mips/sgi-ip27/Kconfig"
>> 1018 source "arch/mips/sibyte/Kconfig"
>> 1019 source "arch/mips/txx9/Kconfig"
>> 1020 source "arch/mips/vr41xx/Kconfig"
>> 1021 source "arch/mips/cavium-octeon/Kconfig"
>> 1022 source "arch/mips/loongson2ef/Kconfig"
>> 1023 source "arch/mips/loongson32/Kconfig"
>> 1024 source "arch/mips/loongson64/Kconfig"
>> 1025
>> 1026 endmenu
67 1027
68 config GENERIC_HWEIGHT 1028 config GENERIC_HWEIGHT
69 def_bool y !! 1029 bool
>> 1030 default y
70 1031
71 config ARCH_HAS_ILOG2_U32 !! 1032 config GENERIC_CALIBRATE_DELAY
72 def_bool n !! 1033 bool
>> 1034 default y
73 1035
74 config ARCH_HAS_ILOG2_U64 !! 1036 config SCHED_OMIT_FRAME_POINTER
75 def_bool n !! 1037 bool
>> 1038 default y
76 1039
77 config ARCH_MTD_XIP !! 1040 #
78 def_bool y !! 1041 # Select some configuration options automatically based on user selections.
>> 1042 #
>> 1043 config FW_ARC
>> 1044 bool
>> 1045
>> 1046 config ARCH_MAY_HAVE_PC_FDC
>> 1047 bool
>> 1048
>> 1049 config BOOT_RAW
>> 1050 bool
>> 1051
>> 1052 config CEVT_BCM1480
>> 1053 bool
>> 1054
>> 1055 config CEVT_DS1287
>> 1056 bool
>> 1057
>> 1058 config CEVT_GT641XX
>> 1059 bool
>> 1060
>> 1061 config CEVT_R4K
>> 1062 bool
>> 1063
>> 1064 config CEVT_SB1250
>> 1065 bool
>> 1066
>> 1067 config CEVT_TXX9
>> 1068 bool
>> 1069
>> 1070 config CSRC_BCM1480
>> 1071 bool
>> 1072
>> 1073 config CSRC_IOASIC
>> 1074 bool
>> 1075
>> 1076 config CSRC_R4K
>> 1077 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1078 bool
>> 1079
>> 1080 config CSRC_SB1250
>> 1081 bool
>> 1082
>> 1083 config MIPS_CLOCK_VSYSCALL
>> 1084 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1085
>> 1086 config GPIO_TXX9
>> 1087 select GPIOLIB
>> 1088 bool
>> 1089
>> 1090 config FW_CFE
>> 1091 bool
>> 1092
>> 1093 config ARCH_SUPPORTS_UPROBES
>> 1094 bool
>> 1095
>> 1096 config DMA_PERDEV_COHERENT
>> 1097 bool
>> 1098 select ARCH_HAS_SETUP_DMA_OPS
>> 1099 select DMA_NONCOHERENT
>> 1100
>> 1101 config DMA_NONCOHERENT
>> 1102 bool
>> 1103 #
>> 1104 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1105 # Attribute bits. It is believed that the uncached access through
>> 1106 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1107 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1108 # significant advantages.
>> 1109 #
>> 1110 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1111 select ARCH_HAS_DMA_PREP_COHERENT
>> 1112 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1113 select ARCH_HAS_DMA_SET_UNCACHED
>> 1114 select DMA_NONCOHERENT_MMAP
>> 1115 select NEED_DMA_MAP_STATE
>> 1116
>> 1117 config SYS_HAS_EARLY_PRINTK
>> 1118 bool
>> 1119
>> 1120 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1121 bool
>> 1122
>> 1123 config MIPS_BONITO64
>> 1124 bool
>> 1125
>> 1126 config MIPS_MSC
>> 1127 bool
>> 1128
>> 1129 config SYNC_R4K
>> 1130 bool
79 1131
80 config NO_IOPORT_MAP 1132 config NO_IOPORT_MAP
81 def_bool n 1133 def_bool n
82 1134
83 config HZ !! 1135 config GENERIC_CSUM
84 int !! 1136 def_bool CPU_NO_LOAD_STORE_LR
85 default 100 <<
86 1137
87 config LOCKDEP_SUPPORT !! 1138 config GENERIC_ISA_DMA
88 def_bool y !! 1139 bool
>> 1140 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1141 select ISA_DMA_API
89 1142
90 config STACKTRACE_SUPPORT !! 1143 config GENERIC_ISA_DMA_SUPPORT_BROKEN
91 def_bool y !! 1144 bool
>> 1145 select GENERIC_ISA_DMA
92 1146
93 config MMU !! 1147 config HAVE_PLAT_DELAY
94 def_bool n !! 1148 bool
95 select PFAULT <<
96 1149
97 config HAVE_XTENSA_GPIO32 !! 1150 config HAVE_PLAT_FW_INIT_CMDLINE
98 def_bool n !! 1151 bool
99 1152
100 config KASAN_SHADOW_OFFSET !! 1153 config HAVE_PLAT_MEMCPY
101 hex !! 1154 bool
102 default 0x6e400000 !! 1155
>> 1156 config ISA_DMA_API
>> 1157 bool
>> 1158
>> 1159 config SYS_SUPPORTS_RELOCATABLE
>> 1160 bool
>> 1161 help
>> 1162 Selected if the platform supports relocating the kernel.
>> 1163 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1164 to allow access to command line and entropy sources.
>> 1165
>> 1166 #
>> 1167 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1168 # answer,so we try hard to limit the available choices. Also the use of a
>> 1169 # choice statement should be more obvious to the user.
>> 1170 #
>> 1171 choice
>> 1172 prompt "Endianness selection"
>> 1173 help
>> 1174 Some MIPS machines can be configured for either little or big endian
>> 1175 byte order. These modes require different kernels and a different
>> 1176 Linux distribution. In general there is one preferred byteorder for a
>> 1177 particular system but some systems are just as commonly used in the
>> 1178 one or the other endianness.
103 1179
104 config CPU_BIG_ENDIAN 1180 config CPU_BIG_ENDIAN
105 def_bool $(success,test "$(shell,echo !! 1181 bool "Big endian"
>> 1182 depends on SYS_SUPPORTS_BIG_ENDIAN
106 1183
107 config CPU_LITTLE_ENDIAN 1184 config CPU_LITTLE_ENDIAN
108 def_bool !CPU_BIG_ENDIAN !! 1185 bool "Little endian"
>> 1186 depends on SYS_SUPPORTS_LITTLE_ENDIAN
>> 1187
>> 1188 endchoice
>> 1189
>> 1190 config EXPORT_UASM
>> 1191 bool
>> 1192
>> 1193 config SYS_SUPPORTS_APM_EMULATION
>> 1194 bool
>> 1195
>> 1196 config SYS_SUPPORTS_BIG_ENDIAN
>> 1197 bool
>> 1198
>> 1199 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1200 bool
>> 1201
>> 1202 config MIPS_HUGE_TLB_SUPPORT
>> 1203 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
>> 1204
>> 1205 config IRQ_MSP_SLP
>> 1206 bool
>> 1207
>> 1208 config IRQ_MSP_CIC
>> 1209 bool
>> 1210
>> 1211 config IRQ_TXX9
>> 1212 bool
>> 1213
>> 1214 config IRQ_GT641XX
>> 1215 bool
>> 1216
>> 1217 config PCI_GT64XXX_PCI0
>> 1218 bool
>> 1219
>> 1220 config PCI_XTALK_BRIDGE
>> 1221 bool
>> 1222
>> 1223 config NO_EXCEPT_FILL
>> 1224 bool
>> 1225
>> 1226 config MIPS_SPRAM
>> 1227 bool
>> 1228
>> 1229 config SWAP_IO_SPACE
>> 1230 bool
>> 1231
>> 1232 config SGI_HAS_INDYDOG
>> 1233 bool
>> 1234
>> 1235 config SGI_HAS_HAL2
>> 1236 bool
>> 1237
>> 1238 config SGI_HAS_SEEQ
>> 1239 bool
109 1240
110 config CC_HAVE_CALL0_ABI !! 1241 config SGI_HAS_WD93
111 def_bool $(success,test "$(shell,echo !! 1242 bool
>> 1243
>> 1244 config SGI_HAS_ZILOG
>> 1245 bool
>> 1246
>> 1247 config SGI_HAS_I8042
>> 1248 bool
>> 1249
>> 1250 config DEFAULT_SGI_PARTITION
>> 1251 bool
>> 1252
>> 1253 config FW_ARC32
>> 1254 bool
>> 1255
>> 1256 config FW_SNIPROM
>> 1257 bool
>> 1258
>> 1259 config BOOT_ELF32
>> 1260 bool
>> 1261
>> 1262 config MIPS_L1_CACHE_SHIFT_4
>> 1263 bool
>> 1264
>> 1265 config MIPS_L1_CACHE_SHIFT_5
>> 1266 bool
>> 1267
>> 1268 config MIPS_L1_CACHE_SHIFT_6
>> 1269 bool
>> 1270
>> 1271 config MIPS_L1_CACHE_SHIFT_7
>> 1272 bool
>> 1273
>> 1274 config MIPS_L1_CACHE_SHIFT
>> 1275 int
>> 1276 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1277 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1278 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1279 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1280 default "5"
>> 1281
>> 1282 config ARC_CMDLINE_ONLY
>> 1283 bool
>> 1284
>> 1285 config ARC_CONSOLE
>> 1286 bool "ARC console support"
>> 1287 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
>> 1288
>> 1289 config ARC_MEMORY
>> 1290 bool
>> 1291
>> 1292 config ARC_PROMLIB
>> 1293 bool
112 1294
113 menu "Processor type and features" !! 1295 config FW_ARC64
>> 1296 bool
>> 1297
>> 1298 config BOOT_ELF64
>> 1299 bool
>> 1300
>> 1301 menu "CPU selection"
114 1302
115 choice 1303 choice
116 prompt "Xtensa Processor Configuration !! 1304 prompt "CPU type"
117 default XTENSA_VARIANT_FSF !! 1305 default CPU_R4X00
118 1306
119 config XTENSA_VARIANT_FSF !! 1307 config CPU_LOONGSON64
120 bool "fsf - default (not generic) conf !! 1308 bool "Loongson 64-bit CPU"
121 select MMU !! 1309 depends on SYS_HAS_CPU_LOONGSON64
>> 1310 select ARCH_HAS_PHYS_TO_DMA
>> 1311 select CPU_MIPSR2
>> 1312 select CPU_HAS_PREFETCH
>> 1313 select CPU_SUPPORTS_64BIT_KERNEL
>> 1314 select CPU_SUPPORTS_HIGHMEM
>> 1315 select CPU_SUPPORTS_HUGEPAGES
>> 1316 select CPU_SUPPORTS_MSA
>> 1317 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1318 select CPU_MIPSR2_IRQ_VI
>> 1319 select WEAK_ORDERING
>> 1320 select WEAK_REORDERING_BEYOND_LLSC
>> 1321 select MIPS_ASID_BITS_VARIABLE
>> 1322 select MIPS_PGD_C0_CONTEXT
>> 1323 select MIPS_L1_CACHE_SHIFT_6
>> 1324 select MIPS_FP_SUPPORT
>> 1325 select GPIOLIB
>> 1326 select SWIOTLB
>> 1327 select HAVE_KVM
>> 1328 help
>> 1329 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1330 cores implements the MIPS64R2 instruction set with many extensions,
>> 1331 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1332 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1333 Loongson-2E/2F is not covered here and will be removed in future.
122 1334
123 config XTENSA_VARIANT_DC232B !! 1335 config LOONGSON3_ENHANCEMENT
124 bool "dc232b - Diamond 232L Standard C !! 1336 bool "New Loongson-3 CPU Enhancements"
125 select MMU !! 1337 default n
126 select HAVE_XTENSA_GPIO32 !! 1338 depends on CPU_LOONGSON64
127 help 1339 help
128 This variant refers to Tensilica's D !! 1340 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1341 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1342 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1343 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1344 Fast TLB refill support, etc.
>> 1345
>> 1346 This option enable those enhancements which are not probed at run
>> 1347 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1348 please say 'N' here. If you want a high-performance kernel to run on
>> 1349 new Loongson-3 machines only, please say 'Y' here.
>> 1350
>> 1351 config CPU_LOONGSON3_WORKAROUNDS
>> 1352 bool "Old Loongson-3 LLSC Workarounds"
>> 1353 default y if SMP
>> 1354 depends on CPU_LOONGSON64
>> 1355 help
>> 1356 Loongson-3 processors have the llsc issues which require workarounds.
>> 1357 Without workarounds the system may hang unexpectedly.
>> 1358
>> 1359 Newer Loongson-3 will fix these issues and no workarounds are needed.
>> 1360 The workarounds have no significant side effect on them but may
>> 1361 decrease the performance of the system so this option should be
>> 1362 disabled unless the kernel is intended to be run on old systems.
129 1363
130 config XTENSA_VARIANT_DC233C !! 1364 If unsure, please say Y.
131 bool "dc233c - Diamond 233L Standard C <<
132 select MMU <<
133 select HAVE_XTENSA_GPIO32 <<
134 help <<
135 This variant refers to Tensilica's D <<
136 1365
137 config XTENSA_VARIANT_CUSTOM !! 1366 config CPU_LOONGSON3_CPUCFG_EMULATION
138 bool "Custom Xtensa processor configur !! 1367 bool "Emulate the CPUCFG instruction on older Loongson cores"
139 select HAVE_XTENSA_GPIO32 !! 1368 default y
>> 1369 depends on CPU_LOONGSON64
140 help 1370 help
141 Select this variant to use a custom !! 1371 Loongson-3A R4 and newer have the CPUCFG instruction available for
142 You will be prompted for a processor !! 1372 userland to query CPU capabilities, much like CPUID on x86. This
143 endchoice !! 1373 option provides emulation of the instruction on older Loongson
144 !! 1374 cores, back to Loongson-3A1000.
145 config XTENSA_VARIANT_CUSTOM_NAME !! 1375
146 string "Xtensa Processor Custom Core V !! 1376 If unsure, please say Y.
147 depends on XTENSA_VARIANT_CUSTOM !! 1377
148 help !! 1378 config CPU_LOONGSON2E
149 Provide the name of a custom Xtensa !! 1379 bool "Loongson 2E"
150 This CORENAME selects arch/xtensa/va !! 1380 depends on SYS_HAS_CPU_LOONGSON2E
151 Don't forget you have to select MMU !! 1381 select CPU_LOONGSON2EF
152 !! 1382 help
153 config XTENSA_VARIANT_NAME !! 1383 The Loongson 2E processor implements the MIPS III instruction set
154 string !! 1384 with many extensions.
155 default "dc232b" !! 1385
156 default "dc233c" !! 1386 It has an internal FPGA northbridge, which is compatible to
157 default "fsf" !! 1387 bonito64.
158 default XTENSA_VARIANT_CUSTOM_NAME !! 1388
159 !! 1389 config CPU_LOONGSON2F
160 config XTENSA_VARIANT_MMU !! 1390 bool "Loongson 2F"
161 bool "Core variant has a Full MMU (TLB !! 1391 depends on SYS_HAS_CPU_LOONGSON2F
162 depends on XTENSA_VARIANT_CUSTOM !! 1392 select CPU_LOONGSON2EF
163 default y !! 1393 select GPIOLIB
164 select MMU !! 1394 help
165 help !! 1395 The Loongson 2F processor implements the MIPS III instruction set
166 Build a Conventional Kernel with ful !! 1396 with many extensions.
167 ie: it supports a TLB with auto-load !! 1397
168 !! 1398 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
169 config XTENSA_VARIANT_HAVE_PERF_EVENTS !! 1399 have a similar programming interface with FPGA northbridge used in
170 bool "Core variant has Performance Mon !! 1400 Loongson2E.
171 depends on XTENSA_VARIANT_CUSTOM !! 1401
172 default n !! 1402 config CPU_LOONGSON1B
>> 1403 bool "Loongson 1B"
>> 1404 depends on SYS_HAS_CPU_LOONGSON1B
>> 1405 select CPU_LOONGSON32
>> 1406 select LEDS_GPIO_REGISTER
>> 1407 help
>> 1408 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1409 Release 1 instruction set and part of the MIPS32 Release 2
>> 1410 instruction set.
>> 1411
>> 1412 config CPU_LOONGSON1C
>> 1413 bool "Loongson 1C"
>> 1414 depends on SYS_HAS_CPU_LOONGSON1C
>> 1415 select CPU_LOONGSON32
>> 1416 select LEDS_GPIO_REGISTER
>> 1417 help
>> 1418 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1419 Release 1 instruction set and part of the MIPS32 Release 2
>> 1420 instruction set.
>> 1421
>> 1422 config CPU_MIPS32_R1
>> 1423 bool "MIPS32 Release 1"
>> 1424 depends on SYS_HAS_CPU_MIPS32_R1
>> 1425 select CPU_HAS_PREFETCH
>> 1426 select CPU_SUPPORTS_32BIT_KERNEL
>> 1427 select CPU_SUPPORTS_HIGHMEM
>> 1428 help
>> 1429 Choose this option to build a kernel for release 1 or later of the
>> 1430 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1431 MIPS processor are based on a MIPS32 processor. If you know the
>> 1432 specific type of processor in your system, choose those that one
>> 1433 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1434 Release 2 of the MIPS32 architecture is available since several
>> 1435 years so chances are you even have a MIPS32 Release 2 processor
>> 1436 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1437 performance.
>> 1438
>> 1439 config CPU_MIPS32_R2
>> 1440 bool "MIPS32 Release 2"
>> 1441 depends on SYS_HAS_CPU_MIPS32_R2
>> 1442 select CPU_HAS_PREFETCH
>> 1443 select CPU_SUPPORTS_32BIT_KERNEL
>> 1444 select CPU_SUPPORTS_HIGHMEM
>> 1445 select CPU_SUPPORTS_MSA
>> 1446 select HAVE_KVM
>> 1447 help
>> 1448 Choose this option to build a kernel for release 2 or later of the
>> 1449 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1450 MIPS processor are based on a MIPS32 processor. If you know the
>> 1451 specific type of processor in your system, choose those that one
>> 1452 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1453
>> 1454 config CPU_MIPS32_R5
>> 1455 bool "MIPS32 Release 5"
>> 1456 depends on SYS_HAS_CPU_MIPS32_R5
>> 1457 select CPU_HAS_PREFETCH
>> 1458 select CPU_SUPPORTS_32BIT_KERNEL
>> 1459 select CPU_SUPPORTS_HIGHMEM
>> 1460 select CPU_SUPPORTS_MSA
>> 1461 select HAVE_KVM
>> 1462 select MIPS_O32_FP64_SUPPORT
>> 1463 help
>> 1464 Choose this option to build a kernel for release 5 or later of the
>> 1465 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1466 family, are based on a MIPS32r5 processor. If you own an older
>> 1467 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1468
>> 1469 config CPU_MIPS32_R6
>> 1470 bool "MIPS32 Release 6"
>> 1471 depends on SYS_HAS_CPU_MIPS32_R6
>> 1472 select CPU_HAS_PREFETCH
>> 1473 select CPU_NO_LOAD_STORE_LR
>> 1474 select CPU_SUPPORTS_32BIT_KERNEL
>> 1475 select CPU_SUPPORTS_HIGHMEM
>> 1476 select CPU_SUPPORTS_MSA
>> 1477 select HAVE_KVM
>> 1478 select MIPS_O32_FP64_SUPPORT
>> 1479 help
>> 1480 Choose this option to build a kernel for release 6 or later of the
>> 1481 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1482 family, are based on a MIPS32r6 processor. If you own an older
>> 1483 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1484
>> 1485 config CPU_MIPS64_R1
>> 1486 bool "MIPS64 Release 1"
>> 1487 depends on SYS_HAS_CPU_MIPS64_R1
>> 1488 select CPU_HAS_PREFETCH
>> 1489 select CPU_SUPPORTS_32BIT_KERNEL
>> 1490 select CPU_SUPPORTS_64BIT_KERNEL
>> 1491 select CPU_SUPPORTS_HIGHMEM
>> 1492 select CPU_SUPPORTS_HUGEPAGES
>> 1493 help
>> 1494 Choose this option to build a kernel for release 1 or later of the
>> 1495 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1496 MIPS processor are based on a MIPS64 processor. If you know the
>> 1497 specific type of processor in your system, choose those that one
>> 1498 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1499 Release 2 of the MIPS64 architecture is available since several
>> 1500 years so chances are you even have a MIPS64 Release 2 processor
>> 1501 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1502 performance.
>> 1503
>> 1504 config CPU_MIPS64_R2
>> 1505 bool "MIPS64 Release 2"
>> 1506 depends on SYS_HAS_CPU_MIPS64_R2
>> 1507 select CPU_HAS_PREFETCH
>> 1508 select CPU_SUPPORTS_32BIT_KERNEL
>> 1509 select CPU_SUPPORTS_64BIT_KERNEL
>> 1510 select CPU_SUPPORTS_HIGHMEM
>> 1511 select CPU_SUPPORTS_HUGEPAGES
>> 1512 select CPU_SUPPORTS_MSA
>> 1513 select HAVE_KVM
>> 1514 help
>> 1515 Choose this option to build a kernel for release 2 or later of the
>> 1516 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1517 MIPS processor are based on a MIPS64 processor. If you know the
>> 1518 specific type of processor in your system, choose those that one
>> 1519 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1520
>> 1521 config CPU_MIPS64_R5
>> 1522 bool "MIPS64 Release 5"
>> 1523 depends on SYS_HAS_CPU_MIPS64_R5
>> 1524 select CPU_HAS_PREFETCH
>> 1525 select CPU_SUPPORTS_32BIT_KERNEL
>> 1526 select CPU_SUPPORTS_64BIT_KERNEL
>> 1527 select CPU_SUPPORTS_HIGHMEM
>> 1528 select CPU_SUPPORTS_HUGEPAGES
>> 1529 select CPU_SUPPORTS_MSA
>> 1530 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1531 select HAVE_KVM
>> 1532 help
>> 1533 Choose this option to build a kernel for release 5 or later of the
>> 1534 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1535 release partly implementing release 6 features. Though there is no
>> 1536 any hardware known to be based on this release.
>> 1537
>> 1538 config CPU_MIPS64_R6
>> 1539 bool "MIPS64 Release 6"
>> 1540 depends on SYS_HAS_CPU_MIPS64_R6
>> 1541 select CPU_HAS_PREFETCH
>> 1542 select CPU_NO_LOAD_STORE_LR
>> 1543 select CPU_SUPPORTS_32BIT_KERNEL
>> 1544 select CPU_SUPPORTS_64BIT_KERNEL
>> 1545 select CPU_SUPPORTS_HIGHMEM
>> 1546 select CPU_SUPPORTS_HUGEPAGES
>> 1547 select CPU_SUPPORTS_MSA
>> 1548 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1549 select HAVE_KVM
>> 1550 help
>> 1551 Choose this option to build a kernel for release 6 or later of the
>> 1552 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1553 family, are based on a MIPS64r6 processor. If you own an older
>> 1554 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1555
>> 1556 config CPU_P5600
>> 1557 bool "MIPS Warrior P5600"
>> 1558 depends on SYS_HAS_CPU_P5600
>> 1559 select CPU_HAS_PREFETCH
>> 1560 select CPU_SUPPORTS_32BIT_KERNEL
>> 1561 select CPU_SUPPORTS_HIGHMEM
>> 1562 select CPU_SUPPORTS_MSA
>> 1563 select CPU_SUPPORTS_CPUFREQ
>> 1564 select CPU_MIPSR2_IRQ_VI
>> 1565 select CPU_MIPSR2_IRQ_EI
>> 1566 select HAVE_KVM
>> 1567 select MIPS_O32_FP64_SUPPORT
>> 1568 help
>> 1569 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1570 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1571 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1572 level features like up to six P5600 calculation cores, CM2 with L2
>> 1573 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1574 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1575 eJTAG and PDtrace.
>> 1576
>> 1577 config CPU_R3000
>> 1578 bool "R3000"
>> 1579 depends on SYS_HAS_CPU_R3000
>> 1580 select CPU_HAS_WB
>> 1581 select CPU_R3K_TLB
>> 1582 select CPU_SUPPORTS_32BIT_KERNEL
>> 1583 select CPU_SUPPORTS_HIGHMEM
>> 1584 help
>> 1585 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1586 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1587 *not* work on R4000 machines and vice versa. However, since most
>> 1588 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1589 might be a safe bet. If the resulting kernel does not work,
>> 1590 try to recompile with R3000.
>> 1591
>> 1592 config CPU_TX39XX
>> 1593 bool "R39XX"
>> 1594 depends on SYS_HAS_CPU_TX39XX
>> 1595 select CPU_SUPPORTS_32BIT_KERNEL
>> 1596 select CPU_R3K_TLB
>> 1597
>> 1598 config CPU_VR41XX
>> 1599 bool "R41xx"
>> 1600 depends on SYS_HAS_CPU_VR41XX
>> 1601 select CPU_SUPPORTS_32BIT_KERNEL
>> 1602 select CPU_SUPPORTS_64BIT_KERNEL
>> 1603 help
>> 1604 The options selects support for the NEC VR4100 series of processors.
>> 1605 Only choose this option if you have one of these processors as a
>> 1606 kernel built with this option will not run on any other type of
>> 1607 processor or vice versa.
>> 1608
>> 1609 config CPU_R4300
>> 1610 bool "R4300"
>> 1611 depends on SYS_HAS_CPU_R4300
>> 1612 select CPU_SUPPORTS_32BIT_KERNEL
>> 1613 select CPU_SUPPORTS_64BIT_KERNEL
>> 1614 select CPU_HAS_LOAD_STORE_LR
>> 1615 help
>> 1616 MIPS Technologies R4300-series processors.
>> 1617
>> 1618 config CPU_R4X00
>> 1619 bool "R4x00"
>> 1620 depends on SYS_HAS_CPU_R4X00
>> 1621 select CPU_SUPPORTS_32BIT_KERNEL
>> 1622 select CPU_SUPPORTS_64BIT_KERNEL
>> 1623 select CPU_SUPPORTS_HUGEPAGES
>> 1624 help
>> 1625 MIPS Technologies R4000-series processors other than 4300, including
>> 1626 the R4000, R4400, R4600, and 4700.
>> 1627
>> 1628 config CPU_TX49XX
>> 1629 bool "R49XX"
>> 1630 depends on SYS_HAS_CPU_TX49XX
>> 1631 select CPU_HAS_PREFETCH
>> 1632 select CPU_SUPPORTS_32BIT_KERNEL
>> 1633 select CPU_SUPPORTS_64BIT_KERNEL
>> 1634 select CPU_SUPPORTS_HUGEPAGES
>> 1635
>> 1636 config CPU_R5000
>> 1637 bool "R5000"
>> 1638 depends on SYS_HAS_CPU_R5000
>> 1639 select CPU_SUPPORTS_32BIT_KERNEL
>> 1640 select CPU_SUPPORTS_64BIT_KERNEL
>> 1641 select CPU_SUPPORTS_HUGEPAGES
>> 1642 help
>> 1643 MIPS Technologies R5000-series processors other than the Nevada.
>> 1644
>> 1645 config CPU_R5500
>> 1646 bool "R5500"
>> 1647 depends on SYS_HAS_CPU_R5500
>> 1648 select CPU_SUPPORTS_32BIT_KERNEL
>> 1649 select CPU_SUPPORTS_64BIT_KERNEL
>> 1650 select CPU_SUPPORTS_HUGEPAGES
>> 1651 help
>> 1652 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1653 instruction set.
>> 1654
>> 1655 config CPU_NEVADA
>> 1656 bool "RM52xx"
>> 1657 depends on SYS_HAS_CPU_NEVADA
>> 1658 select CPU_SUPPORTS_32BIT_KERNEL
>> 1659 select CPU_SUPPORTS_64BIT_KERNEL
>> 1660 select CPU_SUPPORTS_HUGEPAGES
>> 1661 help
>> 1662 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1663
>> 1664 config CPU_R10000
>> 1665 bool "R10000"
>> 1666 depends on SYS_HAS_CPU_R10000
>> 1667 select CPU_HAS_PREFETCH
>> 1668 select CPU_SUPPORTS_32BIT_KERNEL
>> 1669 select CPU_SUPPORTS_64BIT_KERNEL
>> 1670 select CPU_SUPPORTS_HIGHMEM
>> 1671 select CPU_SUPPORTS_HUGEPAGES
>> 1672 help
>> 1673 MIPS Technologies R10000-series processors.
>> 1674
>> 1675 config CPU_RM7000
>> 1676 bool "RM7000"
>> 1677 depends on SYS_HAS_CPU_RM7000
>> 1678 select CPU_HAS_PREFETCH
>> 1679 select CPU_SUPPORTS_32BIT_KERNEL
>> 1680 select CPU_SUPPORTS_64BIT_KERNEL
>> 1681 select CPU_SUPPORTS_HIGHMEM
>> 1682 select CPU_SUPPORTS_HUGEPAGES
>> 1683
>> 1684 config CPU_SB1
>> 1685 bool "SB1"
>> 1686 depends on SYS_HAS_CPU_SB1
>> 1687 select CPU_SUPPORTS_32BIT_KERNEL
>> 1688 select CPU_SUPPORTS_64BIT_KERNEL
>> 1689 select CPU_SUPPORTS_HIGHMEM
>> 1690 select CPU_SUPPORTS_HUGEPAGES
>> 1691 select WEAK_ORDERING
>> 1692
>> 1693 config CPU_CAVIUM_OCTEON
>> 1694 bool "Cavium Octeon processor"
>> 1695 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1696 select CPU_HAS_PREFETCH
>> 1697 select CPU_SUPPORTS_64BIT_KERNEL
>> 1698 select WEAK_ORDERING
>> 1699 select CPU_SUPPORTS_HIGHMEM
>> 1700 select CPU_SUPPORTS_HUGEPAGES
>> 1701 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1702 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1703 select MIPS_L1_CACHE_SHIFT_7
>> 1704 select HAVE_KVM
>> 1705 help
>> 1706 The Cavium Octeon processor is a highly integrated chip containing
>> 1707 many ethernet hardware widgets for networking tasks. The processor
>> 1708 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1709 Full details can be found at http://www.caviumnetworks.com.
>> 1710
>> 1711 config CPU_BMIPS
>> 1712 bool "Broadcom BMIPS"
>> 1713 depends on SYS_HAS_CPU_BMIPS
>> 1714 select CPU_MIPS32
>> 1715 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1716 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1717 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1718 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1719 select CPU_SUPPORTS_32BIT_KERNEL
>> 1720 select DMA_NONCOHERENT
>> 1721 select IRQ_MIPS_CPU
>> 1722 select SWAP_IO_SPACE
>> 1723 select WEAK_ORDERING
>> 1724 select CPU_SUPPORTS_HIGHMEM
>> 1725 select CPU_HAS_PREFETCH
>> 1726 select CPU_SUPPORTS_CPUFREQ
>> 1727 select MIPS_EXTERNAL_TIMER
>> 1728 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
173 help 1729 help
174 Enable if core variant has Performan !! 1730 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
175 External Registers Interface. <<
176 1731
177 If unsure, say N. !! 1732 endchoice
178 1733
179 config XTENSA_FAKE_NMI !! 1734 config CPU_MIPS32_3_5_FEATURES
180 bool "Treat PMM IRQ as NMI" !! 1735 bool "MIPS32 Release 3.5 Features"
181 depends on XTENSA_VARIANT_HAVE_PERF_EV !! 1736 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1737 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1738 CPU_P5600
>> 1739 help
>> 1740 Choose this option to build a kernel for release 2 or later of the
>> 1741 MIPS32 architecture including features from the 3.5 release such as
>> 1742 support for Enhanced Virtual Addressing (EVA).
>> 1743
>> 1744 config CPU_MIPS32_3_5_EVA
>> 1745 bool "Enhanced Virtual Addressing (EVA)"
>> 1746 depends on CPU_MIPS32_3_5_FEATURES
>> 1747 select EVA
>> 1748 default y
>> 1749 help
>> 1750 Choose this option if you want to enable the Enhanced Virtual
>> 1751 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1752 One of its primary benefits is an increase in the maximum size
>> 1753 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1754
>> 1755 config CPU_MIPS32_R5_FEATURES
>> 1756 bool "MIPS32 Release 5 Features"
>> 1757 depends on SYS_HAS_CPU_MIPS32_R5
>> 1758 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1759 help
>> 1760 Choose this option to build a kernel for release 2 or later of the
>> 1761 MIPS32 architecture including features from release 5 such as
>> 1762 support for Extended Physical Addressing (XPA).
>> 1763
>> 1764 config CPU_MIPS32_R5_XPA
>> 1765 bool "Extended Physical Addressing (XPA)"
>> 1766 depends on CPU_MIPS32_R5_FEATURES
>> 1767 depends on !EVA
>> 1768 depends on !PAGE_SIZE_4KB
>> 1769 depends on SYS_SUPPORTS_HIGHMEM
>> 1770 select XPA
>> 1771 select HIGHMEM
>> 1772 select PHYS_ADDR_T_64BIT
182 default n 1773 default n
183 help 1774 help
184 If PMM IRQ is the only IRQ at EXCM l !! 1775 Choose this option if you want to enable the Extended Physical
185 treat it as NMI, which improves accu !! 1776 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1777 benefit is to increase physical addressing equal to or greater
>> 1778 than 40 bits. Note that this has the side effect of turning on
>> 1779 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1780 If unsure, say 'N' here.
186 1781
187 If there are other interrupts at or !! 1782 if CPU_LOONGSON2F
188 but not above the EXCM level, PMM IR !! 1783 config CPU_NOP_WORKAROUNDS
189 but only if these IRQs are not used. !! 1784 bool
190 saying that this is not safe, and a <<
191 actually fire. <<
192 1785
193 If unsure, say N. !! 1786 config CPU_JUMP_WORKAROUNDS
>> 1787 bool
194 1788
195 config PFAULT !! 1789 config CPU_LOONGSON2F_WORKAROUNDS
196 bool "Handle protection faults" if EXP !! 1790 bool "Loongson 2F Workarounds"
197 default y 1791 default y
>> 1792 select CPU_NOP_WORKAROUNDS
>> 1793 select CPU_JUMP_WORKAROUNDS
198 help 1794 help
199 Handle protection faults. MMU config !! 1795 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
200 noMMU configurations may disable it !! 1796 require workarounds. Without workarounds the system may hang
201 generates protection faults or fault !! 1797 unexpectedly. For more information please refer to the gas
>> 1798 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1799
>> 1800 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1801 are needed. The workarounds have no significant side effect on them
>> 1802 but may decrease the performance of the system so this option should
>> 1803 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1804 systems.
202 1805
203 If unsure, say Y. !! 1806 If unsure, please say Y.
>> 1807 endif # CPU_LOONGSON2F
>> 1808
>> 1809 config SYS_SUPPORTS_ZBOOT
>> 1810 bool
>> 1811 select HAVE_KERNEL_GZIP
>> 1812 select HAVE_KERNEL_BZIP2
>> 1813 select HAVE_KERNEL_LZ4
>> 1814 select HAVE_KERNEL_LZMA
>> 1815 select HAVE_KERNEL_LZO
>> 1816 select HAVE_KERNEL_XZ
>> 1817 select HAVE_KERNEL_ZSTD
>> 1818
>> 1819 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1820 bool
>> 1821 select SYS_SUPPORTS_ZBOOT
>> 1822
>> 1823 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1824 bool
>> 1825 select SYS_SUPPORTS_ZBOOT
>> 1826
>> 1827 config CPU_LOONGSON2EF
>> 1828 bool
>> 1829 select CPU_SUPPORTS_32BIT_KERNEL
>> 1830 select CPU_SUPPORTS_64BIT_KERNEL
>> 1831 select CPU_SUPPORTS_HIGHMEM
>> 1832 select CPU_SUPPORTS_HUGEPAGES
>> 1833 select ARCH_HAS_PHYS_TO_DMA
>> 1834
>> 1835 config CPU_LOONGSON32
>> 1836 bool
>> 1837 select CPU_MIPS32
>> 1838 select CPU_MIPSR2
>> 1839 select CPU_HAS_PREFETCH
>> 1840 select CPU_SUPPORTS_32BIT_KERNEL
>> 1841 select CPU_SUPPORTS_HIGHMEM
>> 1842 select CPU_SUPPORTS_CPUFREQ
>> 1843
>> 1844 config CPU_BMIPS32_3300
>> 1845 select SMP_UP if SMP
>> 1846 bool
>> 1847
>> 1848 config CPU_BMIPS4350
>> 1849 bool
>> 1850 select SYS_SUPPORTS_SMP
>> 1851 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1852
>> 1853 config CPU_BMIPS4380
>> 1854 bool
>> 1855 select MIPS_L1_CACHE_SHIFT_6
>> 1856 select SYS_SUPPORTS_SMP
>> 1857 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1858 select CPU_HAS_RIXI
>> 1859
>> 1860 config CPU_BMIPS5000
>> 1861 bool
>> 1862 select MIPS_CPU_SCACHE
>> 1863 select MIPS_L1_CACHE_SHIFT_7
>> 1864 select SYS_SUPPORTS_SMP
>> 1865 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1866 select CPU_HAS_RIXI
>> 1867
>> 1868 config SYS_HAS_CPU_LOONGSON64
>> 1869 bool
>> 1870 select CPU_SUPPORTS_CPUFREQ
>> 1871 select CPU_HAS_RIXI
>> 1872
>> 1873 config SYS_HAS_CPU_LOONGSON2E
>> 1874 bool
>> 1875
>> 1876 config SYS_HAS_CPU_LOONGSON2F
>> 1877 bool
>> 1878 select CPU_SUPPORTS_CPUFREQ
>> 1879 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1880
>> 1881 config SYS_HAS_CPU_LOONGSON1B
>> 1882 bool
>> 1883
>> 1884 config SYS_HAS_CPU_LOONGSON1C
>> 1885 bool
>> 1886
>> 1887 config SYS_HAS_CPU_MIPS32_R1
>> 1888 bool
>> 1889
>> 1890 config SYS_HAS_CPU_MIPS32_R2
>> 1891 bool
>> 1892
>> 1893 config SYS_HAS_CPU_MIPS32_R3_5
>> 1894 bool
>> 1895
>> 1896 config SYS_HAS_CPU_MIPS32_R5
>> 1897 bool
>> 1898 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1899
>> 1900 config SYS_HAS_CPU_MIPS32_R6
>> 1901 bool
>> 1902 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1903
>> 1904 config SYS_HAS_CPU_MIPS64_R1
>> 1905 bool
>> 1906
>> 1907 config SYS_HAS_CPU_MIPS64_R2
>> 1908 bool
>> 1909
>> 1910 config SYS_HAS_CPU_MIPS64_R5
>> 1911 bool
>> 1912 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1913
>> 1914 config SYS_HAS_CPU_MIPS64_R6
>> 1915 bool
>> 1916 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1917
>> 1918 config SYS_HAS_CPU_P5600
>> 1919 bool
>> 1920 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1921
>> 1922 config SYS_HAS_CPU_R3000
>> 1923 bool
>> 1924
>> 1925 config SYS_HAS_CPU_TX39XX
>> 1926 bool
>> 1927
>> 1928 config SYS_HAS_CPU_VR41XX
>> 1929 bool
>> 1930
>> 1931 config SYS_HAS_CPU_R4300
>> 1932 bool
>> 1933
>> 1934 config SYS_HAS_CPU_R4X00
>> 1935 bool
>> 1936
>> 1937 config SYS_HAS_CPU_TX49XX
>> 1938 bool
>> 1939
>> 1940 config SYS_HAS_CPU_R5000
>> 1941 bool
>> 1942
>> 1943 config SYS_HAS_CPU_R5500
>> 1944 bool
>> 1945
>> 1946 config SYS_HAS_CPU_NEVADA
>> 1947 bool
204 1948
205 config XTENSA_UNALIGNED_USER !! 1949 config SYS_HAS_CPU_R10000
206 bool "Unaligned memory access in user !! 1950 bool
>> 1951 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1952
>> 1953 config SYS_HAS_CPU_RM7000
>> 1954 bool
>> 1955
>> 1956 config SYS_HAS_CPU_SB1
>> 1957 bool
>> 1958
>> 1959 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1960 bool
>> 1961
>> 1962 config SYS_HAS_CPU_BMIPS
>> 1963 bool
>> 1964
>> 1965 config SYS_HAS_CPU_BMIPS32_3300
>> 1966 bool
>> 1967 select SYS_HAS_CPU_BMIPS
>> 1968
>> 1969 config SYS_HAS_CPU_BMIPS4350
>> 1970 bool
>> 1971 select SYS_HAS_CPU_BMIPS
>> 1972
>> 1973 config SYS_HAS_CPU_BMIPS4380
>> 1974 bool
>> 1975 select SYS_HAS_CPU_BMIPS
>> 1976
>> 1977 config SYS_HAS_CPU_BMIPS5000
>> 1978 bool
>> 1979 select SYS_HAS_CPU_BMIPS
>> 1980 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 1981
>> 1982 #
>> 1983 # CPU may reorder R->R, R->W, W->R, W->W
>> 1984 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1985 #
>> 1986 config WEAK_ORDERING
>> 1987 bool
>> 1988
>> 1989 #
>> 1990 # CPU may reorder reads and writes beyond LL/SC
>> 1991 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 1992 #
>> 1993 config WEAK_REORDERING_BEYOND_LLSC
>> 1994 bool
>> 1995 endmenu
>> 1996
>> 1997 #
>> 1998 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1999 #
>> 2000 config CPU_MIPS32
>> 2001 bool
>> 2002 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 2003 CPU_MIPS32_R6 || CPU_P5600
>> 2004
>> 2005 config CPU_MIPS64
>> 2006 bool
>> 2007 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 2008 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
>> 2009
>> 2010 #
>> 2011 # These indicate the revision of the architecture
>> 2012 #
>> 2013 config CPU_MIPSR1
>> 2014 bool
>> 2015 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 2016
>> 2017 config CPU_MIPSR2
>> 2018 bool
>> 2019 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2020 select CPU_HAS_RIXI
>> 2021 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2022 select MIPS_SPRAM
>> 2023
>> 2024 config CPU_MIPSR5
>> 2025 bool
>> 2026 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 2027 select CPU_HAS_RIXI
>> 2028 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2029 select MIPS_SPRAM
>> 2030
>> 2031 config CPU_MIPSR6
>> 2032 bool
>> 2033 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2034 select CPU_HAS_RIXI
>> 2035 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2036 select HAVE_ARCH_BITREVERSE
>> 2037 select MIPS_ASID_BITS_VARIABLE
>> 2038 select MIPS_CRC_SUPPORT
>> 2039 select MIPS_SPRAM
>> 2040
>> 2041 config TARGET_ISA_REV
>> 2042 int
>> 2043 default 1 if CPU_MIPSR1
>> 2044 default 2 if CPU_MIPSR2
>> 2045 default 5 if CPU_MIPSR5
>> 2046 default 6 if CPU_MIPSR6
>> 2047 default 0
207 help 2048 help
208 The Xtensa architecture currently do !! 2049 Reflects the ISA revision being targeted by the kernel build. This
209 memory accesses in hardware but thro !! 2050 is effectively the Kconfig equivalent of MIPS_ISA_REV.
210 Per default, unaligned memory access <<
211 2051
212 Say Y here to enable unaligned memor !! 2052 config EVA
>> 2053 bool
>> 2054
>> 2055 config XPA
>> 2056 bool
213 2057
214 config XTENSA_LOAD_STORE !! 2058 config SYS_SUPPORTS_32BIT_KERNEL
215 bool "Load/store exception handler for !! 2059 bool
>> 2060 config SYS_SUPPORTS_64BIT_KERNEL
>> 2061 bool
>> 2062 config CPU_SUPPORTS_32BIT_KERNEL
>> 2063 bool
>> 2064 config CPU_SUPPORTS_64BIT_KERNEL
>> 2065 bool
>> 2066 config CPU_SUPPORTS_CPUFREQ
>> 2067 bool
>> 2068 config CPU_SUPPORTS_ADDRWINCFG
>> 2069 bool
>> 2070 config CPU_SUPPORTS_HUGEPAGES
>> 2071 bool
>> 2072 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2073 config MIPS_PGD_C0_CONTEXT
>> 2074 bool
>> 2075 depends on 64BIT
>> 2076 default y if (CPU_MIPSR2 || CPU_MIPSR6)
>> 2077
>> 2078 #
>> 2079 # Set to y for ptrace access to watch registers.
>> 2080 #
>> 2081 config HARDWARE_WATCHPOINTS
>> 2082 bool
>> 2083 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
>> 2084
>> 2085 menu "Kernel type"
>> 2086
>> 2087 choice
>> 2088 prompt "Kernel code model"
216 help 2089 help
217 The Xtensa architecture only allows !! 2090 You should only select this option if you have a workload that
218 instruction bus with l32r and l32i i !! 2091 actually benefits from 64-bit processing or if your machine has
219 instructions raise an exception with !! 2092 large memory. You will only be presented a single option in this
220 This makes it hard to use some confi !! 2093 menu if your system does not support both 32-bit and 64-bit kernels.
221 literals in FLASH memory attached to <<
222 2094
223 Say Y here to enable exception handl !! 2095 config 32BIT
224 byte and 2-byte access to memory att !! 2096 bool "32-bit kernel"
>> 2097 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2098 select TRAD_SIGNALS
>> 2099 help
>> 2100 Select this option if you want to build a 32-bit kernel.
225 2101
226 config HAVE_SMP !! 2102 config 64BIT
227 bool "System Supports SMP (MX)" !! 2103 bool "64-bit kernel"
228 depends on XTENSA_VARIANT_CUSTOM !! 2104 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
229 select XTENSA_MX <<
230 help 2105 help
231 This option is used to indicate that !! 2106 Select this option if you want to build a 64-bit kernel.
232 supports Multiprocessing. Multiproce <<
233 the CPU core definition and currentl <<
234 2107
235 Multiprocessor support is implemente !! 2108 endchoice
236 interrupt controllers. <<
237 2109
238 The MX interrupt distributer adds In !! 2110 config MIPS_VA_BITS_48
239 and causes the IRQ numbers to be inc !! 2111 bool "48 bits virtual memory"
240 like the open cores ethernet driver !! 2112 depends on 64BIT
>> 2113 help
>> 2114 Support a maximum at least 48 bits of application virtual
>> 2115 memory. Default is 40 bits or less, depending on the CPU.
>> 2116 For page sizes 16k and above, this option results in a small
>> 2117 memory overhead for page tables. For 4k page size, a fourth
>> 2118 level of page tables is added which imposes both a memory
>> 2119 overhead as well as slower TLB fault handling.
241 2120
242 You still have to select "Enable SMP !! 2121 If unsure, say N.
243 2122
244 config SMP !! 2123 choice
245 bool "Enable Symmetric multi-processin !! 2124 prompt "Kernel page size"
246 depends on HAVE_SMP !! 2125 default PAGE_SIZE_4KB
247 select GENERIC_SMP_IDLE_THREAD <<
248 help <<
249 Enabled SMP Software; allows more th <<
250 to be activated during startup. <<
251 2126
252 config NR_CPUS !! 2127 config PAGE_SIZE_4KB
253 depends on SMP !! 2128 bool "4kB"
254 int "Maximum number of CPUs (2-32)" !! 2129 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
255 range 2 32 !! 2130 help
256 default "4" !! 2131 This option select the standard 4kB Linux page size. On some
>> 2132 R3000-family processors this is the only available page size. Using
>> 2133 4kB page size will minimize memory consumption and is therefore
>> 2134 recommended for low memory systems.
>> 2135
>> 2136 config PAGE_SIZE_8KB
>> 2137 bool "8kB"
>> 2138 depends on CPU_CAVIUM_OCTEON
>> 2139 depends on !MIPS_VA_BITS_48
>> 2140 help
>> 2141 Using 8kB page size will result in higher performance kernel at
>> 2142 the price of higher memory consumption. This option is available
>> 2143 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2144 distribution to support this.
>> 2145
>> 2146 config PAGE_SIZE_16KB
>> 2147 bool "16kB"
>> 2148 depends on !CPU_R3000 && !CPU_TX39XX
>> 2149 help
>> 2150 Using 16kB page size will result in higher performance kernel at
>> 2151 the price of higher memory consumption. This option is available on
>> 2152 all non-R3000 family processors. Note that you will need a suitable
>> 2153 Linux distribution to support this.
>> 2154
>> 2155 config PAGE_SIZE_32KB
>> 2156 bool "32kB"
>> 2157 depends on CPU_CAVIUM_OCTEON
>> 2158 depends on !MIPS_VA_BITS_48
>> 2159 help
>> 2160 Using 32kB page size will result in higher performance kernel at
>> 2161 the price of higher memory consumption. This option is available
>> 2162 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2163 distribution to support this.
>> 2164
>> 2165 config PAGE_SIZE_64KB
>> 2166 bool "64kB"
>> 2167 depends on !CPU_R3000 && !CPU_TX39XX
>> 2168 help
>> 2169 Using 64kB page size will result in higher performance kernel at
>> 2170 the price of higher memory consumption. This option is available on
>> 2171 all non-R3000 family processor. Not that at the time of this
>> 2172 writing this option is still high experimental.
257 2173
258 config HOTPLUG_CPU !! 2174 endchoice
259 bool "Enable CPU hotplug support" !! 2175
260 depends on SMP !! 2176 config FORCE_MAX_ZONEORDER
>> 2177 int "Maximum zone order"
>> 2178 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2179 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2180 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2181 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2182 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2183 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2184 range 0 64
>> 2185 default "11"
>> 2186 help
>> 2187 The kernel memory allocator divides physically contiguous memory
>> 2188 blocks into "zones", where each zone is a power of two number of
>> 2189 pages. This option selects the largest power of two that the kernel
>> 2190 keeps in the memory allocator. If you need to allocate very large
>> 2191 blocks of physically contiguous memory, then you may need to
>> 2192 increase this value.
>> 2193
>> 2194 This config option is actually maximum order plus one. For example,
>> 2195 a value of 11 means that the largest free memory block is 2^10 pages.
>> 2196
>> 2197 The page size is not necessarily 4KB. Keep this in mind
>> 2198 when choosing a value for this option.
>> 2199
>> 2200 config BOARD_SCACHE
>> 2201 bool
>> 2202
>> 2203 config IP22_CPU_SCACHE
>> 2204 bool
>> 2205 select BOARD_SCACHE
>> 2206
>> 2207 #
>> 2208 # Support for a MIPS32 / MIPS64 style S-caches
>> 2209 #
>> 2210 config MIPS_CPU_SCACHE
>> 2211 bool
>> 2212 select BOARD_SCACHE
>> 2213
>> 2214 config R5000_CPU_SCACHE
>> 2215 bool
>> 2216 select BOARD_SCACHE
>> 2217
>> 2218 config RM7000_CPU_SCACHE
>> 2219 bool
>> 2220 select BOARD_SCACHE
>> 2221
>> 2222 config SIBYTE_DMA_PAGEOPS
>> 2223 bool "Use DMA to clear/copy pages"
>> 2224 depends on CPU_SB1
261 help 2225 help
262 Say Y here to allow turning CPUs off !! 2226 Instead of using the CPU to zero and copy pages, use a Data Mover
263 controlled through /sys/devices/syst !! 2227 channel. These DMA channels are otherwise unused by the standard
>> 2228 SiByte Linux port. Seems to give a small performance benefit.
264 2229
265 Say N if you want to disable CPU hot !! 2230 config CPU_HAS_PREFETCH
>> 2231 bool
266 2232
267 config SECONDARY_RESET_VECTOR !! 2233 config CPU_GENERIC_DUMP_TLB
268 bool "Secondary cores use alternative !! 2234 bool
>> 2235 default y if !(CPU_R3000 || CPU_TX39XX)
>> 2236
>> 2237 config MIPS_FP_SUPPORT
>> 2238 bool "Floating Point support" if EXPERT
269 default y 2239 default y
270 depends on HAVE_SMP <<
271 help 2240 help
272 Secondary cores may be configured to !! 2241 Select y to include support for floating point in the kernel
273 or all cores may use primary reset v !! 2242 including initialization of FPU hardware, FP context save & restore
274 Say Y here to supply handler for the !! 2243 and emulation of an FPU where necessary. Without this support any
>> 2244 userland program attempting to use floating point instructions will
>> 2245 receive a SIGILL.
>> 2246
>> 2247 If you know that your userland will not attempt to use floating point
>> 2248 instructions then you can say n here to shrink the kernel a little.
>> 2249
>> 2250 If unsure, say y.
>> 2251
>> 2252 config CPU_R2300_FPU
>> 2253 bool
>> 2254 depends on MIPS_FP_SUPPORT
>> 2255 default y if CPU_R3000 || CPU_TX39XX
>> 2256
>> 2257 config CPU_R3K_TLB
>> 2258 bool
>> 2259
>> 2260 config CPU_R4K_FPU
>> 2261 bool
>> 2262 depends on MIPS_FP_SUPPORT
>> 2263 default y if !CPU_R2300_FPU
>> 2264
>> 2265 config CPU_R4K_CACHE_TLB
>> 2266 bool
>> 2267 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2268
>> 2269 config MIPS_MT_SMP
>> 2270 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2271 default y
>> 2272 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2273 select CPU_MIPSR2_IRQ_VI
>> 2274 select CPU_MIPSR2_IRQ_EI
>> 2275 select SYNC_R4K
>> 2276 select MIPS_MT
>> 2277 select SMP
>> 2278 select SMP_UP
>> 2279 select SYS_SUPPORTS_SMP
>> 2280 select SYS_SUPPORTS_SCHED_SMT
>> 2281 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2282 help
>> 2283 This is a kernel model which is known as SMVP. This is supported
>> 2284 on cores with the MT ASE and uses the available VPEs to implement
>> 2285 virtual processors which supports SMP. This is equivalent to the
>> 2286 Intel Hyperthreading feature. For further information go to
>> 2287 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2288
>> 2289 config MIPS_MT
>> 2290 bool
275 2291
276 config FAST_SYSCALL_XTENSA !! 2292 config SCHED_SMT
277 bool "Enable fast atomic syscalls" !! 2293 bool "SMT (multithreading) scheduler support"
>> 2294 depends on SYS_SUPPORTS_SCHED_SMT
278 default n 2295 default n
279 help 2296 help
280 fast_syscall_xtensa is a syscall tha !! 2297 SMT scheduler support improves the CPU scheduler's decision making
281 on UP kernel when processor has no s !! 2298 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2299 increased overhead in some places. If unsure say N here.
282 2300
283 This syscall is deprecated. It may h !! 2301 config SYS_SUPPORTS_SCHED_SMT
284 invalid arguments. It is provided on !! 2302 bool
285 Only enable it if your userspace sof <<
286 2303
287 If unsure, say N. !! 2304 config SYS_SUPPORTS_MULTITHREADING
>> 2305 bool
288 2306
289 config FAST_SYSCALL_SPILL_REGISTERS !! 2307 config MIPS_MT_FPAFF
290 bool "Enable spill registers syscall" !! 2308 bool "Dynamic FPU affinity for FP-intensive threads"
291 default n !! 2309 default y
>> 2310 depends on MIPS_MT_SMP
>> 2311
>> 2312 config MIPSR2_TO_R6_EMULATOR
>> 2313 bool "MIPS R2-to-R6 emulator"
>> 2314 depends on CPU_MIPSR6
>> 2315 depends on MIPS_FP_SUPPORT
>> 2316 default y
292 help 2317 help
293 fast_syscall_spill_registers is a sy !! 2318 Choose this option if you want to run non-R6 MIPS userland code.
294 register windows of a calling usersp !! 2319 Even if you say 'Y' here, the emulator will still be disabled by
>> 2320 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2321 The only reason this is a build-time option is to save ~14K from the
>> 2322 final kernel image.
295 2323
296 This syscall is deprecated. It may h !! 2324 config SYS_SUPPORTS_VPE_LOADER
297 invalid arguments. It is provided on !! 2325 bool
298 Only enable it if your userspace sof !! 2326 depends on SYS_SUPPORTS_MULTITHREADING
>> 2327 help
>> 2328 Indicates that the platform supports the VPE loader, and provides
>> 2329 physical_memsize.
299 2330
300 If unsure, say N. !! 2331 config MIPS_VPE_LOADER
>> 2332 bool "VPE loader support."
>> 2333 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2334 select CPU_MIPSR2_IRQ_VI
>> 2335 select CPU_MIPSR2_IRQ_EI
>> 2336 select MIPS_MT
>> 2337 help
>> 2338 Includes a loader for loading an elf relocatable object
>> 2339 onto another VPE and running it.
301 2340
302 choice !! 2341 config MIPS_VPE_LOADER_CMP
303 prompt "Kernel ABI" !! 2342 bool
304 default KERNEL_ABI_DEFAULT !! 2343 default "y"
>> 2344 depends on MIPS_VPE_LOADER && MIPS_CMP
>> 2345
>> 2346 config MIPS_VPE_LOADER_MT
>> 2347 bool
>> 2348 default "y"
>> 2349 depends on MIPS_VPE_LOADER && !MIPS_CMP
>> 2350
>> 2351 config MIPS_VPE_LOADER_TOM
>> 2352 bool "Load VPE program into memory hidden from linux"
>> 2353 depends on MIPS_VPE_LOADER
>> 2354 default y
305 help 2355 help
306 Select ABI for the kernel code. This !! 2356 The loader can use memory that is present but has been hidden from
307 supported userspace ABI and any comb !! 2357 Linux using the kernel command line option "mem=xxMB". It's up to
308 kernel/userspace ABI is possible and !! 2358 you to ensure the amount you put in the option and the space your
309 !! 2359 program requires is less or equal to the amount physically present.
310 In case both kernel and userspace su !! 2360
311 all register windows support code wi !! 2361 config MIPS_VPE_APSP_API
312 build. !! 2362 bool "Enable support for AP/SP API (RTLX)"
313 !! 2363 depends on MIPS_VPE_LOADER
314 If unsure, choose the default ABI. <<
315 <<
316 config KERNEL_ABI_DEFAULT <<
317 bool "Default ABI" <<
318 help <<
319 Select this option to compile kernel <<
320 selected for the toolchain. <<
321 Normally cores with windowed registe <<
322 cores without it use call0 ABI. <<
323 <<
324 config KERNEL_ABI_CALL0 <<
325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI <<
326 help <<
327 Select this option to compile kernel <<
328 toolchain that defaults to windowed <<
329 When this option is not selected the <<
330 be used for the kernel code. <<
331 2364
332 endchoice !! 2365 config MIPS_VPE_APSP_API_CMP
>> 2366 bool
>> 2367 default "y"
>> 2368 depends on MIPS_VPE_APSP_API && MIPS_CMP
333 2369
334 config USER_ABI_CALL0 !! 2370 config MIPS_VPE_APSP_API_MT
335 bool 2371 bool
>> 2372 default "y"
>> 2373 depends on MIPS_VPE_APSP_API && !MIPS_CMP
336 2374
337 choice !! 2375 config MIPS_CMP
338 prompt "Userspace ABI" !! 2376 bool "MIPS CMP framework support (DEPRECATED)"
339 default USER_ABI_DEFAULT !! 2377 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2378 select SMP
>> 2379 select SYNC_R4K
>> 2380 select SYS_SUPPORTS_SMP
>> 2381 select WEAK_ORDERING
>> 2382 default n
340 help 2383 help
341 Select supported userspace ABI. !! 2384 Select this if you are using a bootloader which implements the "CMP
>> 2385 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2386 its ability to start secondary CPUs.
>> 2387
>> 2388 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2389 instead of this.
>> 2390
>> 2391 config MIPS_CPS
>> 2392 bool "MIPS Coherent Processing System support"
>> 2393 depends on SYS_SUPPORTS_MIPS_CPS
>> 2394 select MIPS_CM
>> 2395 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2396 select SMP
>> 2397 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2398 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2399 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2400 select SYS_SUPPORTS_SMP
>> 2401 select WEAK_ORDERING
>> 2402 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2403 help
>> 2404 Select this if you wish to run an SMP kernel across multiple cores
>> 2405 within a MIPS Coherent Processing System. When this option is
>> 2406 enabled the kernel will probe for other cores and boot them with
>> 2407 no external assistance. It is safe to enable this when hardware
>> 2408 support is unavailable.
>> 2409
>> 2410 config MIPS_CPS_PM
>> 2411 depends on MIPS_CPS
>> 2412 bool
>> 2413
>> 2414 config MIPS_CM
>> 2415 bool
>> 2416 select MIPS_CPC
>> 2417
>> 2418 config MIPS_CPC
>> 2419 bool
>> 2420
>> 2421 config SB1_PASS_2_WORKAROUNDS
>> 2422 bool
>> 2423 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2424 default y
342 2425
343 If unsure, choose the default ABI. !! 2426 config SB1_PASS_2_1_WORKAROUNDS
>> 2427 bool
>> 2428 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2429 default y
>> 2430
>> 2431 choice
>> 2432 prompt "SmartMIPS or microMIPS ASE support"
344 2433
345 config USER_ABI_DEFAULT !! 2434 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
346 bool "Default ABI only" !! 2435 bool "None"
347 help 2436 help
348 Assume default userspace ABI. For XE !! 2437 Select this if you want neither microMIPS nor SmartMIPS support
349 call0 ABI binaries may be run on suc <<
350 will not work correctly for them. <<
351 2438
352 config USER_ABI_CALL0_ONLY !! 2439 config CPU_HAS_SMARTMIPS
353 bool "Call0 ABI only" !! 2440 depends on SYS_SUPPORTS_SMARTMIPS
354 select USER_ABI_CALL0 !! 2441 bool "SmartMIPS"
>> 2442 help
>> 2443 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2444 increased security at both hardware and software level for
>> 2445 smartcards. Enabling this option will allow proper use of the
>> 2446 SmartMIPS instructions by Linux applications. However a kernel with
>> 2447 this option will not work on a MIPS core without SmartMIPS core. If
>> 2448 you don't know you probably don't have SmartMIPS and should say N
>> 2449 here.
>> 2450
>> 2451 config CPU_MICROMIPS
>> 2452 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2453 bool "microMIPS"
355 help 2454 help
356 Select this option to support only c !! 2455 When this option is enabled the kernel will be built using the
357 Windowed ABI binaries will crash wit !! 2456 microMIPS ISA
358 an illegal instruction exception on <<
359 2457
360 Choose this option if you're plannin !! 2458 endchoice
361 built with call0 ABI. <<
362 2459
363 config USER_ABI_CALL0_PROBE !! 2460 config CPU_HAS_MSA
364 bool "Support both windowed and call0 !! 2461 bool "Support for the MIPS SIMD Architecture"
365 select USER_ABI_CALL0 !! 2462 depends on CPU_SUPPORTS_MSA
366 help !! 2463 depends on MIPS_FP_SUPPORT
367 Select this option to support both w !! 2464 depends on 64BIT || MIPS_O32_FP64_SUPPORT
368 ABIs. When enabled all processes are !! 2465 help
369 and a fast user exception handler fo !! 2466 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
370 used to turn on PS.WOE bit on the fi !! 2467 and a set of SIMD instructions to operate on them. When this option
371 the userspace. !! 2468 is enabled the kernel will support allocating & switching MSA
>> 2469 vector register contexts. If you know that your kernel will only be
>> 2470 running on CPUs which do not support MSA or that your userland will
>> 2471 not be making use of it then you may wish to say N here to reduce
>> 2472 the size & complexity of your kernel.
372 2473
373 This option should be enabled for th !! 2474 If unsure, say Y.
374 both call0 and windowed ABIs in user <<
375 2475
376 Note that Xtensa ISA does not guaran !! 2476 config CPU_HAS_WB
377 raise an illegal instruction excepti !! 2477 bool
378 PS.WOE is disabled, check whether th <<
379 2478
380 endchoice !! 2479 config XKS01
>> 2480 bool
381 2481
382 endmenu !! 2482 config CPU_HAS_DIEI
>> 2483 depends on !CPU_DIEI_BROKEN
>> 2484 bool
383 2485
384 config XTENSA_CALIBRATE_CCOUNT !! 2486 config CPU_DIEI_BROKEN
385 def_bool n !! 2487 bool
>> 2488
>> 2489 config CPU_HAS_RIXI
>> 2490 bool
>> 2491
>> 2492 config CPU_NO_LOAD_STORE_LR
>> 2493 bool
386 help 2494 help
387 On some platforms (XT2000, for examp !! 2495 CPU lacks support for unaligned load and store instructions:
388 vary. The frequency can be determin !! 2496 LWL, LWR, SWL, SWR (Load/store word left/right).
389 against a well known, fixed frequenc !! 2497 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2498 systems).
>> 2499
>> 2500 #
>> 2501 # Vectored interrupt mode is an R2 feature
>> 2502 #
>> 2503 config CPU_MIPSR2_IRQ_VI
>> 2504 bool
390 2505
391 config SERIAL_CONSOLE !! 2506 #
392 def_bool n !! 2507 # Extended interrupt mode is an R2 feature
>> 2508 #
>> 2509 config CPU_MIPSR2_IRQ_EI
>> 2510 bool
393 2511
394 config PLATFORM_HAVE_XIP !! 2512 config CPU_HAS_SYNC
395 def_bool n !! 2513 bool
>> 2514 depends on !CPU_R3000
>> 2515 default y
396 2516
397 menu "Platform options" !! 2517 #
>> 2518 # CPU non-features
>> 2519 #
>> 2520 config CPU_DADDI_WORKAROUNDS
>> 2521 bool
398 2522
399 choice !! 2523 config CPU_R4000_WORKAROUNDS
400 prompt "Xtensa System Type" !! 2524 bool
401 default XTENSA_PLATFORM_ISS !! 2525 select CPU_R4400_WORKAROUNDS
402 2526
403 config XTENSA_PLATFORM_ISS !! 2527 config CPU_R4400_WORKAROUNDS
404 bool "ISS" !! 2528 bool
405 select XTENSA_CALIBRATE_CCOUNT <<
406 select SERIAL_CONSOLE <<
407 help <<
408 ISS is an acronym for Tensilica's In <<
409 <<
410 config XTENSA_PLATFORM_XT2000 <<
411 bool "XT2000" <<
412 help <<
413 XT2000 is the name of Tensilica's fe <<
414 This hardware is capable of running <<
415 <<
416 config XTENSA_PLATFORM_XTFPGA <<
417 bool "XTFPGA" <<
418 select ETHOC if ETHERNET <<
419 select PLATFORM_WANT_DEFAULT_MEM if !M <<
420 select SERIAL_CONSOLE <<
421 select XTENSA_CALIBRATE_CCOUNT <<
422 select PLATFORM_HAVE_XIP <<
423 help <<
424 XTFPGA is the name of Tensilica boar <<
425 This hardware is capable of running <<
426 2529
427 endchoice !! 2530 config CPU_R4X00_BUGS64
>> 2531 bool
>> 2532 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
428 2533
429 config PLATFORM_NR_IRQS !! 2534 config MIPS_ASID_SHIFT
430 int 2535 int
431 default 3 if XTENSA_PLATFORM_XT2000 !! 2536 default 6 if CPU_R3000 || CPU_TX39XX
432 default 0 2537 default 0
433 2538
434 config XTENSA_CPU_CLOCK !! 2539 config MIPS_ASID_BITS
435 int "CPU clock rate [MHz]" !! 2540 int
436 depends on !XTENSA_CALIBRATE_CCOUNT !! 2541 default 0 if MIPS_ASID_BITS_VARIABLE
437 default 16 !! 2542 default 6 if CPU_R3000 || CPU_TX39XX
>> 2543 default 8
438 2544
439 config GENERIC_CALIBRATE_DELAY !! 2545 config MIPS_ASID_BITS_VARIABLE
440 bool "Auto calibration of the BogoMIPS !! 2546 bool
441 help <<
442 The BogoMIPS value can easily be der <<
443 2547
444 config CMDLINE_BOOL !! 2548 config MIPS_CRC_SUPPORT
445 bool "Default bootloader kernel argume !! 2549 bool
446 2550
447 config CMDLINE !! 2551 # R4600 erratum. Due to the lack of errata information the exact
448 string "Initial kernel command string" !! 2552 # technical details aren't known. I've experimentally found that disabling
449 depends on CMDLINE_BOOL !! 2553 # interrupts during indexed I-cache flushes seems to be sufficient to deal
450 default "console=ttyS0,38400 root=/dev !! 2554 # with the issue.
451 help !! 2555 config WAR_R4600_V1_INDEX_ICACHEOP
452 On some architectures (EBSA110 and C !! 2556 bool
453 for the boot loader to pass argument <<
454 architectures, you should supply som <<
455 time by entering them here. As a min <<
456 memory size and the root device (e.g <<
457 2557
458 config USE_OF !! 2558 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
459 bool "Flattened Device Tree support" !! 2559 #
460 select OF !! 2560 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
461 select OF_EARLY_FLATTREE !! 2561 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
462 help !! 2562 # executed if there is no other dcache activity. If the dcache is
463 Include support for flattened device !! 2563 # accessed for another instruction immediately preceding when these
>> 2564 # cache instructions are executing, it is possible that the dcache
>> 2565 # tag match outputs used by these cache instructions will be
>> 2566 # incorrect. These cache instructions should be preceded by at least
>> 2567 # four instructions that are not any kind of load or store
>> 2568 # instruction.
>> 2569 #
>> 2570 # This is not allowed: lw
>> 2571 # nop
>> 2572 # nop
>> 2573 # nop
>> 2574 # cache Hit_Writeback_Invalidate_D
>> 2575 #
>> 2576 # This is allowed: lw
>> 2577 # nop
>> 2578 # nop
>> 2579 # nop
>> 2580 # nop
>> 2581 # cache Hit_Writeback_Invalidate_D
>> 2582 config WAR_R4600_V1_HIT_CACHEOP
>> 2583 bool
464 2584
465 config BUILTIN_DTB_SOURCE !! 2585 # Writeback and invalidate the primary cache dcache before DMA.
466 string "DTB to build into the kernel i !! 2586 #
467 depends on OF !! 2587 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2588 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2589 # operate correctly if the internal data cache refill buffer is empty. These
>> 2590 # CACHE instructions should be separated from any potential data cache miss
>> 2591 # by a load instruction to an uncached address to empty the response buffer."
>> 2592 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2593 # in .pdf format.)
>> 2594 config WAR_R4600_V2_HIT_CACHEOP
>> 2595 bool
468 2596
469 config PARSE_BOOTPARAM !! 2597 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
470 bool "Parse bootparam block" !! 2598 # the line which this instruction itself exists, the following
471 default y !! 2599 # operation is not guaranteed."
472 help !! 2600 #
473 Parse parameters passed to the kerne !! 2601 # Workaround: do two phase flushing for Index_Invalidate_I
474 be disabled if the kernel is known t !! 2602 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2603 bool
475 2604
476 If unsure, say Y. !! 2605 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2606 # opposes it being called that) where invalid instructions in the same
>> 2607 # I-cache line worth of instructions being fetched may case spurious
>> 2608 # exceptions.
>> 2609 config WAR_ICACHE_REFILLS
>> 2610 bool
477 2611
478 choice !! 2612 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
479 prompt "Semihosting interface" !! 2613 # may cause ll / sc and lld / scd sequences to execute non-atomically.
480 default XTENSA_SIMCALL_ISS !! 2614 config WAR_R10000_LLSC
481 depends on XTENSA_PLATFORM_ISS !! 2615 bool
482 help <<
483 Choose semihosting interface that wi <<
484 block device and networking. <<
485 2616
486 config XTENSA_SIMCALL_ISS !! 2617 # 34K core erratum: "Problems Executing the TLBR Instruction"
487 bool "simcall" !! 2618 config WAR_MIPS34K_MISSED_ITLB
488 help !! 2619 bool
489 Use simcall instruction. simcall is <<
490 it does nothing on hardware. <<
491 2620
492 config XTENSA_SIMCALL_GDBIO !! 2621 #
493 bool "GDBIO" !! 2622 # - Highmem only makes sense for the 32-bit kernel.
>> 2623 # - The current highmem code will only work properly on physically indexed
>> 2624 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2625 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2626 # moment we protect the user and offer the highmem option only on machines
>> 2627 # where it's known to be safe. This will not offer highmem on a few systems
>> 2628 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2629 # indexed CPUs but we're playing safe.
>> 2630 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2631 # know they might have memory configurations that could make use of highmem
>> 2632 # support.
>> 2633 #
>> 2634 config HIGHMEM
>> 2635 bool "High Memory Support"
>> 2636 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2637 select KMAP_LOCAL
>> 2638
>> 2639 config CPU_SUPPORTS_HIGHMEM
>> 2640 bool
>> 2641
>> 2642 config SYS_SUPPORTS_HIGHMEM
>> 2643 bool
>> 2644
>> 2645 config SYS_SUPPORTS_SMARTMIPS
>> 2646 bool
>> 2647
>> 2648 config SYS_SUPPORTS_MICROMIPS
>> 2649 bool
>> 2650
>> 2651 config SYS_SUPPORTS_MIPS16
>> 2652 bool
494 help 2653 help
495 Use break instruction. It is availab !! 2654 This option must be set if a kernel might be executed on a MIPS16-
496 is attached to it via JTAG. !! 2655 enabled CPU even if MIPS16 is not actually being used. In other
>> 2656 words, it makes the kernel MIPS16-tolerant.
497 2657
498 endchoice !! 2658 config CPU_SUPPORTS_MSA
>> 2659 bool
499 2660
500 config BLK_DEV_SIMDISK !! 2661 config ARCH_FLATMEM_ENABLE
501 tristate "Host file-based simulated bl !! 2662 def_bool y
502 default n !! 2663 depends on !NUMA && !CPU_LOONGSON2EF
503 depends on XTENSA_PLATFORM_ISS && BLOC !! 2664
>> 2665 config ARCH_SPARSEMEM_ENABLE
>> 2666 bool
>> 2667 select SPARSEMEM_STATIC if !SGI_IP27
>> 2668
>> 2669 config NUMA
>> 2670 bool "NUMA Support"
>> 2671 depends on SYS_SUPPORTS_NUMA
>> 2672 select SMP
>> 2673 help
>> 2674 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2675 Access). This option improves performance on systems with more
>> 2676 than two nodes; on two node systems it is generally better to
>> 2677 leave it disabled; on single node systems leave this option
>> 2678 disabled.
>> 2679
>> 2680 config SYS_SUPPORTS_NUMA
>> 2681 bool
>> 2682
>> 2683 config HAVE_SETUP_PER_CPU_AREA
>> 2684 def_bool y
>> 2685 depends on NUMA
>> 2686
>> 2687 config NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2688 def_bool y
>> 2689 depends on NUMA
>> 2690
>> 2691 config RELOCATABLE
>> 2692 bool "Relocatable kernel"
>> 2693 depends on SYS_SUPPORTS_RELOCATABLE
>> 2694 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2695 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2696 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2697 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2698 CPU_LOONGSON64
>> 2699 help
>> 2700 This builds a kernel image that retains relocation information
>> 2701 so it can be loaded someplace besides the default 1MB.
>> 2702 The relocations make the kernel binary about 15% larger,
>> 2703 but are discarded at runtime
>> 2704
>> 2705 config RELOCATION_TABLE_SIZE
>> 2706 hex "Relocation table size"
>> 2707 depends on RELOCATABLE
>> 2708 range 0x0 0x01000000
>> 2709 default "0x00200000" if CPU_LOONGSON64
>> 2710 default "0x00100000"
>> 2711 help
>> 2712 A table of relocation data will be appended to the kernel binary
>> 2713 and parsed at boot to fix up the relocated kernel.
>> 2714
>> 2715 This option allows the amount of space reserved for the table to be
>> 2716 adjusted, although the default of 1Mb should be ok in most cases.
>> 2717
>> 2718 The build will fail and a valid size suggested if this is too small.
>> 2719
>> 2720 If unsure, leave at the default value.
>> 2721
>> 2722 config RANDOMIZE_BASE
>> 2723 bool "Randomize the address of the kernel image"
>> 2724 depends on RELOCATABLE
>> 2725 help
>> 2726 Randomizes the physical and virtual address at which the
>> 2727 kernel image is loaded, as a security feature that
>> 2728 deters exploit attempts relying on knowledge of the location
>> 2729 of kernel internals.
>> 2730
>> 2731 Entropy is generated using any coprocessor 0 registers available.
>> 2732
>> 2733 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2734
>> 2735 If unsure, say N.
>> 2736
>> 2737 config RANDOMIZE_BASE_MAX_OFFSET
>> 2738 hex "Maximum kASLR offset" if EXPERT
>> 2739 depends on RANDOMIZE_BASE
>> 2740 range 0x0 0x40000000 if EVA || 64BIT
>> 2741 range 0x0 0x08000000
>> 2742 default "0x01000000"
>> 2743 help
>> 2744 When kASLR is active, this provides the maximum offset that will
>> 2745 be applied to the kernel image. It should be set according to the
>> 2746 amount of physical RAM available in the target system minus
>> 2747 PHYSICAL_START and must be a power of 2.
>> 2748
>> 2749 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2750 EVA or 64-bit. The default is 16Mb.
>> 2751
>> 2752 config NODES_SHIFT
>> 2753 int
>> 2754 default "6"
>> 2755 depends on NUMA
>> 2756
>> 2757 config HW_PERF_EVENTS
>> 2758 bool "Enable hardware performance counter support for perf events"
>> 2759 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
>> 2760 default y
504 help 2761 help
505 Create block devices that map to fil !! 2762 Enable hardware performance counter support for perf events. If
506 Device binding to host file may be c !! 2763 disabled, perf events will use software events only.
507 interface provided the device is not !! 2764
508 !! 2765 config DMI
509 config BLK_DEV_SIMDISK_COUNT !! 2766 bool "Enable DMI scanning"
510 int "Number of host file-based simulat !! 2767 depends on MACH_LOONGSON64
511 range 1 10 !! 2768 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
512 depends on BLK_DEV_SIMDISK !! 2769 default y
513 default 2 <<
514 help 2770 help
515 This is the default minimal number o !! 2771 Enabled scanning of DMI to identify machine quirks. Say Y
516 Kernel/module parameter 'simdisk_cou !! 2772 here unless you have verified that your setup is not
517 value at runtime. More file names (b !! 2773 affected by entries in the DMI blacklist. Required by PNP
518 specified as parameters, simdisk_cou !! 2774 BIOS code.
519 !! 2775
520 config SIMDISK0_FILENAME !! 2776 config SMP
521 string "Host filename for the first si !! 2777 bool "Multi-Processing support"
522 depends on BLK_DEV_SIMDISK = y !! 2778 depends on SYS_SUPPORTS_SMP
523 default "" <<
524 help <<
525 Attach a first simdisk to a host fil <<
526 contains a root file system. <<
527 <<
528 config SIMDISK1_FILENAME <<
529 string "Host filename for the second s <<
530 depends on BLK_DEV_SIMDISK = y && BLK_ <<
531 default "" <<
532 help <<
533 Another simulated disk in a host fil <<
534 storage. <<
535 <<
536 config XTFPGA_LCD <<
537 bool "Enable XTFPGA LCD driver" <<
538 depends on XTENSA_PLATFORM_XTFPGA <<
539 default n <<
540 help 2779 help
541 There's a 2x16 LCD on most of XTFPGA !! 2780 This enables support for systems with more than one CPU. If you have
542 progress messages there during bootu !! 2781 a system with only one CPU, say N. If you have a system with more
543 during board bringup. !! 2782 than one CPU, say Y.
>> 2783
>> 2784 If you say N here, the kernel will run on uni- and multiprocessor
>> 2785 machines, but will use only one CPU of a multiprocessor machine. If
>> 2786 you say Y here, the kernel will run on many, but not all,
>> 2787 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2788 will run faster if you say N here.
544 2789
545 If unsure, say N. !! 2790 People using multiprocessor machines who say Y here should also say
>> 2791 Y to "Enhanced Real Time Clock Support", below.
546 2792
547 config XTFPGA_LCD_BASE_ADDR !! 2793 See also the SMP-HOWTO available at
548 hex "XTFPGA LCD base address" !! 2794 <https://www.tldp.org/docs.html#howto>.
549 depends on XTFPGA_LCD !! 2795
550 default "0x0d0c0000" !! 2796 If you don't know what to do here, say N.
551 help !! 2797
552 Base address of the LCD controller i !! 2798 config HOTPLUG_CPU
553 Different boards from XTFPGA family !! 2799 bool "Support for hot-pluggable CPUs"
554 addresses. Please consult prototypin !! 2800 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
555 the correct address. Wrong address h <<
556 <<
557 config XTFPGA_LCD_8BIT_ACCESS <<
558 bool "Use 8-bit access to XTFPGA LCD" <<
559 depends on XTFPGA_LCD <<
560 default n <<
561 help 2801 help
562 LCD may be connected with 4- or 8-bi !! 2802 Say Y here to allow turning CPUs off and on. CPUs can be
563 only be used with 8-bit interface. P !! 2803 controlled through /sys/devices/system/cpu.
564 guide for your board for the correct !! 2804 (Note: power management support will enable this option
565 !! 2805 automatically on SMP systems. )
566 comment "Kernel memory layout" !! 2806 Say N if you want to disable CPU hotplug.
567 <<
568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX <<
569 bool "Initialize Xtensa MMU inside the <<
570 depends on !XTENSA_VARIANT_FSF && !XTE <<
571 default y if XTENSA_VARIANT_DC233C || <<
572 help <<
573 Earlier version initialized the MMU <<
574 before jumping to _startup in head.S <<
575 it was possible to place a software <<
576 then enter your normal kernel breakp <<
577 to the kernel mappings (0XC0000000). <<
578 <<
579 This unfortunately won't work for U- <<
580 work for using KEXEC to have a hot k <<
581 KDUMP. <<
582 <<
583 So now the MMU is initialized in hea <<
584 use hardware breakpoints (gdb 'hbrea <<
585 xt-gdb can't place a Software Breakp <<
586 to mapping the MMU and after mapping <<
587 was mapped gdb wouldn't remove the b <<
588 PC wouldn't match. Since Hardware Br <<
589 Linux configurations it seems reason <<
590 and leave this older mechanism for u <<
591 not to follow Tensilica's recommenda <<
592 <<
593 Selecting this will cause U-Boot to <<
594 address at 0x00003000 instead of the <<
595 <<
596 If in doubt, say Y. <<
597 <<
598 config XIP_KERNEL <<
599 bool "Kernel Execute-In-Place from ROM <<
600 depends on PLATFORM_HAVE_XIP <<
601 help <<
602 Execute-In-Place allows the kernel t <<
603 directly addressable by the CPU, suc <<
604 space since the text section of the <<
605 to RAM. Read-write sections, such as <<
606 are still copied to RAM. The XIP ker <<
607 it has to run directly from flash, s <<
608 store it. The flash address used to <<
609 and for storing it, is configuration <<
610 say Y here, you must know the proper <<
611 store the kernel image depending on <<
612 <<
613 Also note that the make target becom <<
614 "make Image" or "make uImage". The f <<
615 ROM memory will be arch/xtensa/boot/ <<
616 2807
617 If unsure, say N. !! 2808 config SMP_UP
>> 2809 bool
>> 2810
>> 2811 config SYS_SUPPORTS_MIPS_CMP
>> 2812 bool
618 2813
619 config MEMMAP_CACHEATTR !! 2814 config SYS_SUPPORTS_MIPS_CPS
620 hex "Cache attributes for the memory a !! 2815 bool
621 depends on !MMU <<
622 default 0x22222222 <<
623 help <<
624 These cache attributes are set up fo <<
625 specifies cache attributes for the c <<
626 region: bits 0..3 -- for addresses 0 <<
627 bits 4..7 -- for addresses 0x2000000 <<
628 <<
629 Cache attribute values are specific <<
630 For region protection MMUs: <<
631 1: WT cached, <<
632 2: cache bypass, <<
633 4: WB cached, <<
634 f: illegal. <<
635 For full MMU: <<
636 bit 0: executable, <<
637 bit 1: writable, <<
638 bits 2..3: <<
639 0: cache bypass, <<
640 1: WB cache, <<
641 2: WT cache, <<
642 3: special (c and e are illegal, <<
643 For MPU: <<
644 0: illegal, <<
645 1: WB cache, <<
646 2: WB, no-write-allocate cache, <<
647 3: WT cache, <<
648 4: cache bypass. <<
649 <<
650 config KSEG_PADDR <<
651 hex "Physical address of the KSEG mapp <<
652 depends on INITIALIZE_XTENSA_MMU_INSID <<
653 default 0x00000000 <<
654 help <<
655 This is the physical address where K <<
656 the chosen KSEG layout help for the <<
657 Unpacked kernel image (including vec <<
658 within KSEG. <<
659 Physical memory below this address i <<
660 <<
661 If unsure, leave the default value h <<
662 <<
663 config KERNEL_VIRTUAL_ADDRESS <<
664 hex "Kernel virtual address" <<
665 depends on MMU && XIP_KERNEL <<
666 default 0xd0003000 <<
667 help <<
668 This is the virtual address where th <<
669 XIP kernel may be mapped into KSEG o <<
670 provided here must match kernel load <<
671 KERNEL_LOAD_ADDRESS. <<
672 <<
673 config KERNEL_LOAD_ADDRESS <<
674 hex "Kernel load address" <<
675 default 0x60003000 if !MMU <<
676 default 0x00003000 if MMU && INITIALIZ <<
677 default 0xd0003000 if MMU && !INITIALI <<
678 help <<
679 This is the address where the kernel <<
680 It is virtual address for MMUv2 conf <<
681 for all other configurations. <<
682 2816
683 If unsure, leave the default value h !! 2817 config SYS_SUPPORTS_SMP
>> 2818 bool
>> 2819
>> 2820 config NR_CPUS_DEFAULT_4
>> 2821 bool
>> 2822
>> 2823 config NR_CPUS_DEFAULT_8
>> 2824 bool
>> 2825
>> 2826 config NR_CPUS_DEFAULT_16
>> 2827 bool
>> 2828
>> 2829 config NR_CPUS_DEFAULT_32
>> 2830 bool
>> 2831
>> 2832 config NR_CPUS_DEFAULT_64
>> 2833 bool
>> 2834
>> 2835 config NR_CPUS
>> 2836 int "Maximum number of CPUs (2-256)"
>> 2837 range 2 256
>> 2838 depends on SMP
>> 2839 default "4" if NR_CPUS_DEFAULT_4
>> 2840 default "8" if NR_CPUS_DEFAULT_8
>> 2841 default "16" if NR_CPUS_DEFAULT_16
>> 2842 default "32" if NR_CPUS_DEFAULT_32
>> 2843 default "64" if NR_CPUS_DEFAULT_64
>> 2844 help
>> 2845 This allows you to specify the maximum number of CPUs which this
>> 2846 kernel will support. The maximum supported value is 32 for 32-bit
>> 2847 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2848 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2849 and 2 for all others.
>> 2850
>> 2851 This is purely to save memory - each supported CPU adds
>> 2852 approximately eight kilobytes to the kernel image. For best
>> 2853 performance should round up your number of processors to the next
>> 2854 power of two.
>> 2855
>> 2856 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2857 bool
>> 2858
>> 2859 config MIPS_NR_CPU_NR_MAP_1024
>> 2860 bool
>> 2861
>> 2862 config MIPS_NR_CPU_NR_MAP
>> 2863 int
>> 2864 depends on SMP
>> 2865 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2866 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
>> 2867
>> 2868 #
>> 2869 # Timer Interrupt Frequency Configuration
>> 2870 #
684 2871
685 choice 2872 choice
686 prompt "Relocatable vectors location" !! 2873 prompt "Timer frequency"
687 default XTENSA_VECTORS_IN_TEXT !! 2874 default HZ_250
688 help 2875 help
689 Choose whether relocatable vectors a !! 2876 Allows the configuration of the timer frequency.
690 or placed separately at runtime. Thi !! 2877
691 configurations without VECBASE regis !! 2878 config HZ_24
692 placed at their hardware-defined loc !! 2879 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
693 !! 2880
694 config XTENSA_VECTORS_IN_TEXT !! 2881 config HZ_48
695 bool "Merge relocatable vectors into k !! 2882 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
696 depends on !MTD_XIP !! 2883
697 help !! 2884 config HZ_100
698 This option puts relocatable vectors !! 2885 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
699 with proper alignment. !! 2886
700 This is a safe choice for most confi !! 2887 config HZ_128
701 !! 2888 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
702 config XTENSA_VECTORS_SEPARATE !! 2889
703 bool "Put relocatable vectors at fixed !! 2890 config HZ_250
704 help !! 2891 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
705 This option puts relocatable vectors !! 2892
706 Vectors are merged with the .init da !! 2893 config HZ_256
707 are copied into their designated loc !! 2894 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
708 Use it to put vectors into IRAM or o !! 2895
709 XIP-aware MTD support. !! 2896 config HZ_1000
>> 2897 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2898
>> 2899 config HZ_1024
>> 2900 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
710 2901
711 endchoice 2902 endchoice
712 2903
713 config VECTORS_ADDR !! 2904 config SYS_SUPPORTS_24HZ
714 hex "Kernel vectors virtual address" !! 2905 bool
715 default 0x00000000 <<
716 depends on XTENSA_VECTORS_SEPARATE <<
717 help <<
718 This is the virtual address of the ( <<
719 It must be within KSEG if MMU is use <<
720 <<
721 config XIP_DATA_ADDR <<
722 hex "XIP kernel data virtual address" <<
723 depends on XIP_KERNEL <<
724 default 0x00000000 <<
725 help <<
726 This is the virtual address where XI <<
727 It must be within KSEG if MMU is use <<
728 2906
729 config PLATFORM_WANT_DEFAULT_MEM !! 2907 config SYS_SUPPORTS_48HZ
730 def_bool n !! 2908 bool
731 2909
732 config DEFAULT_MEM_START !! 2910 config SYS_SUPPORTS_100HZ
733 hex !! 2911 bool
734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !M <<
735 default 0x60000000 if PLATFORM_WANT_DE <<
736 default 0x00000000 <<
737 help <<
738 This is the base address used for bo <<
739 in noMMU configurations. <<
740 2912
741 If unsure, leave the default value h !! 2913 config SYS_SUPPORTS_128HZ
>> 2914 bool
>> 2915
>> 2916 config SYS_SUPPORTS_250HZ
>> 2917 bool
>> 2918
>> 2919 config SYS_SUPPORTS_256HZ
>> 2920 bool
>> 2921
>> 2922 config SYS_SUPPORTS_1000HZ
>> 2923 bool
>> 2924
>> 2925 config SYS_SUPPORTS_1024HZ
>> 2926 bool
>> 2927
>> 2928 config SYS_SUPPORTS_ARBIT_HZ
>> 2929 bool
>> 2930 default y if !SYS_SUPPORTS_24HZ && \
>> 2931 !SYS_SUPPORTS_48HZ && \
>> 2932 !SYS_SUPPORTS_100HZ && \
>> 2933 !SYS_SUPPORTS_128HZ && \
>> 2934 !SYS_SUPPORTS_250HZ && \
>> 2935 !SYS_SUPPORTS_256HZ && \
>> 2936 !SYS_SUPPORTS_1000HZ && \
>> 2937 !SYS_SUPPORTS_1024HZ
>> 2938
>> 2939 config HZ
>> 2940 int
>> 2941 default 24 if HZ_24
>> 2942 default 48 if HZ_48
>> 2943 default 100 if HZ_100
>> 2944 default 128 if HZ_128
>> 2945 default 250 if HZ_250
>> 2946 default 256 if HZ_256
>> 2947 default 1000 if HZ_1000
>> 2948 default 1024 if HZ_1024
>> 2949
>> 2950 config SCHED_HRTICK
>> 2951 def_bool HIGH_RES_TIMERS
>> 2952
>> 2953 config KEXEC
>> 2954 bool "Kexec system call"
>> 2955 select KEXEC_CORE
>> 2956 help
>> 2957 kexec is a system call that implements the ability to shutdown your
>> 2958 current kernel, and to start another kernel. It is like a reboot
>> 2959 but it is independent of the system firmware. And like a reboot
>> 2960 you can start any kernel with it, not just Linux.
>> 2961
>> 2962 The name comes from the similarity to the exec system call.
>> 2963
>> 2964 It is an ongoing process to be certain the hardware in a machine
>> 2965 is properly shutdown, so do not be surprised if this code does not
>> 2966 initially work for you. As of this writing the exact hardware
>> 2967 interface is strongly in flux, so no good recommendation can be
>> 2968 made.
>> 2969
>> 2970 config CRASH_DUMP
>> 2971 bool "Kernel crash dumps"
>> 2972 help
>> 2973 Generate crash dump after being started by kexec.
>> 2974 This should be normally only set in special crash dump kernels
>> 2975 which are loaded in the main kernel with kexec-tools into
>> 2976 a specially reserved region and then later executed after
>> 2977 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2978 to a memory address not used by the main kernel or firmware using
>> 2979 PHYSICAL_START.
>> 2980
>> 2981 config PHYSICAL_START
>> 2982 hex "Physical address where the kernel is loaded"
>> 2983 default "0xffffffff84000000"
>> 2984 depends on CRASH_DUMP
>> 2985 help
>> 2986 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2987 If you plan to use kernel for capturing the crash dump change
>> 2988 this value to start of the reserved region (the "X" value as
>> 2989 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2990 passed to the panic-ed kernel).
>> 2991
>> 2992 config MIPS_O32_FP64_SUPPORT
>> 2993 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2994 depends on 32BIT || MIPS32_O32
>> 2995 help
>> 2996 When this is enabled, the kernel will support use of 64-bit floating
>> 2997 point registers with binaries using the O32 ABI along with the
>> 2998 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2999 32-bit MIPS systems this support is at the cost of increasing the
>> 3000 size and complexity of the compiled FPU emulator. Thus if you are
>> 3001 running a MIPS32 system and know that none of your userland binaries
>> 3002 will require 64-bit floating point, you may wish to reduce the size
>> 3003 of your kernel & potentially improve FP emulation performance by
>> 3004 saying N here.
>> 3005
>> 3006 Although binutils currently supports use of this flag the details
>> 3007 concerning its effect upon the O32 ABI in userland are still being
>> 3008 worked on. In order to avoid userland becoming dependent upon current
>> 3009 behaviour before the details have been finalised, this option should
>> 3010 be considered experimental and only enabled by those working upon
>> 3011 said details.
>> 3012
>> 3013 If unsure, say N.
>> 3014
>> 3015 config USE_OF
>> 3016 bool
>> 3017 select OF
>> 3018 select OF_EARLY_FLATTREE
>> 3019 select IRQ_DOMAIN
>> 3020
>> 3021 config UHI_BOOT
>> 3022 bool
>> 3023
>> 3024 config BUILTIN_DTB
>> 3025 bool
742 3026
743 choice 3027 choice
744 prompt "KSEG layout" !! 3028 prompt "Kernel appended dtb support" if USE_OF
745 depends on MMU !! 3029 default MIPS_NO_APPENDED_DTB
746 default XTENSA_KSEG_MMU_V2 <<
747 <<
748 config XTENSA_KSEG_MMU_V2 <<
749 bool "MMUv2: 128MB cached + 128MB unca <<
750 help <<
751 MMUv2 compatible kernel memory map: <<
752 at KSEG_PADDR to 0xd0000000 with cac <<
753 without cache. <<
754 KSEG_PADDR must be aligned to 128MB. <<
755 <<
756 config XTENSA_KSEG_256M <<
757 bool "256MB cached + 256MB uncached" <<
758 depends on INITIALIZE_XTENSA_MMU_INSID <<
759 help <<
760 TLB way 6 maps 256MB starting at KSE <<
761 with cache and to 0xc0000000 without <<
762 KSEG_PADDR must be aligned to 256MB. <<
763 <<
764 config XTENSA_KSEG_512M <<
765 bool "512MB cached + 512MB uncached" <<
766 depends on INITIALIZE_XTENSA_MMU_INSID <<
767 help <<
768 TLB way 6 maps 512MB starting at KSE <<
769 with cache and to 0xc0000000 without <<
770 KSEG_PADDR must be aligned to 256MB. <<
771 3030
>> 3031 config MIPS_NO_APPENDED_DTB
>> 3032 bool "None"
>> 3033 help
>> 3034 Do not enable appended dtb support.
>> 3035
>> 3036 config MIPS_ELF_APPENDED_DTB
>> 3037 bool "vmlinux"
>> 3038 help
>> 3039 With this option, the boot code will look for a device tree binary
>> 3040 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3041 it is empty and the DTB can be appended using binutils command
>> 3042 objcopy:
>> 3043
>> 3044 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3045
>> 3046 This is meant as a backward compatibility convenience for those
>> 3047 systems with a bootloader that can't be upgraded to accommodate
>> 3048 the documented boot protocol using a device tree.
>> 3049
>> 3050 config MIPS_RAW_APPENDED_DTB
>> 3051 bool "vmlinux.bin or vmlinuz.bin"
>> 3052 help
>> 3053 With this option, the boot code will look for a device tree binary
>> 3054 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3055 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3056
>> 3057 This is meant as a backward compatibility convenience for those
>> 3058 systems with a bootloader that can't be upgraded to accommodate
>> 3059 the documented boot protocol using a device tree.
>> 3060
>> 3061 Beware that there is very little in terms of protection against
>> 3062 this option being confused by leftover garbage in memory that might
>> 3063 look like a DTB header after a reboot if no actual DTB is appended
>> 3064 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3065 if you don't intend to always append a DTB.
772 endchoice 3066 endchoice
773 3067
774 config HIGHMEM !! 3068 choice
775 bool "High Memory Support" !! 3069 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
776 depends on MMU !! 3070 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
777 select KMAP_LOCAL !! 3071 !MACH_LOONGSON64 && !MIPS_MALTA && \
778 help !! 3072 !CAVIUM_OCTEON_SOC
779 Linux can use the full amount of RAM !! 3073 default MIPS_CMDLINE_FROM_BOOTLOADER
780 default. However, the default MMUv2 !! 3074
781 lowermost 128 MB of memory linearly !! 3075 config MIPS_CMDLINE_FROM_DTB
782 at 0xd0000000 (cached) and 0xd800000 !! 3076 depends on USE_OF
783 When there are more than 128 MB memo !! 3077 bool "Dtb kernel arguments if available"
784 all of it can be "permanently mapped !! 3078
785 The physical memory that's not perma !! 3079 config MIPS_CMDLINE_DTB_EXTEND
786 "high memory". !! 3080 depends on USE_OF
787 !! 3081 bool "Extend dtb kernel arguments with bootloader arguments"
788 If you are compiling a kernel which !! 3082
789 machine with more than 128 MB total !! 3083 config MIPS_CMDLINE_FROM_BOOTLOADER
790 N here. !! 3084 bool "Bootloader kernel arguments if available"
>> 3085
>> 3086 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3087 depends on CMDLINE_BOOL
>> 3088 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3089 endchoice
791 3090
792 If unsure, say Y. !! 3091 endmenu
>> 3092
>> 3093 config LOCKDEP_SUPPORT
>> 3094 bool
>> 3095 default y
>> 3096
>> 3097 config STACKTRACE_SUPPORT
>> 3098 bool
>> 3099 default y
>> 3100
>> 3101 config PGTABLE_LEVELS
>> 3102 int
>> 3103 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3104 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3105 default 2
>> 3106
>> 3107 config MIPS_AUTO_PFN_OFFSET
>> 3108 bool
>> 3109
>> 3110 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
>> 3111
>> 3112 config PCI_DRIVERS_GENERIC
>> 3113 select PCI_DOMAINS_GENERIC if PCI
>> 3114 bool
>> 3115
>> 3116 config PCI_DRIVERS_LEGACY
>> 3117 def_bool !PCI_DRIVERS_GENERIC
>> 3118 select NO_GENERIC_PCI_IOPORT_MAP
>> 3119 select PCI_DOMAINS if PCI
>> 3120
>> 3121 #
>> 3122 # ISA support is now enabled via select. Too many systems still have the one
>> 3123 # or other ISA chip on the board that users don't know about so don't expect
>> 3124 # users to choose the right thing ...
>> 3125 #
>> 3126 config ISA
>> 3127 bool
>> 3128
>> 3129 config TC
>> 3130 bool "TURBOchannel support"
>> 3131 depends on MACH_DECSTATION
>> 3132 help
>> 3133 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3134 processors. TURBOchannel programming specifications are available
>> 3135 at:
>> 3136 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3137 and:
>> 3138 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3139 Linux driver support status is documented at:
>> 3140 <http://www.linux-mips.org/wiki/DECstation>
>> 3141
>> 3142 config MMU
>> 3143 bool
>> 3144 default y
>> 3145
>> 3146 config ARCH_MMAP_RND_BITS_MIN
>> 3147 default 12 if 64BIT
>> 3148 default 8
>> 3149
>> 3150 config ARCH_MMAP_RND_BITS_MAX
>> 3151 default 18 if 64BIT
>> 3152 default 15
793 3153
794 config ARCH_FORCE_MAX_ORDER !! 3154 config ARCH_MMAP_RND_COMPAT_BITS_MIN
795 int "Order of maximal physically conti !! 3155 default 8
796 default "10" <<
797 help <<
798 The kernel page allocator limits the <<
799 contiguous allocations. The limit is <<
800 defines the maximal power of two of <<
801 allocated as a single contiguous blo <<
802 overriding the default setting when <<
803 large blocks of physically contiguou <<
804 3156
805 Don't change if unsure. !! 3157 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3158 default 15
806 3159
>> 3160 config I8253
>> 3161 bool
>> 3162 select CLKSRC_I8253
>> 3163 select CLKEVT_I8253
>> 3164 select MIPS_EXTERNAL_TIMER
807 endmenu 3165 endmenu
808 3166
>> 3167 config TRAD_SIGNALS
>> 3168 bool
>> 3169
>> 3170 config MIPS32_COMPAT
>> 3171 bool
>> 3172
>> 3173 config COMPAT
>> 3174 bool
>> 3175
>> 3176 config SYSVIPC_COMPAT
>> 3177 bool
>> 3178
>> 3179 config MIPS32_O32
>> 3180 bool "Kernel support for o32 binaries"
>> 3181 depends on 64BIT
>> 3182 select ARCH_WANT_OLD_COMPAT_IPC
>> 3183 select COMPAT
>> 3184 select MIPS32_COMPAT
>> 3185 select SYSVIPC_COMPAT if SYSVIPC
>> 3186 help
>> 3187 Select this option if you want to run o32 binaries. These are pure
>> 3188 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3189 existing binaries are in this format.
>> 3190
>> 3191 If unsure, say Y.
>> 3192
>> 3193 config MIPS32_N32
>> 3194 bool "Kernel support for n32 binaries"
>> 3195 depends on 64BIT
>> 3196 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3197 select COMPAT
>> 3198 select MIPS32_COMPAT
>> 3199 select SYSVIPC_COMPAT if SYSVIPC
>> 3200 help
>> 3201 Select this option if you want to run n32 binaries. These are
>> 3202 64-bit binaries using 32-bit quantities for addressing and certain
>> 3203 data that would normally be 64-bit. They are used in special
>> 3204 cases.
>> 3205
>> 3206 If unsure, say N.
>> 3207
809 menu "Power management options" 3208 menu "Power management options"
810 3209
811 config ARCH_HIBERNATION_POSSIBLE 3210 config ARCH_HIBERNATION_POSSIBLE
812 def_bool y 3211 def_bool y
>> 3212 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3213
>> 3214 config ARCH_SUSPEND_POSSIBLE
>> 3215 def_bool y
>> 3216 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
813 3217
814 source "kernel/power/Kconfig" 3218 source "kernel/power/Kconfig"
815 3219
816 endmenu 3220 endmenu
>> 3221
>> 3222 config MIPS_EXTERNAL_TIMER
>> 3223 bool
>> 3224
>> 3225 menu "CPU Power Management"
>> 3226
>> 3227 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3228 source "drivers/cpufreq/Kconfig"
>> 3229 endif
>> 3230
>> 3231 source "drivers/cpuidle/Kconfig"
>> 3232
>> 3233 endmenu
>> 3234
>> 3235 source "arch/mips/kvm/Kconfig"
>> 3236
>> 3237 source "arch/mips/vdso/Kconfig"
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