1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 config XTENSA !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ARCH_32BIT_OFF_T !! 4 default y
5 select ARCH_HAS_CPU_CACHE_ALIASING !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_HAS_BINFMT_FLAT if !MMU !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CURRENT_STACK_POINTER !! 7 select ARCH_CLOCKSOURCE_DATA
8 select ARCH_HAS_DEBUG_VM_PGTABLE !! 8 select ARCH_HAS_FORTIFY_SOURCE
9 select ARCH_HAS_DMA_PREP_COHERENT if M <<
10 select ARCH_HAS_GCOV_PROFILE_ALL <<
11 select ARCH_HAS_KCOV 9 select ARCH_HAS_KCOV
12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MM !! 10 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if !! 11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
14 select ARCH_HAS_DMA_SET_UNCACHED if MM !! 12 select ARCH_HAS_UBSAN_SANITIZE_ALL
15 select ARCH_HAS_STRNCPY_FROM_USER if ! !! 13 select ARCH_SUPPORTS_UPROBES
16 select ARCH_HAS_STRNLEN_USER !! 14 select ARCH_USE_BUILTIN_BSWAP
17 select ARCH_NEED_CMPXCHG_1_EMU !! 15 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
18 select ARCH_USE_MEMTEST <<
19 select ARCH_USE_QUEUED_RWLOCKS 16 select ARCH_USE_QUEUED_RWLOCKS
20 select ARCH_USE_QUEUED_SPINLOCKS 17 select ARCH_USE_QUEUED_SPINLOCKS
>> 18 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
21 select ARCH_WANT_IPC_PARSE_VERSION 19 select ARCH_WANT_IPC_PARSE_VERSION
22 select BUILDTIME_TABLE_SORT 20 select BUILDTIME_TABLE_SORT
23 select CLONE_BACKWARDS 21 select CLONE_BACKWARDS
24 select COMMON_CLK !! 22 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
25 select DMA_NONCOHERENT_MMAP if MMU !! 23 select CPU_PM if CPU_IDLE
26 select GENERIC_ATOMIC64 !! 24 select GENERIC_ATOMIC64 if !64BIT
>> 25 select GENERIC_CLOCKEVENTS
>> 26 select GENERIC_CMOS_UPDATE
>> 27 select GENERIC_CPU_AUTOPROBE
>> 28 select GENERIC_GETTIMEOFDAY
>> 29 select GENERIC_IOMAP
>> 30 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW 31 select GENERIC_IRQ_SHOW
>> 32 select GENERIC_ISA_DMA if EISA
>> 33 select GENERIC_LIB_ASHLDI3
>> 34 select GENERIC_LIB_ASHRDI3
28 select GENERIC_LIB_CMPDI2 35 select GENERIC_LIB_CMPDI2
29 select GENERIC_LIB_MULDI3 !! 36 select GENERIC_LIB_LSHRDI3
30 select GENERIC_LIB_UCMPDI2 37 select GENERIC_LIB_UCMPDI2
31 select GENERIC_PCI_IOMAP !! 38 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
32 select GENERIC_SCHED_CLOCK !! 39 select GENERIC_SMP_IDLE_THREAD
33 select GENERIC_IOREMAP if MMU !! 40 select GENERIC_TIME_VSYSCALL
34 select HAVE_ARCH_AUDITSYSCALL !! 41 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
35 select HAVE_ARCH_JUMP_LABEL if !XIP_KE !! 42 select HANDLE_DOMAIN_IRQ
36 select HAVE_ARCH_KASAN if MMU && !XIP_ !! 43 select HAVE_ARCH_COMPILER_H
37 select HAVE_ARCH_KCSAN !! 44 select HAVE_ARCH_JUMP_LABEL
>> 45 select HAVE_ARCH_KGDB
>> 46 select HAVE_ARCH_MMAP_RND_BITS if MMU
>> 47 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
38 select HAVE_ARCH_SECCOMP_FILTER 48 select HAVE_ARCH_SECCOMP_FILTER
39 select HAVE_ARCH_TRACEHOOK 49 select HAVE_ARCH_TRACEHOOK
>> 50 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
40 select HAVE_ASM_MODVERSIONS 51 select HAVE_ASM_MODVERSIONS
41 select HAVE_CONTEXT_TRACKING_USER !! 52 select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
>> 53 select HAVE_CONTEXT_TRACKING
>> 54 select HAVE_COPY_THREAD_TLS
>> 55 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK 56 select HAVE_DEBUG_KMEMLEAK
>> 57 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_DMA_CONTIGUOUS 58 select HAVE_DMA_CONTIGUOUS
>> 59 select HAVE_DYNAMIC_FTRACE
>> 60 select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
44 select HAVE_EXIT_THREAD 61 select HAVE_EXIT_THREAD
>> 62 select HAVE_FAST_GUP
>> 63 select HAVE_FTRACE_MCOUNT_RECORD
>> 64 select HAVE_FUNCTION_GRAPH_TRACER
45 select HAVE_FUNCTION_TRACER 65 select HAVE_FUNCTION_TRACER
46 select HAVE_GCC_PLUGINS if GCC_VERSION !! 66 select HAVE_GCC_PLUGINS
47 select HAVE_HW_BREAKPOINT if PERF_EVEN !! 67 select HAVE_GENERIC_VDSO
>> 68 select HAVE_IDE
>> 69 select HAVE_IOREMAP_PROT
>> 70 select HAVE_IRQ_EXIT_ON_IRQ_STACK
48 select HAVE_IRQ_TIME_ACCOUNTING 71 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_PAGE_SIZE_4KB !! 72 select HAVE_KPROBES
50 select HAVE_PCI !! 73 select HAVE_KRETPROBES
>> 74 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 75 select HAVE_MEMBLOCK_NODE_MAP
>> 76 select HAVE_MOD_ARCH_SPECIFIC
>> 77 select HAVE_NMI
>> 78 select HAVE_OPROFILE
51 select HAVE_PERF_EVENTS 79 select HAVE_PERF_EVENTS
>> 80 select HAVE_REGS_AND_STACK_ACCESS_API
>> 81 select HAVE_RSEQ
>> 82 select HAVE_SPARSE_SYSCALL_NR
52 select HAVE_STACKPROTECTOR 83 select HAVE_STACKPROTECTOR
53 select HAVE_SYSCALL_TRACEPOINTS 84 select HAVE_SYSCALL_TRACEPOINTS
54 select HAVE_VIRT_CPU_ACCOUNTING_GEN !! 85 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
55 select IRQ_DOMAIN !! 86 select IRQ_FORCED_THREADING
56 select LOCK_MM_AND_FIND_VMA !! 87 select ISA if EISA
57 select MODULES_USE_ELF_RELA !! 88 select MODULES_USE_ELF_REL if MODULES
>> 89 select MODULES_USE_ELF_RELA if MODULES && 64BIT
58 select PERF_USE_VMALLOC 90 select PERF_USE_VMALLOC
59 select TRACE_IRQFLAGS_SUPPORT !! 91 select RTC_LIB
>> 92 select SYSCTL_EXCEPTION_TRACE
>> 93 select VIRT_TO_BUS
>> 94
>> 95 menu "Machine selection"
>> 96
>> 97 choice
>> 98 prompt "System type"
>> 99 default MIPS_GENERIC
>> 100
>> 101 config MIPS_GENERIC
>> 102 bool "Generic board-agnostic MIPS kernel"
>> 103 select BOOT_RAW
>> 104 select BUILTIN_DTB
>> 105 select CEVT_R4K
>> 106 select CLKSRC_MIPS_GIC
>> 107 select COMMON_CLK
>> 108 select CPU_MIPSR2_IRQ_EI
>> 109 select CPU_MIPSR2_IRQ_VI
>> 110 select CSRC_R4K
>> 111 select DMA_PERDEV_COHERENT
>> 112 select HAVE_PCI
>> 113 select IRQ_MIPS_CPU
>> 114 select MIPS_AUTO_PFN_OFFSET
>> 115 select MIPS_CPU_SCACHE
>> 116 select MIPS_GIC
>> 117 select MIPS_L1_CACHE_SHIFT_7
>> 118 select NO_EXCEPT_FILL
>> 119 select PCI_DRIVERS_GENERIC
>> 120 select SMP_UP if SMP
>> 121 select SWAP_IO_SPACE
>> 122 select SYS_HAS_CPU_MIPS32_R1
>> 123 select SYS_HAS_CPU_MIPS32_R2
>> 124 select SYS_HAS_CPU_MIPS32_R6
>> 125 select SYS_HAS_CPU_MIPS64_R1
>> 126 select SYS_HAS_CPU_MIPS64_R2
>> 127 select SYS_HAS_CPU_MIPS64_R6
>> 128 select SYS_SUPPORTS_32BIT_KERNEL
>> 129 select SYS_SUPPORTS_64BIT_KERNEL
>> 130 select SYS_SUPPORTS_BIG_ENDIAN
>> 131 select SYS_SUPPORTS_HIGHMEM
>> 132 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 133 select SYS_SUPPORTS_MICROMIPS
>> 134 select SYS_SUPPORTS_MIPS16
>> 135 select SYS_SUPPORTS_MIPS_CPS
>> 136 select SYS_SUPPORTS_MULTITHREADING
>> 137 select SYS_SUPPORTS_RELOCATABLE
>> 138 select SYS_SUPPORTS_SMARTMIPS
>> 139 select UHI_BOOT
>> 140 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 141 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 142 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 143 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 144 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 145 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 146 select USE_OF
>> 147 help
>> 148 Select this to build a kernel which aims to support multiple boards,
>> 149 generally using a flattened device tree passed from the bootloader
>> 150 using the boot protocol defined in the UHI (Unified Hosting
>> 151 Interface) specification.
>> 152
>> 153 config MIPS_ALCHEMY
>> 154 bool "Alchemy processor based machines"
>> 155 select PHYS_ADDR_T_64BIT
>> 156 select CEVT_R4K
>> 157 select CSRC_R4K
>> 158 select IRQ_MIPS_CPU
>> 159 select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
>> 160 select SYS_HAS_CPU_MIPS32_R1
>> 161 select SYS_SUPPORTS_32BIT_KERNEL
>> 162 select SYS_SUPPORTS_APM_EMULATION
>> 163 select GPIOLIB
>> 164 select SYS_SUPPORTS_ZBOOT
>> 165 select COMMON_CLK
>> 166
>> 167 config AR7
>> 168 bool "Texas Instruments AR7"
>> 169 select BOOT_ELF32
>> 170 select DMA_NONCOHERENT
>> 171 select CEVT_R4K
>> 172 select CSRC_R4K
>> 173 select IRQ_MIPS_CPU
>> 174 select NO_EXCEPT_FILL
>> 175 select SWAP_IO_SPACE
>> 176 select SYS_HAS_CPU_MIPS32_R1
>> 177 select SYS_HAS_EARLY_PRINTK
>> 178 select SYS_SUPPORTS_32BIT_KERNEL
>> 179 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 180 select SYS_SUPPORTS_MIPS16
>> 181 select SYS_SUPPORTS_ZBOOT_UART16550
>> 182 select GPIOLIB
>> 183 select VLYNQ
>> 184 select HAVE_CLK
>> 185 help
>> 186 Support for the Texas Instruments AR7 System-on-a-Chip
>> 187 family: TNETD7100, 7200 and 7300.
>> 188
>> 189 config ATH25
>> 190 bool "Atheros AR231x/AR531x SoC support"
>> 191 select CEVT_R4K
>> 192 select CSRC_R4K
>> 193 select DMA_NONCOHERENT
>> 194 select IRQ_MIPS_CPU
>> 195 select IRQ_DOMAIN
>> 196 select SYS_HAS_CPU_MIPS32_R1
>> 197 select SYS_SUPPORTS_BIG_ENDIAN
>> 198 select SYS_SUPPORTS_32BIT_KERNEL
>> 199 select SYS_HAS_EARLY_PRINTK
>> 200 help
>> 201 Support for Atheros AR231x and Atheros AR531x based boards
>> 202
>> 203 config ATH79
>> 204 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 205 select ARCH_HAS_RESET_CONTROLLER
>> 206 select BOOT_RAW
>> 207 select CEVT_R4K
>> 208 select CSRC_R4K
>> 209 select DMA_NONCOHERENT
>> 210 select GPIOLIB
>> 211 select PINCTRL
>> 212 select HAVE_CLK
>> 213 select COMMON_CLK
>> 214 select CLKDEV_LOOKUP
>> 215 select IRQ_MIPS_CPU
>> 216 select SYS_HAS_CPU_MIPS32_R2
>> 217 select SYS_HAS_EARLY_PRINTK
>> 218 select SYS_SUPPORTS_32BIT_KERNEL
>> 219 select SYS_SUPPORTS_BIG_ENDIAN
>> 220 select SYS_SUPPORTS_MIPS16
>> 221 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 222 select USE_OF
>> 223 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 224 help
>> 225 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 226
>> 227 config BMIPS_GENERIC
>> 228 bool "Broadcom Generic BMIPS kernel"
>> 229 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 230 select ARCH_HAS_PHYS_TO_DMA
>> 231 select BOOT_RAW
>> 232 select NO_EXCEPT_FILL
>> 233 select USE_OF
>> 234 select CEVT_R4K
>> 235 select CSRC_R4K
>> 236 select SYNC_R4K
>> 237 select COMMON_CLK
>> 238 select BCM6345_L1_IRQ
>> 239 select BCM7038_L1_IRQ
>> 240 select BCM7120_L2_IRQ
>> 241 select BRCMSTB_L2_IRQ
>> 242 select IRQ_MIPS_CPU
>> 243 select DMA_NONCOHERENT
>> 244 select SYS_SUPPORTS_32BIT_KERNEL
>> 245 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 246 select SYS_SUPPORTS_BIG_ENDIAN
>> 247 select SYS_SUPPORTS_HIGHMEM
>> 248 select SYS_HAS_CPU_BMIPS32_3300
>> 249 select SYS_HAS_CPU_BMIPS4350
>> 250 select SYS_HAS_CPU_BMIPS4380
>> 251 select SYS_HAS_CPU_BMIPS5000
>> 252 select SWAP_IO_SPACE
>> 253 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 254 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 255 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 256 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 257 select HARDIRQS_SW_RESEND
>> 258 help
>> 259 Build a generic DT-based kernel image that boots on select
>> 260 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
>> 261 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
>> 262 must be set appropriately for your board.
>> 263
>> 264 config BCM47XX
>> 265 bool "Broadcom BCM47XX based boards"
>> 266 select BOOT_RAW
>> 267 select CEVT_R4K
>> 268 select CSRC_R4K
>> 269 select DMA_NONCOHERENT
>> 270 select HAVE_PCI
>> 271 select IRQ_MIPS_CPU
>> 272 select SYS_HAS_CPU_MIPS32_R1
>> 273 select NO_EXCEPT_FILL
>> 274 select SYS_SUPPORTS_32BIT_KERNEL
>> 275 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 276 select SYS_SUPPORTS_MIPS16
>> 277 select SYS_SUPPORTS_ZBOOT
>> 278 select SYS_HAS_EARLY_PRINTK
>> 279 select USE_GENERIC_EARLY_PRINTK_8250
>> 280 select GPIOLIB
>> 281 select LEDS_GPIO_REGISTER
>> 282 select BCM47XX_NVRAM
>> 283 select BCM47XX_SPROM
>> 284 select BCM47XX_SSB if !BCM47XX_BCMA
>> 285 help
>> 286 Support for BCM47XX based boards
>> 287
>> 288 config BCM63XX
>> 289 bool "Broadcom BCM63XX based boards"
>> 290 select BOOT_RAW
>> 291 select CEVT_R4K
>> 292 select CSRC_R4K
>> 293 select SYNC_R4K
>> 294 select DMA_NONCOHERENT
>> 295 select IRQ_MIPS_CPU
>> 296 select SYS_SUPPORTS_32BIT_KERNEL
>> 297 select SYS_SUPPORTS_BIG_ENDIAN
>> 298 select SYS_HAS_EARLY_PRINTK
>> 299 select SWAP_IO_SPACE
>> 300 select GPIOLIB
>> 301 select HAVE_CLK
>> 302 select MIPS_L1_CACHE_SHIFT_4
>> 303 select CLKDEV_LOOKUP
>> 304 help
>> 305 Support for BCM63XX based boards
>> 306
>> 307 config MIPS_COBALT
>> 308 bool "Cobalt Server"
>> 309 select CEVT_R4K
>> 310 select CSRC_R4K
>> 311 select CEVT_GT641XX
>> 312 select DMA_NONCOHERENT
>> 313 select FORCE_PCI
>> 314 select I8253
>> 315 select I8259
>> 316 select IRQ_MIPS_CPU
>> 317 select IRQ_GT641XX
>> 318 select PCI_GT64XXX_PCI0
>> 319 select SYS_HAS_CPU_NEVADA
>> 320 select SYS_HAS_EARLY_PRINTK
>> 321 select SYS_SUPPORTS_32BIT_KERNEL
>> 322 select SYS_SUPPORTS_64BIT_KERNEL
>> 323 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 324 select USE_GENERIC_EARLY_PRINTK_8250
>> 325
>> 326 config MACH_DECSTATION
>> 327 bool "DECstations"
>> 328 select BOOT_ELF32
>> 329 select CEVT_DS1287
>> 330 select CEVT_R4K if CPU_R4X00
>> 331 select CSRC_IOASIC
>> 332 select CSRC_R4K if CPU_R4X00
>> 333 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 334 select CPU_R4000_WORKAROUNDS if 64BIT
>> 335 select CPU_R4400_WORKAROUNDS if 64BIT
>> 336 select DMA_NONCOHERENT
>> 337 select NO_IOPORT_MAP
>> 338 select IRQ_MIPS_CPU
>> 339 select SYS_HAS_CPU_R3000
>> 340 select SYS_HAS_CPU_R4X00
>> 341 select SYS_SUPPORTS_32BIT_KERNEL
>> 342 select SYS_SUPPORTS_64BIT_KERNEL
>> 343 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 344 select SYS_SUPPORTS_128HZ
>> 345 select SYS_SUPPORTS_256HZ
>> 346 select SYS_SUPPORTS_1024HZ
>> 347 select MIPS_L1_CACHE_SHIFT_4
>> 348 help
>> 349 This enables support for DEC's MIPS based workstations. For details
>> 350 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 351 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 352
>> 353 If you have one of the following DECstation Models you definitely
>> 354 want to choose R4xx0 for the CPU Type:
>> 355
>> 356 DECstation 5000/50
>> 357 DECstation 5000/150
>> 358 DECstation 5000/260
>> 359 DECsystem 5900/260
>> 360
>> 361 otherwise choose R3000.
>> 362
>> 363 config MACH_JAZZ
>> 364 bool "Jazz family of machines"
>> 365 select ARC_MEMORY
>> 366 select ARC_PROMLIB
>> 367 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 368 select ARCH_MIGHT_HAVE_PC_SERIO
>> 369 select FW_ARC
>> 370 select FW_ARC32
>> 371 select ARCH_MAY_HAVE_PC_FDC
>> 372 select CEVT_R4K
>> 373 select CSRC_R4K
>> 374 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 375 select GENERIC_ISA_DMA
>> 376 select HAVE_PCSPKR_PLATFORM
>> 377 select IRQ_MIPS_CPU
>> 378 select I8253
>> 379 select I8259
>> 380 select ISA
>> 381 select SYS_HAS_CPU_R4X00
>> 382 select SYS_SUPPORTS_32BIT_KERNEL
>> 383 select SYS_SUPPORTS_64BIT_KERNEL
>> 384 select SYS_SUPPORTS_100HZ
>> 385 help
>> 386 This a family of machines based on the MIPS R4030 chipset which was
>> 387 used by several vendors to build RISC/os and Windows NT workstations.
>> 388 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 389 Olivetti M700-10 workstations.
>> 390
>> 391 config MACH_INGENIC
>> 392 bool "Ingenic SoC based machines"
>> 393 select SYS_SUPPORTS_32BIT_KERNEL
>> 394 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 395 select SYS_SUPPORTS_ZBOOT_UART16550
>> 396 select CPU_SUPPORTS_HUGEPAGES
>> 397 select DMA_NONCOHERENT
>> 398 select IRQ_MIPS_CPU
>> 399 select PINCTRL
>> 400 select GPIOLIB
>> 401 select COMMON_CLK
>> 402 select GENERIC_IRQ_CHIP
>> 403 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 404 select USE_OF
>> 405
>> 406 config LANTIQ
>> 407 bool "Lantiq based platforms"
>> 408 select DMA_NONCOHERENT
>> 409 select IRQ_MIPS_CPU
>> 410 select CEVT_R4K
>> 411 select CSRC_R4K
>> 412 select SYS_HAS_CPU_MIPS32_R1
>> 413 select SYS_HAS_CPU_MIPS32_R2
>> 414 select SYS_SUPPORTS_BIG_ENDIAN
>> 415 select SYS_SUPPORTS_32BIT_KERNEL
>> 416 select SYS_SUPPORTS_MIPS16
>> 417 select SYS_SUPPORTS_MULTITHREADING
>> 418 select SYS_SUPPORTS_VPE_LOADER
>> 419 select SYS_HAS_EARLY_PRINTK
>> 420 select GPIOLIB
>> 421 select SWAP_IO_SPACE
>> 422 select BOOT_RAW
>> 423 select CLKDEV_LOOKUP
>> 424 select USE_OF
>> 425 select PINCTRL
>> 426 select PINCTRL_LANTIQ
>> 427 select ARCH_HAS_RESET_CONTROLLER
>> 428 select RESET_CONTROLLER
>> 429
>> 430 config LASAT
>> 431 bool "LASAT Networks platforms"
>> 432 select CEVT_R4K
>> 433 select CRC32
>> 434 select CSRC_R4K
>> 435 select DMA_NONCOHERENT
>> 436 select SYS_HAS_EARLY_PRINTK
>> 437 select HAVE_PCI
>> 438 select IRQ_MIPS_CPU
>> 439 select PCI_GT64XXX_PCI0
>> 440 select MIPS_NILE4
>> 441 select R5000_CPU_SCACHE
>> 442 select SYS_HAS_CPU_R5000
>> 443 select SYS_SUPPORTS_32BIT_KERNEL
>> 444 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
>> 445 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 446
>> 447 config MACH_LOONGSON32
>> 448 bool "Loongson 32-bit family of machines"
>> 449 select SYS_SUPPORTS_ZBOOT
>> 450 help
>> 451 This enables support for the Loongson-1 family of machines.
>> 452
>> 453 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 454 the Institute of Computing Technology (ICT), Chinese Academy of
>> 455 Sciences (CAS).
>> 456
>> 457 config MACH_LOONGSON2EF
>> 458 bool "Loongson-2E/F family of machines"
>> 459 select SYS_SUPPORTS_ZBOOT
>> 460 help
>> 461 This enables the support of early Loongson-2E/F family of machines.
>> 462
>> 463 config MACH_LOONGSON64
>> 464 bool "Loongson 64-bit family of machines"
>> 465 select ARCH_SPARSEMEM_ENABLE
>> 466 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 467 select ARCH_MIGHT_HAVE_PC_SERIO
>> 468 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 469 select BOOT_ELF32
>> 470 select BOARD_SCACHE
>> 471 select CSRC_R4K
>> 472 select CEVT_R4K
>> 473 select CPU_HAS_WB
>> 474 select FORCE_PCI
>> 475 select ISA
>> 476 select I8259
>> 477 select IRQ_MIPS_CPU
>> 478 select NR_CPUS_DEFAULT_4
>> 479 select USE_GENERIC_EARLY_PRINTK_8250
>> 480 select SYS_HAS_CPU_LOONGSON64
>> 481 select SYS_HAS_EARLY_PRINTK
>> 482 select SYS_SUPPORTS_SMP
>> 483 select SYS_SUPPORTS_HOTPLUG_CPU
>> 484 select SYS_SUPPORTS_NUMA
>> 485 select SYS_SUPPORTS_64BIT_KERNEL
>> 486 select SYS_SUPPORTS_HIGHMEM
>> 487 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 488 select SYS_SUPPORTS_ZBOOT
>> 489 select LOONGSON_MC146818
>> 490 select ZONE_DMA32
>> 491 select NUMA
>> 492 help
>> 493 This enables the support of Loongson-2/3 family of machines.
>> 494
>> 495 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 496 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 497 and Loongson-2F which will be removed), developed by the Institute
>> 498 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 499
>> 500 config MACH_PISTACHIO
>> 501 bool "IMG Pistachio SoC based boards"
>> 502 select BOOT_ELF32
>> 503 select BOOT_RAW
>> 504 select CEVT_R4K
>> 505 select CLKSRC_MIPS_GIC
>> 506 select COMMON_CLK
>> 507 select CSRC_R4K
>> 508 select DMA_NONCOHERENT
>> 509 select GPIOLIB
>> 510 select IRQ_MIPS_CPU
>> 511 select MFD_SYSCON
>> 512 select MIPS_CPU_SCACHE
>> 513 select MIPS_GIC
>> 514 select PINCTRL
>> 515 select REGULATOR
>> 516 select SYS_HAS_CPU_MIPS32_R2
>> 517 select SYS_SUPPORTS_32BIT_KERNEL
>> 518 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 519 select SYS_SUPPORTS_MIPS_CPS
>> 520 select SYS_SUPPORTS_MULTITHREADING
>> 521 select SYS_SUPPORTS_RELOCATABLE
>> 522 select SYS_SUPPORTS_ZBOOT
>> 523 select SYS_HAS_EARLY_PRINTK
>> 524 select USE_GENERIC_EARLY_PRINTK_8250
>> 525 select USE_OF
>> 526 help
>> 527 This enables support for the IMG Pistachio SoC platform.
>> 528
>> 529 config MIPS_MALTA
>> 530 bool "MIPS Malta board"
>> 531 select ARCH_MAY_HAVE_PC_FDC
>> 532 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 533 select ARCH_MIGHT_HAVE_PC_SERIO
>> 534 select BOOT_ELF32
>> 535 select BOOT_RAW
>> 536 select BUILTIN_DTB
>> 537 select CEVT_R4K
>> 538 select CLKSRC_MIPS_GIC
>> 539 select COMMON_CLK
>> 540 select CSRC_R4K
>> 541 select DMA_MAYBE_COHERENT
>> 542 select GENERIC_ISA_DMA
>> 543 select HAVE_PCSPKR_PLATFORM
>> 544 select HAVE_PCI
>> 545 select I8253
>> 546 select I8259
>> 547 select IRQ_MIPS_CPU
>> 548 select MIPS_BONITO64
>> 549 select MIPS_CPU_SCACHE
>> 550 select MIPS_GIC
>> 551 select MIPS_L1_CACHE_SHIFT_6
>> 552 select MIPS_MSC
>> 553 select PCI_GT64XXX_PCI0
>> 554 select SMP_UP if SMP
>> 555 select SWAP_IO_SPACE
>> 556 select SYS_HAS_CPU_MIPS32_R1
>> 557 select SYS_HAS_CPU_MIPS32_R2
>> 558 select SYS_HAS_CPU_MIPS32_R3_5
>> 559 select SYS_HAS_CPU_MIPS32_R5
>> 560 select SYS_HAS_CPU_MIPS32_R6
>> 561 select SYS_HAS_CPU_MIPS64_R1
>> 562 select SYS_HAS_CPU_MIPS64_R2
>> 563 select SYS_HAS_CPU_MIPS64_R6
>> 564 select SYS_HAS_CPU_NEVADA
>> 565 select SYS_HAS_CPU_RM7000
>> 566 select SYS_SUPPORTS_32BIT_KERNEL
>> 567 select SYS_SUPPORTS_64BIT_KERNEL
>> 568 select SYS_SUPPORTS_BIG_ENDIAN
>> 569 select SYS_SUPPORTS_HIGHMEM
>> 570 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 571 select SYS_SUPPORTS_MICROMIPS
>> 572 select SYS_SUPPORTS_MIPS16
>> 573 select SYS_SUPPORTS_MIPS_CMP
>> 574 select SYS_SUPPORTS_MIPS_CPS
>> 575 select SYS_SUPPORTS_MULTITHREADING
>> 576 select SYS_SUPPORTS_RELOCATABLE
>> 577 select SYS_SUPPORTS_SMARTMIPS
>> 578 select SYS_SUPPORTS_VPE_LOADER
>> 579 select SYS_SUPPORTS_ZBOOT
>> 580 select USE_OF
>> 581 select ZONE_DMA32 if 64BIT
>> 582 help
>> 583 This enables support for the MIPS Technologies Malta evaluation
>> 584 board.
>> 585
>> 586 config MACH_PIC32
>> 587 bool "Microchip PIC32 Family"
>> 588 help
>> 589 This enables support for the Microchip PIC32 family of platforms.
>> 590
>> 591 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 592 microcontrollers.
>> 593
>> 594 config NEC_MARKEINS
>> 595 bool "NEC EMMA2RH Mark-eins board"
>> 596 select SOC_EMMA2RH
>> 597 select HAVE_PCI
>> 598 help
>> 599 This enables support for the NEC Electronics Mark-eins boards.
>> 600
>> 601 config MACH_VR41XX
>> 602 bool "NEC VR4100 series based machines"
>> 603 select CEVT_R4K
>> 604 select CSRC_R4K
>> 605 select SYS_HAS_CPU_VR41XX
>> 606 select SYS_SUPPORTS_MIPS16
>> 607 select GPIOLIB
>> 608
>> 609 config NXP_STB220
>> 610 bool "NXP STB220 board"
>> 611 select SOC_PNX833X
>> 612 help
>> 613 Support for NXP Semiconductors STB220 Development Board.
>> 614
>> 615 config NXP_STB225
>> 616 bool "NXP 225 board"
>> 617 select SOC_PNX833X
>> 618 select SOC_PNX8335
>> 619 help
>> 620 Support for NXP Semiconductors STB225 Development Board.
>> 621
>> 622 config PMC_MSP
>> 623 bool "PMC-Sierra MSP chipsets"
>> 624 select CEVT_R4K
>> 625 select CSRC_R4K
>> 626 select DMA_NONCOHERENT
>> 627 select SWAP_IO_SPACE
>> 628 select NO_EXCEPT_FILL
>> 629 select BOOT_RAW
>> 630 select SYS_HAS_CPU_MIPS32_R1
>> 631 select SYS_HAS_CPU_MIPS32_R2
>> 632 select SYS_SUPPORTS_32BIT_KERNEL
>> 633 select SYS_SUPPORTS_BIG_ENDIAN
>> 634 select SYS_SUPPORTS_MIPS16
>> 635 select IRQ_MIPS_CPU
>> 636 select SERIAL_8250
>> 637 select SERIAL_8250_CONSOLE
>> 638 select USB_EHCI_BIG_ENDIAN_MMIO
>> 639 select USB_EHCI_BIG_ENDIAN_DESC
>> 640 help
>> 641 This adds support for the PMC-Sierra family of Multi-Service
>> 642 Processor System-On-A-Chips. These parts include a number
>> 643 of integrated peripherals, interfaces and DSPs in addition to
>> 644 a variety of MIPS cores.
>> 645
>> 646 config RALINK
>> 647 bool "Ralink based machines"
>> 648 select CEVT_R4K
>> 649 select CSRC_R4K
>> 650 select BOOT_RAW
>> 651 select DMA_NONCOHERENT
>> 652 select IRQ_MIPS_CPU
>> 653 select USE_OF
>> 654 select SYS_HAS_CPU_MIPS32_R1
>> 655 select SYS_HAS_CPU_MIPS32_R2
>> 656 select SYS_SUPPORTS_32BIT_KERNEL
>> 657 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 658 select SYS_SUPPORTS_MIPS16
>> 659 select SYS_HAS_EARLY_PRINTK
>> 660 select CLKDEV_LOOKUP
>> 661 select ARCH_HAS_RESET_CONTROLLER
>> 662 select RESET_CONTROLLER
>> 663
>> 664 config SGI_IP22
>> 665 bool "SGI IP22 (Indy/Indigo2)"
>> 666 select ARC_MEMORY
>> 667 select ARC_PROMLIB
>> 668 select FW_ARC
>> 669 select FW_ARC32
>> 670 select ARCH_MIGHT_HAVE_PC_SERIO
>> 671 select BOOT_ELF32
>> 672 select CEVT_R4K
>> 673 select CSRC_R4K
>> 674 select DEFAULT_SGI_PARTITION
>> 675 select DMA_NONCOHERENT
>> 676 select HAVE_EISA
>> 677 select I8253
>> 678 select I8259
>> 679 select IP22_CPU_SCACHE
>> 680 select IRQ_MIPS_CPU
>> 681 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 682 select SGI_HAS_I8042
>> 683 select SGI_HAS_INDYDOG
>> 684 select SGI_HAS_HAL2
>> 685 select SGI_HAS_SEEQ
>> 686 select SGI_HAS_WD93
>> 687 select SGI_HAS_ZILOG
>> 688 select SWAP_IO_SPACE
>> 689 select SYS_HAS_CPU_R4X00
>> 690 select SYS_HAS_CPU_R5000
>> 691 select SYS_HAS_EARLY_PRINTK
>> 692 select SYS_SUPPORTS_32BIT_KERNEL
>> 693 select SYS_SUPPORTS_64BIT_KERNEL
>> 694 select SYS_SUPPORTS_BIG_ENDIAN
>> 695 select MIPS_L1_CACHE_SHIFT_7
>> 696 help
>> 697 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 698 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 699 that runs on these, say Y here.
>> 700
>> 701 config SGI_IP27
>> 702 bool "SGI IP27 (Origin200/2000)"
>> 703 select ARCH_HAS_PHYS_TO_DMA
>> 704 select ARCH_SPARSEMEM_ENABLE
>> 705 select FW_ARC
>> 706 select FW_ARC64
>> 707 select ARC_CMDLINE_ONLY
>> 708 select BOOT_ELF64
>> 709 select DEFAULT_SGI_PARTITION
>> 710 select SYS_HAS_EARLY_PRINTK
>> 711 select HAVE_PCI
>> 712 select IRQ_MIPS_CPU
>> 713 select IRQ_DOMAIN_HIERARCHY
>> 714 select NR_CPUS_DEFAULT_64
>> 715 select PCI_DRIVERS_GENERIC
>> 716 select PCI_XTALK_BRIDGE
>> 717 select SYS_HAS_CPU_R10000
>> 718 select SYS_SUPPORTS_64BIT_KERNEL
>> 719 select SYS_SUPPORTS_BIG_ENDIAN
>> 720 select SYS_SUPPORTS_NUMA
>> 721 select SYS_SUPPORTS_SMP
>> 722 select MIPS_L1_CACHE_SHIFT_7
>> 723 help
>> 724 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 725 workstations. To compile a Linux kernel that runs on these, say Y
>> 726 here.
>> 727
>> 728 config SGI_IP28
>> 729 bool "SGI IP28 (Indigo2 R10k)"
>> 730 select ARC_MEMORY
>> 731 select ARC_PROMLIB
>> 732 select FW_ARC
>> 733 select FW_ARC64
>> 734 select ARCH_MIGHT_HAVE_PC_SERIO
>> 735 select BOOT_ELF64
>> 736 select CEVT_R4K
>> 737 select CSRC_R4K
>> 738 select DEFAULT_SGI_PARTITION
>> 739 select DMA_NONCOHERENT
>> 740 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 741 select IRQ_MIPS_CPU
>> 742 select HAVE_EISA
>> 743 select I8253
>> 744 select I8259
>> 745 select SGI_HAS_I8042
>> 746 select SGI_HAS_INDYDOG
>> 747 select SGI_HAS_HAL2
>> 748 select SGI_HAS_SEEQ
>> 749 select SGI_HAS_WD93
>> 750 select SGI_HAS_ZILOG
>> 751 select SWAP_IO_SPACE
>> 752 select SYS_HAS_CPU_R10000
>> 753 select SYS_HAS_EARLY_PRINTK
>> 754 select SYS_SUPPORTS_64BIT_KERNEL
>> 755 select SYS_SUPPORTS_BIG_ENDIAN
>> 756 select MIPS_L1_CACHE_SHIFT_7
>> 757 help
>> 758 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 759 kernel that runs on these, say Y here.
>> 760
>> 761 config SGI_IP30
>> 762 bool "SGI IP30 (Octane/Octane2)"
>> 763 select ARCH_HAS_PHYS_TO_DMA
>> 764 select FW_ARC
>> 765 select FW_ARC64
>> 766 select BOOT_ELF64
>> 767 select CEVT_R4K
>> 768 select CSRC_R4K
>> 769 select SYNC_R4K if SMP
>> 770 select ZONE_DMA32
>> 771 select HAVE_PCI
>> 772 select IRQ_MIPS_CPU
>> 773 select IRQ_DOMAIN_HIERARCHY
>> 774 select NR_CPUS_DEFAULT_2
>> 775 select PCI_DRIVERS_GENERIC
>> 776 select PCI_XTALK_BRIDGE
>> 777 select SYS_HAS_EARLY_PRINTK
>> 778 select SYS_HAS_CPU_R10000
>> 779 select SYS_SUPPORTS_64BIT_KERNEL
>> 780 select SYS_SUPPORTS_BIG_ENDIAN
>> 781 select SYS_SUPPORTS_SMP
>> 782 select MIPS_L1_CACHE_SHIFT_7
>> 783 select ARC_MEMORY
>> 784 help
>> 785 These are the SGI Octane and Octane2 graphics workstations. To
>> 786 compile a Linux kernel that runs on these, say Y here.
>> 787
>> 788 config SGI_IP32
>> 789 bool "SGI IP32 (O2)"
>> 790 select ARC_MEMORY
>> 791 select ARC_PROMLIB
>> 792 select ARCH_HAS_PHYS_TO_DMA
>> 793 select FW_ARC
>> 794 select FW_ARC32
>> 795 select BOOT_ELF32
>> 796 select CEVT_R4K
>> 797 select CSRC_R4K
>> 798 select DMA_NONCOHERENT
>> 799 select HAVE_PCI
>> 800 select IRQ_MIPS_CPU
>> 801 select R5000_CPU_SCACHE
>> 802 select RM7000_CPU_SCACHE
>> 803 select SYS_HAS_CPU_R5000
>> 804 select SYS_HAS_CPU_R10000 if BROKEN
>> 805 select SYS_HAS_CPU_RM7000
>> 806 select SYS_HAS_CPU_NEVADA
>> 807 select SYS_SUPPORTS_64BIT_KERNEL
>> 808 select SYS_SUPPORTS_BIG_ENDIAN
>> 809 help
>> 810 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 811
>> 812 config SIBYTE_CRHINE
>> 813 bool "Sibyte BCM91120C-CRhine"
>> 814 select BOOT_ELF32
>> 815 select SIBYTE_BCM1120
>> 816 select SWAP_IO_SPACE
>> 817 select SYS_HAS_CPU_SB1
>> 818 select SYS_SUPPORTS_BIG_ENDIAN
>> 819 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 820
>> 821 config SIBYTE_CARMEL
>> 822 bool "Sibyte BCM91120x-Carmel"
>> 823 select BOOT_ELF32
>> 824 select SIBYTE_BCM1120
>> 825 select SWAP_IO_SPACE
>> 826 select SYS_HAS_CPU_SB1
>> 827 select SYS_SUPPORTS_BIG_ENDIAN
>> 828 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 829
>> 830 config SIBYTE_CRHONE
>> 831 bool "Sibyte BCM91125C-CRhone"
>> 832 select BOOT_ELF32
>> 833 select SIBYTE_BCM1125
>> 834 select SWAP_IO_SPACE
>> 835 select SYS_HAS_CPU_SB1
>> 836 select SYS_SUPPORTS_BIG_ENDIAN
>> 837 select SYS_SUPPORTS_HIGHMEM
>> 838 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 839
>> 840 config SIBYTE_RHONE
>> 841 bool "Sibyte BCM91125E-Rhone"
>> 842 select BOOT_ELF32
>> 843 select SIBYTE_BCM1125H
>> 844 select SWAP_IO_SPACE
>> 845 select SYS_HAS_CPU_SB1
>> 846 select SYS_SUPPORTS_BIG_ENDIAN
>> 847 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 848
>> 849 config SIBYTE_SWARM
>> 850 bool "Sibyte BCM91250A-SWARM"
>> 851 select BOOT_ELF32
>> 852 select HAVE_PATA_PLATFORM
>> 853 select SIBYTE_SB1250
>> 854 select SWAP_IO_SPACE
>> 855 select SYS_HAS_CPU_SB1
>> 856 select SYS_SUPPORTS_BIG_ENDIAN
>> 857 select SYS_SUPPORTS_HIGHMEM
>> 858 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 859 select ZONE_DMA32 if 64BIT
>> 860 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 861
>> 862 config SIBYTE_LITTLESUR
>> 863 bool "Sibyte BCM91250C2-LittleSur"
>> 864 select BOOT_ELF32
>> 865 select HAVE_PATA_PLATFORM
>> 866 select SIBYTE_SB1250
>> 867 select SWAP_IO_SPACE
>> 868 select SYS_HAS_CPU_SB1
>> 869 select SYS_SUPPORTS_BIG_ENDIAN
>> 870 select SYS_SUPPORTS_HIGHMEM
>> 871 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 872 select ZONE_DMA32 if 64BIT
>> 873
>> 874 config SIBYTE_SENTOSA
>> 875 bool "Sibyte BCM91250E-Sentosa"
>> 876 select BOOT_ELF32
>> 877 select SIBYTE_SB1250
>> 878 select SWAP_IO_SPACE
>> 879 select SYS_HAS_CPU_SB1
>> 880 select SYS_SUPPORTS_BIG_ENDIAN
>> 881 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 882 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 883
>> 884 config SIBYTE_BIGSUR
>> 885 bool "Sibyte BCM91480B-BigSur"
>> 886 select BOOT_ELF32
>> 887 select NR_CPUS_DEFAULT_4
>> 888 select SIBYTE_BCM1x80
>> 889 select SWAP_IO_SPACE
>> 890 select SYS_HAS_CPU_SB1
>> 891 select SYS_SUPPORTS_BIG_ENDIAN
>> 892 select SYS_SUPPORTS_HIGHMEM
>> 893 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 894 select ZONE_DMA32 if 64BIT
>> 895 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 896
>> 897 config SNI_RM
>> 898 bool "SNI RM200/300/400"
>> 899 select ARC_MEMORY
>> 900 select ARC_PROMLIB
>> 901 select FW_ARC if CPU_LITTLE_ENDIAN
>> 902 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 903 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 904 select ARCH_MAY_HAVE_PC_FDC
>> 905 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 906 select ARCH_MIGHT_HAVE_PC_SERIO
>> 907 select BOOT_ELF32
>> 908 select CEVT_R4K
>> 909 select CSRC_R4K
>> 910 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 911 select DMA_NONCOHERENT
>> 912 select GENERIC_ISA_DMA
>> 913 select HAVE_EISA
>> 914 select HAVE_PCSPKR_PLATFORM
>> 915 select HAVE_PCI
>> 916 select IRQ_MIPS_CPU
>> 917 select I8253
>> 918 select I8259
>> 919 select ISA
>> 920 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 921 select SYS_HAS_CPU_R4X00
>> 922 select SYS_HAS_CPU_R5000
>> 923 select SYS_HAS_CPU_R10000
>> 924 select R5000_CPU_SCACHE
>> 925 select SYS_HAS_EARLY_PRINTK
>> 926 select SYS_SUPPORTS_32BIT_KERNEL
>> 927 select SYS_SUPPORTS_64BIT_KERNEL
>> 928 select SYS_SUPPORTS_BIG_ENDIAN
>> 929 select SYS_SUPPORTS_HIGHMEM
>> 930 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 931 help
>> 932 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 933 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 934 Technology and now in turn merged with Fujitsu. Say Y here to
>> 935 support this machine type.
>> 936
>> 937 config MACH_TX39XX
>> 938 bool "Toshiba TX39 series based machines"
>> 939
>> 940 config MACH_TX49XX
>> 941 bool "Toshiba TX49 series based machines"
>> 942
>> 943 config MIKROTIK_RB532
>> 944 bool "Mikrotik RB532 boards"
>> 945 select CEVT_R4K
>> 946 select CSRC_R4K
>> 947 select DMA_NONCOHERENT
>> 948 select HAVE_PCI
>> 949 select IRQ_MIPS_CPU
>> 950 select SYS_HAS_CPU_MIPS32_R1
>> 951 select SYS_SUPPORTS_32BIT_KERNEL
>> 952 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 953 select SWAP_IO_SPACE
>> 954 select BOOT_RAW
>> 955 select GPIOLIB
>> 956 select MIPS_L1_CACHE_SHIFT_4
>> 957 help
>> 958 Support the Mikrotik(tm) RouterBoard 532 series,
>> 959 based on the IDT RC32434 SoC.
>> 960
>> 961 config CAVIUM_OCTEON_SOC
>> 962 bool "Cavium Networks Octeon SoC based boards"
>> 963 select CEVT_R4K
>> 964 select ARCH_HAS_PHYS_TO_DMA
>> 965 select HAVE_RAPIDIO
>> 966 select PHYS_ADDR_T_64BIT
>> 967 select SYS_SUPPORTS_64BIT_KERNEL
>> 968 select SYS_SUPPORTS_BIG_ENDIAN
>> 969 select EDAC_SUPPORT
>> 970 select EDAC_ATOMIC_SCRUB
>> 971 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 972 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 973 select SYS_HAS_EARLY_PRINTK
>> 974 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 975 select HAVE_PCI
>> 976 select ZONE_DMA32
>> 977 select HOLES_IN_ZONE
>> 978 select GPIOLIB
>> 979 select USE_OF
>> 980 select ARCH_SPARSEMEM_ENABLE
>> 981 select SYS_SUPPORTS_SMP
>> 982 select NR_CPUS_DEFAULT_64
>> 983 select MIPS_NR_CPU_NR_MAP_1024
>> 984 select BUILTIN_DTB
>> 985 select MTD_COMPLEX_MAPPINGS
>> 986 select SWIOTLB
>> 987 select SYS_SUPPORTS_RELOCATABLE
>> 988 help
>> 989 This option supports all of the Octeon reference boards from Cavium
>> 990 Networks. It builds a kernel that dynamically determines the Octeon
>> 991 CPU type and supports all known board reference implementations.
>> 992 Some of the supported boards are:
>> 993 EBT3000
>> 994 EBH3000
>> 995 EBH3100
>> 996 Thunder
>> 997 Kodama
>> 998 Hikari
>> 999 Say Y here for most Octeon reference boards.
>> 1000
>> 1001 config NLM_XLR_BOARD
>> 1002 bool "Netlogic XLR/XLS based systems"
>> 1003 select BOOT_ELF32
>> 1004 select NLM_COMMON
>> 1005 select SYS_HAS_CPU_XLR
>> 1006 select SYS_SUPPORTS_SMP
>> 1007 select HAVE_PCI
>> 1008 select SWAP_IO_SPACE
>> 1009 select SYS_SUPPORTS_32BIT_KERNEL
>> 1010 select SYS_SUPPORTS_64BIT_KERNEL
>> 1011 select PHYS_ADDR_T_64BIT
>> 1012 select SYS_SUPPORTS_BIG_ENDIAN
>> 1013 select SYS_SUPPORTS_HIGHMEM
>> 1014 select NR_CPUS_DEFAULT_32
>> 1015 select CEVT_R4K
>> 1016 select CSRC_R4K
>> 1017 select IRQ_MIPS_CPU
>> 1018 select ZONE_DMA32 if 64BIT
>> 1019 select SYNC_R4K
>> 1020 select SYS_HAS_EARLY_PRINTK
>> 1021 select SYS_SUPPORTS_ZBOOT
>> 1022 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1023 help
>> 1024 Support for systems based on Netlogic XLR and XLS processors.
>> 1025 Say Y here if you have a XLR or XLS based board.
>> 1026
>> 1027 config NLM_XLP_BOARD
>> 1028 bool "Netlogic XLP based systems"
>> 1029 select BOOT_ELF32
>> 1030 select NLM_COMMON
>> 1031 select SYS_HAS_CPU_XLP
>> 1032 select SYS_SUPPORTS_SMP
>> 1033 select HAVE_PCI
>> 1034 select SYS_SUPPORTS_32BIT_KERNEL
>> 1035 select SYS_SUPPORTS_64BIT_KERNEL
>> 1036 select PHYS_ADDR_T_64BIT
>> 1037 select GPIOLIB
>> 1038 select SYS_SUPPORTS_BIG_ENDIAN
>> 1039 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1040 select SYS_SUPPORTS_HIGHMEM
>> 1041 select NR_CPUS_DEFAULT_32
>> 1042 select CEVT_R4K
>> 1043 select CSRC_R4K
>> 1044 select IRQ_MIPS_CPU
>> 1045 select ZONE_DMA32 if 64BIT
>> 1046 select SYNC_R4K
>> 1047 select SYS_HAS_EARLY_PRINTK
>> 1048 select USE_OF
>> 1049 select SYS_SUPPORTS_ZBOOT
>> 1050 select SYS_SUPPORTS_ZBOOT_UART16550
>> 1051 help
>> 1052 This board is based on Netlogic XLP Processor.
>> 1053 Say Y here if you have a XLP based board.
>> 1054
>> 1055 config MIPS_PARAVIRT
>> 1056 bool "Para-Virtualized guest system"
>> 1057 select CEVT_R4K
>> 1058 select CSRC_R4K
>> 1059 select SYS_SUPPORTS_64BIT_KERNEL
>> 1060 select SYS_SUPPORTS_32BIT_KERNEL
>> 1061 select SYS_SUPPORTS_BIG_ENDIAN
>> 1062 select SYS_SUPPORTS_SMP
>> 1063 select NR_CPUS_DEFAULT_4
>> 1064 select SYS_HAS_EARLY_PRINTK
>> 1065 select SYS_HAS_CPU_MIPS32_R2
>> 1066 select SYS_HAS_CPU_MIPS64_R2
>> 1067 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 1068 select HAVE_PCI
>> 1069 select SWAP_IO_SPACE
60 help 1070 help
61 Xtensa processors are 32-bit RISC ma !! 1071 This option supports guest running under ????
62 primarily for embedded systems. The !! 1072
63 configurable and extensible. The Li !! 1073 endchoice
64 architecture supports all processor !! 1074
65 with reasonable minimum requirements !! 1075 source "arch/mips/alchemy/Kconfig"
66 a home page at <http://www.linux-xte !! 1076 source "arch/mips/ath25/Kconfig"
>> 1077 source "arch/mips/ath79/Kconfig"
>> 1078 source "arch/mips/bcm47xx/Kconfig"
>> 1079 source "arch/mips/bcm63xx/Kconfig"
>> 1080 source "arch/mips/bmips/Kconfig"
>> 1081 source "arch/mips/generic/Kconfig"
>> 1082 source "arch/mips/jazz/Kconfig"
>> 1083 source "arch/mips/jz4740/Kconfig"
>> 1084 source "arch/mips/lantiq/Kconfig"
>> 1085 source "arch/mips/lasat/Kconfig"
>> 1086 source "arch/mips/pic32/Kconfig"
>> 1087 source "arch/mips/pistachio/Kconfig"
>> 1088 source "arch/mips/pmcs-msp71xx/Kconfig"
>> 1089 source "arch/mips/ralink/Kconfig"
>> 1090 source "arch/mips/sgi-ip27/Kconfig"
>> 1091 source "arch/mips/sibyte/Kconfig"
>> 1092 source "arch/mips/txx9/Kconfig"
>> 1093 source "arch/mips/vr41xx/Kconfig"
>> 1094 source "arch/mips/cavium-octeon/Kconfig"
>> 1095 source "arch/mips/loongson2ef/Kconfig"
>> 1096 source "arch/mips/loongson32/Kconfig"
>> 1097 source "arch/mips/loongson64/Kconfig"
>> 1098 source "arch/mips/netlogic/Kconfig"
>> 1099 source "arch/mips/paravirt/Kconfig"
>> 1100
>> 1101 endmenu
67 1102
68 config GENERIC_HWEIGHT 1103 config GENERIC_HWEIGHT
69 def_bool y !! 1104 bool
>> 1105 default y
70 1106
71 config ARCH_HAS_ILOG2_U32 !! 1107 config GENERIC_CALIBRATE_DELAY
72 def_bool n !! 1108 bool
>> 1109 default y
73 1110
74 config ARCH_HAS_ILOG2_U64 !! 1111 config SCHED_OMIT_FRAME_POINTER
75 def_bool n !! 1112 bool
>> 1113 default y
76 1114
77 config ARCH_MTD_XIP !! 1115 #
78 def_bool y !! 1116 # Select some configuration options automatically based on user selections.
>> 1117 #
>> 1118 config FW_ARC
>> 1119 bool
>> 1120
>> 1121 config ARCH_MAY_HAVE_PC_FDC
>> 1122 bool
>> 1123
>> 1124 config BOOT_RAW
>> 1125 bool
>> 1126
>> 1127 config CEVT_BCM1480
>> 1128 bool
>> 1129
>> 1130 config CEVT_DS1287
>> 1131 bool
>> 1132
>> 1133 config CEVT_GT641XX
>> 1134 bool
>> 1135
>> 1136 config CEVT_R4K
>> 1137 bool
>> 1138
>> 1139 config CEVT_SB1250
>> 1140 bool
>> 1141
>> 1142 config CEVT_TXX9
>> 1143 bool
>> 1144
>> 1145 config CSRC_BCM1480
>> 1146 bool
>> 1147
>> 1148 config CSRC_IOASIC
>> 1149 bool
>> 1150
>> 1151 config CSRC_R4K
>> 1152 bool
>> 1153
>> 1154 config CSRC_SB1250
>> 1155 bool
>> 1156
>> 1157 config MIPS_CLOCK_VSYSCALL
>> 1158 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1159
>> 1160 config GPIO_TXX9
>> 1161 select GPIOLIB
>> 1162 bool
>> 1163
>> 1164 config FW_CFE
>> 1165 bool
>> 1166
>> 1167 config ARCH_SUPPORTS_UPROBES
>> 1168 bool
>> 1169
>> 1170 config DMA_MAYBE_COHERENT
>> 1171 select ARCH_HAS_DMA_COHERENCE_H
>> 1172 select DMA_NONCOHERENT
>> 1173 bool
>> 1174
>> 1175 config DMA_PERDEV_COHERENT
>> 1176 bool
>> 1177 select ARCH_HAS_SETUP_DMA_OPS
>> 1178 select DMA_NONCOHERENT
>> 1179
>> 1180 config DMA_NONCOHERENT
>> 1181 bool
>> 1182 #
>> 1183 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1184 # Attribute bits. It is believed that the uncached access through
>> 1185 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1186 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1187 # significant advantages.
>> 1188 #
>> 1189 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1190 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1191 select ARCH_HAS_UNCACHED_SEGMENT
>> 1192 select DMA_NONCOHERENT_MMAP
>> 1193 select DMA_NONCOHERENT_CACHE_SYNC
>> 1194 select NEED_DMA_MAP_STATE
>> 1195
>> 1196 config SYS_HAS_EARLY_PRINTK
>> 1197 bool
>> 1198
>> 1199 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1200 bool
>> 1201
>> 1202 config MIPS_BONITO64
>> 1203 bool
>> 1204
>> 1205 config MIPS_MSC
>> 1206 bool
>> 1207
>> 1208 config MIPS_NILE4
>> 1209 bool
>> 1210
>> 1211 config SYNC_R4K
>> 1212 bool
>> 1213
>> 1214 config MIPS_MACHINE
>> 1215 def_bool n
79 1216
80 config NO_IOPORT_MAP 1217 config NO_IOPORT_MAP
81 def_bool n 1218 def_bool n
82 1219
83 config HZ !! 1220 config GENERIC_CSUM
84 int !! 1221 def_bool CPU_NO_LOAD_STORE_LR
85 default 100 <<
86 1222
87 config LOCKDEP_SUPPORT !! 1223 config GENERIC_ISA_DMA
88 def_bool y !! 1224 bool
>> 1225 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1226 select ISA_DMA_API
89 1227
90 config STACKTRACE_SUPPORT !! 1228 config GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 1229 bool
>> 1230 select GENERIC_ISA_DMA
>> 1231
>> 1232 config ISA_DMA_API
>> 1233 bool
>> 1234
>> 1235 config HOLES_IN_ZONE
>> 1236 bool
>> 1237
>> 1238 config SYS_SUPPORTS_RELOCATABLE
>> 1239 bool
>> 1240 help
>> 1241 Selected if the platform supports relocating the kernel.
>> 1242 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1243 to allow access to command line and entropy sources.
>> 1244
>> 1245 config MIPS_CBPF_JIT
91 def_bool y 1246 def_bool y
>> 1247 depends on BPF_JIT && HAVE_CBPF_JIT
92 1248
93 config MMU !! 1249 config MIPS_EBPF_JIT
94 def_bool n !! 1250 def_bool y
95 select PFAULT !! 1251 depends on BPF_JIT && HAVE_EBPF_JIT
96 1252
97 config HAVE_XTENSA_GPIO32 <<
98 def_bool n <<
99 1253
100 config KASAN_SHADOW_OFFSET !! 1254 #
101 hex !! 1255 # Endianness selection. Sufficiently obscure so many users don't know what to
102 default 0x6e400000 !! 1256 # answer,so we try hard to limit the available choices. Also the use of a
>> 1257 # choice statement should be more obvious to the user.
>> 1258 #
>> 1259 choice
>> 1260 prompt "Endianness selection"
>> 1261 help
>> 1262 Some MIPS machines can be configured for either little or big endian
>> 1263 byte order. These modes require different kernels and a different
>> 1264 Linux distribution. In general there is one preferred byteorder for a
>> 1265 particular system but some systems are just as commonly used in the
>> 1266 one or the other endianness.
103 1267
104 config CPU_BIG_ENDIAN 1268 config CPU_BIG_ENDIAN
105 def_bool $(success,test "$(shell,echo !! 1269 bool "Big endian"
>> 1270 depends on SYS_SUPPORTS_BIG_ENDIAN
106 1271
107 config CPU_LITTLE_ENDIAN 1272 config CPU_LITTLE_ENDIAN
108 def_bool !CPU_BIG_ENDIAN !! 1273 bool "Little endian"
>> 1274 depends on SYS_SUPPORTS_LITTLE_ENDIAN
109 1275
110 config CC_HAVE_CALL0_ABI !! 1276 endchoice
111 def_bool $(success,test "$(shell,echo <<
112 1277
113 menu "Processor type and features" !! 1278 config EXPORT_UASM
>> 1279 bool
114 1280
115 choice !! 1281 config SYS_SUPPORTS_APM_EMULATION
116 prompt "Xtensa Processor Configuration !! 1282 bool
117 default XTENSA_VARIANT_FSF <<
118 1283
119 config XTENSA_VARIANT_FSF !! 1284 config SYS_SUPPORTS_BIG_ENDIAN
120 bool "fsf - default (not generic) conf !! 1285 bool
121 select MMU <<
122 1286
123 config XTENSA_VARIANT_DC232B !! 1287 config SYS_SUPPORTS_LITTLE_ENDIAN
124 bool "dc232b - Diamond 232L Standard C !! 1288 bool
125 select MMU <<
126 select HAVE_XTENSA_GPIO32 <<
127 help <<
128 This variant refers to Tensilica's D <<
129 1289
130 config XTENSA_VARIANT_DC233C !! 1290 config SYS_SUPPORTS_HUGETLBFS
131 bool "dc233c - Diamond 233L Standard C !! 1291 bool
132 select MMU !! 1292 depends on CPU_SUPPORTS_HUGEPAGES
133 select HAVE_XTENSA_GPIO32 !! 1293 default y
134 help <<
135 This variant refers to Tensilica's D <<
136 1294
137 config XTENSA_VARIANT_CUSTOM !! 1295 config MIPS_HUGE_TLB_SUPPORT
138 bool "Custom Xtensa processor configur !! 1296 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
139 select HAVE_XTENSA_GPIO32 !! 1297
140 help !! 1298 config IRQ_CPU_RM7K
141 Select this variant to use a custom !! 1299 bool
142 You will be prompted for a processor !! 1300
143 endchoice !! 1301 config IRQ_MSP_SLP
>> 1302 bool
>> 1303
>> 1304 config IRQ_MSP_CIC
>> 1305 bool
>> 1306
>> 1307 config IRQ_TXX9
>> 1308 bool
>> 1309
>> 1310 config IRQ_GT641XX
>> 1311 bool
>> 1312
>> 1313 config PCI_GT64XXX_PCI0
>> 1314 bool
>> 1315
>> 1316 config PCI_XTALK_BRIDGE
>> 1317 bool
>> 1318
>> 1319 config NO_EXCEPT_FILL
>> 1320 bool
>> 1321
>> 1322 config SOC_EMMA2RH
>> 1323 bool
>> 1324 select CEVT_R4K
>> 1325 select CSRC_R4K
>> 1326 select DMA_NONCOHERENT
>> 1327 select IRQ_MIPS_CPU
>> 1328 select SWAP_IO_SPACE
>> 1329 select SYS_HAS_CPU_R5500
>> 1330 select SYS_SUPPORTS_32BIT_KERNEL
>> 1331 select SYS_SUPPORTS_64BIT_KERNEL
>> 1332 select SYS_SUPPORTS_BIG_ENDIAN
>> 1333
>> 1334 config SOC_PNX833X
>> 1335 bool
>> 1336 select CEVT_R4K
>> 1337 select CSRC_R4K
>> 1338 select IRQ_MIPS_CPU
>> 1339 select DMA_NONCOHERENT
>> 1340 select SYS_HAS_CPU_MIPS32_R2
>> 1341 select SYS_SUPPORTS_32BIT_KERNEL
>> 1342 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 1343 select SYS_SUPPORTS_BIG_ENDIAN
>> 1344 select SYS_SUPPORTS_MIPS16
>> 1345 select CPU_MIPSR2_IRQ_VI
144 1346
145 config XTENSA_VARIANT_CUSTOM_NAME !! 1347 config SOC_PNX8335
146 string "Xtensa Processor Custom Core V !! 1348 bool
147 depends on XTENSA_VARIANT_CUSTOM !! 1349 select SOC_PNX833X
148 help !! 1350
149 Provide the name of a custom Xtensa !! 1351 config MIPS_SPRAM
150 This CORENAME selects arch/xtensa/va !! 1352 bool
151 Don't forget you have to select MMU !! 1353
152 !! 1354 config SWAP_IO_SPACE
153 config XTENSA_VARIANT_NAME !! 1355 bool
154 string !! 1356
155 default "dc232b" !! 1357 config SGI_HAS_INDYDOG
156 default "dc233c" !! 1358 bool
157 default "fsf" !! 1359
158 default XTENSA_VARIANT_CUSTOM_NAME !! 1360 config SGI_HAS_HAL2
159 !! 1361 bool
160 config XTENSA_VARIANT_MMU !! 1362
161 bool "Core variant has a Full MMU (TLB !! 1363 config SGI_HAS_SEEQ
162 depends on XTENSA_VARIANT_CUSTOM !! 1364 bool
163 default y !! 1365
164 select MMU !! 1366 config SGI_HAS_WD93
165 help !! 1367 bool
166 Build a Conventional Kernel with ful !! 1368
167 ie: it supports a TLB with auto-load !! 1369 config SGI_HAS_ZILOG
168 !! 1370 bool
169 config XTENSA_VARIANT_HAVE_PERF_EVENTS !! 1371
170 bool "Core variant has Performance Mon !! 1372 config SGI_HAS_I8042
171 depends on XTENSA_VARIANT_CUSTOM !! 1373 bool
>> 1374
>> 1375 config DEFAULT_SGI_PARTITION
>> 1376 bool
>> 1377
>> 1378 config FW_ARC32
>> 1379 bool
>> 1380
>> 1381 config FW_SNIPROM
>> 1382 bool
>> 1383
>> 1384 config BOOT_ELF32
>> 1385 bool
>> 1386
>> 1387 config MIPS_L1_CACHE_SHIFT_4
>> 1388 bool
>> 1389
>> 1390 config MIPS_L1_CACHE_SHIFT_5
>> 1391 bool
>> 1392
>> 1393 config MIPS_L1_CACHE_SHIFT_6
>> 1394 bool
>> 1395
>> 1396 config MIPS_L1_CACHE_SHIFT_7
>> 1397 bool
>> 1398
>> 1399 config MIPS_L1_CACHE_SHIFT
>> 1400 int
>> 1401 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1402 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1403 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1404 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1405 default "5"
>> 1406
>> 1407 config HAVE_STD_PC_SERIAL_PORT
>> 1408 bool
>> 1409
>> 1410 config ARC_CMDLINE_ONLY
>> 1411 bool
>> 1412
>> 1413 config ARC_CONSOLE
>> 1414 bool "ARC console support"
>> 1415 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
>> 1416
>> 1417 config ARC_MEMORY
>> 1418 bool
>> 1419
>> 1420 config ARC_PROMLIB
>> 1421 bool
>> 1422
>> 1423 config FW_ARC64
>> 1424 bool
>> 1425
>> 1426 config BOOT_ELF64
>> 1427 bool
>> 1428
>> 1429 menu "CPU selection"
>> 1430
>> 1431 choice
>> 1432 prompt "CPU type"
>> 1433 default CPU_R4X00
>> 1434
>> 1435 config CPU_LOONGSON64
>> 1436 bool "Loongson 64-bit CPU"
>> 1437 depends on SYS_HAS_CPU_LOONGSON64
>> 1438 select ARCH_HAS_PHYS_TO_DMA
>> 1439 select CPU_MIPSR2
>> 1440 select CPU_HAS_PREFETCH
>> 1441 select CPU_SUPPORTS_64BIT_KERNEL
>> 1442 select CPU_SUPPORTS_HIGHMEM
>> 1443 select CPU_SUPPORTS_HUGEPAGES
>> 1444 select CPU_SUPPORTS_MSA
>> 1445 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1446 select CPU_MIPSR2_IRQ_VI
>> 1447 select WEAK_ORDERING
>> 1448 select WEAK_REORDERING_BEYOND_LLSC
>> 1449 select MIPS_ASID_BITS_VARIABLE
>> 1450 select MIPS_PGD_C0_CONTEXT
>> 1451 select MIPS_L1_CACHE_SHIFT_6
>> 1452 select GPIOLIB
>> 1453 select SWIOTLB
>> 1454 help
>> 1455 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1456 cores implements the MIPS64R2 instruction set with many extensions,
>> 1457 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1458 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1459 Loongson-2E/2F is not covered here and will be removed in future.
>> 1460
>> 1461 config LOONGSON3_ENHANCEMENT
>> 1462 bool "New Loongson-3 CPU Enhancements"
172 default n 1463 default n
>> 1464 depends on CPU_LOONGSON64
173 help 1465 help
174 Enable if core variant has Performan !! 1466 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
175 External Registers Interface. !! 1467 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
176 !! 1468 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
177 If unsure, say N. !! 1469 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1470 Fast TLB refill support, etc.
>> 1471
>> 1472 This option enable those enhancements which are not probed at run
>> 1473 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1474 please say 'N' here. If you want a high-performance kernel to run on
>> 1475 new Loongson-3 machines only, please say 'Y' here.
>> 1476
>> 1477 config CPU_LOONGSON3_WORKAROUNDS
>> 1478 bool "Old Loongson-3 LLSC Workarounds"
>> 1479 default y if SMP
>> 1480 depends on CPU_LOONGSON64
>> 1481 help
>> 1482 Loongson-3 processors have the llsc issues which require workarounds.
>> 1483 Without workarounds the system may hang unexpectedly.
>> 1484
>> 1485 Newer Loongson-3 will fix these issues and no workarounds are needed.
>> 1486 The workarounds have no significant side effect on them but may
>> 1487 decrease the performance of the system so this option should be
>> 1488 disabled unless the kernel is intended to be run on old systems.
>> 1489
>> 1490 If unsure, please say Y.
>> 1491
>> 1492 config CPU_LOONGSON2E
>> 1493 bool "Loongson 2E"
>> 1494 depends on SYS_HAS_CPU_LOONGSON2E
>> 1495 select CPU_LOONGSON2EF
>> 1496 help
>> 1497 The Loongson 2E processor implements the MIPS III instruction set
>> 1498 with many extensions.
>> 1499
>> 1500 It has an internal FPGA northbridge, which is compatible to
>> 1501 bonito64.
>> 1502
>> 1503 config CPU_LOONGSON2F
>> 1504 bool "Loongson 2F"
>> 1505 depends on SYS_HAS_CPU_LOONGSON2F
>> 1506 select CPU_LOONGSON2EF
>> 1507 select GPIOLIB
>> 1508 help
>> 1509 The Loongson 2F processor implements the MIPS III instruction set
>> 1510 with many extensions.
>> 1511
>> 1512 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1513 have a similar programming interface with FPGA northbridge used in
>> 1514 Loongson2E.
>> 1515
>> 1516 config CPU_LOONGSON1B
>> 1517 bool "Loongson 1B"
>> 1518 depends on SYS_HAS_CPU_LOONGSON1B
>> 1519 select CPU_LOONGSON32
>> 1520 select LEDS_GPIO_REGISTER
>> 1521 help
>> 1522 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1523 Release 1 instruction set and part of the MIPS32 Release 2
>> 1524 instruction set.
>> 1525
>> 1526 config CPU_LOONGSON1C
>> 1527 bool "Loongson 1C"
>> 1528 depends on SYS_HAS_CPU_LOONGSON1C
>> 1529 select CPU_LOONGSON32
>> 1530 select LEDS_GPIO_REGISTER
>> 1531 help
>> 1532 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1533 Release 1 instruction set and part of the MIPS32 Release 2
>> 1534 instruction set.
>> 1535
>> 1536 config CPU_MIPS32_R1
>> 1537 bool "MIPS32 Release 1"
>> 1538 depends on SYS_HAS_CPU_MIPS32_R1
>> 1539 select CPU_HAS_PREFETCH
>> 1540 select CPU_SUPPORTS_32BIT_KERNEL
>> 1541 select CPU_SUPPORTS_HIGHMEM
>> 1542 help
>> 1543 Choose this option to build a kernel for release 1 or later of the
>> 1544 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1545 MIPS processor are based on a MIPS32 processor. If you know the
>> 1546 specific type of processor in your system, choose those that one
>> 1547 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1548 Release 2 of the MIPS32 architecture is available since several
>> 1549 years so chances are you even have a MIPS32 Release 2 processor
>> 1550 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1551 performance.
>> 1552
>> 1553 config CPU_MIPS32_R2
>> 1554 bool "MIPS32 Release 2"
>> 1555 depends on SYS_HAS_CPU_MIPS32_R2
>> 1556 select CPU_HAS_PREFETCH
>> 1557 select CPU_SUPPORTS_32BIT_KERNEL
>> 1558 select CPU_SUPPORTS_HIGHMEM
>> 1559 select CPU_SUPPORTS_MSA
>> 1560 select HAVE_KVM
>> 1561 help
>> 1562 Choose this option to build a kernel for release 2 or later of the
>> 1563 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1564 MIPS processor are based on a MIPS32 processor. If you know the
>> 1565 specific type of processor in your system, choose those that one
>> 1566 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1567
>> 1568 config CPU_MIPS32_R6
>> 1569 bool "MIPS32 Release 6"
>> 1570 depends on SYS_HAS_CPU_MIPS32_R6
>> 1571 select CPU_HAS_PREFETCH
>> 1572 select CPU_NO_LOAD_STORE_LR
>> 1573 select CPU_SUPPORTS_32BIT_KERNEL
>> 1574 select CPU_SUPPORTS_HIGHMEM
>> 1575 select CPU_SUPPORTS_MSA
>> 1576 select HAVE_KVM
>> 1577 select MIPS_O32_FP64_SUPPORT
>> 1578 help
>> 1579 Choose this option to build a kernel for release 6 or later of the
>> 1580 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1581 family, are based on a MIPS32r6 processor. If you own an older
>> 1582 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1583
>> 1584 config CPU_MIPS64_R1
>> 1585 bool "MIPS64 Release 1"
>> 1586 depends on SYS_HAS_CPU_MIPS64_R1
>> 1587 select CPU_HAS_PREFETCH
>> 1588 select CPU_SUPPORTS_32BIT_KERNEL
>> 1589 select CPU_SUPPORTS_64BIT_KERNEL
>> 1590 select CPU_SUPPORTS_HIGHMEM
>> 1591 select CPU_SUPPORTS_HUGEPAGES
>> 1592 help
>> 1593 Choose this option to build a kernel for release 1 or later of the
>> 1594 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1595 MIPS processor are based on a MIPS64 processor. If you know the
>> 1596 specific type of processor in your system, choose those that one
>> 1597 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1598 Release 2 of the MIPS64 architecture is available since several
>> 1599 years so chances are you even have a MIPS64 Release 2 processor
>> 1600 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1601 performance.
>> 1602
>> 1603 config CPU_MIPS64_R2
>> 1604 bool "MIPS64 Release 2"
>> 1605 depends on SYS_HAS_CPU_MIPS64_R2
>> 1606 select CPU_HAS_PREFETCH
>> 1607 select CPU_SUPPORTS_32BIT_KERNEL
>> 1608 select CPU_SUPPORTS_64BIT_KERNEL
>> 1609 select CPU_SUPPORTS_HIGHMEM
>> 1610 select CPU_SUPPORTS_HUGEPAGES
>> 1611 select CPU_SUPPORTS_MSA
>> 1612 select HAVE_KVM
>> 1613 help
>> 1614 Choose this option to build a kernel for release 2 or later of the
>> 1615 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1616 MIPS processor are based on a MIPS64 processor. If you know the
>> 1617 specific type of processor in your system, choose those that one
>> 1618 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1619
>> 1620 config CPU_MIPS64_R6
>> 1621 bool "MIPS64 Release 6"
>> 1622 depends on SYS_HAS_CPU_MIPS64_R6
>> 1623 select CPU_HAS_PREFETCH
>> 1624 select CPU_NO_LOAD_STORE_LR
>> 1625 select CPU_SUPPORTS_32BIT_KERNEL
>> 1626 select CPU_SUPPORTS_64BIT_KERNEL
>> 1627 select CPU_SUPPORTS_HIGHMEM
>> 1628 select CPU_SUPPORTS_HUGEPAGES
>> 1629 select CPU_SUPPORTS_MSA
>> 1630 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1631 select HAVE_KVM
>> 1632 help
>> 1633 Choose this option to build a kernel for release 6 or later of the
>> 1634 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1635 family, are based on a MIPS64r6 processor. If you own an older
>> 1636 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1637
>> 1638 config CPU_R3000
>> 1639 bool "R3000"
>> 1640 depends on SYS_HAS_CPU_R3000
>> 1641 select CPU_HAS_WB
>> 1642 select CPU_R3K_TLB
>> 1643 select CPU_SUPPORTS_32BIT_KERNEL
>> 1644 select CPU_SUPPORTS_HIGHMEM
>> 1645 help
>> 1646 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1647 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1648 *not* work on R4000 machines and vice versa. However, since most
>> 1649 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1650 might be a safe bet. If the resulting kernel does not work,
>> 1651 try to recompile with R3000.
>> 1652
>> 1653 config CPU_TX39XX
>> 1654 bool "R39XX"
>> 1655 depends on SYS_HAS_CPU_TX39XX
>> 1656 select CPU_SUPPORTS_32BIT_KERNEL
>> 1657 select CPU_R3K_TLB
>> 1658
>> 1659 config CPU_VR41XX
>> 1660 bool "R41xx"
>> 1661 depends on SYS_HAS_CPU_VR41XX
>> 1662 select CPU_SUPPORTS_32BIT_KERNEL
>> 1663 select CPU_SUPPORTS_64BIT_KERNEL
>> 1664 help
>> 1665 The options selects support for the NEC VR4100 series of processors.
>> 1666 Only choose this option if you have one of these processors as a
>> 1667 kernel built with this option will not run on any other type of
>> 1668 processor or vice versa.
>> 1669
>> 1670 config CPU_R4X00
>> 1671 bool "R4x00"
>> 1672 depends on SYS_HAS_CPU_R4X00
>> 1673 select CPU_SUPPORTS_32BIT_KERNEL
>> 1674 select CPU_SUPPORTS_64BIT_KERNEL
>> 1675 select CPU_SUPPORTS_HUGEPAGES
>> 1676 help
>> 1677 MIPS Technologies R4000-series processors other than 4300, including
>> 1678 the R4000, R4400, R4600, and 4700.
>> 1679
>> 1680 config CPU_TX49XX
>> 1681 bool "R49XX"
>> 1682 depends on SYS_HAS_CPU_TX49XX
>> 1683 select CPU_HAS_PREFETCH
>> 1684 select CPU_SUPPORTS_32BIT_KERNEL
>> 1685 select CPU_SUPPORTS_64BIT_KERNEL
>> 1686 select CPU_SUPPORTS_HUGEPAGES
>> 1687
>> 1688 config CPU_R5000
>> 1689 bool "R5000"
>> 1690 depends on SYS_HAS_CPU_R5000
>> 1691 select CPU_SUPPORTS_32BIT_KERNEL
>> 1692 select CPU_SUPPORTS_64BIT_KERNEL
>> 1693 select CPU_SUPPORTS_HUGEPAGES
>> 1694 help
>> 1695 MIPS Technologies R5000-series processors other than the Nevada.
>> 1696
>> 1697 config CPU_R5500
>> 1698 bool "R5500"
>> 1699 depends on SYS_HAS_CPU_R5500
>> 1700 select CPU_SUPPORTS_32BIT_KERNEL
>> 1701 select CPU_SUPPORTS_64BIT_KERNEL
>> 1702 select CPU_SUPPORTS_HUGEPAGES
>> 1703 help
>> 1704 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1705 instruction set.
>> 1706
>> 1707 config CPU_NEVADA
>> 1708 bool "RM52xx"
>> 1709 depends on SYS_HAS_CPU_NEVADA
>> 1710 select CPU_SUPPORTS_32BIT_KERNEL
>> 1711 select CPU_SUPPORTS_64BIT_KERNEL
>> 1712 select CPU_SUPPORTS_HUGEPAGES
>> 1713 help
>> 1714 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1715
>> 1716 config CPU_R10000
>> 1717 bool "R10000"
>> 1718 depends on SYS_HAS_CPU_R10000
>> 1719 select CPU_HAS_PREFETCH
>> 1720 select CPU_SUPPORTS_32BIT_KERNEL
>> 1721 select CPU_SUPPORTS_64BIT_KERNEL
>> 1722 select CPU_SUPPORTS_HIGHMEM
>> 1723 select CPU_SUPPORTS_HUGEPAGES
>> 1724 help
>> 1725 MIPS Technologies R10000-series processors.
>> 1726
>> 1727 config CPU_RM7000
>> 1728 bool "RM7000"
>> 1729 depends on SYS_HAS_CPU_RM7000
>> 1730 select CPU_HAS_PREFETCH
>> 1731 select CPU_SUPPORTS_32BIT_KERNEL
>> 1732 select CPU_SUPPORTS_64BIT_KERNEL
>> 1733 select CPU_SUPPORTS_HIGHMEM
>> 1734 select CPU_SUPPORTS_HUGEPAGES
>> 1735
>> 1736 config CPU_SB1
>> 1737 bool "SB1"
>> 1738 depends on SYS_HAS_CPU_SB1
>> 1739 select CPU_SUPPORTS_32BIT_KERNEL
>> 1740 select CPU_SUPPORTS_64BIT_KERNEL
>> 1741 select CPU_SUPPORTS_HIGHMEM
>> 1742 select CPU_SUPPORTS_HUGEPAGES
>> 1743 select WEAK_ORDERING
>> 1744
>> 1745 config CPU_CAVIUM_OCTEON
>> 1746 bool "Cavium Octeon processor"
>> 1747 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1748 select CPU_HAS_PREFETCH
>> 1749 select CPU_SUPPORTS_64BIT_KERNEL
>> 1750 select WEAK_ORDERING
>> 1751 select CPU_SUPPORTS_HIGHMEM
>> 1752 select CPU_SUPPORTS_HUGEPAGES
>> 1753 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1754 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1755 select MIPS_L1_CACHE_SHIFT_7
>> 1756 select HAVE_KVM
>> 1757 help
>> 1758 The Cavium Octeon processor is a highly integrated chip containing
>> 1759 many ethernet hardware widgets for networking tasks. The processor
>> 1760 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1761 Full details can be found at http://www.caviumnetworks.com.
>> 1762
>> 1763 config CPU_BMIPS
>> 1764 bool "Broadcom BMIPS"
>> 1765 depends on SYS_HAS_CPU_BMIPS
>> 1766 select CPU_MIPS32
>> 1767 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1768 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1769 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1770 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1771 select CPU_SUPPORTS_32BIT_KERNEL
>> 1772 select DMA_NONCOHERENT
>> 1773 select IRQ_MIPS_CPU
>> 1774 select SWAP_IO_SPACE
>> 1775 select WEAK_ORDERING
>> 1776 select CPU_SUPPORTS_HIGHMEM
>> 1777 select CPU_HAS_PREFETCH
>> 1778 select CPU_SUPPORTS_CPUFREQ
>> 1779 select MIPS_EXTERNAL_TIMER
>> 1780 help
>> 1781 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
>> 1782
>> 1783 config CPU_XLR
>> 1784 bool "Netlogic XLR SoC"
>> 1785 depends on SYS_HAS_CPU_XLR
>> 1786 select CPU_SUPPORTS_32BIT_KERNEL
>> 1787 select CPU_SUPPORTS_64BIT_KERNEL
>> 1788 select CPU_SUPPORTS_HIGHMEM
>> 1789 select CPU_SUPPORTS_HUGEPAGES
>> 1790 select WEAK_ORDERING
>> 1791 select WEAK_REORDERING_BEYOND_LLSC
>> 1792 help
>> 1793 Netlogic Microsystems XLR/XLS processors.
>> 1794
>> 1795 config CPU_XLP
>> 1796 bool "Netlogic XLP SoC"
>> 1797 depends on SYS_HAS_CPU_XLP
>> 1798 select CPU_SUPPORTS_32BIT_KERNEL
>> 1799 select CPU_SUPPORTS_64BIT_KERNEL
>> 1800 select CPU_SUPPORTS_HIGHMEM
>> 1801 select WEAK_ORDERING
>> 1802 select WEAK_REORDERING_BEYOND_LLSC
>> 1803 select CPU_HAS_PREFETCH
>> 1804 select CPU_MIPSR2
>> 1805 select CPU_SUPPORTS_HUGEPAGES
>> 1806 select MIPS_ASID_BITS_VARIABLE
>> 1807 help
>> 1808 Netlogic Microsystems XLP processors.
>> 1809 endchoice
178 1810
179 config XTENSA_FAKE_NMI !! 1811 config CPU_MIPS32_3_5_FEATURES
180 bool "Treat PMM IRQ as NMI" !! 1812 bool "MIPS32 Release 3.5 Features"
181 depends on XTENSA_VARIANT_HAVE_PERF_EV !! 1813 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1814 depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 1815 help
>> 1816 Choose this option to build a kernel for release 2 or later of the
>> 1817 MIPS32 architecture including features from the 3.5 release such as
>> 1818 support for Enhanced Virtual Addressing (EVA).
>> 1819
>> 1820 config CPU_MIPS32_3_5_EVA
>> 1821 bool "Enhanced Virtual Addressing (EVA)"
>> 1822 depends on CPU_MIPS32_3_5_FEATURES
>> 1823 select EVA
>> 1824 default y
>> 1825 help
>> 1826 Choose this option if you want to enable the Enhanced Virtual
>> 1827 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1828 One of its primary benefits is an increase in the maximum size
>> 1829 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1830
>> 1831 config CPU_MIPS32_R5_FEATURES
>> 1832 bool "MIPS32 Release 5 Features"
>> 1833 depends on SYS_HAS_CPU_MIPS32_R5
>> 1834 depends on CPU_MIPS32_R2
>> 1835 help
>> 1836 Choose this option to build a kernel for release 2 or later of the
>> 1837 MIPS32 architecture including features from release 5 such as
>> 1838 support for Extended Physical Addressing (XPA).
>> 1839
>> 1840 config CPU_MIPS32_R5_XPA
>> 1841 bool "Extended Physical Addressing (XPA)"
>> 1842 depends on CPU_MIPS32_R5_FEATURES
>> 1843 depends on !EVA
>> 1844 depends on !PAGE_SIZE_4KB
>> 1845 depends on SYS_SUPPORTS_HIGHMEM
>> 1846 select XPA
>> 1847 select HIGHMEM
>> 1848 select PHYS_ADDR_T_64BIT
182 default n 1849 default n
183 help 1850 help
184 If PMM IRQ is the only IRQ at EXCM l !! 1851 Choose this option if you want to enable the Extended Physical
185 treat it as NMI, which improves accu !! 1852 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1853 benefit is to increase physical addressing equal to or greater
>> 1854 than 40 bits. Note that this has the side effect of turning on
>> 1855 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1856 If unsure, say 'N' here.
186 1857
187 If there are other interrupts at or !! 1858 if CPU_LOONGSON2F
188 but not above the EXCM level, PMM IR !! 1859 config CPU_NOP_WORKAROUNDS
189 but only if these IRQs are not used. !! 1860 bool
190 saying that this is not safe, and a <<
191 actually fire. <<
192 1861
193 If unsure, say N. !! 1862 config CPU_JUMP_WORKAROUNDS
>> 1863 bool
194 1864
195 config PFAULT !! 1865 config CPU_LOONGSON2F_WORKAROUNDS
196 bool "Handle protection faults" if EXP !! 1866 bool "Loongson 2F Workarounds"
197 default y 1867 default y
>> 1868 select CPU_NOP_WORKAROUNDS
>> 1869 select CPU_JUMP_WORKAROUNDS
198 help 1870 help
199 Handle protection faults. MMU config !! 1871 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
200 noMMU configurations may disable it !! 1872 require workarounds. Without workarounds the system may hang
201 generates protection faults or fault !! 1873 unexpectedly. For more information please refer to the gas
>> 1874 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1875
>> 1876 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1877 are needed. The workarounds have no significant side effect on them
>> 1878 but may decrease the performance of the system so this option should
>> 1879 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1880 systems.
202 1881
203 If unsure, say Y. !! 1882 If unsure, please say Y.
>> 1883 endif # CPU_LOONGSON2F
204 1884
205 config XTENSA_UNALIGNED_USER !! 1885 config SYS_SUPPORTS_ZBOOT
206 bool "Unaligned memory access in user !! 1886 bool
207 help !! 1887 select HAVE_KERNEL_GZIP
208 The Xtensa architecture currently do !! 1888 select HAVE_KERNEL_BZIP2
209 memory accesses in hardware but thro !! 1889 select HAVE_KERNEL_LZ4
210 Per default, unaligned memory access !! 1890 select HAVE_KERNEL_LZMA
>> 1891 select HAVE_KERNEL_LZO
>> 1892 select HAVE_KERNEL_XZ
211 1893
212 Say Y here to enable unaligned memor !! 1894 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1895 bool
>> 1896 select SYS_SUPPORTS_ZBOOT
213 1897
214 config XTENSA_LOAD_STORE !! 1898 config SYS_SUPPORTS_ZBOOT_UART_PROM
215 bool "Load/store exception handler for !! 1899 bool
216 help !! 1900 select SYS_SUPPORTS_ZBOOT
217 The Xtensa architecture only allows <<
218 instruction bus with l32r and l32i i <<
219 instructions raise an exception with <<
220 This makes it hard to use some confi <<
221 literals in FLASH memory attached to <<
222 1901
223 Say Y here to enable exception handl !! 1902 config CPU_LOONGSON2EF
224 byte and 2-byte access to memory att !! 1903 bool
>> 1904 select CPU_SUPPORTS_32BIT_KERNEL
>> 1905 select CPU_SUPPORTS_64BIT_KERNEL
>> 1906 select CPU_SUPPORTS_HIGHMEM
>> 1907 select CPU_SUPPORTS_HUGEPAGES
>> 1908 select ARCH_HAS_PHYS_TO_DMA
225 1909
226 config HAVE_SMP !! 1910 config CPU_LOONGSON32
227 bool "System Supports SMP (MX)" !! 1911 bool
228 depends on XTENSA_VARIANT_CUSTOM !! 1912 select CPU_MIPS32
229 select XTENSA_MX !! 1913 select CPU_MIPSR2
230 help !! 1914 select CPU_HAS_PREFETCH
231 This option is used to indicate that !! 1915 select CPU_SUPPORTS_32BIT_KERNEL
232 supports Multiprocessing. Multiproce !! 1916 select CPU_SUPPORTS_HIGHMEM
233 the CPU core definition and currentl !! 1917 select CPU_SUPPORTS_CPUFREQ
234 1918
235 Multiprocessor support is implemente !! 1919 config CPU_BMIPS32_3300
236 interrupt controllers. !! 1920 select SMP_UP if SMP
>> 1921 bool
237 1922
238 The MX interrupt distributer adds In !! 1923 config CPU_BMIPS4350
239 and causes the IRQ numbers to be inc !! 1924 bool
240 like the open cores ethernet driver !! 1925 select SYS_SUPPORTS_SMP
>> 1926 select SYS_SUPPORTS_HOTPLUG_CPU
241 1927
242 You still have to select "Enable SMP !! 1928 config CPU_BMIPS4380
>> 1929 bool
>> 1930 select MIPS_L1_CACHE_SHIFT_6
>> 1931 select SYS_SUPPORTS_SMP
>> 1932 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1933 select CPU_HAS_RIXI
243 1934
244 config SMP !! 1935 config CPU_BMIPS5000
245 bool "Enable Symmetric multi-processin !! 1936 bool
246 depends on HAVE_SMP !! 1937 select MIPS_CPU_SCACHE
247 select GENERIC_SMP_IDLE_THREAD !! 1938 select MIPS_L1_CACHE_SHIFT_7
248 help !! 1939 select SYS_SUPPORTS_SMP
249 Enabled SMP Software; allows more th !! 1940 select SYS_SUPPORTS_HOTPLUG_CPU
250 to be activated during startup. !! 1941 select CPU_HAS_RIXI
251 1942
252 config NR_CPUS !! 1943 config SYS_HAS_CPU_LOONGSON64
253 depends on SMP !! 1944 bool
254 int "Maximum number of CPUs (2-32)" !! 1945 select CPU_SUPPORTS_CPUFREQ
255 range 2 32 !! 1946 select CPU_HAS_RIXI
256 default "4" <<
257 1947
258 config HOTPLUG_CPU !! 1948 config SYS_HAS_CPU_LOONGSON2E
259 bool "Enable CPU hotplug support" !! 1949 bool
260 depends on SMP !! 1950
>> 1951 config SYS_HAS_CPU_LOONGSON2F
>> 1952 bool
>> 1953 select CPU_SUPPORTS_CPUFREQ
>> 1954 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1955
>> 1956 config SYS_HAS_CPU_LOONGSON1B
>> 1957 bool
>> 1958
>> 1959 config SYS_HAS_CPU_LOONGSON1C
>> 1960 bool
>> 1961
>> 1962 config SYS_HAS_CPU_MIPS32_R1
>> 1963 bool
>> 1964
>> 1965 config SYS_HAS_CPU_MIPS32_R2
>> 1966 bool
>> 1967
>> 1968 config SYS_HAS_CPU_MIPS32_R3_5
>> 1969 bool
>> 1970
>> 1971 config SYS_HAS_CPU_MIPS32_R5
>> 1972 bool
>> 1973 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1974
>> 1975 config SYS_HAS_CPU_MIPS32_R6
>> 1976 bool
>> 1977 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1978
>> 1979 config SYS_HAS_CPU_MIPS64_R1
>> 1980 bool
>> 1981
>> 1982 config SYS_HAS_CPU_MIPS64_R2
>> 1983 bool
>> 1984
>> 1985 config SYS_HAS_CPU_MIPS64_R6
>> 1986 bool
>> 1987 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1988
>> 1989 config SYS_HAS_CPU_R3000
>> 1990 bool
>> 1991
>> 1992 config SYS_HAS_CPU_TX39XX
>> 1993 bool
>> 1994
>> 1995 config SYS_HAS_CPU_VR41XX
>> 1996 bool
>> 1997
>> 1998 config SYS_HAS_CPU_R4X00
>> 1999 bool
>> 2000
>> 2001 config SYS_HAS_CPU_TX49XX
>> 2002 bool
>> 2003
>> 2004 config SYS_HAS_CPU_R5000
>> 2005 bool
>> 2006
>> 2007 config SYS_HAS_CPU_R5500
>> 2008 bool
>> 2009
>> 2010 config SYS_HAS_CPU_NEVADA
>> 2011 bool
>> 2012
>> 2013 config SYS_HAS_CPU_R10000
>> 2014 bool
>> 2015 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 2016
>> 2017 config SYS_HAS_CPU_RM7000
>> 2018 bool
>> 2019
>> 2020 config SYS_HAS_CPU_SB1
>> 2021 bool
>> 2022
>> 2023 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 2024 bool
>> 2025
>> 2026 config SYS_HAS_CPU_BMIPS
>> 2027 bool
>> 2028
>> 2029 config SYS_HAS_CPU_BMIPS32_3300
>> 2030 bool
>> 2031 select SYS_HAS_CPU_BMIPS
>> 2032
>> 2033 config SYS_HAS_CPU_BMIPS4350
>> 2034 bool
>> 2035 select SYS_HAS_CPU_BMIPS
>> 2036
>> 2037 config SYS_HAS_CPU_BMIPS4380
>> 2038 bool
>> 2039 select SYS_HAS_CPU_BMIPS
>> 2040
>> 2041 config SYS_HAS_CPU_BMIPS5000
>> 2042 bool
>> 2043 select SYS_HAS_CPU_BMIPS
>> 2044 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 2045
>> 2046 config SYS_HAS_CPU_XLR
>> 2047 bool
>> 2048
>> 2049 config SYS_HAS_CPU_XLP
>> 2050 bool
>> 2051
>> 2052 #
>> 2053 # CPU may reorder R->R, R->W, W->R, W->W
>> 2054 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 2055 #
>> 2056 config WEAK_ORDERING
>> 2057 bool
>> 2058
>> 2059 #
>> 2060 # CPU may reorder reads and writes beyond LL/SC
>> 2061 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 2062 #
>> 2063 config WEAK_REORDERING_BEYOND_LLSC
>> 2064 bool
>> 2065 endmenu
>> 2066
>> 2067 #
>> 2068 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 2069 #
>> 2070 config CPU_MIPS32
>> 2071 bool
>> 2072 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
>> 2073
>> 2074 config CPU_MIPS64
>> 2075 bool
>> 2076 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
>> 2077
>> 2078 #
>> 2079 # These indicate the revision of the architecture
>> 2080 #
>> 2081 config CPU_MIPSR1
>> 2082 bool
>> 2083 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 2084
>> 2085 config CPU_MIPSR2
>> 2086 bool
>> 2087 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 2088 select CPU_HAS_RIXI
>> 2089 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2090 select MIPS_SPRAM
>> 2091
>> 2092 config CPU_MIPSR6
>> 2093 bool
>> 2094 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2095 select CPU_HAS_RIXI
>> 2096 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2097 select HAVE_ARCH_BITREVERSE
>> 2098 select MIPS_ASID_BITS_VARIABLE
>> 2099 select MIPS_CRC_SUPPORT
>> 2100 select MIPS_SPRAM
>> 2101
>> 2102 config TARGET_ISA_REV
>> 2103 int
>> 2104 default 1 if CPU_MIPSR1
>> 2105 default 2 if CPU_MIPSR2
>> 2106 default 6 if CPU_MIPSR6
>> 2107 default 0
261 help 2108 help
262 Say Y here to allow turning CPUs off !! 2109 Reflects the ISA revision being targeted by the kernel build. This
263 controlled through /sys/devices/syst !! 2110 is effectively the Kconfig equivalent of MIPS_ISA_REV.
264 2111
265 Say N if you want to disable CPU hot !! 2112 config EVA
>> 2113 bool
266 2114
267 config SECONDARY_RESET_VECTOR !! 2115 config XPA
268 bool "Secondary cores use alternative !! 2116 bool
269 default y !! 2117
270 depends on HAVE_SMP !! 2118 config SYS_SUPPORTS_32BIT_KERNEL
>> 2119 bool
>> 2120 config SYS_SUPPORTS_64BIT_KERNEL
>> 2121 bool
>> 2122 config CPU_SUPPORTS_32BIT_KERNEL
>> 2123 bool
>> 2124 config CPU_SUPPORTS_64BIT_KERNEL
>> 2125 bool
>> 2126 config CPU_SUPPORTS_CPUFREQ
>> 2127 bool
>> 2128 config CPU_SUPPORTS_ADDRWINCFG
>> 2129 bool
>> 2130 config CPU_SUPPORTS_HUGEPAGES
>> 2131 bool
>> 2132 depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA))
>> 2133 config MIPS_PGD_C0_CONTEXT
>> 2134 bool
>> 2135 default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
>> 2136
>> 2137 #
>> 2138 # Set to y for ptrace access to watch registers.
>> 2139 #
>> 2140 config HARDWARE_WATCHPOINTS
>> 2141 bool
>> 2142 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
>> 2143
>> 2144 menu "Kernel type"
>> 2145
>> 2146 choice
>> 2147 prompt "Kernel code model"
271 help 2148 help
272 Secondary cores may be configured to !! 2149 You should only select this option if you have a workload that
273 or all cores may use primary reset v !! 2150 actually benefits from 64-bit processing or if your machine has
274 Say Y here to supply handler for the !! 2151 large memory. You will only be presented a single option in this
>> 2152 menu if your system does not support both 32-bit and 64-bit kernels.
275 2153
276 config FAST_SYSCALL_XTENSA !! 2154 config 32BIT
277 bool "Enable fast atomic syscalls" !! 2155 bool "32-bit kernel"
278 default n !! 2156 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2157 select TRAD_SIGNALS
279 help 2158 help
280 fast_syscall_xtensa is a syscall tha !! 2159 Select this option if you want to build a 32-bit kernel.
281 on UP kernel when processor has no s <<
282 2160
283 This syscall is deprecated. It may h !! 2161 config 64BIT
284 invalid arguments. It is provided on !! 2162 bool "64-bit kernel"
285 Only enable it if your userspace sof !! 2163 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
>> 2164 help
>> 2165 Select this option if you want to build a 64-bit kernel.
286 2166
287 If unsure, say N. !! 2167 endchoice
288 2168
289 config FAST_SYSCALL_SPILL_REGISTERS !! 2169 config KVM_GUEST
290 bool "Enable spill registers syscall" !! 2170 bool "KVM Guest Kernel"
291 default n !! 2171 depends on BROKEN_ON_SMP
>> 2172 help
>> 2173 Select this option if building a guest kernel for KVM (Trap & Emulate)
>> 2174 mode.
>> 2175
>> 2176 config KVM_GUEST_TIMER_FREQ
>> 2177 int "Count/Compare Timer Frequency (MHz)"
>> 2178 depends on KVM_GUEST
>> 2179 default 100
292 help 2180 help
293 fast_syscall_spill_registers is a sy !! 2181 Set this to non-zero if building a guest kernel for KVM to skip RTC
294 register windows of a calling usersp !! 2182 emulation when determining guest CPU Frequency. Instead, the guest's
295 !! 2183 timer frequency is specified directly.
296 This syscall is deprecated. It may h !! 2184
297 invalid arguments. It is provided on !! 2185 config MIPS_VA_BITS_48
298 Only enable it if your userspace sof !! 2186 bool "48 bits virtual memory"
>> 2187 depends on 64BIT
>> 2188 help
>> 2189 Support a maximum at least 48 bits of application virtual
>> 2190 memory. Default is 40 bits or less, depending on the CPU.
>> 2191 For page sizes 16k and above, this option results in a small
>> 2192 memory overhead for page tables. For 4k page size, a fourth
>> 2193 level of page tables is added which imposes both a memory
>> 2194 overhead as well as slower TLB fault handling.
299 2195
300 If unsure, say N. 2196 If unsure, say N.
301 2197
302 choice 2198 choice
303 prompt "Kernel ABI" !! 2199 prompt "Kernel page size"
304 default KERNEL_ABI_DEFAULT !! 2200 default PAGE_SIZE_4KB
305 help !! 2201
306 Select ABI for the kernel code. This !! 2202 config PAGE_SIZE_4KB
307 supported userspace ABI and any comb !! 2203 bool "4kB"
308 kernel/userspace ABI is possible and !! 2204 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
309 !! 2205 help
310 In case both kernel and userspace su !! 2206 This option select the standard 4kB Linux page size. On some
311 all register windows support code wi !! 2207 R3000-family processors this is the only available page size. Using
312 build. !! 2208 4kB page size will minimize memory consumption and is therefore
313 !! 2209 recommended for low memory systems.
314 If unsure, choose the default ABI. !! 2210
315 !! 2211 config PAGE_SIZE_8KB
316 config KERNEL_ABI_DEFAULT !! 2212 bool "8kB"
317 bool "Default ABI" !! 2213 depends on CPU_CAVIUM_OCTEON
318 help !! 2214 depends on !MIPS_VA_BITS_48
319 Select this option to compile kernel !! 2215 help
320 selected for the toolchain. !! 2216 Using 8kB page size will result in higher performance kernel at
321 Normally cores with windowed registe !! 2217 the price of higher memory consumption. This option is available
322 cores without it use call0 ABI. !! 2218 only on cnMIPS processors. Note that you will need a suitable Linux
323 !! 2219 distribution to support this.
324 config KERNEL_ABI_CALL0 !! 2220
325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI !! 2221 config PAGE_SIZE_16KB
326 help !! 2222 bool "16kB"
327 Select this option to compile kernel !! 2223 depends on !CPU_R3000 && !CPU_TX39XX
328 toolchain that defaults to windowed !! 2224 help
329 When this option is not selected the !! 2225 Using 16kB page size will result in higher performance kernel at
330 be used for the kernel code. !! 2226 the price of higher memory consumption. This option is available on
>> 2227 all non-R3000 family processors. Note that you will need a suitable
>> 2228 Linux distribution to support this.
>> 2229
>> 2230 config PAGE_SIZE_32KB
>> 2231 bool "32kB"
>> 2232 depends on CPU_CAVIUM_OCTEON
>> 2233 depends on !MIPS_VA_BITS_48
>> 2234 help
>> 2235 Using 32kB page size will result in higher performance kernel at
>> 2236 the price of higher memory consumption. This option is available
>> 2237 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2238 distribution to support this.
>> 2239
>> 2240 config PAGE_SIZE_64KB
>> 2241 bool "64kB"
>> 2242 depends on !CPU_R3000 && !CPU_TX39XX
>> 2243 help
>> 2244 Using 64kB page size will result in higher performance kernel at
>> 2245 the price of higher memory consumption. This option is available on
>> 2246 all non-R3000 family processor. Not that at the time of this
>> 2247 writing this option is still high experimental.
331 2248
332 endchoice 2249 endchoice
333 2250
334 config USER_ABI_CALL0 !! 2251 config FORCE_MAX_ZONEORDER
>> 2252 int "Maximum zone order"
>> 2253 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2254 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2255 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2256 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2257 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2258 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2259 range 11 64
>> 2260 default "11"
>> 2261 help
>> 2262 The kernel memory allocator divides physically contiguous memory
>> 2263 blocks into "zones", where each zone is a power of two number of
>> 2264 pages. This option selects the largest power of two that the kernel
>> 2265 keeps in the memory allocator. If you need to allocate very large
>> 2266 blocks of physically contiguous memory, then you may need to
>> 2267 increase this value.
>> 2268
>> 2269 This config option is actually maximum order plus one. For example,
>> 2270 a value of 11 means that the largest free memory block is 2^10 pages.
>> 2271
>> 2272 The page size is not necessarily 4KB. Keep this in mind
>> 2273 when choosing a value for this option.
>> 2274
>> 2275 config BOARD_SCACHE
335 bool 2276 bool
336 2277
337 choice !! 2278 config IP22_CPU_SCACHE
338 prompt "Userspace ABI" !! 2279 bool
339 default USER_ABI_DEFAULT !! 2280 select BOARD_SCACHE
340 help <<
341 Select supported userspace ABI. <<
342 2281
343 If unsure, choose the default ABI. !! 2282 #
>> 2283 # Support for a MIPS32 / MIPS64 style S-caches
>> 2284 #
>> 2285 config MIPS_CPU_SCACHE
>> 2286 bool
>> 2287 select BOARD_SCACHE
344 2288
345 config USER_ABI_DEFAULT !! 2289 config R5000_CPU_SCACHE
346 bool "Default ABI only" !! 2290 bool
347 help !! 2291 select BOARD_SCACHE
348 Assume default userspace ABI. For XE <<
349 call0 ABI binaries may be run on suc <<
350 will not work correctly for them. <<
351 2292
352 config USER_ABI_CALL0_ONLY !! 2293 config RM7000_CPU_SCACHE
353 bool "Call0 ABI only" !! 2294 bool
354 select USER_ABI_CALL0 !! 2295 select BOARD_SCACHE
>> 2296
>> 2297 config SIBYTE_DMA_PAGEOPS
>> 2298 bool "Use DMA to clear/copy pages"
>> 2299 depends on CPU_SB1
355 help 2300 help
356 Select this option to support only c !! 2301 Instead of using the CPU to zero and copy pages, use a Data Mover
357 Windowed ABI binaries will crash wit !! 2302 channel. These DMA channels are otherwise unused by the standard
358 an illegal instruction exception on !! 2303 SiByte Linux port. Seems to give a small performance benefit.
>> 2304
>> 2305 config CPU_HAS_PREFETCH
>> 2306 bool
359 2307
360 Choose this option if you're plannin !! 2308 config CPU_GENERIC_DUMP_TLB
361 built with call0 ABI. !! 2309 bool
>> 2310 default y if !(CPU_R3000 || CPU_TX39XX)
362 2311
363 config USER_ABI_CALL0_PROBE !! 2312 config MIPS_FP_SUPPORT
364 bool "Support both windowed and call0 !! 2313 bool "Floating Point support" if EXPERT
365 select USER_ABI_CALL0 !! 2314 default y
366 help 2315 help
367 Select this option to support both w !! 2316 Select y to include support for floating point in the kernel
368 ABIs. When enabled all processes are !! 2317 including initialization of FPU hardware, FP context save & restore
369 and a fast user exception handler fo !! 2318 and emulation of an FPU where necessary. Without this support any
370 used to turn on PS.WOE bit on the fi !! 2319 userland program attempting to use floating point instructions will
371 the userspace. !! 2320 receive a SIGILL.
372 2321
373 This option should be enabled for th !! 2322 If you know that your userland will not attempt to use floating point
374 both call0 and windowed ABIs in user !! 2323 instructions then you can say n here to shrink the kernel a little.
375 2324
376 Note that Xtensa ISA does not guaran !! 2325 If unsure, say y.
377 raise an illegal instruction excepti <<
378 PS.WOE is disabled, check whether th <<
379 2326
380 endchoice !! 2327 config CPU_R2300_FPU
>> 2328 bool
>> 2329 depends on MIPS_FP_SUPPORT
>> 2330 default y if CPU_R3000 || CPU_TX39XX
381 2331
382 endmenu !! 2332 config CPU_R3K_TLB
>> 2333 bool
383 2334
384 config XTENSA_CALIBRATE_CCOUNT !! 2335 config CPU_R4K_FPU
385 def_bool n !! 2336 bool
>> 2337 depends on MIPS_FP_SUPPORT
>> 2338 default y if !CPU_R2300_FPU
>> 2339
>> 2340 config CPU_R4K_CACHE_TLB
>> 2341 bool
>> 2342 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2343
>> 2344 config MIPS_MT_SMP
>> 2345 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2346 default y
>> 2347 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2348 select CPU_MIPSR2_IRQ_VI
>> 2349 select CPU_MIPSR2_IRQ_EI
>> 2350 select SYNC_R4K
>> 2351 select MIPS_MT
>> 2352 select SMP
>> 2353 select SMP_UP
>> 2354 select SYS_SUPPORTS_SMP
>> 2355 select SYS_SUPPORTS_SCHED_SMT
>> 2356 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2357 help
>> 2358 This is a kernel model which is known as SMVP. This is supported
>> 2359 on cores with the MT ASE and uses the available VPEs to implement
>> 2360 virtual processors which supports SMP. This is equivalent to the
>> 2361 Intel Hyperthreading feature. For further information go to
>> 2362 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2363
>> 2364 config MIPS_MT
>> 2365 bool
>> 2366
>> 2367 config SCHED_SMT
>> 2368 bool "SMT (multithreading) scheduler support"
>> 2369 depends on SYS_SUPPORTS_SCHED_SMT
>> 2370 default n
386 help 2371 help
387 On some platforms (XT2000, for examp !! 2372 SMT scheduler support improves the CPU scheduler's decision making
388 vary. The frequency can be determin !! 2373 when dealing with MIPS MT enabled cores at a cost of slightly
389 against a well known, fixed frequenc !! 2374 increased overhead in some places. If unsure say N here.
390 2375
391 config SERIAL_CONSOLE !! 2376 config SYS_SUPPORTS_SCHED_SMT
392 def_bool n !! 2377 bool
393 2378
394 config PLATFORM_HAVE_XIP !! 2379 config SYS_SUPPORTS_MULTITHREADING
395 def_bool n !! 2380 bool
396 2381
397 menu "Platform options" !! 2382 config MIPS_MT_FPAFF
>> 2383 bool "Dynamic FPU affinity for FP-intensive threads"
>> 2384 default y
>> 2385 depends on MIPS_MT_SMP
398 2386
399 choice !! 2387 config MIPSR2_TO_R6_EMULATOR
400 prompt "Xtensa System Type" !! 2388 bool "MIPS R2-to-R6 emulator"
401 default XTENSA_PLATFORM_ISS !! 2389 depends on CPU_MIPSR6
>> 2390 depends on MIPS_FP_SUPPORT
>> 2391 default y
>> 2392 help
>> 2393 Choose this option if you want to run non-R6 MIPS userland code.
>> 2394 Even if you say 'Y' here, the emulator will still be disabled by
>> 2395 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2396 The only reason this is a build-time option is to save ~14K from the
>> 2397 final kernel image.
402 2398
403 config XTENSA_PLATFORM_ISS !! 2399 config SYS_SUPPORTS_VPE_LOADER
404 bool "ISS" !! 2400 bool
405 select XTENSA_CALIBRATE_CCOUNT !! 2401 depends on SYS_SUPPORTS_MULTITHREADING
406 select SERIAL_CONSOLE <<
407 help <<
408 ISS is an acronym for Tensilica's In <<
409 <<
410 config XTENSA_PLATFORM_XT2000 <<
411 bool "XT2000" <<
412 help <<
413 XT2000 is the name of Tensilica's fe <<
414 This hardware is capable of running <<
415 <<
416 config XTENSA_PLATFORM_XTFPGA <<
417 bool "XTFPGA" <<
418 select ETHOC if ETHERNET <<
419 select PLATFORM_WANT_DEFAULT_MEM if !M <<
420 select SERIAL_CONSOLE <<
421 select XTENSA_CALIBRATE_CCOUNT <<
422 select PLATFORM_HAVE_XIP <<
423 help 2402 help
424 XTFPGA is the name of Tensilica boar !! 2403 Indicates that the platform supports the VPE loader, and provides
425 This hardware is capable of running !! 2404 physical_memsize.
426 2405
427 endchoice !! 2406 config MIPS_VPE_LOADER
>> 2407 bool "VPE loader support."
>> 2408 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2409 select CPU_MIPSR2_IRQ_VI
>> 2410 select CPU_MIPSR2_IRQ_EI
>> 2411 select MIPS_MT
>> 2412 help
>> 2413 Includes a loader for loading an elf relocatable object
>> 2414 onto another VPE and running it.
428 2415
429 config PLATFORM_NR_IRQS !! 2416 config MIPS_VPE_LOADER_CMP
430 int !! 2417 bool
431 default 3 if XTENSA_PLATFORM_XT2000 !! 2418 default "y"
432 default 0 !! 2419 depends on MIPS_VPE_LOADER && MIPS_CMP
433 2420
434 config XTENSA_CPU_CLOCK !! 2421 config MIPS_VPE_LOADER_MT
435 int "CPU clock rate [MHz]" !! 2422 bool
436 depends on !XTENSA_CALIBRATE_CCOUNT !! 2423 default "y"
437 default 16 !! 2424 depends on MIPS_VPE_LOADER && !MIPS_CMP
438 2425
439 config GENERIC_CALIBRATE_DELAY !! 2426 config MIPS_VPE_LOADER_TOM
440 bool "Auto calibration of the BogoMIPS !! 2427 bool "Load VPE program into memory hidden from linux"
>> 2428 depends on MIPS_VPE_LOADER
>> 2429 default y
441 help 2430 help
442 The BogoMIPS value can easily be der !! 2431 The loader can use memory that is present but has been hidden from
>> 2432 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2433 you to ensure the amount you put in the option and the space your
>> 2434 program requires is less or equal to the amount physically present.
>> 2435
>> 2436 config MIPS_VPE_APSP_API
>> 2437 bool "Enable support for AP/SP API (RTLX)"
>> 2438 depends on MIPS_VPE_LOADER
443 2439
444 config CMDLINE_BOOL !! 2440 config MIPS_VPE_APSP_API_CMP
445 bool "Default bootloader kernel argume !! 2441 bool
>> 2442 default "y"
>> 2443 depends on MIPS_VPE_APSP_API && MIPS_CMP
446 2444
447 config CMDLINE !! 2445 config MIPS_VPE_APSP_API_MT
448 string "Initial kernel command string" !! 2446 bool
449 depends on CMDLINE_BOOL !! 2447 default "y"
450 default "console=ttyS0,38400 root=/dev !! 2448 depends on MIPS_VPE_APSP_API && !MIPS_CMP
451 help <<
452 On some architectures (EBSA110 and C <<
453 for the boot loader to pass argument <<
454 architectures, you should supply som <<
455 time by entering them here. As a min <<
456 memory size and the root device (e.g <<
457 2449
458 config USE_OF !! 2450 config MIPS_CMP
459 bool "Flattened Device Tree support" !! 2451 bool "MIPS CMP framework support (DEPRECATED)"
460 select OF !! 2452 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
461 select OF_EARLY_FLATTREE !! 2453 select SMP
>> 2454 select SYNC_R4K
>> 2455 select SYS_SUPPORTS_SMP
>> 2456 select WEAK_ORDERING
>> 2457 default n
462 help 2458 help
463 Include support for flattened device !! 2459 Select this if you are using a bootloader which implements the "CMP
>> 2460 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2461 its ability to start secondary CPUs.
>> 2462
>> 2463 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2464 instead of this.
>> 2465
>> 2466 config MIPS_CPS
>> 2467 bool "MIPS Coherent Processing System support"
>> 2468 depends on SYS_SUPPORTS_MIPS_CPS
>> 2469 select MIPS_CM
>> 2470 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2471 select SMP
>> 2472 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2473 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2474 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2475 select SYS_SUPPORTS_SMP
>> 2476 select WEAK_ORDERING
>> 2477 help
>> 2478 Select this if you wish to run an SMP kernel across multiple cores
>> 2479 within a MIPS Coherent Processing System. When this option is
>> 2480 enabled the kernel will probe for other cores and boot them with
>> 2481 no external assistance. It is safe to enable this when hardware
>> 2482 support is unavailable.
>> 2483
>> 2484 config MIPS_CPS_PM
>> 2485 depends on MIPS_CPS
>> 2486 bool
>> 2487
>> 2488 config MIPS_CM
>> 2489 bool
>> 2490 select MIPS_CPC
464 2491
465 config BUILTIN_DTB_SOURCE !! 2492 config MIPS_CPC
466 string "DTB to build into the kernel i !! 2493 bool
467 depends on OF <<
468 2494
469 config PARSE_BOOTPARAM !! 2495 config SB1_PASS_2_WORKAROUNDS
470 bool "Parse bootparam block" !! 2496 bool
>> 2497 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
471 default y 2498 default y
472 help <<
473 Parse parameters passed to the kerne <<
474 be disabled if the kernel is known t <<
475 2499
476 If unsure, say Y. !! 2500 config SB1_PASS_2_1_WORKAROUNDS
>> 2501 bool
>> 2502 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2503 default y
477 2504
478 choice 2505 choice
479 prompt "Semihosting interface" !! 2506 prompt "SmartMIPS or microMIPS ASE support"
480 default XTENSA_SIMCALL_ISS <<
481 depends on XTENSA_PLATFORM_ISS <<
482 help <<
483 Choose semihosting interface that wi <<
484 block device and networking. <<
485 2507
486 config XTENSA_SIMCALL_ISS !! 2508 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
487 bool "simcall" !! 2509 bool "None"
488 help 2510 help
489 Use simcall instruction. simcall is !! 2511 Select this if you want neither microMIPS nor SmartMIPS support
490 it does nothing on hardware. <<
491 2512
492 config XTENSA_SIMCALL_GDBIO !! 2513 config CPU_HAS_SMARTMIPS
493 bool "GDBIO" !! 2514 depends on SYS_SUPPORTS_SMARTMIPS
>> 2515 bool "SmartMIPS"
>> 2516 help
>> 2517 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2518 increased security at both hardware and software level for
>> 2519 smartcards. Enabling this option will allow proper use of the
>> 2520 SmartMIPS instructions by Linux applications. However a kernel with
>> 2521 this option will not work on a MIPS core without SmartMIPS core. If
>> 2522 you don't know you probably don't have SmartMIPS and should say N
>> 2523 here.
>> 2524
>> 2525 config CPU_MICROMIPS
>> 2526 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2527 bool "microMIPS"
494 help 2528 help
495 Use break instruction. It is availab !! 2529 When this option is enabled the kernel will be built using the
496 is attached to it via JTAG. !! 2530 microMIPS ISA
497 2531
498 endchoice 2532 endchoice
499 2533
500 config BLK_DEV_SIMDISK !! 2534 config CPU_HAS_MSA
501 tristate "Host file-based simulated bl !! 2535 bool "Support for the MIPS SIMD Architecture"
502 default n !! 2536 depends on CPU_SUPPORTS_MSA
503 depends on XTENSA_PLATFORM_ISS && BLOC !! 2537 depends on MIPS_FP_SUPPORT
504 help !! 2538 depends on 64BIT || MIPS_O32_FP64_SUPPORT
505 Create block devices that map to fil !! 2539 help
506 Device binding to host file may be c !! 2540 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
507 interface provided the device is not !! 2541 and a set of SIMD instructions to operate on them. When this option
508 !! 2542 is enabled the kernel will support allocating & switching MSA
509 config BLK_DEV_SIMDISK_COUNT !! 2543 vector register contexts. If you know that your kernel will only be
510 int "Number of host file-based simulat !! 2544 running on CPUs which do not support MSA or that your userland will
511 range 1 10 !! 2545 not be making use of it then you may wish to say N here to reduce
512 depends on BLK_DEV_SIMDISK !! 2546 the size & complexity of your kernel.
513 default 2 !! 2547
>> 2548 If unsure, say Y.
>> 2549
>> 2550 config CPU_HAS_WB
>> 2551 bool
>> 2552
>> 2553 config XKS01
>> 2554 bool
>> 2555
>> 2556 config CPU_HAS_DIEI
>> 2557 depends on !CPU_DIEI_BROKEN
>> 2558 bool
>> 2559
>> 2560 config CPU_DIEI_BROKEN
>> 2561 bool
>> 2562
>> 2563 config CPU_HAS_RIXI
>> 2564 bool
>> 2565
>> 2566 config CPU_NO_LOAD_STORE_LR
>> 2567 bool
514 help 2568 help
515 This is the default minimal number o !! 2569 CPU lacks support for unaligned load and store instructions:
516 Kernel/module parameter 'simdisk_cou !! 2570 LWL, LWR, SWL, SWR (Load/store word left/right).
517 value at runtime. More file names (b !! 2571 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
518 specified as parameters, simdisk_cou !! 2572 systems).
519 !! 2573
520 config SIMDISK0_FILENAME !! 2574 #
521 string "Host filename for the first si !! 2575 # Vectored interrupt mode is an R2 feature
522 depends on BLK_DEV_SIMDISK = y !! 2576 #
523 default "" !! 2577 config CPU_MIPSR2_IRQ_VI
524 help !! 2578 bool
525 Attach a first simdisk to a host fil !! 2579
526 contains a root file system. !! 2580 #
527 !! 2581 # Extended interrupt mode is an R2 feature
528 config SIMDISK1_FILENAME !! 2582 #
529 string "Host filename for the second s !! 2583 config CPU_MIPSR2_IRQ_EI
530 depends on BLK_DEV_SIMDISK = y && BLK_ !! 2584 bool
531 default "" !! 2585
532 help !! 2586 config CPU_HAS_SYNC
533 Another simulated disk in a host fil !! 2587 bool
534 storage. !! 2588 depends on !CPU_R3000
535 !! 2589 default y
536 config XTFPGA_LCD !! 2590
537 bool "Enable XTFPGA LCD driver" !! 2591 #
538 depends on XTENSA_PLATFORM_XTFPGA !! 2592 # CPU non-features
539 default n !! 2593 #
>> 2594 config CPU_DADDI_WORKAROUNDS
>> 2595 bool
>> 2596
>> 2597 config CPU_R4000_WORKAROUNDS
>> 2598 bool
>> 2599 select CPU_R4400_WORKAROUNDS
>> 2600
>> 2601 config CPU_R4400_WORKAROUNDS
>> 2602 bool
>> 2603
>> 2604 config CPU_R4X00_BUGS64
>> 2605 bool
>> 2606 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
>> 2607
>> 2608 config MIPS_ASID_SHIFT
>> 2609 int
>> 2610 default 6 if CPU_R3000 || CPU_TX39XX
>> 2611 default 0
>> 2612
>> 2613 config MIPS_ASID_BITS
>> 2614 int
>> 2615 default 0 if MIPS_ASID_BITS_VARIABLE
>> 2616 default 6 if CPU_R3000 || CPU_TX39XX
>> 2617 default 8
>> 2618
>> 2619 config MIPS_ASID_BITS_VARIABLE
>> 2620 bool
>> 2621
>> 2622 config MIPS_CRC_SUPPORT
>> 2623 bool
>> 2624
>> 2625 #
>> 2626 # - Highmem only makes sense for the 32-bit kernel.
>> 2627 # - The current highmem code will only work properly on physically indexed
>> 2628 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2629 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2630 # moment we protect the user and offer the highmem option only on machines
>> 2631 # where it's known to be safe. This will not offer highmem on a few systems
>> 2632 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2633 # indexed CPUs but we're playing safe.
>> 2634 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2635 # know they might have memory configurations that could make use of highmem
>> 2636 # support.
>> 2637 #
>> 2638 config HIGHMEM
>> 2639 bool "High Memory Support"
>> 2640 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2641
>> 2642 config CPU_SUPPORTS_HIGHMEM
>> 2643 bool
>> 2644
>> 2645 config SYS_SUPPORTS_HIGHMEM
>> 2646 bool
>> 2647
>> 2648 config SYS_SUPPORTS_SMARTMIPS
>> 2649 bool
>> 2650
>> 2651 config SYS_SUPPORTS_MICROMIPS
>> 2652 bool
>> 2653
>> 2654 config SYS_SUPPORTS_MIPS16
>> 2655 bool
540 help 2656 help
541 There's a 2x16 LCD on most of XTFPGA !! 2657 This option must be set if a kernel might be executed on a MIPS16-
542 progress messages there during bootu !! 2658 enabled CPU even if MIPS16 is not actually being used. In other
543 during board bringup. !! 2659 words, it makes the kernel MIPS16-tolerant.
>> 2660
>> 2661 config CPU_SUPPORTS_MSA
>> 2662 bool
>> 2663
>> 2664 config ARCH_FLATMEM_ENABLE
>> 2665 def_bool y
>> 2666 depends on !NUMA && !CPU_LOONGSON2EF
>> 2667
>> 2668 config ARCH_SPARSEMEM_ENABLE
>> 2669 bool
>> 2670 select SPARSEMEM_STATIC if !SGI_IP27
>> 2671
>> 2672 config NUMA
>> 2673 bool "NUMA Support"
>> 2674 depends on SYS_SUPPORTS_NUMA
>> 2675 help
>> 2676 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2677 Access). This option improves performance on systems with more
>> 2678 than two nodes; on two node systems it is generally better to
>> 2679 leave it disabled; on single node systems disable this option
>> 2680 disabled.
>> 2681
>> 2682 config SYS_SUPPORTS_NUMA
>> 2683 bool
>> 2684
>> 2685 config HAVE_SETUP_PER_CPU_AREA
>> 2686 def_bool y
>> 2687 depends on NUMA
>> 2688
>> 2689 config NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2690 def_bool y
>> 2691 depends on NUMA
>> 2692
>> 2693 config RELOCATABLE
>> 2694 bool "Relocatable kernel"
>> 2695 depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
>> 2696 help
>> 2697 This builds a kernel image that retains relocation information
>> 2698 so it can be loaded someplace besides the default 1MB.
>> 2699 The relocations make the kernel binary about 15% larger,
>> 2700 but are discarded at runtime
>> 2701
>> 2702 config RELOCATION_TABLE_SIZE
>> 2703 hex "Relocation table size"
>> 2704 depends on RELOCATABLE
>> 2705 range 0x0 0x01000000
>> 2706 default "0x00100000"
>> 2707 ---help---
>> 2708 A table of relocation data will be appended to the kernel binary
>> 2709 and parsed at boot to fix up the relocated kernel.
>> 2710
>> 2711 This option allows the amount of space reserved for the table to be
>> 2712 adjusted, although the default of 1Mb should be ok in most cases.
>> 2713
>> 2714 The build will fail and a valid size suggested if this is too small.
>> 2715
>> 2716 If unsure, leave at the default value.
>> 2717
>> 2718 config RANDOMIZE_BASE
>> 2719 bool "Randomize the address of the kernel image"
>> 2720 depends on RELOCATABLE
>> 2721 ---help---
>> 2722 Randomizes the physical and virtual address at which the
>> 2723 kernel image is loaded, as a security feature that
>> 2724 deters exploit attempts relying on knowledge of the location
>> 2725 of kernel internals.
>> 2726
>> 2727 Entropy is generated using any coprocessor 0 registers available.
>> 2728
>> 2729 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
544 2730
545 If unsure, say N. 2731 If unsure, say N.
546 2732
547 config XTFPGA_LCD_BASE_ADDR !! 2733 config RANDOMIZE_BASE_MAX_OFFSET
548 hex "XTFPGA LCD base address" !! 2734 hex "Maximum kASLR offset" if EXPERT
549 depends on XTFPGA_LCD !! 2735 depends on RANDOMIZE_BASE
550 default "0x0d0c0000" !! 2736 range 0x0 0x40000000 if EVA || 64BIT
551 help !! 2737 range 0x0 0x08000000
552 Base address of the LCD controller i !! 2738 default "0x01000000"
553 Different boards from XTFPGA family !! 2739 ---help---
554 addresses. Please consult prototypin !! 2740 When kASLR is active, this provides the maximum offset that will
555 the correct address. Wrong address h !! 2741 be applied to the kernel image. It should be set according to the
556 !! 2742 amount of physical RAM available in the target system minus
557 config XTFPGA_LCD_8BIT_ACCESS !! 2743 PHYSICAL_START and must be a power of 2.
558 bool "Use 8-bit access to XTFPGA LCD" !! 2744
559 depends on XTFPGA_LCD !! 2745 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
560 default n !! 2746 EVA or 64-bit. The default is 16Mb.
>> 2747
>> 2748 config NODES_SHIFT
>> 2749 int
>> 2750 default "6"
>> 2751 depends on NEED_MULTIPLE_NODES
>> 2752
>> 2753 config HW_PERF_EVENTS
>> 2754 bool "Enable hardware performance counter support for perf events"
>> 2755 depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
>> 2756 default y
561 help 2757 help
562 LCD may be connected with 4- or 8-bi !! 2758 Enable hardware performance counter support for perf events. If
563 only be used with 8-bit interface. P !! 2759 disabled, perf events will use software events only.
564 guide for your board for the correct <<
565 <<
566 comment "Kernel memory layout" <<
567 <<
568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX <<
569 bool "Initialize Xtensa MMU inside the <<
570 depends on !XTENSA_VARIANT_FSF && !XTE <<
571 default y if XTENSA_VARIANT_DC233C || <<
572 help <<
573 Earlier version initialized the MMU <<
574 before jumping to _startup in head.S <<
575 it was possible to place a software <<
576 then enter your normal kernel breakp <<
577 to the kernel mappings (0XC0000000). <<
578 <<
579 This unfortunately won't work for U- <<
580 work for using KEXEC to have a hot k <<
581 KDUMP. <<
582 <<
583 So now the MMU is initialized in hea <<
584 use hardware breakpoints (gdb 'hbrea <<
585 xt-gdb can't place a Software Breakp <<
586 to mapping the MMU and after mapping <<
587 was mapped gdb wouldn't remove the b <<
588 PC wouldn't match. Since Hardware Br <<
589 Linux configurations it seems reason <<
590 and leave this older mechanism for u <<
591 not to follow Tensilica's recommenda <<
592 <<
593 Selecting this will cause U-Boot to <<
594 address at 0x00003000 instead of the <<
595 <<
596 If in doubt, say Y. <<
597 <<
598 config XIP_KERNEL <<
599 bool "Kernel Execute-In-Place from ROM <<
600 depends on PLATFORM_HAVE_XIP <<
601 help <<
602 Execute-In-Place allows the kernel t <<
603 directly addressable by the CPU, suc <<
604 space since the text section of the <<
605 to RAM. Read-write sections, such as <<
606 are still copied to RAM. The XIP ker <<
607 it has to run directly from flash, s <<
608 store it. The flash address used to <<
609 and for storing it, is configuration <<
610 say Y here, you must know the proper <<
611 store the kernel image depending on <<
612 <<
613 Also note that the make target becom <<
614 "make Image" or "make uImage". The f <<
615 ROM memory will be arch/xtensa/boot/ <<
616 2760
617 If unsure, say N. !! 2761 config SMP
>> 2762 bool "Multi-Processing support"
>> 2763 depends on SYS_SUPPORTS_SMP
>> 2764 help
>> 2765 This enables support for systems with more than one CPU. If you have
>> 2766 a system with only one CPU, say N. If you have a system with more
>> 2767 than one CPU, say Y.
>> 2768
>> 2769 If you say N here, the kernel will run on uni- and multiprocessor
>> 2770 machines, but will use only one CPU of a multiprocessor machine. If
>> 2771 you say Y here, the kernel will run on many, but not all,
>> 2772 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2773 will run faster if you say N here.
>> 2774
>> 2775 People using multiprocessor machines who say Y here should also say
>> 2776 Y to "Enhanced Real Time Clock Support", below.
>> 2777
>> 2778 See also the SMP-HOWTO available at
>> 2779 <http://www.tldp.org/docs.html#howto>.
>> 2780
>> 2781 If you don't know what to do here, say N.
618 2782
619 config MEMMAP_CACHEATTR !! 2783 config HOTPLUG_CPU
620 hex "Cache attributes for the memory a !! 2784 bool "Support for hot-pluggable CPUs"
621 depends on !MMU !! 2785 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
622 default 0x22222222 !! 2786 help
623 help !! 2787 Say Y here to allow turning CPUs off and on. CPUs can be
624 These cache attributes are set up fo !! 2788 controlled through /sys/devices/system/cpu.
625 specifies cache attributes for the c !! 2789 (Note: power management support will enable this option
626 region: bits 0..3 -- for addresses 0 !! 2790 automatically on SMP systems. )
627 bits 4..7 -- for addresses 0x2000000 !! 2791 Say N if you want to disable CPU hotplug.
628 !! 2792
629 Cache attribute values are specific !! 2793 config SMP_UP
630 For region protection MMUs: !! 2794 bool
631 1: WT cached, !! 2795
632 2: cache bypass, !! 2796 config SYS_SUPPORTS_MIPS_CMP
633 4: WB cached, !! 2797 bool
634 f: illegal. !! 2798
635 For full MMU: !! 2799 config SYS_SUPPORTS_MIPS_CPS
636 bit 0: executable, !! 2800 bool
637 bit 1: writable, !! 2801
638 bits 2..3: !! 2802 config SYS_SUPPORTS_SMP
639 0: cache bypass, !! 2803 bool
640 1: WB cache, !! 2804
641 2: WT cache, !! 2805 config NR_CPUS_DEFAULT_4
642 3: special (c and e are illegal, !! 2806 bool
643 For MPU: <<
644 0: illegal, <<
645 1: WB cache, <<
646 2: WB, no-write-allocate cache, <<
647 3: WT cache, <<
648 4: cache bypass. <<
649 <<
650 config KSEG_PADDR <<
651 hex "Physical address of the KSEG mapp <<
652 depends on INITIALIZE_XTENSA_MMU_INSID <<
653 default 0x00000000 <<
654 help <<
655 This is the physical address where K <<
656 the chosen KSEG layout help for the <<
657 Unpacked kernel image (including vec <<
658 within KSEG. <<
659 Physical memory below this address i <<
660 <<
661 If unsure, leave the default value h <<
662 <<
663 config KERNEL_VIRTUAL_ADDRESS <<
664 hex "Kernel virtual address" <<
665 depends on MMU && XIP_KERNEL <<
666 default 0xd0003000 <<
667 help <<
668 This is the virtual address where th <<
669 XIP kernel may be mapped into KSEG o <<
670 provided here must match kernel load <<
671 KERNEL_LOAD_ADDRESS. <<
672 <<
673 config KERNEL_LOAD_ADDRESS <<
674 hex "Kernel load address" <<
675 default 0x60003000 if !MMU <<
676 default 0x00003000 if MMU && INITIALIZ <<
677 default 0xd0003000 if MMU && !INITIALI <<
678 help <<
679 This is the address where the kernel <<
680 It is virtual address for MMUv2 conf <<
681 for all other configurations. <<
682 2807
683 If unsure, leave the default value h !! 2808 config NR_CPUS_DEFAULT_8
>> 2809 bool
>> 2810
>> 2811 config NR_CPUS_DEFAULT_16
>> 2812 bool
>> 2813
>> 2814 config NR_CPUS_DEFAULT_32
>> 2815 bool
>> 2816
>> 2817 config NR_CPUS_DEFAULT_64
>> 2818 bool
>> 2819
>> 2820 config NR_CPUS
>> 2821 int "Maximum number of CPUs (2-256)"
>> 2822 range 2 256
>> 2823 depends on SMP
>> 2824 default "4" if NR_CPUS_DEFAULT_4
>> 2825 default "8" if NR_CPUS_DEFAULT_8
>> 2826 default "16" if NR_CPUS_DEFAULT_16
>> 2827 default "32" if NR_CPUS_DEFAULT_32
>> 2828 default "64" if NR_CPUS_DEFAULT_64
>> 2829 help
>> 2830 This allows you to specify the maximum number of CPUs which this
>> 2831 kernel will support. The maximum supported value is 32 for 32-bit
>> 2832 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2833 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2834 and 2 for all others.
>> 2835
>> 2836 This is purely to save memory - each supported CPU adds
>> 2837 approximately eight kilobytes to the kernel image. For best
>> 2838 performance should round up your number of processors to the next
>> 2839 power of two.
>> 2840
>> 2841 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2842 bool
>> 2843
>> 2844 config MIPS_NR_CPU_NR_MAP_1024
>> 2845 bool
>> 2846
>> 2847 config MIPS_NR_CPU_NR_MAP
>> 2848 int
>> 2849 depends on SMP
>> 2850 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2851 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
>> 2852
>> 2853 #
>> 2854 # Timer Interrupt Frequency Configuration
>> 2855 #
684 2856
685 choice 2857 choice
686 prompt "Relocatable vectors location" !! 2858 prompt "Timer frequency"
687 default XTENSA_VECTORS_IN_TEXT !! 2859 default HZ_250
688 help 2860 help
689 Choose whether relocatable vectors a !! 2861 Allows the configuration of the timer frequency.
690 or placed separately at runtime. Thi !! 2862
691 configurations without VECBASE regis !! 2863 config HZ_24
692 placed at their hardware-defined loc !! 2864 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
693 !! 2865
694 config XTENSA_VECTORS_IN_TEXT !! 2866 config HZ_48
695 bool "Merge relocatable vectors into k !! 2867 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
696 depends on !MTD_XIP !! 2868
697 help !! 2869 config HZ_100
698 This option puts relocatable vectors !! 2870 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
699 with proper alignment. !! 2871
700 This is a safe choice for most confi !! 2872 config HZ_128
701 !! 2873 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
702 config XTENSA_VECTORS_SEPARATE !! 2874
703 bool "Put relocatable vectors at fixed !! 2875 config HZ_250
704 help !! 2876 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
705 This option puts relocatable vectors !! 2877
706 Vectors are merged with the .init da !! 2878 config HZ_256
707 are copied into their designated loc !! 2879 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
708 Use it to put vectors into IRAM or o !! 2880
709 XIP-aware MTD support. !! 2881 config HZ_1000
>> 2882 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2883
>> 2884 config HZ_1024
>> 2885 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
710 2886
711 endchoice 2887 endchoice
712 2888
713 config VECTORS_ADDR !! 2889 config SYS_SUPPORTS_24HZ
714 hex "Kernel vectors virtual address" !! 2890 bool
715 default 0x00000000 <<
716 depends on XTENSA_VECTORS_SEPARATE <<
717 help <<
718 This is the virtual address of the ( <<
719 It must be within KSEG if MMU is use <<
720 <<
721 config XIP_DATA_ADDR <<
722 hex "XIP kernel data virtual address" <<
723 depends on XIP_KERNEL <<
724 default 0x00000000 <<
725 help <<
726 This is the virtual address where XI <<
727 It must be within KSEG if MMU is use <<
728 2891
729 config PLATFORM_WANT_DEFAULT_MEM !! 2892 config SYS_SUPPORTS_48HZ
730 def_bool n !! 2893 bool
>> 2894
>> 2895 config SYS_SUPPORTS_100HZ
>> 2896 bool
>> 2897
>> 2898 config SYS_SUPPORTS_128HZ
>> 2899 bool
>> 2900
>> 2901 config SYS_SUPPORTS_250HZ
>> 2902 bool
>> 2903
>> 2904 config SYS_SUPPORTS_256HZ
>> 2905 bool
>> 2906
>> 2907 config SYS_SUPPORTS_1000HZ
>> 2908 bool
>> 2909
>> 2910 config SYS_SUPPORTS_1024HZ
>> 2911 bool
>> 2912
>> 2913 config SYS_SUPPORTS_ARBIT_HZ
>> 2914 bool
>> 2915 default y if !SYS_SUPPORTS_24HZ && \
>> 2916 !SYS_SUPPORTS_48HZ && \
>> 2917 !SYS_SUPPORTS_100HZ && \
>> 2918 !SYS_SUPPORTS_128HZ && \
>> 2919 !SYS_SUPPORTS_250HZ && \
>> 2920 !SYS_SUPPORTS_256HZ && \
>> 2921 !SYS_SUPPORTS_1000HZ && \
>> 2922 !SYS_SUPPORTS_1024HZ
731 2923
732 config DEFAULT_MEM_START !! 2924 config HZ
733 hex !! 2925 int
734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !M !! 2926 default 24 if HZ_24
735 default 0x60000000 if PLATFORM_WANT_DE !! 2927 default 48 if HZ_48
736 default 0x00000000 !! 2928 default 100 if HZ_100
>> 2929 default 128 if HZ_128
>> 2930 default 250 if HZ_250
>> 2931 default 256 if HZ_256
>> 2932 default 1000 if HZ_1000
>> 2933 default 1024 if HZ_1024
>> 2934
>> 2935 config SCHED_HRTICK
>> 2936 def_bool HIGH_RES_TIMERS
>> 2937
>> 2938 config KEXEC
>> 2939 bool "Kexec system call"
>> 2940 select KEXEC_CORE
>> 2941 help
>> 2942 kexec is a system call that implements the ability to shutdown your
>> 2943 current kernel, and to start another kernel. It is like a reboot
>> 2944 but it is independent of the system firmware. And like a reboot
>> 2945 you can start any kernel with it, not just Linux.
>> 2946
>> 2947 The name comes from the similarity to the exec system call.
>> 2948
>> 2949 It is an ongoing process to be certain the hardware in a machine
>> 2950 is properly shutdown, so do not be surprised if this code does not
>> 2951 initially work for you. As of this writing the exact hardware
>> 2952 interface is strongly in flux, so no good recommendation can be
>> 2953 made.
>> 2954
>> 2955 config CRASH_DUMP
>> 2956 bool "Kernel crash dumps"
>> 2957 help
>> 2958 Generate crash dump after being started by kexec.
>> 2959 This should be normally only set in special crash dump kernels
>> 2960 which are loaded in the main kernel with kexec-tools into
>> 2961 a specially reserved region and then later executed after
>> 2962 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2963 to a memory address not used by the main kernel or firmware using
>> 2964 PHYSICAL_START.
>> 2965
>> 2966 config PHYSICAL_START
>> 2967 hex "Physical address where the kernel is loaded"
>> 2968 default "0xffffffff84000000"
>> 2969 depends on CRASH_DUMP
>> 2970 help
>> 2971 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2972 If you plan to use kernel for capturing the crash dump change
>> 2973 this value to start of the reserved region (the "X" value as
>> 2974 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2975 passed to the panic-ed kernel).
>> 2976
>> 2977 config SECCOMP
>> 2978 bool "Enable seccomp to safely compute untrusted bytecode"
>> 2979 depends on PROC_FS
>> 2980 default y
737 help 2981 help
738 This is the base address used for bo !! 2982 This kernel feature is useful for number crunching applications
739 in noMMU configurations. !! 2983 that may need to compute untrusted bytecode during their
>> 2984 execution. By using pipes or other transports made available to
>> 2985 the process as file descriptors supporting the read/write
>> 2986 syscalls, it's possible to isolate those applications in
>> 2987 their own address space using seccomp. Once seccomp is
>> 2988 enabled via /proc/<pid>/seccomp, it cannot be disabled
>> 2989 and the task is only allowed to execute a few safe syscalls
>> 2990 defined by each seccomp mode.
>> 2991
>> 2992 If unsure, say Y. Only embedded should say N here.
>> 2993
>> 2994 config MIPS_O32_FP64_SUPPORT
>> 2995 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2996 depends on 32BIT || MIPS32_O32
>> 2997 help
>> 2998 When this is enabled, the kernel will support use of 64-bit floating
>> 2999 point registers with binaries using the O32 ABI along with the
>> 3000 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3001 32-bit MIPS systems this support is at the cost of increasing the
>> 3002 size and complexity of the compiled FPU emulator. Thus if you are
>> 3003 running a MIPS32 system and know that none of your userland binaries
>> 3004 will require 64-bit floating point, you may wish to reduce the size
>> 3005 of your kernel & potentially improve FP emulation performance by
>> 3006 saying N here.
>> 3007
>> 3008 Although binutils currently supports use of this flag the details
>> 3009 concerning its effect upon the O32 ABI in userland are still being
>> 3010 worked on. In order to avoid userland becoming dependant upon current
>> 3011 behaviour before the details have been finalised, this option should
>> 3012 be considered experimental and only enabled by those working upon
>> 3013 said details.
>> 3014
>> 3015 If unsure, say N.
>> 3016
>> 3017 config USE_OF
>> 3018 bool
>> 3019 select OF
>> 3020 select OF_EARLY_FLATTREE
>> 3021 select IRQ_DOMAIN
740 3022
741 If unsure, leave the default value h !! 3023 config UHI_BOOT
>> 3024 bool
>> 3025
>> 3026 config BUILTIN_DTB
>> 3027 bool
742 3028
743 choice 3029 choice
744 prompt "KSEG layout" !! 3030 prompt "Kernel appended dtb support" if USE_OF
745 depends on MMU !! 3031 default MIPS_NO_APPENDED_DTB
746 default XTENSA_KSEG_MMU_V2 <<
747 <<
748 config XTENSA_KSEG_MMU_V2 <<
749 bool "MMUv2: 128MB cached + 128MB unca <<
750 help <<
751 MMUv2 compatible kernel memory map: <<
752 at KSEG_PADDR to 0xd0000000 with cac <<
753 without cache. <<
754 KSEG_PADDR must be aligned to 128MB. <<
755 <<
756 config XTENSA_KSEG_256M <<
757 bool "256MB cached + 256MB uncached" <<
758 depends on INITIALIZE_XTENSA_MMU_INSID <<
759 help <<
760 TLB way 6 maps 256MB starting at KSE <<
761 with cache and to 0xc0000000 without <<
762 KSEG_PADDR must be aligned to 256MB. <<
763 <<
764 config XTENSA_KSEG_512M <<
765 bool "512MB cached + 512MB uncached" <<
766 depends on INITIALIZE_XTENSA_MMU_INSID <<
767 help <<
768 TLB way 6 maps 512MB starting at KSE <<
769 with cache and to 0xc0000000 without <<
770 KSEG_PADDR must be aligned to 256MB. <<
771 3032
>> 3033 config MIPS_NO_APPENDED_DTB
>> 3034 bool "None"
>> 3035 help
>> 3036 Do not enable appended dtb support.
>> 3037
>> 3038 config MIPS_ELF_APPENDED_DTB
>> 3039 bool "vmlinux"
>> 3040 help
>> 3041 With this option, the boot code will look for a device tree binary
>> 3042 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3043 it is empty and the DTB can be appended using binutils command
>> 3044 objcopy:
>> 3045
>> 3046 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3047
>> 3048 This is meant as a backward compatiblity convenience for those
>> 3049 systems with a bootloader that can't be upgraded to accommodate
>> 3050 the documented boot protocol using a device tree.
>> 3051
>> 3052 config MIPS_RAW_APPENDED_DTB
>> 3053 bool "vmlinux.bin or vmlinuz.bin"
>> 3054 help
>> 3055 With this option, the boot code will look for a device tree binary
>> 3056 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3057 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3058
>> 3059 This is meant as a backward compatibility convenience for those
>> 3060 systems with a bootloader that can't be upgraded to accommodate
>> 3061 the documented boot protocol using a device tree.
>> 3062
>> 3063 Beware that there is very little in terms of protection against
>> 3064 this option being confused by leftover garbage in memory that might
>> 3065 look like a DTB header after a reboot if no actual DTB is appended
>> 3066 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3067 if you don't intend to always append a DTB.
772 endchoice 3068 endchoice
773 3069
774 config HIGHMEM !! 3070 choice
775 bool "High Memory Support" !! 3071 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
776 depends on MMU !! 3072 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
777 select KMAP_LOCAL !! 3073 !MIPS_MALTA && \
778 help !! 3074 !CAVIUM_OCTEON_SOC
779 Linux can use the full amount of RAM !! 3075 default MIPS_CMDLINE_FROM_BOOTLOADER
780 default. However, the default MMUv2 !! 3076
781 lowermost 128 MB of memory linearly !! 3077 config MIPS_CMDLINE_FROM_DTB
782 at 0xd0000000 (cached) and 0xd800000 !! 3078 depends on USE_OF
783 When there are more than 128 MB memo !! 3079 bool "Dtb kernel arguments if available"
784 all of it can be "permanently mapped !! 3080
785 The physical memory that's not perma !! 3081 config MIPS_CMDLINE_DTB_EXTEND
786 "high memory". !! 3082 depends on USE_OF
787 !! 3083 bool "Extend dtb kernel arguments with bootloader arguments"
788 If you are compiling a kernel which !! 3084
789 machine with more than 128 MB total !! 3085 config MIPS_CMDLINE_FROM_BOOTLOADER
790 N here. !! 3086 bool "Bootloader kernel arguments if available"
>> 3087
>> 3088 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3089 depends on CMDLINE_BOOL
>> 3090 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3091 endchoice
791 3092
792 If unsure, say Y. !! 3093 endmenu
>> 3094
>> 3095 config LOCKDEP_SUPPORT
>> 3096 bool
>> 3097 default y
>> 3098
>> 3099 config STACKTRACE_SUPPORT
>> 3100 bool
>> 3101 default y
>> 3102
>> 3103 config PGTABLE_LEVELS
>> 3104 int
>> 3105 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3106 default 3 if 64BIT && !PAGE_SIZE_64KB
>> 3107 default 2
>> 3108
>> 3109 config MIPS_AUTO_PFN_OFFSET
>> 3110 bool
>> 3111
>> 3112 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
793 3113
794 config ARCH_FORCE_MAX_ORDER !! 3114 config PCI_DRIVERS_GENERIC
795 int "Order of maximal physically conti !! 3115 select PCI_DOMAINS_GENERIC if PCI
796 default "10" !! 3116 bool
797 help !! 3117
798 The kernel page allocator limits the !! 3118 config PCI_DRIVERS_LEGACY
799 contiguous allocations. The limit is !! 3119 def_bool !PCI_DRIVERS_GENERIC
800 defines the maximal power of two of !! 3120 select NO_GENERIC_PCI_IOPORT_MAP
801 allocated as a single contiguous blo !! 3121 select PCI_DOMAINS if PCI
802 overriding the default setting when !! 3122
803 large blocks of physically contiguou !! 3123 #
>> 3124 # ISA support is now enabled via select. Too many systems still have the one
>> 3125 # or other ISA chip on the board that users don't know about so don't expect
>> 3126 # users to choose the right thing ...
>> 3127 #
>> 3128 config ISA
>> 3129 bool
804 3130
805 Don't change if unsure. !! 3131 config TC
>> 3132 bool "TURBOchannel support"
>> 3133 depends on MACH_DECSTATION
>> 3134 help
>> 3135 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3136 processors. TURBOchannel programming specifications are available
>> 3137 at:
>> 3138 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3139 and:
>> 3140 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3141 Linux driver support status is documented at:
>> 3142 <http://www.linux-mips.org/wiki/DECstation>
>> 3143
>> 3144 config MMU
>> 3145 bool
>> 3146 default y
>> 3147
>> 3148 config ARCH_MMAP_RND_BITS_MIN
>> 3149 default 12 if 64BIT
>> 3150 default 8
>> 3151
>> 3152 config ARCH_MMAP_RND_BITS_MAX
>> 3153 default 18 if 64BIT
>> 3154 default 15
>> 3155
>> 3156 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3157 default 8
>> 3158
>> 3159 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3160 default 15
>> 3161
>> 3162 config I8253
>> 3163 bool
>> 3164 select CLKSRC_I8253
>> 3165 select CLKEVT_I8253
>> 3166 select MIPS_EXTERNAL_TIMER
>> 3167
>> 3168 config ZONE_DMA
>> 3169 bool
>> 3170
>> 3171 config ZONE_DMA32
>> 3172 bool
806 3173
807 endmenu 3174 endmenu
808 3175
>> 3176 config TRAD_SIGNALS
>> 3177 bool
>> 3178
>> 3179 config MIPS32_COMPAT
>> 3180 bool
>> 3181
>> 3182 config COMPAT
>> 3183 bool
>> 3184
>> 3185 config SYSVIPC_COMPAT
>> 3186 bool
>> 3187
>> 3188 config MIPS32_O32
>> 3189 bool "Kernel support for o32 binaries"
>> 3190 depends on 64BIT
>> 3191 select ARCH_WANT_OLD_COMPAT_IPC
>> 3192 select COMPAT
>> 3193 select MIPS32_COMPAT
>> 3194 select SYSVIPC_COMPAT if SYSVIPC
>> 3195 help
>> 3196 Select this option if you want to run o32 binaries. These are pure
>> 3197 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3198 existing binaries are in this format.
>> 3199
>> 3200 If unsure, say Y.
>> 3201
>> 3202 config MIPS32_N32
>> 3203 bool "Kernel support for n32 binaries"
>> 3204 depends on 64BIT
>> 3205 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3206 select COMPAT
>> 3207 select MIPS32_COMPAT
>> 3208 select SYSVIPC_COMPAT if SYSVIPC
>> 3209 help
>> 3210 Select this option if you want to run n32 binaries. These are
>> 3211 64-bit binaries using 32-bit quantities for addressing and certain
>> 3212 data that would normally be 64-bit. They are used in special
>> 3213 cases.
>> 3214
>> 3215 If unsure, say N.
>> 3216
>> 3217 config BINFMT_ELF32
>> 3218 bool
>> 3219 default y if MIPS32_O32 || MIPS32_N32
>> 3220 select ELFCORE
>> 3221
809 menu "Power management options" 3222 menu "Power management options"
810 3223
811 config ARCH_HIBERNATION_POSSIBLE 3224 config ARCH_HIBERNATION_POSSIBLE
812 def_bool y 3225 def_bool y
>> 3226 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3227
>> 3228 config ARCH_SUSPEND_POSSIBLE
>> 3229 def_bool y
>> 3230 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
813 3231
814 source "kernel/power/Kconfig" 3232 source "kernel/power/Kconfig"
815 3233
816 endmenu 3234 endmenu
>> 3235
>> 3236 config MIPS_EXTERNAL_TIMER
>> 3237 bool
>> 3238
>> 3239 menu "CPU Power Management"
>> 3240
>> 3241 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3242 source "drivers/cpufreq/Kconfig"
>> 3243 endif
>> 3244
>> 3245 source "drivers/cpuidle/Kconfig"
>> 3246
>> 3247 endmenu
>> 3248
>> 3249 source "drivers/firmware/Kconfig"
>> 3250
>> 3251 source "arch/mips/kvm/Kconfig"
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