1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 config XTENSA !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ARCH_32BIT_OFF_T !! 4 default y
5 select ARCH_HAS_CPU_CACHE_ALIASING !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_HAS_BINFMT_FLAT if !MMU !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CURRENT_STACK_POINTER !! 7 select ARCH_HAS_CPU_FINALIZE_INIT
8 select ARCH_HAS_DEBUG_VM_PGTABLE !! 8 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
9 select ARCH_HAS_DMA_PREP_COHERENT if M !! 9 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
10 select ARCH_HAS_GCOV_PROFILE_ALL !! 10 select ARCH_HAS_FORTIFY_SOURCE
11 select ARCH_HAS_KCOV 11 select ARCH_HAS_KCOV
12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MM !! 12 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if !! 13 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
14 select ARCH_HAS_DMA_SET_UNCACHED if MM !! 14 select ARCH_HAS_STRNCPY_FROM_USER
15 select ARCH_HAS_STRNCPY_FROM_USER if ! <<
16 select ARCH_HAS_STRNLEN_USER 15 select ARCH_HAS_STRNLEN_USER
17 select ARCH_NEED_CMPXCHG_1_EMU !! 16 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 17 select ARCH_HAS_UBSAN_SANITIZE_ALL
>> 18 select ARCH_HAS_GCOV_PROFILE_ALL
>> 19 select ARCH_KEEP_MEMBLOCK
>> 20 select ARCH_SUPPORTS_UPROBES
>> 21 select ARCH_USE_BUILTIN_BSWAP
>> 22 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
18 select ARCH_USE_MEMTEST 23 select ARCH_USE_MEMTEST
19 select ARCH_USE_QUEUED_RWLOCKS 24 select ARCH_USE_QUEUED_RWLOCKS
20 select ARCH_USE_QUEUED_SPINLOCKS 25 select ARCH_USE_QUEUED_SPINLOCKS
>> 26 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
>> 27 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
21 select ARCH_WANT_IPC_PARSE_VERSION 28 select ARCH_WANT_IPC_PARSE_VERSION
>> 29 select ARCH_WANT_LD_ORPHAN_WARN
22 select BUILDTIME_TABLE_SORT 30 select BUILDTIME_TABLE_SORT
23 select CLONE_BACKWARDS 31 select CLONE_BACKWARDS
24 select COMMON_CLK !! 32 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
25 select DMA_NONCOHERENT_MMAP if MMU !! 33 select CPU_PM if CPU_IDLE
26 select GENERIC_ATOMIC64 !! 34 select GENERIC_ATOMIC64 if !64BIT
>> 35 select GENERIC_CMOS_UPDATE
>> 36 select GENERIC_CPU_AUTOPROBE
>> 37 select GENERIC_GETTIMEOFDAY
>> 38 select GENERIC_IOMAP
>> 39 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW 40 select GENERIC_IRQ_SHOW
>> 41 select GENERIC_ISA_DMA if EISA
>> 42 select GENERIC_LIB_ASHLDI3
>> 43 select GENERIC_LIB_ASHRDI3
28 select GENERIC_LIB_CMPDI2 44 select GENERIC_LIB_CMPDI2
29 select GENERIC_LIB_MULDI3 !! 45 select GENERIC_LIB_LSHRDI3
30 select GENERIC_LIB_UCMPDI2 46 select GENERIC_LIB_UCMPDI2
31 select GENERIC_PCI_IOMAP !! 47 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
32 select GENERIC_SCHED_CLOCK !! 48 select GENERIC_SMP_IDLE_THREAD
33 select GENERIC_IOREMAP if MMU !! 49 select GENERIC_TIME_VSYSCALL
34 select HAVE_ARCH_AUDITSYSCALL !! 50 select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
35 select HAVE_ARCH_JUMP_LABEL if !XIP_KE !! 51 select HAVE_ARCH_COMPILER_H
36 select HAVE_ARCH_KASAN if MMU && !XIP_ !! 52 select HAVE_ARCH_JUMP_LABEL
37 select HAVE_ARCH_KCSAN !! 53 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
>> 54 select HAVE_ARCH_MMAP_RND_BITS if MMU
>> 55 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
38 select HAVE_ARCH_SECCOMP_FILTER 56 select HAVE_ARCH_SECCOMP_FILTER
39 select HAVE_ARCH_TRACEHOOK 57 select HAVE_ARCH_TRACEHOOK
>> 58 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
40 select HAVE_ASM_MODVERSIONS 59 select HAVE_ASM_MODVERSIONS
41 select HAVE_CONTEXT_TRACKING_USER 60 select HAVE_CONTEXT_TRACKING_USER
>> 61 select HAVE_TIF_NOHZ
>> 62 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK 63 select HAVE_DEBUG_KMEMLEAK
>> 64 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_DMA_CONTIGUOUS 65 select HAVE_DMA_CONTIGUOUS
>> 66 select HAVE_DYNAMIC_FTRACE
>> 67 select HAVE_EBPF_JIT if !CPU_MICROMIPS && \
>> 68 !CPU_DADDI_WORKAROUNDS && \
>> 69 !CPU_R4000_WORKAROUNDS && \
>> 70 !CPU_R4400_WORKAROUNDS
44 select HAVE_EXIT_THREAD 71 select HAVE_EXIT_THREAD
>> 72 select HAVE_FAST_GUP
>> 73 select HAVE_FTRACE_MCOUNT_RECORD
>> 74 select HAVE_FUNCTION_GRAPH_TRACER
45 select HAVE_FUNCTION_TRACER 75 select HAVE_FUNCTION_TRACER
46 select HAVE_GCC_PLUGINS if GCC_VERSION !! 76 select HAVE_GCC_PLUGINS
47 select HAVE_HW_BREAKPOINT if PERF_EVEN !! 77 select HAVE_GENERIC_VDSO
>> 78 select HAVE_IOREMAP_PROT
>> 79 select HAVE_IRQ_EXIT_ON_IRQ_STACK
48 select HAVE_IRQ_TIME_ACCOUNTING 80 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_PAGE_SIZE_4KB !! 81 select HAVE_KPROBES
50 select HAVE_PCI !! 82 select HAVE_KRETPROBES
>> 83 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 84 select HAVE_MOD_ARCH_SPECIFIC
>> 85 select HAVE_NMI
51 select HAVE_PERF_EVENTS 86 select HAVE_PERF_EVENTS
>> 87 select HAVE_PERF_REGS
>> 88 select HAVE_PERF_USER_STACK_DUMP
>> 89 select HAVE_REGS_AND_STACK_ACCESS_API
>> 90 select HAVE_RSEQ
>> 91 select HAVE_SPARSE_SYSCALL_NR
52 select HAVE_STACKPROTECTOR 92 select HAVE_STACKPROTECTOR
53 select HAVE_SYSCALL_TRACEPOINTS 93 select HAVE_SYSCALL_TRACEPOINTS
54 select HAVE_VIRT_CPU_ACCOUNTING_GEN !! 94 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
55 select IRQ_DOMAIN !! 95 select IRQ_FORCED_THREADING
>> 96 select ISA if EISA
56 select LOCK_MM_AND_FIND_VMA 97 select LOCK_MM_AND_FIND_VMA
57 select MODULES_USE_ELF_RELA !! 98 select MODULES_USE_ELF_REL if MODULES
>> 99 select MODULES_USE_ELF_RELA if MODULES && 64BIT
58 select PERF_USE_VMALLOC 100 select PERF_USE_VMALLOC
>> 101 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
>> 102 select RTC_LIB
>> 103 select SYSCTL_EXCEPTION_TRACE
59 select TRACE_IRQFLAGS_SUPPORT 104 select TRACE_IRQFLAGS_SUPPORT
>> 105 select ARCH_HAS_ELFCORE_COMPAT
>> 106 select HAVE_ARCH_KCSAN if 64BIT
>> 107
>> 108 config MIPS_FIXUP_BIGPHYS_ADDR
>> 109 bool
>> 110
>> 111 config MIPS_GENERIC
>> 112 bool
>> 113
>> 114 config MACH_INGENIC
>> 115 bool
>> 116 select SYS_SUPPORTS_32BIT_KERNEL
>> 117 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 118 select SYS_SUPPORTS_ZBOOT
>> 119 select DMA_NONCOHERENT
>> 120 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 121 select IRQ_MIPS_CPU
>> 122 select PINCTRL
>> 123 select GPIOLIB
>> 124 select COMMON_CLK
>> 125 select GENERIC_IRQ_CHIP
>> 126 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 127 select USE_OF
>> 128 select CPU_SUPPORTS_CPUFREQ
>> 129 select MIPS_EXTERNAL_TIMER
>> 130
>> 131 menu "Machine selection"
>> 132
>> 133 choice
>> 134 prompt "System type"
>> 135 default MIPS_GENERIC_KERNEL
>> 136
>> 137 config MIPS_GENERIC_KERNEL
>> 138 bool "Generic board-agnostic MIPS kernel"
>> 139 select ARCH_HAS_SETUP_DMA_OPS
>> 140 select MIPS_GENERIC
>> 141 select BOOT_RAW
>> 142 select BUILTIN_DTB
>> 143 select CEVT_R4K
>> 144 select CLKSRC_MIPS_GIC
>> 145 select COMMON_CLK
>> 146 select CPU_MIPSR2_IRQ_EI
>> 147 select CPU_MIPSR2_IRQ_VI
>> 148 select CSRC_R4K
>> 149 select DMA_NONCOHERENT
>> 150 select HAVE_PCI
>> 151 select IRQ_MIPS_CPU
>> 152 select MIPS_AUTO_PFN_OFFSET
>> 153 select MIPS_CPU_SCACHE
>> 154 select MIPS_GIC
>> 155 select MIPS_L1_CACHE_SHIFT_7
>> 156 select NO_EXCEPT_FILL
>> 157 select PCI_DRIVERS_GENERIC
>> 158 select SMP_UP if SMP
>> 159 select SWAP_IO_SPACE
>> 160 select SYS_HAS_CPU_MIPS32_R1
>> 161 select SYS_HAS_CPU_MIPS32_R2
>> 162 select SYS_HAS_CPU_MIPS32_R6
>> 163 select SYS_HAS_CPU_MIPS64_R1
>> 164 select SYS_HAS_CPU_MIPS64_R2
>> 165 select SYS_HAS_CPU_MIPS64_R6
>> 166 select SYS_SUPPORTS_32BIT_KERNEL
>> 167 select SYS_SUPPORTS_64BIT_KERNEL
>> 168 select SYS_SUPPORTS_BIG_ENDIAN
>> 169 select SYS_SUPPORTS_HIGHMEM
>> 170 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 171 select SYS_SUPPORTS_MICROMIPS
>> 172 select SYS_SUPPORTS_MIPS16
>> 173 select SYS_SUPPORTS_MIPS_CPS
>> 174 select SYS_SUPPORTS_MULTITHREADING
>> 175 select SYS_SUPPORTS_RELOCATABLE
>> 176 select SYS_SUPPORTS_SMARTMIPS
>> 177 select SYS_SUPPORTS_ZBOOT
>> 178 select UHI_BOOT
>> 179 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 180 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 181 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 182 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 183 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 184 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 185 select USE_OF
>> 186 help
>> 187 Select this to build a kernel which aims to support multiple boards,
>> 188 generally using a flattened device tree passed from the bootloader
>> 189 using the boot protocol defined in the UHI (Unified Hosting
>> 190 Interface) specification.
>> 191
>> 192 config MIPS_ALCHEMY
>> 193 bool "Alchemy processor based machines"
>> 194 select PHYS_ADDR_T_64BIT
>> 195 select CEVT_R4K
>> 196 select CSRC_R4K
>> 197 select IRQ_MIPS_CPU
>> 198 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 199 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 200 select SYS_HAS_CPU_MIPS32_R1
>> 201 select SYS_SUPPORTS_32BIT_KERNEL
>> 202 select SYS_SUPPORTS_APM_EMULATION
>> 203 select GPIOLIB
>> 204 select SYS_SUPPORTS_ZBOOT
>> 205 select COMMON_CLK
>> 206
>> 207 config AR7
>> 208 bool "Texas Instruments AR7"
>> 209 select BOOT_ELF32
>> 210 select COMMON_CLK
>> 211 select DMA_NONCOHERENT
>> 212 select CEVT_R4K
>> 213 select CSRC_R4K
>> 214 select IRQ_MIPS_CPU
>> 215 select NO_EXCEPT_FILL
>> 216 select SWAP_IO_SPACE
>> 217 select SYS_HAS_CPU_MIPS32_R1
>> 218 select SYS_HAS_EARLY_PRINTK
>> 219 select SYS_SUPPORTS_32BIT_KERNEL
>> 220 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 221 select SYS_SUPPORTS_MIPS16
>> 222 select SYS_SUPPORTS_ZBOOT_UART16550
>> 223 select GPIOLIB
>> 224 select VLYNQ
>> 225 help
>> 226 Support for the Texas Instruments AR7 System-on-a-Chip
>> 227 family: TNETD7100, 7200 and 7300.
>> 228
>> 229 config ATH25
>> 230 bool "Atheros AR231x/AR531x SoC support"
>> 231 select CEVT_R4K
>> 232 select CSRC_R4K
>> 233 select DMA_NONCOHERENT
>> 234 select IRQ_MIPS_CPU
>> 235 select IRQ_DOMAIN
>> 236 select SYS_HAS_CPU_MIPS32_R1
>> 237 select SYS_SUPPORTS_BIG_ENDIAN
>> 238 select SYS_SUPPORTS_32BIT_KERNEL
>> 239 select SYS_HAS_EARLY_PRINTK
>> 240 help
>> 241 Support for Atheros AR231x and Atheros AR531x based boards
>> 242
>> 243 config ATH79
>> 244 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 245 select ARCH_HAS_RESET_CONTROLLER
>> 246 select BOOT_RAW
>> 247 select CEVT_R4K
>> 248 select CSRC_R4K
>> 249 select DMA_NONCOHERENT
>> 250 select GPIOLIB
>> 251 select PINCTRL
>> 252 select COMMON_CLK
>> 253 select IRQ_MIPS_CPU
>> 254 select SYS_HAS_CPU_MIPS32_R2
>> 255 select SYS_HAS_EARLY_PRINTK
>> 256 select SYS_SUPPORTS_32BIT_KERNEL
>> 257 select SYS_SUPPORTS_BIG_ENDIAN
>> 258 select SYS_SUPPORTS_MIPS16
>> 259 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 260 select USE_OF
>> 261 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 262 help
>> 263 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 264
>> 265 config BMIPS_GENERIC
>> 266 bool "Broadcom Generic BMIPS kernel"
>> 267 select ARCH_HAS_RESET_CONTROLLER
>> 268 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 269 select BOOT_RAW
>> 270 select NO_EXCEPT_FILL
>> 271 select USE_OF
>> 272 select CEVT_R4K
>> 273 select CSRC_R4K
>> 274 select SYNC_R4K
>> 275 select COMMON_CLK
>> 276 select BCM6345_L1_IRQ
>> 277 select BCM7038_L1_IRQ
>> 278 select BCM7120_L2_IRQ
>> 279 select BRCMSTB_L2_IRQ
>> 280 select IRQ_MIPS_CPU
>> 281 select DMA_NONCOHERENT
>> 282 select SYS_SUPPORTS_32BIT_KERNEL
>> 283 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 284 select SYS_SUPPORTS_BIG_ENDIAN
>> 285 select SYS_SUPPORTS_HIGHMEM
>> 286 select SYS_HAS_CPU_BMIPS32_3300
>> 287 select SYS_HAS_CPU_BMIPS4350
>> 288 select SYS_HAS_CPU_BMIPS4380
>> 289 select SYS_HAS_CPU_BMIPS5000
>> 290 select SWAP_IO_SPACE
>> 291 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 292 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 293 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 294 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 295 select HARDIRQS_SW_RESEND
>> 296 select HAVE_PCI
>> 297 select PCI_DRIVERS_GENERIC
>> 298 select FW_CFE
60 help 299 help
61 Xtensa processors are 32-bit RISC ma !! 300 Build a generic DT-based kernel image that boots on select
62 primarily for embedded systems. The !! 301 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
63 configurable and extensible. The Li !! 302 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
64 architecture supports all processor !! 303 must be set appropriately for your board.
65 with reasonable minimum requirements !! 304
66 a home page at <http://www.linux-xte !! 305 config BCM47XX
>> 306 bool "Broadcom BCM47XX based boards"
>> 307 select BOOT_RAW
>> 308 select CEVT_R4K
>> 309 select CSRC_R4K
>> 310 select DMA_NONCOHERENT
>> 311 select HAVE_PCI
>> 312 select IRQ_MIPS_CPU
>> 313 select SYS_HAS_CPU_MIPS32_R1
>> 314 select NO_EXCEPT_FILL
>> 315 select SYS_SUPPORTS_32BIT_KERNEL
>> 316 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 317 select SYS_SUPPORTS_MIPS16
>> 318 select SYS_SUPPORTS_ZBOOT
>> 319 select SYS_HAS_EARLY_PRINTK
>> 320 select USE_GENERIC_EARLY_PRINTK_8250
>> 321 select GPIOLIB
>> 322 select LEDS_GPIO_REGISTER
>> 323 select BCM47XX_NVRAM
>> 324 select BCM47XX_SPROM
>> 325 select BCM47XX_SSB if !BCM47XX_BCMA
>> 326 help
>> 327 Support for BCM47XX based boards
>> 328
>> 329 config BCM63XX
>> 330 bool "Broadcom BCM63XX based boards"
>> 331 select BOOT_RAW
>> 332 select CEVT_R4K
>> 333 select CSRC_R4K
>> 334 select SYNC_R4K
>> 335 select DMA_NONCOHERENT
>> 336 select IRQ_MIPS_CPU
>> 337 select SYS_SUPPORTS_32BIT_KERNEL
>> 338 select SYS_SUPPORTS_BIG_ENDIAN
>> 339 select SYS_HAS_EARLY_PRINTK
>> 340 select SYS_HAS_CPU_BMIPS32_3300
>> 341 select SYS_HAS_CPU_BMIPS4350
>> 342 select SYS_HAS_CPU_BMIPS4380
>> 343 select SWAP_IO_SPACE
>> 344 select GPIOLIB
>> 345 select MIPS_L1_CACHE_SHIFT_4
>> 346 select HAVE_LEGACY_CLK
>> 347 help
>> 348 Support for BCM63XX based boards
>> 349
>> 350 config MIPS_COBALT
>> 351 bool "Cobalt Server"
>> 352 select CEVT_R4K
>> 353 select CSRC_R4K
>> 354 select CEVT_GT641XX
>> 355 select DMA_NONCOHERENT
>> 356 select FORCE_PCI
>> 357 select I8253
>> 358 select I8259
>> 359 select IRQ_MIPS_CPU
>> 360 select IRQ_GT641XX
>> 361 select PCI_GT64XXX_PCI0
>> 362 select SYS_HAS_CPU_NEVADA
>> 363 select SYS_HAS_EARLY_PRINTK
>> 364 select SYS_SUPPORTS_32BIT_KERNEL
>> 365 select SYS_SUPPORTS_64BIT_KERNEL
>> 366 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 367 select USE_GENERIC_EARLY_PRINTK_8250
>> 368
>> 369 config MACH_DECSTATION
>> 370 bool "DECstations"
>> 371 select BOOT_ELF32
>> 372 select CEVT_DS1287
>> 373 select CEVT_R4K if CPU_R4X00
>> 374 select CSRC_IOASIC
>> 375 select CSRC_R4K if CPU_R4X00
>> 376 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 377 select CPU_R4000_WORKAROUNDS if 64BIT
>> 378 select CPU_R4400_WORKAROUNDS if 64BIT
>> 379 select DMA_NONCOHERENT
>> 380 select NO_IOPORT_MAP
>> 381 select IRQ_MIPS_CPU
>> 382 select SYS_HAS_CPU_R3000
>> 383 select SYS_HAS_CPU_R4X00
>> 384 select SYS_SUPPORTS_32BIT_KERNEL
>> 385 select SYS_SUPPORTS_64BIT_KERNEL
>> 386 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 387 select SYS_SUPPORTS_128HZ
>> 388 select SYS_SUPPORTS_256HZ
>> 389 select SYS_SUPPORTS_1024HZ
>> 390 select MIPS_L1_CACHE_SHIFT_4
>> 391 help
>> 392 This enables support for DEC's MIPS based workstations. For details
>> 393 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 394 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 395
>> 396 If you have one of the following DECstation Models you definitely
>> 397 want to choose R4xx0 for the CPU Type:
>> 398
>> 399 DECstation 5000/50
>> 400 DECstation 5000/150
>> 401 DECstation 5000/260
>> 402 DECsystem 5900/260
>> 403
>> 404 otherwise choose R3000.
>> 405
>> 406 config MACH_JAZZ
>> 407 bool "Jazz family of machines"
>> 408 select ARC_MEMORY
>> 409 select ARC_PROMLIB
>> 410 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 411 select ARCH_MIGHT_HAVE_PC_SERIO
>> 412 select DMA_OPS
>> 413 select FW_ARC
>> 414 select FW_ARC32
>> 415 select ARCH_MAY_HAVE_PC_FDC
>> 416 select CEVT_R4K
>> 417 select CSRC_R4K
>> 418 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 419 select GENERIC_ISA_DMA
>> 420 select HAVE_PCSPKR_PLATFORM
>> 421 select IRQ_MIPS_CPU
>> 422 select I8253
>> 423 select I8259
>> 424 select ISA
>> 425 select SYS_HAS_CPU_R4X00
>> 426 select SYS_SUPPORTS_32BIT_KERNEL
>> 427 select SYS_SUPPORTS_64BIT_KERNEL
>> 428 select SYS_SUPPORTS_100HZ
>> 429 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 430 help
>> 431 This a family of machines based on the MIPS R4030 chipset which was
>> 432 used by several vendors to build RISC/os and Windows NT workstations.
>> 433 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 434 Olivetti M700-10 workstations.
>> 435
>> 436 config MACH_INGENIC_SOC
>> 437 bool "Ingenic SoC based machines"
>> 438 select MIPS_GENERIC
>> 439 select MACH_INGENIC
>> 440 select SYS_SUPPORTS_ZBOOT_UART16550
>> 441 select CPU_SUPPORTS_CPUFREQ
>> 442 select MIPS_EXTERNAL_TIMER
>> 443
>> 444 config LANTIQ
>> 445 bool "Lantiq based platforms"
>> 446 select DMA_NONCOHERENT
>> 447 select IRQ_MIPS_CPU
>> 448 select CEVT_R4K
>> 449 select CSRC_R4K
>> 450 select SYS_HAS_CPU_MIPS32_R1
>> 451 select SYS_HAS_CPU_MIPS32_R2
>> 452 select SYS_SUPPORTS_BIG_ENDIAN
>> 453 select SYS_SUPPORTS_32BIT_KERNEL
>> 454 select SYS_SUPPORTS_MIPS16
>> 455 select SYS_SUPPORTS_MULTITHREADING
>> 456 select SYS_SUPPORTS_VPE_LOADER
>> 457 select SYS_HAS_EARLY_PRINTK
>> 458 select GPIOLIB
>> 459 select SWAP_IO_SPACE
>> 460 select BOOT_RAW
>> 461 select HAVE_LEGACY_CLK
>> 462 select USE_OF
>> 463 select PINCTRL
>> 464 select PINCTRL_LANTIQ
>> 465 select ARCH_HAS_RESET_CONTROLLER
>> 466 select RESET_CONTROLLER
>> 467
>> 468 config MACH_LOONGSON32
>> 469 bool "Loongson 32-bit family of machines"
>> 470 select SYS_SUPPORTS_ZBOOT
>> 471 help
>> 472 This enables support for the Loongson-1 family of machines.
>> 473
>> 474 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 475 the Institute of Computing Technology (ICT), Chinese Academy of
>> 476 Sciences (CAS).
>> 477
>> 478 config MACH_LOONGSON2EF
>> 479 bool "Loongson-2E/F family of machines"
>> 480 select SYS_SUPPORTS_ZBOOT
>> 481 help
>> 482 This enables the support of early Loongson-2E/F family of machines.
>> 483
>> 484 config MACH_LOONGSON64
>> 485 bool "Loongson 64-bit family of machines"
>> 486 select ARCH_DMA_DEFAULT_COHERENT
>> 487 select ARCH_SPARSEMEM_ENABLE
>> 488 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 489 select ARCH_MIGHT_HAVE_PC_SERIO
>> 490 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 491 select BOOT_ELF32
>> 492 select BOARD_SCACHE
>> 493 select CSRC_R4K
>> 494 select CEVT_R4K
>> 495 select CPU_HAS_WB
>> 496 select FORCE_PCI
>> 497 select ISA
>> 498 select I8259
>> 499 select IRQ_MIPS_CPU
>> 500 select NO_EXCEPT_FILL
>> 501 select NR_CPUS_DEFAULT_64
>> 502 select USE_GENERIC_EARLY_PRINTK_8250
>> 503 select PCI_DRIVERS_GENERIC
>> 504 select SYS_HAS_CPU_LOONGSON64
>> 505 select SYS_HAS_EARLY_PRINTK
>> 506 select SYS_SUPPORTS_SMP
>> 507 select SYS_SUPPORTS_HOTPLUG_CPU
>> 508 select SYS_SUPPORTS_NUMA
>> 509 select SYS_SUPPORTS_64BIT_KERNEL
>> 510 select SYS_SUPPORTS_HIGHMEM
>> 511 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 512 select SYS_SUPPORTS_ZBOOT
>> 513 select SYS_SUPPORTS_RELOCATABLE
>> 514 select ZONE_DMA32
>> 515 select COMMON_CLK
>> 516 select USE_OF
>> 517 select BUILTIN_DTB
>> 518 select PCI_HOST_GENERIC
>> 519 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 520 help
>> 521 This enables the support of Loongson-2/3 family of machines.
>> 522
>> 523 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 524 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 525 and Loongson-2F which will be removed), developed by the Institute
>> 526 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 527
>> 528 config MIPS_MALTA
>> 529 bool "MIPS Malta board"
>> 530 select ARCH_MAY_HAVE_PC_FDC
>> 531 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 532 select ARCH_MIGHT_HAVE_PC_SERIO
>> 533 select BOOT_ELF32
>> 534 select BOOT_RAW
>> 535 select BUILTIN_DTB
>> 536 select CEVT_R4K
>> 537 select CLKSRC_MIPS_GIC
>> 538 select COMMON_CLK
>> 539 select CSRC_R4K
>> 540 select DMA_NONCOHERENT
>> 541 select GENERIC_ISA_DMA
>> 542 select HAVE_PCSPKR_PLATFORM
>> 543 select HAVE_PCI
>> 544 select I8253
>> 545 select I8259
>> 546 select IRQ_MIPS_CPU
>> 547 select MIPS_BONITO64
>> 548 select MIPS_CPU_SCACHE
>> 549 select MIPS_GIC
>> 550 select MIPS_L1_CACHE_SHIFT_6
>> 551 select MIPS_MSC
>> 552 select PCI_GT64XXX_PCI0
>> 553 select SMP_UP if SMP
>> 554 select SWAP_IO_SPACE
>> 555 select SYS_HAS_CPU_MIPS32_R1
>> 556 select SYS_HAS_CPU_MIPS32_R2
>> 557 select SYS_HAS_CPU_MIPS32_R3_5
>> 558 select SYS_HAS_CPU_MIPS32_R5
>> 559 select SYS_HAS_CPU_MIPS32_R6
>> 560 select SYS_HAS_CPU_MIPS64_R1
>> 561 select SYS_HAS_CPU_MIPS64_R2
>> 562 select SYS_HAS_CPU_MIPS64_R6
>> 563 select SYS_HAS_CPU_NEVADA
>> 564 select SYS_HAS_CPU_RM7000
>> 565 select SYS_SUPPORTS_32BIT_KERNEL
>> 566 select SYS_SUPPORTS_64BIT_KERNEL
>> 567 select SYS_SUPPORTS_BIG_ENDIAN
>> 568 select SYS_SUPPORTS_HIGHMEM
>> 569 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 570 select SYS_SUPPORTS_MICROMIPS
>> 571 select SYS_SUPPORTS_MIPS16
>> 572 select SYS_SUPPORTS_MIPS_CMP
>> 573 select SYS_SUPPORTS_MIPS_CPS
>> 574 select SYS_SUPPORTS_MULTITHREADING
>> 575 select SYS_SUPPORTS_RELOCATABLE
>> 576 select SYS_SUPPORTS_SMARTMIPS
>> 577 select SYS_SUPPORTS_VPE_LOADER
>> 578 select SYS_SUPPORTS_ZBOOT
>> 579 select USE_OF
>> 580 select WAR_ICACHE_REFILLS
>> 581 select ZONE_DMA32 if 64BIT
>> 582 help
>> 583 This enables support for the MIPS Technologies Malta evaluation
>> 584 board.
>> 585
>> 586 config MACH_PIC32
>> 587 bool "Microchip PIC32 Family"
>> 588 help
>> 589 This enables support for the Microchip PIC32 family of platforms.
>> 590
>> 591 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 592 microcontrollers.
>> 593
>> 594 config MACH_NINTENDO64
>> 595 bool "Nintendo 64 console"
>> 596 select CEVT_R4K
>> 597 select CSRC_R4K
>> 598 select SYS_HAS_CPU_R4300
>> 599 select SYS_SUPPORTS_BIG_ENDIAN
>> 600 select SYS_SUPPORTS_ZBOOT
>> 601 select SYS_SUPPORTS_32BIT_KERNEL
>> 602 select SYS_SUPPORTS_64BIT_KERNEL
>> 603 select DMA_NONCOHERENT
>> 604 select IRQ_MIPS_CPU
>> 605
>> 606 config RALINK
>> 607 bool "Ralink based machines"
>> 608 select CEVT_R4K
>> 609 select COMMON_CLK
>> 610 select CSRC_R4K
>> 611 select BOOT_RAW
>> 612 select DMA_NONCOHERENT
>> 613 select IRQ_MIPS_CPU
>> 614 select USE_OF
>> 615 select SYS_HAS_CPU_MIPS32_R1
>> 616 select SYS_HAS_CPU_MIPS32_R2
>> 617 select SYS_SUPPORTS_32BIT_KERNEL
>> 618 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 619 select SYS_SUPPORTS_MIPS16
>> 620 select SYS_SUPPORTS_ZBOOT
>> 621 select SYS_HAS_EARLY_PRINTK
>> 622 select ARCH_HAS_RESET_CONTROLLER
>> 623 select RESET_CONTROLLER
>> 624
>> 625 config MACH_REALTEK_RTL
>> 626 bool "Realtek RTL838x/RTL839x based machines"
>> 627 select MIPS_GENERIC
>> 628 select DMA_NONCOHERENT
>> 629 select IRQ_MIPS_CPU
>> 630 select CSRC_R4K
>> 631 select CEVT_R4K
>> 632 select SYS_HAS_CPU_MIPS32_R1
>> 633 select SYS_HAS_CPU_MIPS32_R2
>> 634 select SYS_SUPPORTS_BIG_ENDIAN
>> 635 select SYS_SUPPORTS_32BIT_KERNEL
>> 636 select SYS_SUPPORTS_MIPS16
>> 637 select SYS_SUPPORTS_MULTITHREADING
>> 638 select SYS_SUPPORTS_VPE_LOADER
>> 639 select BOOT_RAW
>> 640 select PINCTRL
>> 641 select USE_OF
>> 642
>> 643 config SGI_IP22
>> 644 bool "SGI IP22 (Indy/Indigo2)"
>> 645 select ARC_MEMORY
>> 646 select ARC_PROMLIB
>> 647 select FW_ARC
>> 648 select FW_ARC32
>> 649 select ARCH_MIGHT_HAVE_PC_SERIO
>> 650 select BOOT_ELF32
>> 651 select CEVT_R4K
>> 652 select CSRC_R4K
>> 653 select DEFAULT_SGI_PARTITION
>> 654 select DMA_NONCOHERENT
>> 655 select HAVE_EISA
>> 656 select I8253
>> 657 select I8259
>> 658 select IP22_CPU_SCACHE
>> 659 select IRQ_MIPS_CPU
>> 660 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 661 select SGI_HAS_I8042
>> 662 select SGI_HAS_INDYDOG
>> 663 select SGI_HAS_HAL2
>> 664 select SGI_HAS_SEEQ
>> 665 select SGI_HAS_WD93
>> 666 select SGI_HAS_ZILOG
>> 667 select SWAP_IO_SPACE
>> 668 select SYS_HAS_CPU_R4X00
>> 669 select SYS_HAS_CPU_R5000
>> 670 select SYS_HAS_EARLY_PRINTK
>> 671 select SYS_SUPPORTS_32BIT_KERNEL
>> 672 select SYS_SUPPORTS_64BIT_KERNEL
>> 673 select SYS_SUPPORTS_BIG_ENDIAN
>> 674 select WAR_R4600_V1_INDEX_ICACHEOP
>> 675 select WAR_R4600_V1_HIT_CACHEOP
>> 676 select WAR_R4600_V2_HIT_CACHEOP
>> 677 select MIPS_L1_CACHE_SHIFT_7
>> 678 help
>> 679 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 680 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 681 that runs on these, say Y here.
>> 682
>> 683 config SGI_IP27
>> 684 bool "SGI IP27 (Origin200/2000)"
>> 685 select ARCH_HAS_PHYS_TO_DMA
>> 686 select ARCH_SPARSEMEM_ENABLE
>> 687 select FW_ARC
>> 688 select FW_ARC64
>> 689 select ARC_CMDLINE_ONLY
>> 690 select BOOT_ELF64
>> 691 select DEFAULT_SGI_PARTITION
>> 692 select FORCE_PCI
>> 693 select SYS_HAS_EARLY_PRINTK
>> 694 select HAVE_PCI
>> 695 select IRQ_MIPS_CPU
>> 696 select IRQ_DOMAIN_HIERARCHY
>> 697 select NR_CPUS_DEFAULT_64
>> 698 select PCI_DRIVERS_GENERIC
>> 699 select PCI_XTALK_BRIDGE
>> 700 select SYS_HAS_CPU_R10000
>> 701 select SYS_SUPPORTS_64BIT_KERNEL
>> 702 select SYS_SUPPORTS_BIG_ENDIAN
>> 703 select SYS_SUPPORTS_NUMA
>> 704 select SYS_SUPPORTS_SMP
>> 705 select WAR_R10000_LLSC
>> 706 select MIPS_L1_CACHE_SHIFT_7
>> 707 select NUMA
>> 708 select HAVE_ARCH_NODEDATA_EXTENSION
>> 709 help
>> 710 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 711 workstations. To compile a Linux kernel that runs on these, say Y
>> 712 here.
>> 713
>> 714 config SGI_IP28
>> 715 bool "SGI IP28 (Indigo2 R10k)"
>> 716 select ARC_MEMORY
>> 717 select ARC_PROMLIB
>> 718 select FW_ARC
>> 719 select FW_ARC64
>> 720 select ARCH_MIGHT_HAVE_PC_SERIO
>> 721 select BOOT_ELF64
>> 722 select CEVT_R4K
>> 723 select CSRC_R4K
>> 724 select DEFAULT_SGI_PARTITION
>> 725 select DMA_NONCOHERENT
>> 726 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 727 select IRQ_MIPS_CPU
>> 728 select HAVE_EISA
>> 729 select I8253
>> 730 select I8259
>> 731 select SGI_HAS_I8042
>> 732 select SGI_HAS_INDYDOG
>> 733 select SGI_HAS_HAL2
>> 734 select SGI_HAS_SEEQ
>> 735 select SGI_HAS_WD93
>> 736 select SGI_HAS_ZILOG
>> 737 select SWAP_IO_SPACE
>> 738 select SYS_HAS_CPU_R10000
>> 739 select SYS_HAS_EARLY_PRINTK
>> 740 select SYS_SUPPORTS_64BIT_KERNEL
>> 741 select SYS_SUPPORTS_BIG_ENDIAN
>> 742 select WAR_R10000_LLSC
>> 743 select MIPS_L1_CACHE_SHIFT_7
>> 744 help
>> 745 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 746 kernel that runs on these, say Y here.
>> 747
>> 748 config SGI_IP30
>> 749 bool "SGI IP30 (Octane/Octane2)"
>> 750 select ARCH_HAS_PHYS_TO_DMA
>> 751 select FW_ARC
>> 752 select FW_ARC64
>> 753 select BOOT_ELF64
>> 754 select CEVT_R4K
>> 755 select CSRC_R4K
>> 756 select FORCE_PCI
>> 757 select SYNC_R4K if SMP
>> 758 select ZONE_DMA32
>> 759 select HAVE_PCI
>> 760 select IRQ_MIPS_CPU
>> 761 select IRQ_DOMAIN_HIERARCHY
>> 762 select PCI_DRIVERS_GENERIC
>> 763 select PCI_XTALK_BRIDGE
>> 764 select SYS_HAS_EARLY_PRINTK
>> 765 select SYS_HAS_CPU_R10000
>> 766 select SYS_SUPPORTS_64BIT_KERNEL
>> 767 select SYS_SUPPORTS_BIG_ENDIAN
>> 768 select SYS_SUPPORTS_SMP
>> 769 select WAR_R10000_LLSC
>> 770 select MIPS_L1_CACHE_SHIFT_7
>> 771 select ARC_MEMORY
>> 772 help
>> 773 These are the SGI Octane and Octane2 graphics workstations. To
>> 774 compile a Linux kernel that runs on these, say Y here.
>> 775
>> 776 config SGI_IP32
>> 777 bool "SGI IP32 (O2)"
>> 778 select ARC_MEMORY
>> 779 select ARC_PROMLIB
>> 780 select ARCH_HAS_PHYS_TO_DMA
>> 781 select FW_ARC
>> 782 select FW_ARC32
>> 783 select BOOT_ELF32
>> 784 select CEVT_R4K
>> 785 select CSRC_R4K
>> 786 select DMA_NONCOHERENT
>> 787 select HAVE_PCI
>> 788 select IRQ_MIPS_CPU
>> 789 select R5000_CPU_SCACHE
>> 790 select RM7000_CPU_SCACHE
>> 791 select SYS_HAS_CPU_R5000
>> 792 select SYS_HAS_CPU_R10000 if BROKEN
>> 793 select SYS_HAS_CPU_RM7000
>> 794 select SYS_HAS_CPU_NEVADA
>> 795 select SYS_SUPPORTS_64BIT_KERNEL
>> 796 select SYS_SUPPORTS_BIG_ENDIAN
>> 797 select WAR_ICACHE_REFILLS
>> 798 help
>> 799 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 800
>> 801 config SIBYTE_CRHINE
>> 802 bool "Sibyte BCM91120C-CRhine"
>> 803 select BOOT_ELF32
>> 804 select SIBYTE_BCM1120
>> 805 select SWAP_IO_SPACE
>> 806 select SYS_HAS_CPU_SB1
>> 807 select SYS_SUPPORTS_BIG_ENDIAN
>> 808 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 809
>> 810 config SIBYTE_CARMEL
>> 811 bool "Sibyte BCM91120x-Carmel"
>> 812 select BOOT_ELF32
>> 813 select SIBYTE_BCM1120
>> 814 select SWAP_IO_SPACE
>> 815 select SYS_HAS_CPU_SB1
>> 816 select SYS_SUPPORTS_BIG_ENDIAN
>> 817 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 818
>> 819 config SIBYTE_CRHONE
>> 820 bool "Sibyte BCM91125C-CRhone"
>> 821 select BOOT_ELF32
>> 822 select SIBYTE_BCM1125
>> 823 select SWAP_IO_SPACE
>> 824 select SYS_HAS_CPU_SB1
>> 825 select SYS_SUPPORTS_BIG_ENDIAN
>> 826 select SYS_SUPPORTS_HIGHMEM
>> 827 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 828
>> 829 config SIBYTE_RHONE
>> 830 bool "Sibyte BCM91125E-Rhone"
>> 831 select BOOT_ELF32
>> 832 select SIBYTE_BCM1125H
>> 833 select SWAP_IO_SPACE
>> 834 select SYS_HAS_CPU_SB1
>> 835 select SYS_SUPPORTS_BIG_ENDIAN
>> 836 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 837
>> 838 config SIBYTE_SWARM
>> 839 bool "Sibyte BCM91250A-SWARM"
>> 840 select BOOT_ELF32
>> 841 select HAVE_PATA_PLATFORM
>> 842 select SIBYTE_SB1250
>> 843 select SWAP_IO_SPACE
>> 844 select SYS_HAS_CPU_SB1
>> 845 select SYS_SUPPORTS_BIG_ENDIAN
>> 846 select SYS_SUPPORTS_HIGHMEM
>> 847 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 848 select ZONE_DMA32 if 64BIT
>> 849 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 850
>> 851 config SIBYTE_LITTLESUR
>> 852 bool "Sibyte BCM91250C2-LittleSur"
>> 853 select BOOT_ELF32
>> 854 select HAVE_PATA_PLATFORM
>> 855 select SIBYTE_SB1250
>> 856 select SWAP_IO_SPACE
>> 857 select SYS_HAS_CPU_SB1
>> 858 select SYS_SUPPORTS_BIG_ENDIAN
>> 859 select SYS_SUPPORTS_HIGHMEM
>> 860 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 861 select ZONE_DMA32 if 64BIT
>> 862
>> 863 config SIBYTE_SENTOSA
>> 864 bool "Sibyte BCM91250E-Sentosa"
>> 865 select BOOT_ELF32
>> 866 select SIBYTE_SB1250
>> 867 select SWAP_IO_SPACE
>> 868 select SYS_HAS_CPU_SB1
>> 869 select SYS_SUPPORTS_BIG_ENDIAN
>> 870 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 871 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 872
>> 873 config SIBYTE_BIGSUR
>> 874 bool "Sibyte BCM91480B-BigSur"
>> 875 select BOOT_ELF32
>> 876 select NR_CPUS_DEFAULT_4
>> 877 select SIBYTE_BCM1x80
>> 878 select SWAP_IO_SPACE
>> 879 select SYS_HAS_CPU_SB1
>> 880 select SYS_SUPPORTS_BIG_ENDIAN
>> 881 select SYS_SUPPORTS_HIGHMEM
>> 882 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 883 select ZONE_DMA32 if 64BIT
>> 884 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 885
>> 886 config SNI_RM
>> 887 bool "SNI RM200/300/400"
>> 888 select ARC_MEMORY
>> 889 select ARC_PROMLIB
>> 890 select FW_ARC if CPU_LITTLE_ENDIAN
>> 891 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 892 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 893 select ARCH_MAY_HAVE_PC_FDC
>> 894 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 895 select ARCH_MIGHT_HAVE_PC_SERIO
>> 896 select BOOT_ELF32
>> 897 select CEVT_R4K
>> 898 select CSRC_R4K
>> 899 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 900 select DMA_NONCOHERENT
>> 901 select GENERIC_ISA_DMA
>> 902 select HAVE_EISA
>> 903 select HAVE_PCSPKR_PLATFORM
>> 904 select HAVE_PCI
>> 905 select IRQ_MIPS_CPU
>> 906 select I8253
>> 907 select I8259
>> 908 select ISA
>> 909 select MIPS_L1_CACHE_SHIFT_6
>> 910 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 911 select SYS_HAS_CPU_R4X00
>> 912 select SYS_HAS_CPU_R5000
>> 913 select SYS_HAS_CPU_R10000
>> 914 select R5000_CPU_SCACHE
>> 915 select SYS_HAS_EARLY_PRINTK
>> 916 select SYS_SUPPORTS_32BIT_KERNEL
>> 917 select SYS_SUPPORTS_64BIT_KERNEL
>> 918 select SYS_SUPPORTS_BIG_ENDIAN
>> 919 select SYS_SUPPORTS_HIGHMEM
>> 920 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 921 select WAR_R4600_V2_HIT_CACHEOP
>> 922 help
>> 923 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 924 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 925 Technology and now in turn merged with Fujitsu. Say Y here to
>> 926 support this machine type.
>> 927
>> 928 config MACH_TX49XX
>> 929 bool "Toshiba TX49 series based machines"
>> 930 select WAR_TX49XX_ICACHE_INDEX_INV
>> 931
>> 932 config MIKROTIK_RB532
>> 933 bool "Mikrotik RB532 boards"
>> 934 select CEVT_R4K
>> 935 select CSRC_R4K
>> 936 select DMA_NONCOHERENT
>> 937 select HAVE_PCI
>> 938 select IRQ_MIPS_CPU
>> 939 select SYS_HAS_CPU_MIPS32_R1
>> 940 select SYS_SUPPORTS_32BIT_KERNEL
>> 941 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 942 select SWAP_IO_SPACE
>> 943 select BOOT_RAW
>> 944 select GPIOLIB
>> 945 select MIPS_L1_CACHE_SHIFT_4
>> 946 help
>> 947 Support the Mikrotik(tm) RouterBoard 532 series,
>> 948 based on the IDT RC32434 SoC.
>> 949
>> 950 config CAVIUM_OCTEON_SOC
>> 951 bool "Cavium Networks Octeon SoC based boards"
>> 952 select CEVT_R4K
>> 953 select ARCH_HAS_PHYS_TO_DMA
>> 954 select HAVE_RAPIDIO
>> 955 select PHYS_ADDR_T_64BIT
>> 956 select SYS_SUPPORTS_64BIT_KERNEL
>> 957 select SYS_SUPPORTS_BIG_ENDIAN
>> 958 select EDAC_SUPPORT
>> 959 select EDAC_ATOMIC_SCRUB
>> 960 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 961 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 962 select SYS_HAS_EARLY_PRINTK
>> 963 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 964 select HAVE_PCI
>> 965 select HAVE_PLAT_DELAY
>> 966 select HAVE_PLAT_FW_INIT_CMDLINE
>> 967 select HAVE_PLAT_MEMCPY
>> 968 select ZONE_DMA32
>> 969 select GPIOLIB
>> 970 select USE_OF
>> 971 select ARCH_SPARSEMEM_ENABLE
>> 972 select SYS_SUPPORTS_SMP
>> 973 select NR_CPUS_DEFAULT_64
>> 974 select MIPS_NR_CPU_NR_MAP_1024
>> 975 select BUILTIN_DTB
>> 976 select MTD
>> 977 select MTD_COMPLEX_MAPPINGS
>> 978 select SWIOTLB
>> 979 select SYS_SUPPORTS_RELOCATABLE
>> 980 help
>> 981 This option supports all of the Octeon reference boards from Cavium
>> 982 Networks. It builds a kernel that dynamically determines the Octeon
>> 983 CPU type and supports all known board reference implementations.
>> 984 Some of the supported boards are:
>> 985 EBT3000
>> 986 EBH3000
>> 987 EBH3100
>> 988 Thunder
>> 989 Kodama
>> 990 Hikari
>> 991 Say Y here for most Octeon reference boards.
>> 992
>> 993 endchoice
>> 994
>> 995 source "arch/mips/alchemy/Kconfig"
>> 996 source "arch/mips/ath25/Kconfig"
>> 997 source "arch/mips/ath79/Kconfig"
>> 998 source "arch/mips/bcm47xx/Kconfig"
>> 999 source "arch/mips/bcm63xx/Kconfig"
>> 1000 source "arch/mips/bmips/Kconfig"
>> 1001 source "arch/mips/generic/Kconfig"
>> 1002 source "arch/mips/ingenic/Kconfig"
>> 1003 source "arch/mips/jazz/Kconfig"
>> 1004 source "arch/mips/lantiq/Kconfig"
>> 1005 source "arch/mips/pic32/Kconfig"
>> 1006 source "arch/mips/ralink/Kconfig"
>> 1007 source "arch/mips/sgi-ip27/Kconfig"
>> 1008 source "arch/mips/sibyte/Kconfig"
>> 1009 source "arch/mips/txx9/Kconfig"
>> 1010 source "arch/mips/cavium-octeon/Kconfig"
>> 1011 source "arch/mips/loongson2ef/Kconfig"
>> 1012 source "arch/mips/loongson32/Kconfig"
>> 1013 source "arch/mips/loongson64/Kconfig"
>> 1014
>> 1015 endmenu
67 1016
68 config GENERIC_HWEIGHT 1017 config GENERIC_HWEIGHT
69 def_bool y !! 1018 bool
>> 1019 default y
70 1020
71 config ARCH_HAS_ILOG2_U32 !! 1021 config GENERIC_CALIBRATE_DELAY
72 def_bool n !! 1022 bool
>> 1023 default y
73 1024
74 config ARCH_HAS_ILOG2_U64 !! 1025 config SCHED_OMIT_FRAME_POINTER
75 def_bool n !! 1026 bool
>> 1027 default y
76 1028
77 config ARCH_MTD_XIP !! 1029 #
78 def_bool y !! 1030 # Select some configuration options automatically based on user selections.
>> 1031 #
>> 1032 config FW_ARC
>> 1033 bool
>> 1034
>> 1035 config ARCH_MAY_HAVE_PC_FDC
>> 1036 bool
>> 1037
>> 1038 config BOOT_RAW
>> 1039 bool
>> 1040
>> 1041 config CEVT_BCM1480
>> 1042 bool
>> 1043
>> 1044 config CEVT_DS1287
>> 1045 bool
>> 1046
>> 1047 config CEVT_GT641XX
>> 1048 bool
>> 1049
>> 1050 config CEVT_R4K
>> 1051 bool
>> 1052
>> 1053 config CEVT_SB1250
>> 1054 bool
>> 1055
>> 1056 config CEVT_TXX9
>> 1057 bool
>> 1058
>> 1059 config CSRC_BCM1480
>> 1060 bool
>> 1061
>> 1062 config CSRC_IOASIC
>> 1063 bool
>> 1064
>> 1065 config CSRC_R4K
>> 1066 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1067 bool
>> 1068
>> 1069 config CSRC_SB1250
>> 1070 bool
>> 1071
>> 1072 config MIPS_CLOCK_VSYSCALL
>> 1073 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1074
>> 1075 config GPIO_TXX9
>> 1076 select GPIOLIB
>> 1077 bool
>> 1078
>> 1079 config FW_CFE
>> 1080 bool
>> 1081
>> 1082 config ARCH_SUPPORTS_UPROBES
>> 1083 bool
>> 1084
>> 1085 config DMA_PERDEV_COHERENT
>> 1086 bool
>> 1087 select ARCH_HAS_SETUP_DMA_OPS
>> 1088 select DMA_NONCOHERENT
>> 1089
>> 1090 config DMA_NONCOHERENT
>> 1091 bool
>> 1092 #
>> 1093 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1094 # Attribute bits. It is believed that the uncached access through
>> 1095 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1096 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1097 # significant advantages.
>> 1098 #
>> 1099 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1100 select ARCH_HAS_DMA_PREP_COHERENT
>> 1101 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1102 select ARCH_HAS_DMA_SET_UNCACHED
>> 1103 select DMA_NONCOHERENT_MMAP
>> 1104 select NEED_DMA_MAP_STATE
>> 1105
>> 1106 config SYS_HAS_EARLY_PRINTK
>> 1107 bool
>> 1108
>> 1109 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1110 bool
>> 1111
>> 1112 config MIPS_BONITO64
>> 1113 bool
>> 1114
>> 1115 config MIPS_MSC
>> 1116 bool
>> 1117
>> 1118 config SYNC_R4K
>> 1119 bool
79 1120
80 config NO_IOPORT_MAP 1121 config NO_IOPORT_MAP
81 def_bool n 1122 def_bool n
82 1123
83 config HZ !! 1124 config GENERIC_CSUM
84 int !! 1125 def_bool CPU_NO_LOAD_STORE_LR
85 default 100 <<
86 1126
87 config LOCKDEP_SUPPORT !! 1127 config GENERIC_ISA_DMA
88 def_bool y !! 1128 bool
>> 1129 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1130 select ISA_DMA_API
89 1131
90 config STACKTRACE_SUPPORT !! 1132 config GENERIC_ISA_DMA_SUPPORT_BROKEN
91 def_bool y !! 1133 bool
>> 1134 select GENERIC_ISA_DMA
92 1135
93 config MMU !! 1136 config HAVE_PLAT_DELAY
94 def_bool n !! 1137 bool
95 select PFAULT <<
96 1138
97 config HAVE_XTENSA_GPIO32 !! 1139 config HAVE_PLAT_FW_INIT_CMDLINE
98 def_bool n !! 1140 bool
99 1141
100 config KASAN_SHADOW_OFFSET !! 1142 config HAVE_PLAT_MEMCPY
101 hex !! 1143 bool
102 default 0x6e400000 !! 1144
>> 1145 config ISA_DMA_API
>> 1146 bool
>> 1147
>> 1148 config SYS_SUPPORTS_RELOCATABLE
>> 1149 bool
>> 1150 help
>> 1151 Selected if the platform supports relocating the kernel.
>> 1152 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1153 to allow access to command line and entropy sources.
>> 1154
>> 1155 #
>> 1156 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1157 # answer,so we try hard to limit the available choices. Also the use of a
>> 1158 # choice statement should be more obvious to the user.
>> 1159 #
>> 1160 choice
>> 1161 prompt "Endianness selection"
>> 1162 help
>> 1163 Some MIPS machines can be configured for either little or big endian
>> 1164 byte order. These modes require different kernels and a different
>> 1165 Linux distribution. In general there is one preferred byteorder for a
>> 1166 particular system but some systems are just as commonly used in the
>> 1167 one or the other endianness.
103 1168
104 config CPU_BIG_ENDIAN 1169 config CPU_BIG_ENDIAN
105 def_bool $(success,test "$(shell,echo !! 1170 bool "Big endian"
>> 1171 depends on SYS_SUPPORTS_BIG_ENDIAN
106 1172
107 config CPU_LITTLE_ENDIAN 1173 config CPU_LITTLE_ENDIAN
108 def_bool !CPU_BIG_ENDIAN !! 1174 bool "Little endian"
>> 1175 depends on SYS_SUPPORTS_LITTLE_ENDIAN
>> 1176
>> 1177 endchoice
>> 1178
>> 1179 config EXPORT_UASM
>> 1180 bool
>> 1181
>> 1182 config SYS_SUPPORTS_APM_EMULATION
>> 1183 bool
109 1184
110 config CC_HAVE_CALL0_ABI !! 1185 config SYS_SUPPORTS_BIG_ENDIAN
111 def_bool $(success,test "$(shell,echo !! 1186 bool
>> 1187
>> 1188 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1189 bool
>> 1190
>> 1191 config MIPS_HUGE_TLB_SUPPORT
>> 1192 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
>> 1193
>> 1194 config IRQ_MSP_SLP
>> 1195 bool
>> 1196
>> 1197 config IRQ_MSP_CIC
>> 1198 bool
>> 1199
>> 1200 config IRQ_TXX9
>> 1201 bool
112 1202
113 menu "Processor type and features" !! 1203 config IRQ_GT641XX
>> 1204 bool
>> 1205
>> 1206 config PCI_GT64XXX_PCI0
>> 1207 bool
>> 1208
>> 1209 config PCI_XTALK_BRIDGE
>> 1210 bool
>> 1211
>> 1212 config NO_EXCEPT_FILL
>> 1213 bool
>> 1214
>> 1215 config MIPS_SPRAM
>> 1216 bool
>> 1217
>> 1218 config SWAP_IO_SPACE
>> 1219 bool
>> 1220
>> 1221 config SGI_HAS_INDYDOG
>> 1222 bool
>> 1223
>> 1224 config SGI_HAS_HAL2
>> 1225 bool
>> 1226
>> 1227 config SGI_HAS_SEEQ
>> 1228 bool
>> 1229
>> 1230 config SGI_HAS_WD93
>> 1231 bool
>> 1232
>> 1233 config SGI_HAS_ZILOG
>> 1234 bool
>> 1235
>> 1236 config SGI_HAS_I8042
>> 1237 bool
>> 1238
>> 1239 config DEFAULT_SGI_PARTITION
>> 1240 bool
>> 1241
>> 1242 config FW_ARC32
>> 1243 bool
>> 1244
>> 1245 config FW_SNIPROM
>> 1246 bool
>> 1247
>> 1248 config BOOT_ELF32
>> 1249 bool
>> 1250
>> 1251 config MIPS_L1_CACHE_SHIFT_4
>> 1252 bool
>> 1253
>> 1254 config MIPS_L1_CACHE_SHIFT_5
>> 1255 bool
>> 1256
>> 1257 config MIPS_L1_CACHE_SHIFT_6
>> 1258 bool
>> 1259
>> 1260 config MIPS_L1_CACHE_SHIFT_7
>> 1261 bool
>> 1262
>> 1263 config MIPS_L1_CACHE_SHIFT
>> 1264 int
>> 1265 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1266 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1267 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1268 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1269 default "5"
>> 1270
>> 1271 config ARC_CMDLINE_ONLY
>> 1272 bool
>> 1273
>> 1274 config ARC_CONSOLE
>> 1275 bool "ARC console support"
>> 1276 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
>> 1277
>> 1278 config ARC_MEMORY
>> 1279 bool
>> 1280
>> 1281 config ARC_PROMLIB
>> 1282 bool
>> 1283
>> 1284 config FW_ARC64
>> 1285 bool
>> 1286
>> 1287 config BOOT_ELF64
>> 1288 bool
>> 1289
>> 1290 menu "CPU selection"
114 1291
115 choice 1292 choice
116 prompt "Xtensa Processor Configuration !! 1293 prompt "CPU type"
117 default XTENSA_VARIANT_FSF !! 1294 default CPU_R4X00
118 1295
119 config XTENSA_VARIANT_FSF !! 1296 config CPU_LOONGSON64
120 bool "fsf - default (not generic) conf !! 1297 bool "Loongson 64-bit CPU"
121 select MMU !! 1298 depends on SYS_HAS_CPU_LOONGSON64
>> 1299 select ARCH_HAS_PHYS_TO_DMA
>> 1300 select CPU_MIPSR2
>> 1301 select CPU_HAS_PREFETCH
>> 1302 select CPU_SUPPORTS_64BIT_KERNEL
>> 1303 select CPU_SUPPORTS_HIGHMEM
>> 1304 select CPU_SUPPORTS_HUGEPAGES
>> 1305 select CPU_SUPPORTS_MSA
>> 1306 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1307 select CPU_MIPSR2_IRQ_VI
>> 1308 select DMA_NONCOHERENT
>> 1309 select WEAK_ORDERING
>> 1310 select WEAK_REORDERING_BEYOND_LLSC
>> 1311 select MIPS_ASID_BITS_VARIABLE
>> 1312 select MIPS_PGD_C0_CONTEXT
>> 1313 select MIPS_L1_CACHE_SHIFT_6
>> 1314 select MIPS_FP_SUPPORT
>> 1315 select GPIOLIB
>> 1316 select SWIOTLB
>> 1317 select HAVE_KVM
>> 1318 help
>> 1319 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1320 cores implements the MIPS64R2 instruction set with many extensions,
>> 1321 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1322 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1323 Loongson-2E/2F is not covered here and will be removed in future.
122 1324
123 config XTENSA_VARIANT_DC232B !! 1325 config LOONGSON3_ENHANCEMENT
124 bool "dc232b - Diamond 232L Standard C !! 1326 bool "New Loongson-3 CPU Enhancements"
125 select MMU !! 1327 default n
126 select HAVE_XTENSA_GPIO32 !! 1328 depends on CPU_LOONGSON64
127 help 1329 help
128 This variant refers to Tensilica's D !! 1330 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
129 !! 1331 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
130 config XTENSA_VARIANT_DC233C !! 1332 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
131 bool "dc233c - Diamond 233L Standard C !! 1333 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
132 select MMU !! 1334 Fast TLB refill support, etc.
133 select HAVE_XTENSA_GPIO32 !! 1335
>> 1336 This option enable those enhancements which are not probed at run
>> 1337 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1338 please say 'N' here. If you want a high-performance kernel to run on
>> 1339 new Loongson-3 machines only, please say 'Y' here.
>> 1340
>> 1341 config CPU_LOONGSON3_WORKAROUNDS
>> 1342 bool "Loongson-3 LLSC Workarounds"
>> 1343 default y if SMP
>> 1344 depends on CPU_LOONGSON64
134 help 1345 help
135 This variant refers to Tensilica's D !! 1346 Loongson-3 processors have the llsc issues which require workarounds.
>> 1347 Without workarounds the system may hang unexpectedly.
136 1348
137 config XTENSA_VARIANT_CUSTOM !! 1349 Say Y, unless you know what you are doing.
138 bool "Custom Xtensa processor configur <<
139 select HAVE_XTENSA_GPIO32 <<
140 help <<
141 Select this variant to use a custom <<
142 You will be prompted for a processor <<
143 endchoice <<
144 1350
145 config XTENSA_VARIANT_CUSTOM_NAME !! 1351 config CPU_LOONGSON3_CPUCFG_EMULATION
146 string "Xtensa Processor Custom Core V !! 1352 bool "Emulate the CPUCFG instruction on older Loongson cores"
147 depends on XTENSA_VARIANT_CUSTOM !! 1353 default y
148 help !! 1354 depends on CPU_LOONGSON64
149 Provide the name of a custom Xtensa <<
150 This CORENAME selects arch/xtensa/va <<
151 Don't forget you have to select MMU <<
152 <<
153 config XTENSA_VARIANT_NAME <<
154 string <<
155 default "dc232b" <<
156 default "dc233c" <<
157 default "fsf" <<
158 default XTENSA_VARIANT_CUSTOM_NAME <<
159 <<
160 config XTENSA_VARIANT_MMU <<
161 bool "Core variant has a Full MMU (TLB <<
162 depends on XTENSA_VARIANT_CUSTOM <<
163 default y <<
164 select MMU <<
165 help <<
166 Build a Conventional Kernel with ful <<
167 ie: it supports a TLB with auto-load <<
168 <<
169 config XTENSA_VARIANT_HAVE_PERF_EVENTS <<
170 bool "Core variant has Performance Mon <<
171 depends on XTENSA_VARIANT_CUSTOM <<
172 default n <<
173 help 1355 help
174 Enable if core variant has Performan !! 1356 Loongson-3A R4 and newer have the CPUCFG instruction available for
175 External Registers Interface. !! 1357 userland to query CPU capabilities, much like CPUID on x86. This
>> 1358 option provides emulation of the instruction on older Loongson
>> 1359 cores, back to Loongson-3A1000.
>> 1360
>> 1361 If unsure, please say Y.
>> 1362
>> 1363 config CPU_LOONGSON2E
>> 1364 bool "Loongson 2E"
>> 1365 depends on SYS_HAS_CPU_LOONGSON2E
>> 1366 select CPU_LOONGSON2EF
>> 1367 help
>> 1368 The Loongson 2E processor implements the MIPS III instruction set
>> 1369 with many extensions.
>> 1370
>> 1371 It has an internal FPGA northbridge, which is compatible to
>> 1372 bonito64.
>> 1373
>> 1374 config CPU_LOONGSON2F
>> 1375 bool "Loongson 2F"
>> 1376 depends on SYS_HAS_CPU_LOONGSON2F
>> 1377 select CPU_LOONGSON2EF
>> 1378 select GPIOLIB
>> 1379 help
>> 1380 The Loongson 2F processor implements the MIPS III instruction set
>> 1381 with many extensions.
>> 1382
>> 1383 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1384 have a similar programming interface with FPGA northbridge used in
>> 1385 Loongson2E.
>> 1386
>> 1387 config CPU_LOONGSON1B
>> 1388 bool "Loongson 1B"
>> 1389 depends on SYS_HAS_CPU_LOONGSON1B
>> 1390 select CPU_LOONGSON32
>> 1391 select LEDS_GPIO_REGISTER
>> 1392 help
>> 1393 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1394 Release 1 instruction set and part of the MIPS32 Release 2
>> 1395 instruction set.
>> 1396
>> 1397 config CPU_LOONGSON1C
>> 1398 bool "Loongson 1C"
>> 1399 depends on SYS_HAS_CPU_LOONGSON1C
>> 1400 select CPU_LOONGSON32
>> 1401 select LEDS_GPIO_REGISTER
>> 1402 help
>> 1403 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1404 Release 1 instruction set and part of the MIPS32 Release 2
>> 1405 instruction set.
>> 1406
>> 1407 config CPU_MIPS32_R1
>> 1408 bool "MIPS32 Release 1"
>> 1409 depends on SYS_HAS_CPU_MIPS32_R1
>> 1410 select CPU_HAS_PREFETCH
>> 1411 select CPU_SUPPORTS_32BIT_KERNEL
>> 1412 select CPU_SUPPORTS_HIGHMEM
>> 1413 help
>> 1414 Choose this option to build a kernel for release 1 or later of the
>> 1415 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1416 MIPS processor are based on a MIPS32 processor. If you know the
>> 1417 specific type of processor in your system, choose those that one
>> 1418 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1419 Release 2 of the MIPS32 architecture is available since several
>> 1420 years so chances are you even have a MIPS32 Release 2 processor
>> 1421 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1422 performance.
>> 1423
>> 1424 config CPU_MIPS32_R2
>> 1425 bool "MIPS32 Release 2"
>> 1426 depends on SYS_HAS_CPU_MIPS32_R2
>> 1427 select CPU_HAS_PREFETCH
>> 1428 select CPU_SUPPORTS_32BIT_KERNEL
>> 1429 select CPU_SUPPORTS_HIGHMEM
>> 1430 select CPU_SUPPORTS_MSA
>> 1431 select HAVE_KVM
>> 1432 help
>> 1433 Choose this option to build a kernel for release 2 or later of the
>> 1434 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1435 MIPS processor are based on a MIPS32 processor. If you know the
>> 1436 specific type of processor in your system, choose those that one
>> 1437 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1438
>> 1439 config CPU_MIPS32_R5
>> 1440 bool "MIPS32 Release 5"
>> 1441 depends on SYS_HAS_CPU_MIPS32_R5
>> 1442 select CPU_HAS_PREFETCH
>> 1443 select CPU_SUPPORTS_32BIT_KERNEL
>> 1444 select CPU_SUPPORTS_HIGHMEM
>> 1445 select CPU_SUPPORTS_MSA
>> 1446 select HAVE_KVM
>> 1447 select MIPS_O32_FP64_SUPPORT
>> 1448 help
>> 1449 Choose this option to build a kernel for release 5 or later of the
>> 1450 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1451 family, are based on a MIPS32r5 processor. If you own an older
>> 1452 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1453
>> 1454 config CPU_MIPS32_R6
>> 1455 bool "MIPS32 Release 6"
>> 1456 depends on SYS_HAS_CPU_MIPS32_R6
>> 1457 select CPU_HAS_PREFETCH
>> 1458 select CPU_NO_LOAD_STORE_LR
>> 1459 select CPU_SUPPORTS_32BIT_KERNEL
>> 1460 select CPU_SUPPORTS_HIGHMEM
>> 1461 select CPU_SUPPORTS_MSA
>> 1462 select HAVE_KVM
>> 1463 select MIPS_O32_FP64_SUPPORT
>> 1464 help
>> 1465 Choose this option to build a kernel for release 6 or later of the
>> 1466 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1467 family, are based on a MIPS32r6 processor. If you own an older
>> 1468 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1469
>> 1470 config CPU_MIPS64_R1
>> 1471 bool "MIPS64 Release 1"
>> 1472 depends on SYS_HAS_CPU_MIPS64_R1
>> 1473 select CPU_HAS_PREFETCH
>> 1474 select CPU_SUPPORTS_32BIT_KERNEL
>> 1475 select CPU_SUPPORTS_64BIT_KERNEL
>> 1476 select CPU_SUPPORTS_HIGHMEM
>> 1477 select CPU_SUPPORTS_HUGEPAGES
>> 1478 help
>> 1479 Choose this option to build a kernel for release 1 or later of the
>> 1480 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1481 MIPS processor are based on a MIPS64 processor. If you know the
>> 1482 specific type of processor in your system, choose those that one
>> 1483 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1484 Release 2 of the MIPS64 architecture is available since several
>> 1485 years so chances are you even have a MIPS64 Release 2 processor
>> 1486 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1487 performance.
>> 1488
>> 1489 config CPU_MIPS64_R2
>> 1490 bool "MIPS64 Release 2"
>> 1491 depends on SYS_HAS_CPU_MIPS64_R2
>> 1492 select CPU_HAS_PREFETCH
>> 1493 select CPU_SUPPORTS_32BIT_KERNEL
>> 1494 select CPU_SUPPORTS_64BIT_KERNEL
>> 1495 select CPU_SUPPORTS_HIGHMEM
>> 1496 select CPU_SUPPORTS_HUGEPAGES
>> 1497 select CPU_SUPPORTS_MSA
>> 1498 select HAVE_KVM
>> 1499 help
>> 1500 Choose this option to build a kernel for release 2 or later of the
>> 1501 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1502 MIPS processor are based on a MIPS64 processor. If you know the
>> 1503 specific type of processor in your system, choose those that one
>> 1504 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1505
>> 1506 config CPU_MIPS64_R5
>> 1507 bool "MIPS64 Release 5"
>> 1508 depends on SYS_HAS_CPU_MIPS64_R5
>> 1509 select CPU_HAS_PREFETCH
>> 1510 select CPU_SUPPORTS_32BIT_KERNEL
>> 1511 select CPU_SUPPORTS_64BIT_KERNEL
>> 1512 select CPU_SUPPORTS_HIGHMEM
>> 1513 select CPU_SUPPORTS_HUGEPAGES
>> 1514 select CPU_SUPPORTS_MSA
>> 1515 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1516 select HAVE_KVM
>> 1517 help
>> 1518 Choose this option to build a kernel for release 5 or later of the
>> 1519 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1520 release partly implementing release 6 features. Though there is no
>> 1521 any hardware known to be based on this release.
>> 1522
>> 1523 config CPU_MIPS64_R6
>> 1524 bool "MIPS64 Release 6"
>> 1525 depends on SYS_HAS_CPU_MIPS64_R6
>> 1526 select CPU_HAS_PREFETCH
>> 1527 select CPU_NO_LOAD_STORE_LR
>> 1528 select CPU_SUPPORTS_32BIT_KERNEL
>> 1529 select CPU_SUPPORTS_64BIT_KERNEL
>> 1530 select CPU_SUPPORTS_HIGHMEM
>> 1531 select CPU_SUPPORTS_HUGEPAGES
>> 1532 select CPU_SUPPORTS_MSA
>> 1533 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1534 select HAVE_KVM
>> 1535 help
>> 1536 Choose this option to build a kernel for release 6 or later of the
>> 1537 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1538 family, are based on a MIPS64r6 processor. If you own an older
>> 1539 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1540
>> 1541 config CPU_P5600
>> 1542 bool "MIPS Warrior P5600"
>> 1543 depends on SYS_HAS_CPU_P5600
>> 1544 select CPU_HAS_PREFETCH
>> 1545 select CPU_SUPPORTS_32BIT_KERNEL
>> 1546 select CPU_SUPPORTS_HIGHMEM
>> 1547 select CPU_SUPPORTS_MSA
>> 1548 select CPU_SUPPORTS_CPUFREQ
>> 1549 select CPU_MIPSR2_IRQ_VI
>> 1550 select CPU_MIPSR2_IRQ_EI
>> 1551 select HAVE_KVM
>> 1552 select MIPS_O32_FP64_SUPPORT
>> 1553 help
>> 1554 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1555 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1556 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1557 level features like up to six P5600 calculation cores, CM2 with L2
>> 1558 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1559 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1560 eJTAG and PDtrace.
>> 1561
>> 1562 config CPU_R3000
>> 1563 bool "R3000"
>> 1564 depends on SYS_HAS_CPU_R3000
>> 1565 select CPU_HAS_WB
>> 1566 select CPU_R3K_TLB
>> 1567 select CPU_SUPPORTS_32BIT_KERNEL
>> 1568 select CPU_SUPPORTS_HIGHMEM
>> 1569 help
>> 1570 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1571 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1572 *not* work on R4000 machines and vice versa. However, since most
>> 1573 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1574 might be a safe bet. If the resulting kernel does not work,
>> 1575 try to recompile with R3000.
>> 1576
>> 1577 config CPU_R4300
>> 1578 bool "R4300"
>> 1579 depends on SYS_HAS_CPU_R4300
>> 1580 select CPU_SUPPORTS_32BIT_KERNEL
>> 1581 select CPU_SUPPORTS_64BIT_KERNEL
>> 1582 help
>> 1583 MIPS Technologies R4300-series processors.
>> 1584
>> 1585 config CPU_R4X00
>> 1586 bool "R4x00"
>> 1587 depends on SYS_HAS_CPU_R4X00
>> 1588 select CPU_SUPPORTS_32BIT_KERNEL
>> 1589 select CPU_SUPPORTS_64BIT_KERNEL
>> 1590 select CPU_SUPPORTS_HUGEPAGES
>> 1591 help
>> 1592 MIPS Technologies R4000-series processors other than 4300, including
>> 1593 the R4000, R4400, R4600, and 4700.
>> 1594
>> 1595 config CPU_TX49XX
>> 1596 bool "R49XX"
>> 1597 depends on SYS_HAS_CPU_TX49XX
>> 1598 select CPU_HAS_PREFETCH
>> 1599 select CPU_SUPPORTS_32BIT_KERNEL
>> 1600 select CPU_SUPPORTS_64BIT_KERNEL
>> 1601 select CPU_SUPPORTS_HUGEPAGES
>> 1602
>> 1603 config CPU_R5000
>> 1604 bool "R5000"
>> 1605 depends on SYS_HAS_CPU_R5000
>> 1606 select CPU_SUPPORTS_32BIT_KERNEL
>> 1607 select CPU_SUPPORTS_64BIT_KERNEL
>> 1608 select CPU_SUPPORTS_HUGEPAGES
>> 1609 help
>> 1610 MIPS Technologies R5000-series processors other than the Nevada.
>> 1611
>> 1612 config CPU_R5500
>> 1613 bool "R5500"
>> 1614 depends on SYS_HAS_CPU_R5500
>> 1615 select CPU_SUPPORTS_32BIT_KERNEL
>> 1616 select CPU_SUPPORTS_64BIT_KERNEL
>> 1617 select CPU_SUPPORTS_HUGEPAGES
>> 1618 help
>> 1619 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1620 instruction set.
>> 1621
>> 1622 config CPU_NEVADA
>> 1623 bool "RM52xx"
>> 1624 depends on SYS_HAS_CPU_NEVADA
>> 1625 select CPU_SUPPORTS_32BIT_KERNEL
>> 1626 select CPU_SUPPORTS_64BIT_KERNEL
>> 1627 select CPU_SUPPORTS_HUGEPAGES
>> 1628 help
>> 1629 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1630
>> 1631 config CPU_R10000
>> 1632 bool "R10000"
>> 1633 depends on SYS_HAS_CPU_R10000
>> 1634 select CPU_HAS_PREFETCH
>> 1635 select CPU_SUPPORTS_32BIT_KERNEL
>> 1636 select CPU_SUPPORTS_64BIT_KERNEL
>> 1637 select CPU_SUPPORTS_HIGHMEM
>> 1638 select CPU_SUPPORTS_HUGEPAGES
>> 1639 help
>> 1640 MIPS Technologies R10000-series processors.
>> 1641
>> 1642 config CPU_RM7000
>> 1643 bool "RM7000"
>> 1644 depends on SYS_HAS_CPU_RM7000
>> 1645 select CPU_HAS_PREFETCH
>> 1646 select CPU_SUPPORTS_32BIT_KERNEL
>> 1647 select CPU_SUPPORTS_64BIT_KERNEL
>> 1648 select CPU_SUPPORTS_HIGHMEM
>> 1649 select CPU_SUPPORTS_HUGEPAGES
>> 1650
>> 1651 config CPU_SB1
>> 1652 bool "SB1"
>> 1653 depends on SYS_HAS_CPU_SB1
>> 1654 select CPU_SUPPORTS_32BIT_KERNEL
>> 1655 select CPU_SUPPORTS_64BIT_KERNEL
>> 1656 select CPU_SUPPORTS_HIGHMEM
>> 1657 select CPU_SUPPORTS_HUGEPAGES
>> 1658 select WEAK_ORDERING
>> 1659
>> 1660 config CPU_CAVIUM_OCTEON
>> 1661 bool "Cavium Octeon processor"
>> 1662 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1663 select CPU_HAS_PREFETCH
>> 1664 select CPU_SUPPORTS_64BIT_KERNEL
>> 1665 select WEAK_ORDERING
>> 1666 select CPU_SUPPORTS_HIGHMEM
>> 1667 select CPU_SUPPORTS_HUGEPAGES
>> 1668 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1669 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1670 select MIPS_L1_CACHE_SHIFT_7
>> 1671 select HAVE_KVM
>> 1672 help
>> 1673 The Cavium Octeon processor is a highly integrated chip containing
>> 1674 many ethernet hardware widgets for networking tasks. The processor
>> 1675 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1676 Full details can be found at http://www.caviumnetworks.com.
>> 1677
>> 1678 config CPU_BMIPS
>> 1679 bool "Broadcom BMIPS"
>> 1680 depends on SYS_HAS_CPU_BMIPS
>> 1681 select CPU_MIPS32
>> 1682 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1683 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1684 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1685 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1686 select CPU_SUPPORTS_32BIT_KERNEL
>> 1687 select DMA_NONCOHERENT
>> 1688 select IRQ_MIPS_CPU
>> 1689 select SWAP_IO_SPACE
>> 1690 select WEAK_ORDERING
>> 1691 select CPU_SUPPORTS_HIGHMEM
>> 1692 select CPU_HAS_PREFETCH
>> 1693 select CPU_SUPPORTS_CPUFREQ
>> 1694 select MIPS_EXTERNAL_TIMER
>> 1695 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 1696 help
>> 1697 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
176 1698
177 If unsure, say N. !! 1699 endchoice
178 1700
179 config XTENSA_FAKE_NMI !! 1701 config CPU_MIPS32_3_5_FEATURES
180 bool "Treat PMM IRQ as NMI" !! 1702 bool "MIPS32 Release 3.5 Features"
181 depends on XTENSA_VARIANT_HAVE_PERF_EV !! 1703 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1704 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1705 CPU_P5600
>> 1706 help
>> 1707 Choose this option to build a kernel for release 2 or later of the
>> 1708 MIPS32 architecture including features from the 3.5 release such as
>> 1709 support for Enhanced Virtual Addressing (EVA).
>> 1710
>> 1711 config CPU_MIPS32_3_5_EVA
>> 1712 bool "Enhanced Virtual Addressing (EVA)"
>> 1713 depends on CPU_MIPS32_3_5_FEATURES
>> 1714 select EVA
>> 1715 default y
>> 1716 help
>> 1717 Choose this option if you want to enable the Enhanced Virtual
>> 1718 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1719 One of its primary benefits is an increase in the maximum size
>> 1720 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1721
>> 1722 config CPU_MIPS32_R5_FEATURES
>> 1723 bool "MIPS32 Release 5 Features"
>> 1724 depends on SYS_HAS_CPU_MIPS32_R5
>> 1725 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1726 help
>> 1727 Choose this option to build a kernel for release 2 or later of the
>> 1728 MIPS32 architecture including features from release 5 such as
>> 1729 support for Extended Physical Addressing (XPA).
>> 1730
>> 1731 config CPU_MIPS32_R5_XPA
>> 1732 bool "Extended Physical Addressing (XPA)"
>> 1733 depends on CPU_MIPS32_R5_FEATURES
>> 1734 depends on !EVA
>> 1735 depends on !PAGE_SIZE_4KB
>> 1736 depends on SYS_SUPPORTS_HIGHMEM
>> 1737 select XPA
>> 1738 select HIGHMEM
>> 1739 select PHYS_ADDR_T_64BIT
182 default n 1740 default n
183 help 1741 help
184 If PMM IRQ is the only IRQ at EXCM l !! 1742 Choose this option if you want to enable the Extended Physical
185 treat it as NMI, which improves accu !! 1743 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1744 benefit is to increase physical addressing equal to or greater
>> 1745 than 40 bits. Note that this has the side effect of turning on
>> 1746 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1747 If unsure, say 'N' here.
186 1748
187 If there are other interrupts at or !! 1749 if CPU_LOONGSON2F
188 but not above the EXCM level, PMM IR !! 1750 config CPU_NOP_WORKAROUNDS
189 but only if these IRQs are not used. !! 1751 bool
190 saying that this is not safe, and a <<
191 actually fire. <<
192 1752
193 If unsure, say N. !! 1753 config CPU_JUMP_WORKAROUNDS
>> 1754 bool
194 1755
195 config PFAULT !! 1756 config CPU_LOONGSON2F_WORKAROUNDS
196 bool "Handle protection faults" if EXP !! 1757 bool "Loongson 2F Workarounds"
197 default y 1758 default y
>> 1759 select CPU_NOP_WORKAROUNDS
>> 1760 select CPU_JUMP_WORKAROUNDS
198 help 1761 help
199 Handle protection faults. MMU config !! 1762 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
200 noMMU configurations may disable it !! 1763 require workarounds. Without workarounds the system may hang
201 generates protection faults or fault !! 1764 unexpectedly. For more information please refer to the gas
>> 1765 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1766
>> 1767 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1768 are needed. The workarounds have no significant side effect on them
>> 1769 but may decrease the performance of the system so this option should
>> 1770 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1771 systems.
202 1772
203 If unsure, say Y. !! 1773 If unsure, please say Y.
>> 1774 endif # CPU_LOONGSON2F
>> 1775
>> 1776 config SYS_SUPPORTS_ZBOOT
>> 1777 bool
>> 1778 select HAVE_KERNEL_GZIP
>> 1779 select HAVE_KERNEL_BZIP2
>> 1780 select HAVE_KERNEL_LZ4
>> 1781 select HAVE_KERNEL_LZMA
>> 1782 select HAVE_KERNEL_LZO
>> 1783 select HAVE_KERNEL_XZ
>> 1784 select HAVE_KERNEL_ZSTD
>> 1785
>> 1786 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1787 bool
>> 1788 select SYS_SUPPORTS_ZBOOT
>> 1789
>> 1790 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1791 bool
>> 1792 select SYS_SUPPORTS_ZBOOT
>> 1793
>> 1794 config CPU_LOONGSON2EF
>> 1795 bool
>> 1796 select CPU_SUPPORTS_32BIT_KERNEL
>> 1797 select CPU_SUPPORTS_64BIT_KERNEL
>> 1798 select CPU_SUPPORTS_HIGHMEM
>> 1799 select CPU_SUPPORTS_HUGEPAGES
>> 1800 select ARCH_HAS_PHYS_TO_DMA
>> 1801
>> 1802 config CPU_LOONGSON32
>> 1803 bool
>> 1804 select CPU_MIPS32
>> 1805 select CPU_MIPSR2
>> 1806 select CPU_HAS_PREFETCH
>> 1807 select CPU_SUPPORTS_32BIT_KERNEL
>> 1808 select CPU_SUPPORTS_HIGHMEM
>> 1809 select CPU_SUPPORTS_CPUFREQ
>> 1810
>> 1811 config CPU_BMIPS32_3300
>> 1812 select SMP_UP if SMP
>> 1813 bool
>> 1814
>> 1815 config CPU_BMIPS4350
>> 1816 bool
>> 1817 select SYS_SUPPORTS_SMP
>> 1818 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1819
>> 1820 config CPU_BMIPS4380
>> 1821 bool
>> 1822 select MIPS_L1_CACHE_SHIFT_6
>> 1823 select SYS_SUPPORTS_SMP
>> 1824 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1825 select CPU_HAS_RIXI
>> 1826
>> 1827 config CPU_BMIPS5000
>> 1828 bool
>> 1829 select MIPS_CPU_SCACHE
>> 1830 select MIPS_L1_CACHE_SHIFT_7
>> 1831 select SYS_SUPPORTS_SMP
>> 1832 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1833 select CPU_HAS_RIXI
>> 1834
>> 1835 config SYS_HAS_CPU_LOONGSON64
>> 1836 bool
>> 1837 select CPU_SUPPORTS_CPUFREQ
>> 1838 select CPU_HAS_RIXI
>> 1839
>> 1840 config SYS_HAS_CPU_LOONGSON2E
>> 1841 bool
>> 1842
>> 1843 config SYS_HAS_CPU_LOONGSON2F
>> 1844 bool
>> 1845 select CPU_SUPPORTS_CPUFREQ
>> 1846 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1847
>> 1848 config SYS_HAS_CPU_LOONGSON1B
>> 1849 bool
>> 1850
>> 1851 config SYS_HAS_CPU_LOONGSON1C
>> 1852 bool
>> 1853
>> 1854 config SYS_HAS_CPU_MIPS32_R1
>> 1855 bool
204 1856
205 config XTENSA_UNALIGNED_USER !! 1857 config SYS_HAS_CPU_MIPS32_R2
206 bool "Unaligned memory access in user !! 1858 bool
>> 1859
>> 1860 config SYS_HAS_CPU_MIPS32_R3_5
>> 1861 bool
>> 1862
>> 1863 config SYS_HAS_CPU_MIPS32_R5
>> 1864 bool
>> 1865 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1866
>> 1867 config SYS_HAS_CPU_MIPS32_R6
>> 1868 bool
>> 1869 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1870
>> 1871 config SYS_HAS_CPU_MIPS64_R1
>> 1872 bool
>> 1873
>> 1874 config SYS_HAS_CPU_MIPS64_R2
>> 1875 bool
>> 1876
>> 1877 config SYS_HAS_CPU_MIPS64_R5
>> 1878 bool
>> 1879 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1880
>> 1881 config SYS_HAS_CPU_MIPS64_R6
>> 1882 bool
>> 1883 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1884
>> 1885 config SYS_HAS_CPU_P5600
>> 1886 bool
>> 1887 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1888
>> 1889 config SYS_HAS_CPU_R3000
>> 1890 bool
>> 1891
>> 1892 config SYS_HAS_CPU_R4300
>> 1893 bool
>> 1894
>> 1895 config SYS_HAS_CPU_R4X00
>> 1896 bool
>> 1897
>> 1898 config SYS_HAS_CPU_TX49XX
>> 1899 bool
>> 1900
>> 1901 config SYS_HAS_CPU_R5000
>> 1902 bool
>> 1903
>> 1904 config SYS_HAS_CPU_R5500
>> 1905 bool
>> 1906
>> 1907 config SYS_HAS_CPU_NEVADA
>> 1908 bool
>> 1909
>> 1910 config SYS_HAS_CPU_R10000
>> 1911 bool
>> 1912 select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>> 1913
>> 1914 config SYS_HAS_CPU_RM7000
>> 1915 bool
>> 1916
>> 1917 config SYS_HAS_CPU_SB1
>> 1918 bool
>> 1919
>> 1920 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1921 bool
>> 1922
>> 1923 config SYS_HAS_CPU_BMIPS
>> 1924 bool
>> 1925
>> 1926 config SYS_HAS_CPU_BMIPS32_3300
>> 1927 bool
>> 1928 select SYS_HAS_CPU_BMIPS
>> 1929
>> 1930 config SYS_HAS_CPU_BMIPS4350
>> 1931 bool
>> 1932 select SYS_HAS_CPU_BMIPS
>> 1933
>> 1934 config SYS_HAS_CPU_BMIPS4380
>> 1935 bool
>> 1936 select SYS_HAS_CPU_BMIPS
>> 1937
>> 1938 config SYS_HAS_CPU_BMIPS5000
>> 1939 bool
>> 1940 select SYS_HAS_CPU_BMIPS
>> 1941 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 1942
>> 1943 #
>> 1944 # CPU may reorder R->R, R->W, W->R, W->W
>> 1945 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1946 #
>> 1947 config WEAK_ORDERING
>> 1948 bool
>> 1949
>> 1950 #
>> 1951 # CPU may reorder reads and writes beyond LL/SC
>> 1952 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 1953 #
>> 1954 config WEAK_REORDERING_BEYOND_LLSC
>> 1955 bool
>> 1956 endmenu
>> 1957
>> 1958 #
>> 1959 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1960 #
>> 1961 config CPU_MIPS32
>> 1962 bool
>> 1963 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1964 CPU_MIPS32_R6 || CPU_P5600
>> 1965
>> 1966 config CPU_MIPS64
>> 1967 bool
>> 1968 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1969 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
>> 1970
>> 1971 #
>> 1972 # These indicate the revision of the architecture
>> 1973 #
>> 1974 config CPU_MIPSR1
>> 1975 bool
>> 1976 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 1977
>> 1978 config CPU_MIPSR2
>> 1979 bool
>> 1980 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 1981 select CPU_HAS_RIXI
>> 1982 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1983 select MIPS_SPRAM
>> 1984
>> 1985 config CPU_MIPSR5
>> 1986 bool
>> 1987 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 1988 select CPU_HAS_RIXI
>> 1989 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1990 select MIPS_SPRAM
>> 1991
>> 1992 config CPU_MIPSR6
>> 1993 bool
>> 1994 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 1995 select CPU_HAS_RIXI
>> 1996 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1997 select HAVE_ARCH_BITREVERSE
>> 1998 select MIPS_ASID_BITS_VARIABLE
>> 1999 select MIPS_CRC_SUPPORT
>> 2000 select MIPS_SPRAM
>> 2001
>> 2002 config TARGET_ISA_REV
>> 2003 int
>> 2004 default 1 if CPU_MIPSR1
>> 2005 default 2 if CPU_MIPSR2
>> 2006 default 5 if CPU_MIPSR5
>> 2007 default 6 if CPU_MIPSR6
>> 2008 default 0
207 help 2009 help
208 The Xtensa architecture currently do !! 2010 Reflects the ISA revision being targeted by the kernel build. This
209 memory accesses in hardware but thro !! 2011 is effectively the Kconfig equivalent of MIPS_ISA_REV.
210 Per default, unaligned memory access !! 2012
>> 2013 config EVA
>> 2014 bool
>> 2015
>> 2016 config XPA
>> 2017 bool
>> 2018
>> 2019 config SYS_SUPPORTS_32BIT_KERNEL
>> 2020 bool
>> 2021 config SYS_SUPPORTS_64BIT_KERNEL
>> 2022 bool
>> 2023 config CPU_SUPPORTS_32BIT_KERNEL
>> 2024 bool
>> 2025 config CPU_SUPPORTS_64BIT_KERNEL
>> 2026 bool
>> 2027 config CPU_SUPPORTS_CPUFREQ
>> 2028 bool
>> 2029 config CPU_SUPPORTS_ADDRWINCFG
>> 2030 bool
>> 2031 config CPU_SUPPORTS_HUGEPAGES
>> 2032 bool
>> 2033 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2034 config MIPS_PGD_C0_CONTEXT
>> 2035 bool
>> 2036 depends on 64BIT
>> 2037 default y if (CPU_MIPSR2 || CPU_MIPSR6)
>> 2038
>> 2039 #
>> 2040 # Set to y for ptrace access to watch registers.
>> 2041 #
>> 2042 config HARDWARE_WATCHPOINTS
>> 2043 bool
>> 2044 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
211 2045
212 Say Y here to enable unaligned memor !! 2046 menu "Kernel type"
213 2047
214 config XTENSA_LOAD_STORE !! 2048 choice
215 bool "Load/store exception handler for !! 2049 prompt "Kernel code model"
216 help 2050 help
217 The Xtensa architecture only allows !! 2051 You should only select this option if you have a workload that
218 instruction bus with l32r and l32i i !! 2052 actually benefits from 64-bit processing or if your machine has
219 instructions raise an exception with !! 2053 large memory. You will only be presented a single option in this
220 This makes it hard to use some confi !! 2054 menu if your system does not support both 32-bit and 64-bit kernels.
221 literals in FLASH memory attached to <<
222 2055
223 Say Y here to enable exception handl !! 2056 config 32BIT
224 byte and 2-byte access to memory att !! 2057 bool "32-bit kernel"
>> 2058 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2059 select TRAD_SIGNALS
>> 2060 help
>> 2061 Select this option if you want to build a 32-bit kernel.
225 2062
226 config HAVE_SMP !! 2063 config 64BIT
227 bool "System Supports SMP (MX)" !! 2064 bool "64-bit kernel"
228 depends on XTENSA_VARIANT_CUSTOM !! 2065 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
229 select XTENSA_MX <<
230 help 2066 help
231 This option is used to indicate that !! 2067 Select this option if you want to build a 64-bit kernel.
232 supports Multiprocessing. Multiproce <<
233 the CPU core definition and currentl <<
234 2068
235 Multiprocessor support is implemente !! 2069 endchoice
236 interrupt controllers. <<
237 2070
238 The MX interrupt distributer adds In !! 2071 config MIPS_VA_BITS_48
239 and causes the IRQ numbers to be inc !! 2072 bool "48 bits virtual memory"
240 like the open cores ethernet driver !! 2073 depends on 64BIT
>> 2074 help
>> 2075 Support a maximum at least 48 bits of application virtual
>> 2076 memory. Default is 40 bits or less, depending on the CPU.
>> 2077 For page sizes 16k and above, this option results in a small
>> 2078 memory overhead for page tables. For 4k page size, a fourth
>> 2079 level of page tables is added which imposes both a memory
>> 2080 overhead as well as slower TLB fault handling.
241 2081
242 You still have to select "Enable SMP !! 2082 If unsure, say N.
243 2083
244 config SMP !! 2084 config ZBOOT_LOAD_ADDRESS
245 bool "Enable Symmetric multi-processin !! 2085 hex "Compressed kernel load address"
246 depends on HAVE_SMP !! 2086 default 0xffffffff80400000 if BCM47XX
247 select GENERIC_SMP_IDLE_THREAD !! 2087 default 0x0
>> 2088 depends on SYS_SUPPORTS_ZBOOT
248 help 2089 help
249 Enabled SMP Software; allows more th !! 2090 The address to load compressed kernel, aka vmlinuz.
250 to be activated during startup. <<
251 2091
252 config NR_CPUS !! 2092 This is only used if non-zero.
253 depends on SMP <<
254 int "Maximum number of CPUs (2-32)" <<
255 range 2 32 <<
256 default "4" <<
257 2093
258 config HOTPLUG_CPU !! 2094 choice
259 bool "Enable CPU hotplug support" !! 2095 prompt "Kernel page size"
260 depends on SMP !! 2096 default PAGE_SIZE_4KB
>> 2097
>> 2098 config PAGE_SIZE_4KB
>> 2099 bool "4kB"
>> 2100 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2101 help
>> 2102 This option select the standard 4kB Linux page size. On some
>> 2103 R3000-family processors this is the only available page size. Using
>> 2104 4kB page size will minimize memory consumption and is therefore
>> 2105 recommended for low memory systems.
>> 2106
>> 2107 config PAGE_SIZE_8KB
>> 2108 bool "8kB"
>> 2109 depends on CPU_CAVIUM_OCTEON
>> 2110 depends on !MIPS_VA_BITS_48
>> 2111 help
>> 2112 Using 8kB page size will result in higher performance kernel at
>> 2113 the price of higher memory consumption. This option is available
>> 2114 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2115 distribution to support this.
>> 2116
>> 2117 config PAGE_SIZE_16KB
>> 2118 bool "16kB"
>> 2119 depends on !CPU_R3000
>> 2120 help
>> 2121 Using 16kB page size will result in higher performance kernel at
>> 2122 the price of higher memory consumption. This option is available on
>> 2123 all non-R3000 family processors. Note that you will need a suitable
>> 2124 Linux distribution to support this.
>> 2125
>> 2126 config PAGE_SIZE_32KB
>> 2127 bool "32kB"
>> 2128 depends on CPU_CAVIUM_OCTEON
>> 2129 depends on !MIPS_VA_BITS_48
>> 2130 help
>> 2131 Using 32kB page size will result in higher performance kernel at
>> 2132 the price of higher memory consumption. This option is available
>> 2133 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2134 distribution to support this.
>> 2135
>> 2136 config PAGE_SIZE_64KB
>> 2137 bool "64kB"
>> 2138 depends on !CPU_R3000
>> 2139 help
>> 2140 Using 64kB page size will result in higher performance kernel at
>> 2141 the price of higher memory consumption. This option is available on
>> 2142 all non-R3000 family processor. Not that at the time of this
>> 2143 writing this option is still high experimental.
>> 2144
>> 2145 endchoice
>> 2146
>> 2147 config ARCH_FORCE_MAX_ORDER
>> 2148 int "Maximum zone order"
>> 2149 range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2150 default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2151 range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2152 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2153 range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2154 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2155 range 0 64
>> 2156 default "11"
>> 2157 help
>> 2158 The kernel memory allocator divides physically contiguous memory
>> 2159 blocks into "zones", where each zone is a power of two number of
>> 2160 pages. This option selects the largest power of two that the kernel
>> 2161 keeps in the memory allocator. If you need to allocate very large
>> 2162 blocks of physically contiguous memory, then you may need to
>> 2163 increase this value.
>> 2164
>> 2165 This config option is actually maximum order plus one. For example,
>> 2166 a value of 11 means that the largest free memory block is 2^10 pages.
>> 2167
>> 2168 The page size is not necessarily 4KB. Keep this in mind
>> 2169 when choosing a value for this option.
>> 2170
>> 2171 config BOARD_SCACHE
>> 2172 bool
>> 2173
>> 2174 config IP22_CPU_SCACHE
>> 2175 bool
>> 2176 select BOARD_SCACHE
>> 2177
>> 2178 #
>> 2179 # Support for a MIPS32 / MIPS64 style S-caches
>> 2180 #
>> 2181 config MIPS_CPU_SCACHE
>> 2182 bool
>> 2183 select BOARD_SCACHE
>> 2184
>> 2185 config R5000_CPU_SCACHE
>> 2186 bool
>> 2187 select BOARD_SCACHE
>> 2188
>> 2189 config RM7000_CPU_SCACHE
>> 2190 bool
>> 2191 select BOARD_SCACHE
>> 2192
>> 2193 config SIBYTE_DMA_PAGEOPS
>> 2194 bool "Use DMA to clear/copy pages"
>> 2195 depends on CPU_SB1
261 help 2196 help
262 Say Y here to allow turning CPUs off !! 2197 Instead of using the CPU to zero and copy pages, use a Data Mover
263 controlled through /sys/devices/syst !! 2198 channel. These DMA channels are otherwise unused by the standard
>> 2199 SiByte Linux port. Seems to give a small performance benefit.
264 2200
265 Say N if you want to disable CPU hot !! 2201 config CPU_HAS_PREFETCH
>> 2202 bool
266 2203
267 config SECONDARY_RESET_VECTOR !! 2204 config CPU_GENERIC_DUMP_TLB
268 bool "Secondary cores use alternative !! 2205 bool
>> 2206 default y if !CPU_R3000
>> 2207
>> 2208 config MIPS_FP_SUPPORT
>> 2209 bool "Floating Point support" if EXPERT
269 default y 2210 default y
270 depends on HAVE_SMP <<
271 help 2211 help
272 Secondary cores may be configured to !! 2212 Select y to include support for floating point in the kernel
273 or all cores may use primary reset v !! 2213 including initialization of FPU hardware, FP context save & restore
274 Say Y here to supply handler for the !! 2214 and emulation of an FPU where necessary. Without this support any
>> 2215 userland program attempting to use floating point instructions will
>> 2216 receive a SIGILL.
>> 2217
>> 2218 If you know that your userland will not attempt to use floating point
>> 2219 instructions then you can say n here to shrink the kernel a little.
>> 2220
>> 2221 If unsure, say y.
>> 2222
>> 2223 config CPU_R2300_FPU
>> 2224 bool
>> 2225 depends on MIPS_FP_SUPPORT
>> 2226 default y if CPU_R3000
>> 2227
>> 2228 config CPU_R3K_TLB
>> 2229 bool
>> 2230
>> 2231 config CPU_R4K_FPU
>> 2232 bool
>> 2233 depends on MIPS_FP_SUPPORT
>> 2234 default y if !CPU_R2300_FPU
>> 2235
>> 2236 config CPU_R4K_CACHE_TLB
>> 2237 bool
>> 2238 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2239
>> 2240 config MIPS_MT_SMP
>> 2241 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2242 default y
>> 2243 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2244 select CPU_MIPSR2_IRQ_VI
>> 2245 select CPU_MIPSR2_IRQ_EI
>> 2246 select SYNC_R4K
>> 2247 select MIPS_MT
>> 2248 select SMP
>> 2249 select SMP_UP
>> 2250 select SYS_SUPPORTS_SMP
>> 2251 select SYS_SUPPORTS_SCHED_SMT
>> 2252 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2253 help
>> 2254 This is a kernel model which is known as SMVP. This is supported
>> 2255 on cores with the MT ASE and uses the available VPEs to implement
>> 2256 virtual processors which supports SMP. This is equivalent to the
>> 2257 Intel Hyperthreading feature. For further information go to
>> 2258 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2259
>> 2260 config MIPS_MT
>> 2261 bool
275 2262
276 config FAST_SYSCALL_XTENSA !! 2263 config SCHED_SMT
277 bool "Enable fast atomic syscalls" !! 2264 bool "SMT (multithreading) scheduler support"
>> 2265 depends on SYS_SUPPORTS_SCHED_SMT
278 default n 2266 default n
279 help 2267 help
280 fast_syscall_xtensa is a syscall tha !! 2268 SMT scheduler support improves the CPU scheduler's decision making
281 on UP kernel when processor has no s !! 2269 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2270 increased overhead in some places. If unsure say N here.
282 2271
283 This syscall is deprecated. It may h !! 2272 config SYS_SUPPORTS_SCHED_SMT
284 invalid arguments. It is provided on !! 2273 bool
285 Only enable it if your userspace sof <<
286 2274
287 If unsure, say N. !! 2275 config SYS_SUPPORTS_MULTITHREADING
>> 2276 bool
288 2277
289 config FAST_SYSCALL_SPILL_REGISTERS !! 2278 config MIPS_MT_FPAFF
290 bool "Enable spill registers syscall" !! 2279 bool "Dynamic FPU affinity for FP-intensive threads"
291 default n !! 2280 default y
>> 2281 depends on MIPS_MT_SMP
>> 2282
>> 2283 config MIPSR2_TO_R6_EMULATOR
>> 2284 bool "MIPS R2-to-R6 emulator"
>> 2285 depends on CPU_MIPSR6
>> 2286 depends on MIPS_FP_SUPPORT
>> 2287 default y
292 help 2288 help
293 fast_syscall_spill_registers is a sy !! 2289 Choose this option if you want to run non-R6 MIPS userland code.
294 register windows of a calling usersp !! 2290 Even if you say 'Y' here, the emulator will still be disabled by
>> 2291 default. You can enable it using the 'mipsr2emu' kernel option.
>> 2292 The only reason this is a build-time option is to save ~14K from the
>> 2293 final kernel image.
295 2294
296 This syscall is deprecated. It may h !! 2295 config SYS_SUPPORTS_VPE_LOADER
297 invalid arguments. It is provided on !! 2296 bool
298 Only enable it if your userspace sof !! 2297 depends on SYS_SUPPORTS_MULTITHREADING
>> 2298 help
>> 2299 Indicates that the platform supports the VPE loader, and provides
>> 2300 physical_memsize.
299 2301
300 If unsure, say N. !! 2302 config MIPS_VPE_LOADER
>> 2303 bool "VPE loader support."
>> 2304 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2305 select CPU_MIPSR2_IRQ_VI
>> 2306 select CPU_MIPSR2_IRQ_EI
>> 2307 select MIPS_MT
>> 2308 help
>> 2309 Includes a loader for loading an elf relocatable object
>> 2310 onto another VPE and running it.
301 2311
302 choice !! 2312 config MIPS_VPE_LOADER_CMP
303 prompt "Kernel ABI" !! 2313 bool
304 default KERNEL_ABI_DEFAULT !! 2314 default "y"
>> 2315 depends on MIPS_VPE_LOADER && MIPS_CMP
>> 2316
>> 2317 config MIPS_VPE_LOADER_MT
>> 2318 bool
>> 2319 default "y"
>> 2320 depends on MIPS_VPE_LOADER && !MIPS_CMP
>> 2321
>> 2322 config MIPS_VPE_LOADER_TOM
>> 2323 bool "Load VPE program into memory hidden from linux"
>> 2324 depends on MIPS_VPE_LOADER
>> 2325 default y
305 help 2326 help
306 Select ABI for the kernel code. This !! 2327 The loader can use memory that is present but has been hidden from
307 supported userspace ABI and any comb !! 2328 Linux using the kernel command line option "mem=xxMB". It's up to
308 kernel/userspace ABI is possible and !! 2329 you to ensure the amount you put in the option and the space your
309 !! 2330 program requires is less or equal to the amount physically present.
310 In case both kernel and userspace su !! 2331
311 all register windows support code wi !! 2332 config MIPS_VPE_APSP_API
312 build. !! 2333 bool "Enable support for AP/SP API (RTLX)"
313 !! 2334 depends on MIPS_VPE_LOADER
314 If unsure, choose the default ABI. <<
315 <<
316 config KERNEL_ABI_DEFAULT <<
317 bool "Default ABI" <<
318 help <<
319 Select this option to compile kernel <<
320 selected for the toolchain. <<
321 Normally cores with windowed registe <<
322 cores without it use call0 ABI. <<
323 <<
324 config KERNEL_ABI_CALL0 <<
325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI <<
326 help <<
327 Select this option to compile kernel <<
328 toolchain that defaults to windowed <<
329 When this option is not selected the <<
330 be used for the kernel code. <<
331 2335
332 endchoice !! 2336 config MIPS_VPE_APSP_API_CMP
>> 2337 bool
>> 2338 default "y"
>> 2339 depends on MIPS_VPE_APSP_API && MIPS_CMP
333 2340
334 config USER_ABI_CALL0 !! 2341 config MIPS_VPE_APSP_API_MT
335 bool 2342 bool
>> 2343 default "y"
>> 2344 depends on MIPS_VPE_APSP_API && !MIPS_CMP
336 2345
337 choice !! 2346 config MIPS_CMP
338 prompt "Userspace ABI" !! 2347 bool "MIPS CMP framework support (DEPRECATED)"
339 default USER_ABI_DEFAULT !! 2348 depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6
>> 2349 select SMP
>> 2350 select SYNC_R4K
>> 2351 select SYS_SUPPORTS_SMP
>> 2352 select WEAK_ORDERING
>> 2353 default n
340 help 2354 help
341 Select supported userspace ABI. !! 2355 Select this if you are using a bootloader which implements the "CMP
>> 2356 framework" protocol (ie. YAMON) and want your kernel to make use of
>> 2357 its ability to start secondary CPUs.
>> 2358
>> 2359 Unless you have a specific need, you should use CONFIG_MIPS_CPS
>> 2360 instead of this.
>> 2361
>> 2362 config MIPS_CPS
>> 2363 bool "MIPS Coherent Processing System support"
>> 2364 depends on SYS_SUPPORTS_MIPS_CPS
>> 2365 select MIPS_CM
>> 2366 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2367 select SMP
>> 2368 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2369 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2370 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2371 select SYS_SUPPORTS_SMP
>> 2372 select WEAK_ORDERING
>> 2373 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2374 help
>> 2375 Select this if you wish to run an SMP kernel across multiple cores
>> 2376 within a MIPS Coherent Processing System. When this option is
>> 2377 enabled the kernel will probe for other cores and boot them with
>> 2378 no external assistance. It is safe to enable this when hardware
>> 2379 support is unavailable.
>> 2380
>> 2381 config MIPS_CPS_PM
>> 2382 depends on MIPS_CPS
>> 2383 bool
>> 2384
>> 2385 config MIPS_CM
>> 2386 bool
>> 2387 select MIPS_CPC
>> 2388
>> 2389 config MIPS_CPC
>> 2390 bool
>> 2391
>> 2392 config SB1_PASS_2_WORKAROUNDS
>> 2393 bool
>> 2394 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2395 default y
342 2396
343 If unsure, choose the default ABI. !! 2397 config SB1_PASS_2_1_WORKAROUNDS
>> 2398 bool
>> 2399 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2400 default y
>> 2401
>> 2402 choice
>> 2403 prompt "SmartMIPS or microMIPS ASE support"
344 2404
345 config USER_ABI_DEFAULT !! 2405 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
346 bool "Default ABI only" !! 2406 bool "None"
347 help 2407 help
348 Assume default userspace ABI. For XE !! 2408 Select this if you want neither microMIPS nor SmartMIPS support
349 call0 ABI binaries may be run on suc <<
350 will not work correctly for them. <<
351 2409
352 config USER_ABI_CALL0_ONLY !! 2410 config CPU_HAS_SMARTMIPS
353 bool "Call0 ABI only" !! 2411 depends on SYS_SUPPORTS_SMARTMIPS
354 select USER_ABI_CALL0 !! 2412 bool "SmartMIPS"
>> 2413 help
>> 2414 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2415 increased security at both hardware and software level for
>> 2416 smartcards. Enabling this option will allow proper use of the
>> 2417 SmartMIPS instructions by Linux applications. However a kernel with
>> 2418 this option will not work on a MIPS core without SmartMIPS core. If
>> 2419 you don't know you probably don't have SmartMIPS and should say N
>> 2420 here.
>> 2421
>> 2422 config CPU_MICROMIPS
>> 2423 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2424 bool "microMIPS"
355 help 2425 help
356 Select this option to support only c !! 2426 When this option is enabled the kernel will be built using the
357 Windowed ABI binaries will crash wit !! 2427 microMIPS ISA
358 an illegal instruction exception on <<
359 2428
360 Choose this option if you're plannin !! 2429 endchoice
361 built with call0 ABI. <<
362 2430
363 config USER_ABI_CALL0_PROBE !! 2431 config CPU_HAS_MSA
364 bool "Support both windowed and call0 !! 2432 bool "Support for the MIPS SIMD Architecture"
365 select USER_ABI_CALL0 !! 2433 depends on CPU_SUPPORTS_MSA
366 help !! 2434 depends on MIPS_FP_SUPPORT
367 Select this option to support both w !! 2435 depends on 64BIT || MIPS_O32_FP64_SUPPORT
368 ABIs. When enabled all processes are !! 2436 help
369 and a fast user exception handler fo !! 2437 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
370 used to turn on PS.WOE bit on the fi !! 2438 and a set of SIMD instructions to operate on them. When this option
371 the userspace. !! 2439 is enabled the kernel will support allocating & switching MSA
>> 2440 vector register contexts. If you know that your kernel will only be
>> 2441 running on CPUs which do not support MSA or that your userland will
>> 2442 not be making use of it then you may wish to say N here to reduce
>> 2443 the size & complexity of your kernel.
372 2444
373 This option should be enabled for th !! 2445 If unsure, say Y.
374 both call0 and windowed ABIs in user <<
375 2446
376 Note that Xtensa ISA does not guaran !! 2447 config CPU_HAS_WB
377 raise an illegal instruction excepti !! 2448 bool
378 PS.WOE is disabled, check whether th <<
379 2449
380 endchoice !! 2450 config XKS01
>> 2451 bool
381 2452
382 endmenu !! 2453 config CPU_HAS_DIEI
>> 2454 depends on !CPU_DIEI_BROKEN
>> 2455 bool
383 2456
384 config XTENSA_CALIBRATE_CCOUNT !! 2457 config CPU_DIEI_BROKEN
385 def_bool n !! 2458 bool
>> 2459
>> 2460 config CPU_HAS_RIXI
>> 2461 bool
>> 2462
>> 2463 config CPU_NO_LOAD_STORE_LR
>> 2464 bool
386 help 2465 help
387 On some platforms (XT2000, for examp !! 2466 CPU lacks support for unaligned load and store instructions:
388 vary. The frequency can be determin !! 2467 LWL, LWR, SWL, SWR (Load/store word left/right).
389 against a well known, fixed frequenc !! 2468 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2469 systems).
>> 2470
>> 2471 #
>> 2472 # Vectored interrupt mode is an R2 feature
>> 2473 #
>> 2474 config CPU_MIPSR2_IRQ_VI
>> 2475 bool
390 2476
391 config SERIAL_CONSOLE !! 2477 #
392 def_bool n !! 2478 # Extended interrupt mode is an R2 feature
>> 2479 #
>> 2480 config CPU_MIPSR2_IRQ_EI
>> 2481 bool
393 2482
394 config PLATFORM_HAVE_XIP !! 2483 config CPU_HAS_SYNC
395 def_bool n !! 2484 bool
>> 2485 depends on !CPU_R3000
>> 2486 default y
396 2487
397 menu "Platform options" !! 2488 #
>> 2489 # CPU non-features
>> 2490 #
>> 2491
>> 2492 # Work around the "daddi" and "daddiu" CPU errata:
>> 2493 #
>> 2494 # - The `daddi' instruction fails to trap on overflow.
>> 2495 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2496 # erratum #23
>> 2497 #
>> 2498 # - The `daddiu' instruction can produce an incorrect result.
>> 2499 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2500 # erratum #41
>> 2501 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2502 # #15
>> 2503 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2504 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2505 config CPU_DADDI_WORKAROUNDS
>> 2506 bool
398 2507
399 choice !! 2508 # Work around certain R4000 CPU errata (as implemented by GCC):
400 prompt "Xtensa System Type" !! 2509 #
401 default XTENSA_PLATFORM_ISS !! 2510 # - A double-word or a variable shift may give an incorrect result
>> 2511 # if executed immediately after starting an integer division:
>> 2512 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2513 # erratum #28
>> 2514 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2515 # #19
>> 2516 #
>> 2517 # - A double-word or a variable shift may give an incorrect result
>> 2518 # if executed while an integer multiplication is in progress:
>> 2519 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2520 # errata #16 & #28
>> 2521 #
>> 2522 # - An integer division may give an incorrect result if started in
>> 2523 # a delay slot of a taken branch or a jump:
>> 2524 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2525 # erratum #52
>> 2526 config CPU_R4000_WORKAROUNDS
>> 2527 bool
>> 2528 select CPU_R4400_WORKAROUNDS
402 2529
403 config XTENSA_PLATFORM_ISS !! 2530 # Work around certain R4400 CPU errata (as implemented by GCC):
404 bool "ISS" !! 2531 #
405 select XTENSA_CALIBRATE_CCOUNT !! 2532 # - A double-word or a variable shift may give an incorrect result
406 select SERIAL_CONSOLE !! 2533 # if executed immediately after starting an integer division:
407 help !! 2534 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
408 ISS is an acronym for Tensilica's In !! 2535 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
409 !! 2536 config CPU_R4400_WORKAROUNDS
410 config XTENSA_PLATFORM_XT2000 !! 2537 bool
411 bool "XT2000" <<
412 help <<
413 XT2000 is the name of Tensilica's fe <<
414 This hardware is capable of running <<
415 <<
416 config XTENSA_PLATFORM_XTFPGA <<
417 bool "XTFPGA" <<
418 select ETHOC if ETHERNET <<
419 select PLATFORM_WANT_DEFAULT_MEM if !M <<
420 select SERIAL_CONSOLE <<
421 select XTENSA_CALIBRATE_CCOUNT <<
422 select PLATFORM_HAVE_XIP <<
423 help <<
424 XTFPGA is the name of Tensilica boar <<
425 This hardware is capable of running <<
426 2538
427 endchoice !! 2539 config CPU_R4X00_BUGS64
>> 2540 bool
>> 2541 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
428 2542
429 config PLATFORM_NR_IRQS !! 2543 config MIPS_ASID_SHIFT
430 int 2544 int
431 default 3 if XTENSA_PLATFORM_XT2000 !! 2545 default 6 if CPU_R3000
432 default 0 2546 default 0
433 2547
434 config XTENSA_CPU_CLOCK !! 2548 config MIPS_ASID_BITS
435 int "CPU clock rate [MHz]" !! 2549 int
436 depends on !XTENSA_CALIBRATE_CCOUNT !! 2550 default 0 if MIPS_ASID_BITS_VARIABLE
437 default 16 !! 2551 default 6 if CPU_R3000
>> 2552 default 8
438 2553
439 config GENERIC_CALIBRATE_DELAY !! 2554 config MIPS_ASID_BITS_VARIABLE
440 bool "Auto calibration of the BogoMIPS !! 2555 bool
441 help <<
442 The BogoMIPS value can easily be der <<
443 2556
444 config CMDLINE_BOOL !! 2557 config MIPS_CRC_SUPPORT
445 bool "Default bootloader kernel argume !! 2558 bool
446 2559
447 config CMDLINE !! 2560 # R4600 erratum. Due to the lack of errata information the exact
448 string "Initial kernel command string" !! 2561 # technical details aren't known. I've experimentally found that disabling
449 depends on CMDLINE_BOOL !! 2562 # interrupts during indexed I-cache flushes seems to be sufficient to deal
450 default "console=ttyS0,38400 root=/dev !! 2563 # with the issue.
451 help !! 2564 config WAR_R4600_V1_INDEX_ICACHEOP
452 On some architectures (EBSA110 and C !! 2565 bool
453 for the boot loader to pass argument <<
454 architectures, you should supply som <<
455 time by entering them here. As a min <<
456 memory size and the root device (e.g <<
457 2566
458 config USE_OF !! 2567 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
459 bool "Flattened Device Tree support" !! 2568 #
460 select OF !! 2569 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
461 select OF_EARLY_FLATTREE !! 2570 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
462 help !! 2571 # executed if there is no other dcache activity. If the dcache is
463 Include support for flattened device !! 2572 # accessed for another instruction immediately preceding when these
>> 2573 # cache instructions are executing, it is possible that the dcache
>> 2574 # tag match outputs used by these cache instructions will be
>> 2575 # incorrect. These cache instructions should be preceded by at least
>> 2576 # four instructions that are not any kind of load or store
>> 2577 # instruction.
>> 2578 #
>> 2579 # This is not allowed: lw
>> 2580 # nop
>> 2581 # nop
>> 2582 # nop
>> 2583 # cache Hit_Writeback_Invalidate_D
>> 2584 #
>> 2585 # This is allowed: lw
>> 2586 # nop
>> 2587 # nop
>> 2588 # nop
>> 2589 # nop
>> 2590 # cache Hit_Writeback_Invalidate_D
>> 2591 config WAR_R4600_V1_HIT_CACHEOP
>> 2592 bool
464 2593
465 config BUILTIN_DTB_SOURCE !! 2594 # Writeback and invalidate the primary cache dcache before DMA.
466 string "DTB to build into the kernel i !! 2595 #
467 depends on OF !! 2596 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2597 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2598 # operate correctly if the internal data cache refill buffer is empty. These
>> 2599 # CACHE instructions should be separated from any potential data cache miss
>> 2600 # by a load instruction to an uncached address to empty the response buffer."
>> 2601 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2602 # in .pdf format.)
>> 2603 config WAR_R4600_V2_HIT_CACHEOP
>> 2604 bool
468 2605
469 config PARSE_BOOTPARAM !! 2606 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
470 bool "Parse bootparam block" !! 2607 # the line which this instruction itself exists, the following
471 default y !! 2608 # operation is not guaranteed."
472 help !! 2609 #
473 Parse parameters passed to the kerne !! 2610 # Workaround: do two phase flushing for Index_Invalidate_I
474 be disabled if the kernel is known t !! 2611 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2612 bool
475 2613
476 If unsure, say Y. !! 2614 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2615 # opposes it being called that) where invalid instructions in the same
>> 2616 # I-cache line worth of instructions being fetched may case spurious
>> 2617 # exceptions.
>> 2618 config WAR_ICACHE_REFILLS
>> 2619 bool
477 2620
478 choice !! 2621 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
479 prompt "Semihosting interface" !! 2622 # may cause ll / sc and lld / scd sequences to execute non-atomically.
480 default XTENSA_SIMCALL_ISS !! 2623 config WAR_R10000_LLSC
481 depends on XTENSA_PLATFORM_ISS !! 2624 bool
482 help <<
483 Choose semihosting interface that wi <<
484 block device and networking. <<
485 2625
486 config XTENSA_SIMCALL_ISS !! 2626 # 34K core erratum: "Problems Executing the TLBR Instruction"
487 bool "simcall" !! 2627 config WAR_MIPS34K_MISSED_ITLB
488 help !! 2628 bool
489 Use simcall instruction. simcall is <<
490 it does nothing on hardware. <<
491 2629
492 config XTENSA_SIMCALL_GDBIO !! 2630 #
493 bool "GDBIO" !! 2631 # - Highmem only makes sense for the 32-bit kernel.
>> 2632 # - The current highmem code will only work properly on physically indexed
>> 2633 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2634 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2635 # moment we protect the user and offer the highmem option only on machines
>> 2636 # where it's known to be safe. This will not offer highmem on a few systems
>> 2637 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2638 # indexed CPUs but we're playing safe.
>> 2639 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2640 # know they might have memory configurations that could make use of highmem
>> 2641 # support.
>> 2642 #
>> 2643 config HIGHMEM
>> 2644 bool "High Memory Support"
>> 2645 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2646 select KMAP_LOCAL
>> 2647
>> 2648 config CPU_SUPPORTS_HIGHMEM
>> 2649 bool
>> 2650
>> 2651 config SYS_SUPPORTS_HIGHMEM
>> 2652 bool
>> 2653
>> 2654 config SYS_SUPPORTS_SMARTMIPS
>> 2655 bool
>> 2656
>> 2657 config SYS_SUPPORTS_MICROMIPS
>> 2658 bool
>> 2659
>> 2660 config SYS_SUPPORTS_MIPS16
>> 2661 bool
494 help 2662 help
495 Use break instruction. It is availab !! 2663 This option must be set if a kernel might be executed on a MIPS16-
496 is attached to it via JTAG. !! 2664 enabled CPU even if MIPS16 is not actually being used. In other
>> 2665 words, it makes the kernel MIPS16-tolerant.
497 2666
498 endchoice !! 2667 config CPU_SUPPORTS_MSA
>> 2668 bool
499 2669
500 config BLK_DEV_SIMDISK !! 2670 config ARCH_FLATMEM_ENABLE
501 tristate "Host file-based simulated bl !! 2671 def_bool y
502 default n !! 2672 depends on !NUMA && !CPU_LOONGSON2EF
503 depends on XTENSA_PLATFORM_ISS && BLOC !! 2673
>> 2674 config ARCH_SPARSEMEM_ENABLE
>> 2675 bool
>> 2676
>> 2677 config NUMA
>> 2678 bool "NUMA Support"
>> 2679 depends on SYS_SUPPORTS_NUMA
>> 2680 select SMP
>> 2681 select HAVE_SETUP_PER_CPU_AREA
>> 2682 select NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2683 help
>> 2684 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2685 Access). This option improves performance on systems with more
>> 2686 than two nodes; on two node systems it is generally better to
>> 2687 leave it disabled; on single node systems leave this option
>> 2688 disabled.
>> 2689
>> 2690 config SYS_SUPPORTS_NUMA
>> 2691 bool
>> 2692
>> 2693 config HAVE_ARCH_NODEDATA_EXTENSION
>> 2694 bool
>> 2695
>> 2696 config RELOCATABLE
>> 2697 bool "Relocatable kernel"
>> 2698 depends on SYS_SUPPORTS_RELOCATABLE
>> 2699 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2700 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2701 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2702 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2703 CPU_LOONGSON64
>> 2704 help
>> 2705 This builds a kernel image that retains relocation information
>> 2706 so it can be loaded someplace besides the default 1MB.
>> 2707 The relocations make the kernel binary about 15% larger,
>> 2708 but are discarded at runtime
>> 2709
>> 2710 config RELOCATION_TABLE_SIZE
>> 2711 hex "Relocation table size"
>> 2712 depends on RELOCATABLE
>> 2713 range 0x0 0x01000000
>> 2714 default "0x00200000" if CPU_LOONGSON64
>> 2715 default "0x00100000"
>> 2716 help
>> 2717 A table of relocation data will be appended to the kernel binary
>> 2718 and parsed at boot to fix up the relocated kernel.
>> 2719
>> 2720 This option allows the amount of space reserved for the table to be
>> 2721 adjusted, although the default of 1Mb should be ok in most cases.
>> 2722
>> 2723 The build will fail and a valid size suggested if this is too small.
>> 2724
>> 2725 If unsure, leave at the default value.
>> 2726
>> 2727 config RANDOMIZE_BASE
>> 2728 bool "Randomize the address of the kernel image"
>> 2729 depends on RELOCATABLE
>> 2730 help
>> 2731 Randomizes the physical and virtual address at which the
>> 2732 kernel image is loaded, as a security feature that
>> 2733 deters exploit attempts relying on knowledge of the location
>> 2734 of kernel internals.
>> 2735
>> 2736 Entropy is generated using any coprocessor 0 registers available.
>> 2737
>> 2738 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2739
>> 2740 If unsure, say N.
>> 2741
>> 2742 config RANDOMIZE_BASE_MAX_OFFSET
>> 2743 hex "Maximum kASLR offset" if EXPERT
>> 2744 depends on RANDOMIZE_BASE
>> 2745 range 0x0 0x40000000 if EVA || 64BIT
>> 2746 range 0x0 0x08000000
>> 2747 default "0x01000000"
>> 2748 help
>> 2749 When kASLR is active, this provides the maximum offset that will
>> 2750 be applied to the kernel image. It should be set according to the
>> 2751 amount of physical RAM available in the target system minus
>> 2752 PHYSICAL_START and must be a power of 2.
>> 2753
>> 2754 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2755 EVA or 64-bit. The default is 16Mb.
>> 2756
>> 2757 config NODES_SHIFT
>> 2758 int
>> 2759 default "6"
>> 2760 depends on NUMA
>> 2761
>> 2762 config HW_PERF_EVENTS
>> 2763 bool "Enable hardware performance counter support for perf events"
>> 2764 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
>> 2765 default y
504 help 2766 help
505 Create block devices that map to fil !! 2767 Enable hardware performance counter support for perf events. If
506 Device binding to host file may be c !! 2768 disabled, perf events will use software events only.
507 interface provided the device is not !! 2769
508 !! 2770 config DMI
509 config BLK_DEV_SIMDISK_COUNT !! 2771 bool "Enable DMI scanning"
510 int "Number of host file-based simulat !! 2772 depends on MACH_LOONGSON64
511 range 1 10 !! 2773 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
512 depends on BLK_DEV_SIMDISK !! 2774 default y
513 default 2 <<
514 help 2775 help
515 This is the default minimal number o !! 2776 Enabled scanning of DMI to identify machine quirks. Say Y
516 Kernel/module parameter 'simdisk_cou !! 2777 here unless you have verified that your setup is not
517 value at runtime. More file names (b !! 2778 affected by entries in the DMI blacklist. Required by PNP
518 specified as parameters, simdisk_cou !! 2779 BIOS code.
519 !! 2780
520 config SIMDISK0_FILENAME !! 2781 config SMP
521 string "Host filename for the first si !! 2782 bool "Multi-Processing support"
522 depends on BLK_DEV_SIMDISK = y !! 2783 depends on SYS_SUPPORTS_SMP
523 default "" <<
524 help <<
525 Attach a first simdisk to a host fil <<
526 contains a root file system. <<
527 <<
528 config SIMDISK1_FILENAME <<
529 string "Host filename for the second s <<
530 depends on BLK_DEV_SIMDISK = y && BLK_ <<
531 default "" <<
532 help <<
533 Another simulated disk in a host fil <<
534 storage. <<
535 <<
536 config XTFPGA_LCD <<
537 bool "Enable XTFPGA LCD driver" <<
538 depends on XTENSA_PLATFORM_XTFPGA <<
539 default n <<
540 help 2784 help
541 There's a 2x16 LCD on most of XTFPGA !! 2785 This enables support for systems with more than one CPU. If you have
542 progress messages there during bootu !! 2786 a system with only one CPU, say N. If you have a system with more
543 during board bringup. !! 2787 than one CPU, say Y.
>> 2788
>> 2789 If you say N here, the kernel will run on uni- and multiprocessor
>> 2790 machines, but will use only one CPU of a multiprocessor machine. If
>> 2791 you say Y here, the kernel will run on many, but not all,
>> 2792 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2793 will run faster if you say N here.
544 2794
545 If unsure, say N. !! 2795 People using multiprocessor machines who say Y here should also say
>> 2796 Y to "Enhanced Real Time Clock Support", below.
546 2797
547 config XTFPGA_LCD_BASE_ADDR !! 2798 See also the SMP-HOWTO available at
548 hex "XTFPGA LCD base address" !! 2799 <https://www.tldp.org/docs.html#howto>.
549 depends on XTFPGA_LCD !! 2800
550 default "0x0d0c0000" !! 2801 If you don't know what to do here, say N.
551 help !! 2802
552 Base address of the LCD controller i !! 2803 config HOTPLUG_CPU
553 Different boards from XTFPGA family !! 2804 bool "Support for hot-pluggable CPUs"
554 addresses. Please consult prototypin !! 2805 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
555 the correct address. Wrong address h <<
556 <<
557 config XTFPGA_LCD_8BIT_ACCESS <<
558 bool "Use 8-bit access to XTFPGA LCD" <<
559 depends on XTFPGA_LCD <<
560 default n <<
561 help 2806 help
562 LCD may be connected with 4- or 8-bi !! 2807 Say Y here to allow turning CPUs off and on. CPUs can be
563 only be used with 8-bit interface. P !! 2808 controlled through /sys/devices/system/cpu.
564 guide for your board for the correct !! 2809 (Note: power management support will enable this option
565 !! 2810 automatically on SMP systems. )
566 comment "Kernel memory layout" !! 2811 Say N if you want to disable CPU hotplug.
567 <<
568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX <<
569 bool "Initialize Xtensa MMU inside the <<
570 depends on !XTENSA_VARIANT_FSF && !XTE <<
571 default y if XTENSA_VARIANT_DC233C || <<
572 help <<
573 Earlier version initialized the MMU <<
574 before jumping to _startup in head.S <<
575 it was possible to place a software <<
576 then enter your normal kernel breakp <<
577 to the kernel mappings (0XC0000000). <<
578 <<
579 This unfortunately won't work for U- <<
580 work for using KEXEC to have a hot k <<
581 KDUMP. <<
582 <<
583 So now the MMU is initialized in hea <<
584 use hardware breakpoints (gdb 'hbrea <<
585 xt-gdb can't place a Software Breakp <<
586 to mapping the MMU and after mapping <<
587 was mapped gdb wouldn't remove the b <<
588 PC wouldn't match. Since Hardware Br <<
589 Linux configurations it seems reason <<
590 and leave this older mechanism for u <<
591 not to follow Tensilica's recommenda <<
592 <<
593 Selecting this will cause U-Boot to <<
594 address at 0x00003000 instead of the <<
595 <<
596 If in doubt, say Y. <<
597 <<
598 config XIP_KERNEL <<
599 bool "Kernel Execute-In-Place from ROM <<
600 depends on PLATFORM_HAVE_XIP <<
601 help <<
602 Execute-In-Place allows the kernel t <<
603 directly addressable by the CPU, suc <<
604 space since the text section of the <<
605 to RAM. Read-write sections, such as <<
606 are still copied to RAM. The XIP ker <<
607 it has to run directly from flash, s <<
608 store it. The flash address used to <<
609 and for storing it, is configuration <<
610 say Y here, you must know the proper <<
611 store the kernel image depending on <<
612 <<
613 Also note that the make target becom <<
614 "make Image" or "make uImage". The f <<
615 ROM memory will be arch/xtensa/boot/ <<
616 2812
617 If unsure, say N. !! 2813 config SMP_UP
>> 2814 bool
>> 2815
>> 2816 config SYS_SUPPORTS_MIPS_CMP
>> 2817 bool
>> 2818
>> 2819 config SYS_SUPPORTS_MIPS_CPS
>> 2820 bool
618 2821
619 config MEMMAP_CACHEATTR !! 2822 config SYS_SUPPORTS_SMP
620 hex "Cache attributes for the memory a !! 2823 bool
621 depends on !MMU <<
622 default 0x22222222 <<
623 help <<
624 These cache attributes are set up fo <<
625 specifies cache attributes for the c <<
626 region: bits 0..3 -- for addresses 0 <<
627 bits 4..7 -- for addresses 0x2000000 <<
628 <<
629 Cache attribute values are specific <<
630 For region protection MMUs: <<
631 1: WT cached, <<
632 2: cache bypass, <<
633 4: WB cached, <<
634 f: illegal. <<
635 For full MMU: <<
636 bit 0: executable, <<
637 bit 1: writable, <<
638 bits 2..3: <<
639 0: cache bypass, <<
640 1: WB cache, <<
641 2: WT cache, <<
642 3: special (c and e are illegal, <<
643 For MPU: <<
644 0: illegal, <<
645 1: WB cache, <<
646 2: WB, no-write-allocate cache, <<
647 3: WT cache, <<
648 4: cache bypass. <<
649 <<
650 config KSEG_PADDR <<
651 hex "Physical address of the KSEG mapp <<
652 depends on INITIALIZE_XTENSA_MMU_INSID <<
653 default 0x00000000 <<
654 help <<
655 This is the physical address where K <<
656 the chosen KSEG layout help for the <<
657 Unpacked kernel image (including vec <<
658 within KSEG. <<
659 Physical memory below this address i <<
660 <<
661 If unsure, leave the default value h <<
662 <<
663 config KERNEL_VIRTUAL_ADDRESS <<
664 hex "Kernel virtual address" <<
665 depends on MMU && XIP_KERNEL <<
666 default 0xd0003000 <<
667 help <<
668 This is the virtual address where th <<
669 XIP kernel may be mapped into KSEG o <<
670 provided here must match kernel load <<
671 KERNEL_LOAD_ADDRESS. <<
672 <<
673 config KERNEL_LOAD_ADDRESS <<
674 hex "Kernel load address" <<
675 default 0x60003000 if !MMU <<
676 default 0x00003000 if MMU && INITIALIZ <<
677 default 0xd0003000 if MMU && !INITIALI <<
678 help <<
679 This is the address where the kernel <<
680 It is virtual address for MMUv2 conf <<
681 for all other configurations. <<
682 2824
683 If unsure, leave the default value h !! 2825 config NR_CPUS_DEFAULT_4
>> 2826 bool
>> 2827
>> 2828 config NR_CPUS_DEFAULT_8
>> 2829 bool
>> 2830
>> 2831 config NR_CPUS_DEFAULT_16
>> 2832 bool
>> 2833
>> 2834 config NR_CPUS_DEFAULT_32
>> 2835 bool
>> 2836
>> 2837 config NR_CPUS_DEFAULT_64
>> 2838 bool
>> 2839
>> 2840 config NR_CPUS
>> 2841 int "Maximum number of CPUs (2-256)"
>> 2842 range 2 256
>> 2843 depends on SMP
>> 2844 default "4" if NR_CPUS_DEFAULT_4
>> 2845 default "8" if NR_CPUS_DEFAULT_8
>> 2846 default "16" if NR_CPUS_DEFAULT_16
>> 2847 default "32" if NR_CPUS_DEFAULT_32
>> 2848 default "64" if NR_CPUS_DEFAULT_64
>> 2849 help
>> 2850 This allows you to specify the maximum number of CPUs which this
>> 2851 kernel will support. The maximum supported value is 32 for 32-bit
>> 2852 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2853 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2854 and 2 for all others.
>> 2855
>> 2856 This is purely to save memory - each supported CPU adds
>> 2857 approximately eight kilobytes to the kernel image. For best
>> 2858 performance should round up your number of processors to the next
>> 2859 power of two.
>> 2860
>> 2861 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2862 bool
>> 2863
>> 2864 config MIPS_NR_CPU_NR_MAP_1024
>> 2865 bool
>> 2866
>> 2867 config MIPS_NR_CPU_NR_MAP
>> 2868 int
>> 2869 depends on SMP
>> 2870 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2871 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
>> 2872
>> 2873 #
>> 2874 # Timer Interrupt Frequency Configuration
>> 2875 #
684 2876
685 choice 2877 choice
686 prompt "Relocatable vectors location" !! 2878 prompt "Timer frequency"
687 default XTENSA_VECTORS_IN_TEXT !! 2879 default HZ_250
688 help 2880 help
689 Choose whether relocatable vectors a !! 2881 Allows the configuration of the timer frequency.
690 or placed separately at runtime. Thi !! 2882
691 configurations without VECBASE regis !! 2883 config HZ_24
692 placed at their hardware-defined loc !! 2884 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
693 !! 2885
694 config XTENSA_VECTORS_IN_TEXT !! 2886 config HZ_48
695 bool "Merge relocatable vectors into k !! 2887 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
696 depends on !MTD_XIP !! 2888
697 help !! 2889 config HZ_100
698 This option puts relocatable vectors !! 2890 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
699 with proper alignment. !! 2891
700 This is a safe choice for most confi !! 2892 config HZ_128
701 !! 2893 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
702 config XTENSA_VECTORS_SEPARATE !! 2894
703 bool "Put relocatable vectors at fixed !! 2895 config HZ_250
704 help !! 2896 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
705 This option puts relocatable vectors !! 2897
706 Vectors are merged with the .init da !! 2898 config HZ_256
707 are copied into their designated loc !! 2899 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
708 Use it to put vectors into IRAM or o !! 2900
709 XIP-aware MTD support. !! 2901 config HZ_1000
>> 2902 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2903
>> 2904 config HZ_1024
>> 2905 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
710 2906
711 endchoice 2907 endchoice
712 2908
713 config VECTORS_ADDR !! 2909 config SYS_SUPPORTS_24HZ
714 hex "Kernel vectors virtual address" !! 2910 bool
715 default 0x00000000 <<
716 depends on XTENSA_VECTORS_SEPARATE <<
717 help <<
718 This is the virtual address of the ( <<
719 It must be within KSEG if MMU is use <<
720 <<
721 config XIP_DATA_ADDR <<
722 hex "XIP kernel data virtual address" <<
723 depends on XIP_KERNEL <<
724 default 0x00000000 <<
725 help <<
726 This is the virtual address where XI <<
727 It must be within KSEG if MMU is use <<
728 2911
729 config PLATFORM_WANT_DEFAULT_MEM !! 2912 config SYS_SUPPORTS_48HZ
730 def_bool n !! 2913 bool
731 2914
732 config DEFAULT_MEM_START !! 2915 config SYS_SUPPORTS_100HZ
733 hex !! 2916 bool
734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !M <<
735 default 0x60000000 if PLATFORM_WANT_DE <<
736 default 0x00000000 <<
737 help <<
738 This is the base address used for bo <<
739 in noMMU configurations. <<
740 2917
741 If unsure, leave the default value h !! 2918 config SYS_SUPPORTS_128HZ
>> 2919 bool
>> 2920
>> 2921 config SYS_SUPPORTS_250HZ
>> 2922 bool
>> 2923
>> 2924 config SYS_SUPPORTS_256HZ
>> 2925 bool
>> 2926
>> 2927 config SYS_SUPPORTS_1000HZ
>> 2928 bool
>> 2929
>> 2930 config SYS_SUPPORTS_1024HZ
>> 2931 bool
>> 2932
>> 2933 config SYS_SUPPORTS_ARBIT_HZ
>> 2934 bool
>> 2935 default y if !SYS_SUPPORTS_24HZ && \
>> 2936 !SYS_SUPPORTS_48HZ && \
>> 2937 !SYS_SUPPORTS_100HZ && \
>> 2938 !SYS_SUPPORTS_128HZ && \
>> 2939 !SYS_SUPPORTS_250HZ && \
>> 2940 !SYS_SUPPORTS_256HZ && \
>> 2941 !SYS_SUPPORTS_1000HZ && \
>> 2942 !SYS_SUPPORTS_1024HZ
>> 2943
>> 2944 config HZ
>> 2945 int
>> 2946 default 24 if HZ_24
>> 2947 default 48 if HZ_48
>> 2948 default 100 if HZ_100
>> 2949 default 128 if HZ_128
>> 2950 default 250 if HZ_250
>> 2951 default 256 if HZ_256
>> 2952 default 1000 if HZ_1000
>> 2953 default 1024 if HZ_1024
>> 2954
>> 2955 config SCHED_HRTICK
>> 2956 def_bool HIGH_RES_TIMERS
>> 2957
>> 2958 config KEXEC
>> 2959 bool "Kexec system call"
>> 2960 select KEXEC_CORE
>> 2961 help
>> 2962 kexec is a system call that implements the ability to shutdown your
>> 2963 current kernel, and to start another kernel. It is like a reboot
>> 2964 but it is independent of the system firmware. And like a reboot
>> 2965 you can start any kernel with it, not just Linux.
>> 2966
>> 2967 The name comes from the similarity to the exec system call.
>> 2968
>> 2969 It is an ongoing process to be certain the hardware in a machine
>> 2970 is properly shutdown, so do not be surprised if this code does not
>> 2971 initially work for you. As of this writing the exact hardware
>> 2972 interface is strongly in flux, so no good recommendation can be
>> 2973 made.
>> 2974
>> 2975 config CRASH_DUMP
>> 2976 bool "Kernel crash dumps"
>> 2977 help
>> 2978 Generate crash dump after being started by kexec.
>> 2979 This should be normally only set in special crash dump kernels
>> 2980 which are loaded in the main kernel with kexec-tools into
>> 2981 a specially reserved region and then later executed after
>> 2982 a crash by kdump/kexec. The crash dump kernel must be compiled
>> 2983 to a memory address not used by the main kernel or firmware using
>> 2984 PHYSICAL_START.
>> 2985
>> 2986 config PHYSICAL_START
>> 2987 hex "Physical address where the kernel is loaded"
>> 2988 default "0xffffffff84000000"
>> 2989 depends on CRASH_DUMP
>> 2990 help
>> 2991 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2992 If you plan to use kernel for capturing the crash dump change
>> 2993 this value to start of the reserved region (the "X" value as
>> 2994 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2995 passed to the panic-ed kernel).
>> 2996
>> 2997 config MIPS_O32_FP64_SUPPORT
>> 2998 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2999 depends on 32BIT || MIPS32_O32
>> 3000 help
>> 3001 When this is enabled, the kernel will support use of 64-bit floating
>> 3002 point registers with binaries using the O32 ABI along with the
>> 3003 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 3004 32-bit MIPS systems this support is at the cost of increasing the
>> 3005 size and complexity of the compiled FPU emulator. Thus if you are
>> 3006 running a MIPS32 system and know that none of your userland binaries
>> 3007 will require 64-bit floating point, you may wish to reduce the size
>> 3008 of your kernel & potentially improve FP emulation performance by
>> 3009 saying N here.
>> 3010
>> 3011 Although binutils currently supports use of this flag the details
>> 3012 concerning its effect upon the O32 ABI in userland are still being
>> 3013 worked on. In order to avoid userland becoming dependent upon current
>> 3014 behaviour before the details have been finalised, this option should
>> 3015 be considered experimental and only enabled by those working upon
>> 3016 said details.
>> 3017
>> 3018 If unsure, say N.
>> 3019
>> 3020 config USE_OF
>> 3021 bool
>> 3022 select OF
>> 3023 select OF_EARLY_FLATTREE
>> 3024 select IRQ_DOMAIN
>> 3025
>> 3026 config UHI_BOOT
>> 3027 bool
>> 3028
>> 3029 config BUILTIN_DTB
>> 3030 bool
742 3031
743 choice 3032 choice
744 prompt "KSEG layout" !! 3033 prompt "Kernel appended dtb support" if USE_OF
745 depends on MMU !! 3034 default MIPS_NO_APPENDED_DTB
746 default XTENSA_KSEG_MMU_V2 <<
747 <<
748 config XTENSA_KSEG_MMU_V2 <<
749 bool "MMUv2: 128MB cached + 128MB unca <<
750 help <<
751 MMUv2 compatible kernel memory map: <<
752 at KSEG_PADDR to 0xd0000000 with cac <<
753 without cache. <<
754 KSEG_PADDR must be aligned to 128MB. <<
755 <<
756 config XTENSA_KSEG_256M <<
757 bool "256MB cached + 256MB uncached" <<
758 depends on INITIALIZE_XTENSA_MMU_INSID <<
759 help <<
760 TLB way 6 maps 256MB starting at KSE <<
761 with cache and to 0xc0000000 without <<
762 KSEG_PADDR must be aligned to 256MB. <<
763 <<
764 config XTENSA_KSEG_512M <<
765 bool "512MB cached + 512MB uncached" <<
766 depends on INITIALIZE_XTENSA_MMU_INSID <<
767 help <<
768 TLB way 6 maps 512MB starting at KSE <<
769 with cache and to 0xc0000000 without <<
770 KSEG_PADDR must be aligned to 256MB. <<
771 3035
>> 3036 config MIPS_NO_APPENDED_DTB
>> 3037 bool "None"
>> 3038 help
>> 3039 Do not enable appended dtb support.
>> 3040
>> 3041 config MIPS_ELF_APPENDED_DTB
>> 3042 bool "vmlinux"
>> 3043 help
>> 3044 With this option, the boot code will look for a device tree binary
>> 3045 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 3046 it is empty and the DTB can be appended using binutils command
>> 3047 objcopy:
>> 3048
>> 3049 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 3050
>> 3051 This is meant as a backward compatibility convenience for those
>> 3052 systems with a bootloader that can't be upgraded to accommodate
>> 3053 the documented boot protocol using a device tree.
>> 3054
>> 3055 config MIPS_RAW_APPENDED_DTB
>> 3056 bool "vmlinux.bin or vmlinuz.bin"
>> 3057 help
>> 3058 With this option, the boot code will look for a device tree binary
>> 3059 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 3060 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 3061
>> 3062 This is meant as a backward compatibility convenience for those
>> 3063 systems with a bootloader that can't be upgraded to accommodate
>> 3064 the documented boot protocol using a device tree.
>> 3065
>> 3066 Beware that there is very little in terms of protection against
>> 3067 this option being confused by leftover garbage in memory that might
>> 3068 look like a DTB header after a reboot if no actual DTB is appended
>> 3069 to vmlinux.bin. Do not leave this option active in a production kernel
>> 3070 if you don't intend to always append a DTB.
772 endchoice 3071 endchoice
773 3072
774 config HIGHMEM !! 3073 choice
775 bool "High Memory Support" !! 3074 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
776 depends on MMU !! 3075 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
777 select KMAP_LOCAL !! 3076 !MACH_LOONGSON64 && !MIPS_MALTA && \
778 help !! 3077 !CAVIUM_OCTEON_SOC
779 Linux can use the full amount of RAM !! 3078 default MIPS_CMDLINE_FROM_BOOTLOADER
780 default. However, the default MMUv2 !! 3079
781 lowermost 128 MB of memory linearly !! 3080 config MIPS_CMDLINE_FROM_DTB
782 at 0xd0000000 (cached) and 0xd800000 !! 3081 depends on USE_OF
783 When there are more than 128 MB memo !! 3082 bool "Dtb kernel arguments if available"
784 all of it can be "permanently mapped !! 3083
785 The physical memory that's not perma !! 3084 config MIPS_CMDLINE_DTB_EXTEND
786 "high memory". !! 3085 depends on USE_OF
787 !! 3086 bool "Extend dtb kernel arguments with bootloader arguments"
788 If you are compiling a kernel which !! 3087
789 machine with more than 128 MB total !! 3088 config MIPS_CMDLINE_FROM_BOOTLOADER
790 N here. !! 3089 bool "Bootloader kernel arguments if available"
>> 3090
>> 3091 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 3092 depends on CMDLINE_BOOL
>> 3093 bool "Extend builtin kernel arguments with bootloader arguments"
>> 3094 endchoice
791 3095
792 If unsure, say Y. !! 3096 endmenu
793 3097
794 config ARCH_FORCE_MAX_ORDER !! 3098 config LOCKDEP_SUPPORT
795 int "Order of maximal physically conti !! 3099 bool
796 default "10" !! 3100 default y
797 help !! 3101
798 The kernel page allocator limits the !! 3102 config STACKTRACE_SUPPORT
799 contiguous allocations. The limit is !! 3103 bool
800 defines the maximal power of two of !! 3104 default y
801 allocated as a single contiguous blo !! 3105
802 overriding the default setting when !! 3106 config PGTABLE_LEVELS
803 large blocks of physically contiguou !! 3107 int
>> 3108 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3109 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3110 default 2
>> 3111
>> 3112 config MIPS_AUTO_PFN_OFFSET
>> 3113 bool
804 3114
805 Don't change if unsure. !! 3115 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
806 3116
>> 3117 config PCI_DRIVERS_GENERIC
>> 3118 select PCI_DOMAINS_GENERIC if PCI
>> 3119 bool
>> 3120
>> 3121 config PCI_DRIVERS_LEGACY
>> 3122 def_bool !PCI_DRIVERS_GENERIC
>> 3123 select NO_GENERIC_PCI_IOPORT_MAP
>> 3124 select PCI_DOMAINS if PCI
>> 3125
>> 3126 #
>> 3127 # ISA support is now enabled via select. Too many systems still have the one
>> 3128 # or other ISA chip on the board that users don't know about so don't expect
>> 3129 # users to choose the right thing ...
>> 3130 #
>> 3131 config ISA
>> 3132 bool
>> 3133
>> 3134 config TC
>> 3135 bool "TURBOchannel support"
>> 3136 depends on MACH_DECSTATION
>> 3137 help
>> 3138 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3139 processors. TURBOchannel programming specifications are available
>> 3140 at:
>> 3141 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3142 and:
>> 3143 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3144 Linux driver support status is documented at:
>> 3145 <http://www.linux-mips.org/wiki/DECstation>
>> 3146
>> 3147 config MMU
>> 3148 bool
>> 3149 default y
>> 3150
>> 3151 config ARCH_MMAP_RND_BITS_MIN
>> 3152 default 12 if 64BIT
>> 3153 default 8
>> 3154
>> 3155 config ARCH_MMAP_RND_BITS_MAX
>> 3156 default 18 if 64BIT
>> 3157 default 15
>> 3158
>> 3159 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3160 default 8
>> 3161
>> 3162 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3163 default 15
>> 3164
>> 3165 config I8253
>> 3166 bool
>> 3167 select CLKSRC_I8253
>> 3168 select CLKEVT_I8253
>> 3169 select MIPS_EXTERNAL_TIMER
807 endmenu 3170 endmenu
808 3171
>> 3172 config TRAD_SIGNALS
>> 3173 bool
>> 3174
>> 3175 config MIPS32_COMPAT
>> 3176 bool
>> 3177
>> 3178 config COMPAT
>> 3179 bool
>> 3180
>> 3181 config MIPS32_O32
>> 3182 bool "Kernel support for o32 binaries"
>> 3183 depends on 64BIT
>> 3184 select ARCH_WANT_OLD_COMPAT_IPC
>> 3185 select COMPAT
>> 3186 select MIPS32_COMPAT
>> 3187 help
>> 3188 Select this option if you want to run o32 binaries. These are pure
>> 3189 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3190 existing binaries are in this format.
>> 3191
>> 3192 If unsure, say Y.
>> 3193
>> 3194 config MIPS32_N32
>> 3195 bool "Kernel support for n32 binaries"
>> 3196 depends on 64BIT
>> 3197 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3198 select COMPAT
>> 3199 select MIPS32_COMPAT
>> 3200 help
>> 3201 Select this option if you want to run n32 binaries. These are
>> 3202 64-bit binaries using 32-bit quantities for addressing and certain
>> 3203 data that would normally be 64-bit. They are used in special
>> 3204 cases.
>> 3205
>> 3206 If unsure, say N.
>> 3207
>> 3208 config CC_HAS_MNO_BRANCH_LIKELY
>> 3209 def_bool y
>> 3210 depends on $(cc-option,-mno-branch-likely)
>> 3211
809 menu "Power management options" 3212 menu "Power management options"
810 3213
811 config ARCH_HIBERNATION_POSSIBLE 3214 config ARCH_HIBERNATION_POSSIBLE
812 def_bool y 3215 def_bool y
>> 3216 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3217
>> 3218 config ARCH_SUSPEND_POSSIBLE
>> 3219 def_bool y
>> 3220 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
813 3221
814 source "kernel/power/Kconfig" 3222 source "kernel/power/Kconfig"
815 3223
816 endmenu 3224 endmenu
>> 3225
>> 3226 config MIPS_EXTERNAL_TIMER
>> 3227 bool
>> 3228
>> 3229 menu "CPU Power Management"
>> 3230
>> 3231 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3232 source "drivers/cpufreq/Kconfig"
>> 3233 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3234
>> 3235 source "drivers/cpuidle/Kconfig"
>> 3236
>> 3237 endmenu
>> 3238
>> 3239 source "arch/mips/kvm/Kconfig"
>> 3240
>> 3241 source "arch/mips/vdso/Kconfig"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.