1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 config XTENSA !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ARCH_32BIT_OFF_T !! 4 default y
>> 5 select ARCH_32BIT_OFF_T if !64BIT
>> 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
5 select ARCH_HAS_CPU_CACHE_ALIASING 7 select ARCH_HAS_CPU_CACHE_ALIASING
6 select ARCH_HAS_BINFMT_FLAT if !MMU !! 8 select ARCH_HAS_CPU_FINALIZE_INIT
7 select ARCH_HAS_CURRENT_STACK_POINTER !! 9 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
8 select ARCH_HAS_DEBUG_VM_PGTABLE !! 10 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
9 select ARCH_HAS_DMA_PREP_COHERENT if M !! 11 select ARCH_HAS_FORTIFY_SOURCE
10 select ARCH_HAS_GCOV_PROFILE_ALL <<
11 select ARCH_HAS_KCOV 12 select ARCH_HAS_KCOV
12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MM !! 13 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if !! 14 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
14 select ARCH_HAS_DMA_SET_UNCACHED if MM !! 15 select ARCH_HAS_STRNCPY_FROM_USER
15 select ARCH_HAS_STRNCPY_FROM_USER if ! <<
16 select ARCH_HAS_STRNLEN_USER 16 select ARCH_HAS_STRNLEN_USER
17 select ARCH_NEED_CMPXCHG_1_EMU !! 17 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 18 select ARCH_HAS_UBSAN
>> 19 select ARCH_HAS_GCOV_PROFILE_ALL
>> 20 select ARCH_KEEP_MEMBLOCK
>> 21 select ARCH_USE_BUILTIN_BSWAP
>> 22 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
18 select ARCH_USE_MEMTEST 23 select ARCH_USE_MEMTEST
19 select ARCH_USE_QUEUED_RWLOCKS 24 select ARCH_USE_QUEUED_RWLOCKS
20 select ARCH_USE_QUEUED_SPINLOCKS 25 select ARCH_USE_QUEUED_SPINLOCKS
>> 26 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
>> 27 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
21 select ARCH_WANT_IPC_PARSE_VERSION 28 select ARCH_WANT_IPC_PARSE_VERSION
>> 29 select ARCH_WANT_LD_ORPHAN_WARN
22 select BUILDTIME_TABLE_SORT 30 select BUILDTIME_TABLE_SORT
23 select CLONE_BACKWARDS 31 select CLONE_BACKWARDS
24 select COMMON_CLK !! 32 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
25 select DMA_NONCOHERENT_MMAP if MMU !! 33 select CPU_PM if CPU_IDLE
26 select GENERIC_ATOMIC64 !! 34 select GENERIC_ATOMIC64 if !64BIT
>> 35 select GENERIC_CMOS_UPDATE
>> 36 select GENERIC_CPU_AUTOPROBE
>> 37 select GENERIC_GETTIMEOFDAY
>> 38 select GENERIC_IOMAP
>> 39 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW 40 select GENERIC_IRQ_SHOW
>> 41 select GENERIC_ISA_DMA if EISA
>> 42 select GENERIC_LIB_ASHLDI3
>> 43 select GENERIC_LIB_ASHRDI3
28 select GENERIC_LIB_CMPDI2 44 select GENERIC_LIB_CMPDI2
29 select GENERIC_LIB_MULDI3 !! 45 select GENERIC_LIB_LSHRDI3
30 select GENERIC_LIB_UCMPDI2 46 select GENERIC_LIB_UCMPDI2
31 select GENERIC_PCI_IOMAP !! 47 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
32 select GENERIC_SCHED_CLOCK !! 48 select GENERIC_SMP_IDLE_THREAD
33 select GENERIC_IOREMAP if MMU !! 49 select GENERIC_IDLE_POLL_SETUP
34 select HAVE_ARCH_AUDITSYSCALL !! 50 select GENERIC_TIME_VSYSCALL
35 select HAVE_ARCH_JUMP_LABEL if !XIP_KE !! 51 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
36 select HAVE_ARCH_KASAN if MMU && !XIP_ !! 52 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
37 select HAVE_ARCH_KCSAN !! 53 select HAVE_ARCH_COMPILER_H
>> 54 select HAVE_ARCH_JUMP_LABEL
>> 55 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
>> 56 select HAVE_ARCH_MMAP_RND_BITS if MMU
>> 57 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
38 select HAVE_ARCH_SECCOMP_FILTER 58 select HAVE_ARCH_SECCOMP_FILTER
39 select HAVE_ARCH_TRACEHOOK 59 select HAVE_ARCH_TRACEHOOK
>> 60 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
40 select HAVE_ASM_MODVERSIONS 61 select HAVE_ASM_MODVERSIONS
41 select HAVE_CONTEXT_TRACKING_USER 62 select HAVE_CONTEXT_TRACKING_USER
>> 63 select HAVE_TIF_NOHZ
>> 64 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK 65 select HAVE_DEBUG_KMEMLEAK
>> 66 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_DMA_CONTIGUOUS 67 select HAVE_DMA_CONTIGUOUS
>> 68 select HAVE_DYNAMIC_FTRACE
>> 69 select HAVE_EBPF_JIT if !CPU_MICROMIPS
44 select HAVE_EXIT_THREAD 70 select HAVE_EXIT_THREAD
>> 71 select HAVE_GUP_FAST
>> 72 select HAVE_FTRACE_MCOUNT_RECORD
>> 73 select HAVE_FUNCTION_GRAPH_TRACER
45 select HAVE_FUNCTION_TRACER 74 select HAVE_FUNCTION_TRACER
46 select HAVE_GCC_PLUGINS if GCC_VERSION !! 75 select HAVE_GCC_PLUGINS
47 select HAVE_HW_BREAKPOINT if PERF_EVEN !! 76 select HAVE_GENERIC_VDSO
>> 77 select HAVE_IOREMAP_PROT
>> 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
48 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_PAGE_SIZE_4KB !! 80 select HAVE_KPROBES
50 select HAVE_PCI !! 81 select HAVE_KRETPROBES
>> 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 83 select HAVE_MOD_ARCH_SPECIFIC
>> 84 select HAVE_NMI
>> 85 select HAVE_PAGE_SIZE_4KB if !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 86 select HAVE_PAGE_SIZE_16KB if !CPU_R3000
>> 87 select HAVE_PAGE_SIZE_64KB if !CPU_R3000
51 select HAVE_PERF_EVENTS 88 select HAVE_PERF_EVENTS
>> 89 select HAVE_PERF_REGS
>> 90 select HAVE_PERF_USER_STACK_DUMP
>> 91 select HAVE_REGS_AND_STACK_ACCESS_API
>> 92 select HAVE_RSEQ
>> 93 select HAVE_SPARSE_SYSCALL_NR
52 select HAVE_STACKPROTECTOR 94 select HAVE_STACKPROTECTOR
53 select HAVE_SYSCALL_TRACEPOINTS 95 select HAVE_SYSCALL_TRACEPOINTS
54 select HAVE_VIRT_CPU_ACCOUNTING_GEN !! 96 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
55 select IRQ_DOMAIN !! 97 select IRQ_FORCED_THREADING
>> 98 select ISA if EISA
56 select LOCK_MM_AND_FIND_VMA 99 select LOCK_MM_AND_FIND_VMA
57 select MODULES_USE_ELF_RELA !! 100 select MODULES_USE_ELF_REL if MODULES
>> 101 select MODULES_USE_ELF_RELA if MODULES && 64BIT
58 select PERF_USE_VMALLOC 102 select PERF_USE_VMALLOC
>> 103 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
>> 104 select RTC_LIB
>> 105 select SYSCTL_EXCEPTION_TRACE
59 select TRACE_IRQFLAGS_SUPPORT 106 select TRACE_IRQFLAGS_SUPPORT
>> 107 select ARCH_HAS_ELFCORE_COMPAT
>> 108 select HAVE_ARCH_KCSAN if 64BIT
>> 109
>> 110 config MIPS_FIXUP_BIGPHYS_ADDR
>> 111 bool
>> 112
>> 113 config MIPS_GENERIC
>> 114 bool
>> 115
>> 116 config MACH_GENERIC_CORE
>> 117 bool
>> 118
>> 119 config MACH_INGENIC
>> 120 bool
>> 121 select SYS_SUPPORTS_32BIT_KERNEL
>> 122 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 123 select SYS_SUPPORTS_ZBOOT
>> 124 select DMA_NONCOHERENT
>> 125 select IRQ_MIPS_CPU
>> 126 select PINCTRL
>> 127 select GPIOLIB
>> 128 select COMMON_CLK
>> 129 select GENERIC_IRQ_CHIP
>> 130 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 131 select USE_OF
>> 132 select CPU_SUPPORTS_CPUFREQ
>> 133 select MIPS_EXTERNAL_TIMER
>> 134
>> 135 menu "Machine selection"
>> 136
>> 137 choice
>> 138 prompt "System type"
>> 139 default MIPS_GENERIC_KERNEL
>> 140
>> 141 config MIPS_GENERIC_KERNEL
>> 142 bool "Generic board-agnostic MIPS kernel"
>> 143 select MIPS_GENERIC
>> 144 select BOOT_RAW
>> 145 select BUILTIN_DTB
>> 146 select CEVT_R4K
>> 147 select CLKSRC_MIPS_GIC
>> 148 select COMMON_CLK
>> 149 select CPU_MIPSR2_IRQ_EI
>> 150 select CPU_MIPSR2_IRQ_VI
>> 151 select CSRC_R4K
>> 152 select DMA_NONCOHERENT
>> 153 select HAVE_PCI
>> 154 select IRQ_MIPS_CPU
>> 155 select MACH_GENERIC_CORE
>> 156 select MIPS_AUTO_PFN_OFFSET
>> 157 select MIPS_CPU_SCACHE
>> 158 select MIPS_GIC
>> 159 select MIPS_L1_CACHE_SHIFT_7
>> 160 select NO_EXCEPT_FILL
>> 161 select PCI_DRIVERS_GENERIC
>> 162 select SMP_UP if SMP
>> 163 select SWAP_IO_SPACE
>> 164 select SYS_HAS_CPU_MIPS32_R1
>> 165 select SYS_HAS_CPU_MIPS32_R2
>> 166 select SYS_HAS_CPU_MIPS32_R5
>> 167 select SYS_HAS_CPU_MIPS32_R6
>> 168 select SYS_HAS_CPU_MIPS64_R1
>> 169 select SYS_HAS_CPU_MIPS64_R2
>> 170 select SYS_HAS_CPU_MIPS64_R5
>> 171 select SYS_HAS_CPU_MIPS64_R6
>> 172 select SYS_SUPPORTS_32BIT_KERNEL
>> 173 select SYS_SUPPORTS_64BIT_KERNEL
>> 174 select SYS_SUPPORTS_BIG_ENDIAN
>> 175 select SYS_SUPPORTS_HIGHMEM
>> 176 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 177 select SYS_SUPPORTS_MICROMIPS
>> 178 select SYS_SUPPORTS_MIPS16
>> 179 select SYS_SUPPORTS_MIPS_CPS
>> 180 select SYS_SUPPORTS_MULTITHREADING
>> 181 select SYS_SUPPORTS_RELOCATABLE
>> 182 select SYS_SUPPORTS_SMARTMIPS
>> 183 select SYS_SUPPORTS_ZBOOT
>> 184 select UHI_BOOT
>> 185 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 186 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 187 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 188 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 189 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 190 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 191 select USE_OF
>> 192 help
>> 193 Select this to build a kernel which aims to support multiple boards,
>> 194 generally using a flattened device tree passed from the bootloader
>> 195 using the boot protocol defined in the UHI (Unified Hosting
>> 196 Interface) specification.
>> 197
>> 198 config MIPS_ALCHEMY
>> 199 bool "Alchemy processor based machines"
>> 200 select PHYS_ADDR_T_64BIT
>> 201 select CEVT_R4K
>> 202 select CSRC_R4K
>> 203 select IRQ_MIPS_CPU
>> 204 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 205 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 206 select SYS_HAS_CPU_MIPS32_R1
>> 207 select SYS_SUPPORTS_32BIT_KERNEL
>> 208 select SYS_SUPPORTS_APM_EMULATION
>> 209 select GPIOLIB
>> 210 select SYS_SUPPORTS_ZBOOT
>> 211 select COMMON_CLK
>> 212
>> 213 config ATH25
>> 214 bool "Atheros AR231x/AR531x SoC support"
>> 215 select CEVT_R4K
>> 216 select CSRC_R4K
>> 217 select DMA_NONCOHERENT
>> 218 select IRQ_MIPS_CPU
>> 219 select IRQ_DOMAIN
>> 220 select SYS_HAS_CPU_MIPS32_R1
>> 221 select SYS_SUPPORTS_BIG_ENDIAN
>> 222 select SYS_SUPPORTS_32BIT_KERNEL
>> 223 select SYS_HAS_EARLY_PRINTK
>> 224 help
>> 225 Support for Atheros AR231x and Atheros AR531x based boards
>> 226
>> 227 config ATH79
>> 228 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 229 select ARCH_HAS_RESET_CONTROLLER
>> 230 select BOOT_RAW
>> 231 select CEVT_R4K
>> 232 select CSRC_R4K
>> 233 select DMA_NONCOHERENT
>> 234 select GPIOLIB
>> 235 select PINCTRL
>> 236 select COMMON_CLK
>> 237 select IRQ_MIPS_CPU
>> 238 select SYS_HAS_CPU_MIPS32_R2
>> 239 select SYS_HAS_EARLY_PRINTK
>> 240 select SYS_SUPPORTS_32BIT_KERNEL
>> 241 select SYS_SUPPORTS_BIG_ENDIAN
>> 242 select SYS_SUPPORTS_MIPS16
>> 243 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 244 select USE_OF
>> 245 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 246 help
>> 247 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 248
>> 249 config BMIPS_GENERIC
>> 250 bool "Broadcom Generic BMIPS kernel"
>> 251 select ARCH_HAS_RESET_CONTROLLER
>> 252 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 253 select BOOT_RAW
>> 254 select NO_EXCEPT_FILL
>> 255 select USE_OF
>> 256 select CEVT_R4K
>> 257 select CSRC_R4K
>> 258 select SYNC_R4K
>> 259 select COMMON_CLK
>> 260 select BCM6345_L1_IRQ
>> 261 select BCM7038_L1_IRQ
>> 262 select BCM7120_L2_IRQ
>> 263 select BRCMSTB_L2_IRQ
>> 264 select IRQ_MIPS_CPU
>> 265 select DMA_NONCOHERENT
>> 266 select SYS_SUPPORTS_32BIT_KERNEL
>> 267 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 268 select SYS_SUPPORTS_BIG_ENDIAN
>> 269 select SYS_SUPPORTS_HIGHMEM
>> 270 select SYS_HAS_CPU_BMIPS32_3300
>> 271 select SYS_HAS_CPU_BMIPS4350
>> 272 select SYS_HAS_CPU_BMIPS4380
>> 273 select SYS_HAS_CPU_BMIPS5000
>> 274 select SWAP_IO_SPACE
>> 275 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 276 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 277 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 278 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 279 select HARDIRQS_SW_RESEND
>> 280 select HAVE_PCI
>> 281 select PCI_DRIVERS_GENERIC
>> 282 select FW_CFE
60 help 283 help
61 Xtensa processors are 32-bit RISC ma !! 284 Build a generic DT-based kernel image that boots on select
62 primarily for embedded systems. The !! 285 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
63 configurable and extensible. The Li !! 286 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
64 architecture supports all processor !! 287 must be set appropriately for your board.
65 with reasonable minimum requirements !! 288
66 a home page at <http://www.linux-xte !! 289 config BCM47XX
>> 290 bool "Broadcom BCM47XX based boards"
>> 291 select BOOT_RAW
>> 292 select CEVT_R4K
>> 293 select CSRC_R4K
>> 294 select DMA_NONCOHERENT
>> 295 select HAVE_PCI
>> 296 select IRQ_MIPS_CPU
>> 297 select SYS_HAS_CPU_MIPS32_R1
>> 298 select NO_EXCEPT_FILL
>> 299 select SYS_SUPPORTS_32BIT_KERNEL
>> 300 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 301 select SYS_SUPPORTS_MIPS16
>> 302 select SYS_SUPPORTS_ZBOOT
>> 303 select SYS_HAS_EARLY_PRINTK
>> 304 select USE_GENERIC_EARLY_PRINTK_8250
>> 305 select GPIOLIB
>> 306 select LEDS_GPIO_REGISTER
>> 307 select BCM47XX_NVRAM
>> 308 select BCM47XX_SPROM
>> 309 select BCM47XX_SSB if !BCM47XX_BCMA
>> 310 help
>> 311 Support for BCM47XX based boards
>> 312
>> 313 config BCM63XX
>> 314 bool "Broadcom BCM63XX based boards"
>> 315 select BOOT_RAW
>> 316 select CEVT_R4K
>> 317 select CSRC_R4K
>> 318 select SYNC_R4K
>> 319 select DMA_NONCOHERENT
>> 320 select IRQ_MIPS_CPU
>> 321 select SYS_SUPPORTS_32BIT_KERNEL
>> 322 select SYS_SUPPORTS_BIG_ENDIAN
>> 323 select SYS_HAS_EARLY_PRINTK
>> 324 select SYS_HAS_CPU_BMIPS32_3300
>> 325 select SYS_HAS_CPU_BMIPS4350
>> 326 select SYS_HAS_CPU_BMIPS4380
>> 327 select SWAP_IO_SPACE
>> 328 select GPIOLIB
>> 329 select MIPS_L1_CACHE_SHIFT_4
>> 330 select HAVE_LEGACY_CLK
>> 331 help
>> 332 Support for BCM63XX based boards
>> 333
>> 334 config MIPS_COBALT
>> 335 bool "Cobalt Server"
>> 336 select CEVT_R4K
>> 337 select CSRC_R4K
>> 338 select CEVT_GT641XX
>> 339 select DMA_NONCOHERENT
>> 340 select FORCE_PCI
>> 341 select I8253
>> 342 select I8259
>> 343 select IRQ_MIPS_CPU
>> 344 select IRQ_GT641XX
>> 345 select PCI_GT64XXX_PCI0
>> 346 select SYS_HAS_CPU_NEVADA
>> 347 select SYS_HAS_EARLY_PRINTK
>> 348 select SYS_SUPPORTS_32BIT_KERNEL
>> 349 select SYS_SUPPORTS_64BIT_KERNEL
>> 350 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 351 select USE_GENERIC_EARLY_PRINTK_8250
>> 352
>> 353 config MACH_DECSTATION
>> 354 bool "DECstations"
>> 355 select BOOT_ELF32
>> 356 select CEVT_DS1287
>> 357 select CEVT_R4K if CPU_R4X00
>> 358 select CSRC_IOASIC
>> 359 select CSRC_R4K if CPU_R4X00
>> 360 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 361 select CPU_R4000_WORKAROUNDS if 64BIT
>> 362 select CPU_R4400_WORKAROUNDS if 64BIT
>> 363 select DMA_NONCOHERENT
>> 364 select NO_IOPORT_MAP
>> 365 select IRQ_MIPS_CPU
>> 366 select SYS_HAS_CPU_R3000
>> 367 select SYS_HAS_CPU_R4X00
>> 368 select SYS_SUPPORTS_32BIT_KERNEL
>> 369 select SYS_SUPPORTS_64BIT_KERNEL
>> 370 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 371 select SYS_SUPPORTS_128HZ
>> 372 select SYS_SUPPORTS_256HZ
>> 373 select SYS_SUPPORTS_1024HZ
>> 374 select MIPS_L1_CACHE_SHIFT_4
>> 375 help
>> 376 This enables support for DEC's MIPS based workstations. For details
>> 377 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 378 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 379
>> 380 If you have one of the following DECstation Models you definitely
>> 381 want to choose R4xx0 for the CPU Type:
>> 382
>> 383 DECstation 5000/50
>> 384 DECstation 5000/150
>> 385 DECstation 5000/260
>> 386 DECsystem 5900/260
>> 387
>> 388 otherwise choose R3000.
>> 389
>> 390 config MACH_JAZZ
>> 391 bool "Jazz family of machines"
>> 392 select ARC_MEMORY
>> 393 select ARC_PROMLIB
>> 394 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 395 select ARCH_MIGHT_HAVE_PC_SERIO
>> 396 select DMA_OPS
>> 397 select FW_ARC
>> 398 select FW_ARC32
>> 399 select ARCH_MAY_HAVE_PC_FDC
>> 400 select CEVT_R4K
>> 401 select CSRC_R4K
>> 402 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 403 select GENERIC_ISA_DMA
>> 404 select HAVE_PCSPKR_PLATFORM
>> 405 select IRQ_MIPS_CPU
>> 406 select I8253
>> 407 select I8259
>> 408 select ISA
>> 409 select SYS_HAS_CPU_R4X00
>> 410 select SYS_SUPPORTS_32BIT_KERNEL
>> 411 select SYS_SUPPORTS_64BIT_KERNEL
>> 412 select SYS_SUPPORTS_100HZ
>> 413 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 414 help
>> 415 This a family of machines based on the MIPS R4030 chipset which was
>> 416 used by several vendors to build RISC/os and Windows NT workstations.
>> 417 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 418 Olivetti M700-10 workstations.
>> 419
>> 420 config MACH_INGENIC_SOC
>> 421 bool "Ingenic SoC based machines"
>> 422 select MIPS_GENERIC
>> 423 select MACH_INGENIC
>> 424 select MACH_GENERIC_CORE
>> 425 select SYS_SUPPORTS_ZBOOT_UART16550
>> 426 select CPU_SUPPORTS_CPUFREQ
>> 427 select MIPS_EXTERNAL_TIMER
>> 428
>> 429 config LANTIQ
>> 430 bool "Lantiq based platforms"
>> 431 select DMA_NONCOHERENT
>> 432 select IRQ_MIPS_CPU
>> 433 select CEVT_R4K
>> 434 select CSRC_R4K
>> 435 select NO_EXCEPT_FILL
>> 436 select SYS_HAS_CPU_MIPS32_R1
>> 437 select SYS_HAS_CPU_MIPS32_R2
>> 438 select SYS_SUPPORTS_BIG_ENDIAN
>> 439 select SYS_SUPPORTS_32BIT_KERNEL
>> 440 select SYS_SUPPORTS_MIPS16
>> 441 select SYS_SUPPORTS_MULTITHREADING
>> 442 select SYS_SUPPORTS_VPE_LOADER
>> 443 select SYS_HAS_EARLY_PRINTK
>> 444 select GPIOLIB
>> 445 select SWAP_IO_SPACE
>> 446 select BOOT_RAW
>> 447 select HAVE_LEGACY_CLK
>> 448 select USE_OF
>> 449 select PINCTRL
>> 450 select PINCTRL_LANTIQ
>> 451 select ARCH_HAS_RESET_CONTROLLER
>> 452 select RESET_CONTROLLER
>> 453
>> 454 config MACH_LOONGSON32
>> 455 bool "Loongson 32-bit family of machines"
>> 456 select SYS_SUPPORTS_ZBOOT
>> 457 help
>> 458 This enables support for the Loongson-1 family of machines.
>> 459
>> 460 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 461 the Institute of Computing Technology (ICT), Chinese Academy of
>> 462 Sciences (CAS).
>> 463
>> 464 config MACH_LOONGSON2EF
>> 465 bool "Loongson-2E/F family of machines"
>> 466 select SYS_SUPPORTS_ZBOOT
>> 467 help
>> 468 This enables the support of early Loongson-2E/F family of machines.
>> 469
>> 470 config MACH_LOONGSON64
>> 471 bool "Loongson 64-bit family of machines"
>> 472 select ARCH_DMA_DEFAULT_COHERENT
>> 473 select ARCH_SPARSEMEM_ENABLE
>> 474 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 475 select ARCH_MIGHT_HAVE_PC_SERIO
>> 476 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 477 select BOOT_ELF32
>> 478 select BOARD_SCACHE
>> 479 select CSRC_R4K
>> 480 select CEVT_R4K
>> 481 select FORCE_PCI
>> 482 select ISA
>> 483 select I8259
>> 484 select IRQ_MIPS_CPU
>> 485 select NO_EXCEPT_FILL
>> 486 select NR_CPUS_DEFAULT_64
>> 487 select USE_GENERIC_EARLY_PRINTK_8250
>> 488 select PCI_DRIVERS_GENERIC
>> 489 select SYS_HAS_CPU_LOONGSON64
>> 490 select SYS_HAS_EARLY_PRINTK
>> 491 select SYS_SUPPORTS_SMP
>> 492 select SYS_SUPPORTS_HOTPLUG_CPU
>> 493 select SYS_SUPPORTS_NUMA
>> 494 select SYS_SUPPORTS_64BIT_KERNEL
>> 495 select SYS_SUPPORTS_HIGHMEM
>> 496 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 497 select SYS_SUPPORTS_ZBOOT
>> 498 select SYS_SUPPORTS_RELOCATABLE
>> 499 select ZONE_DMA32
>> 500 select COMMON_CLK
>> 501 select USE_OF
>> 502 select BUILTIN_DTB
>> 503 select PCI_HOST_GENERIC
>> 504 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 505 help
>> 506 This enables the support of Loongson-2/3 family of machines.
>> 507
>> 508 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 509 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 510 and Loongson-2F which will be removed), developed by the Institute
>> 511 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 512
>> 513 config MIPS_MALTA
>> 514 bool "MIPS Malta board"
>> 515 select ARCH_MAY_HAVE_PC_FDC
>> 516 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 517 select ARCH_MIGHT_HAVE_PC_SERIO
>> 518 select BOOT_ELF32
>> 519 select BOOT_RAW
>> 520 select BUILTIN_DTB
>> 521 select CEVT_R4K
>> 522 select CLKSRC_MIPS_GIC
>> 523 select COMMON_CLK
>> 524 select CSRC_R4K
>> 525 select DMA_NONCOHERENT
>> 526 select GENERIC_ISA_DMA
>> 527 select HAVE_PCSPKR_PLATFORM
>> 528 select HAVE_PCI
>> 529 select I8253
>> 530 select I8259
>> 531 select IRQ_MIPS_CPU
>> 532 select MIPS_BONITO64
>> 533 select MIPS_CPU_SCACHE
>> 534 select MIPS_GIC
>> 535 select MIPS_L1_CACHE_SHIFT_6
>> 536 select MIPS_MSC
>> 537 select PCI_GT64XXX_PCI0
>> 538 select SMP_UP if SMP
>> 539 select SWAP_IO_SPACE
>> 540 select SYS_HAS_CPU_MIPS32_R1
>> 541 select SYS_HAS_CPU_MIPS32_R2
>> 542 select SYS_HAS_CPU_MIPS32_R3_5
>> 543 select SYS_HAS_CPU_MIPS32_R5
>> 544 select SYS_HAS_CPU_MIPS32_R6
>> 545 select SYS_HAS_CPU_MIPS64_R1
>> 546 select SYS_HAS_CPU_MIPS64_R2
>> 547 select SYS_HAS_CPU_MIPS64_R6
>> 548 select SYS_HAS_CPU_NEVADA
>> 549 select SYS_HAS_CPU_RM7000
>> 550 select SYS_SUPPORTS_32BIT_KERNEL
>> 551 select SYS_SUPPORTS_64BIT_KERNEL
>> 552 select SYS_SUPPORTS_BIG_ENDIAN
>> 553 select SYS_SUPPORTS_HIGHMEM
>> 554 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 555 select SYS_SUPPORTS_MICROMIPS
>> 556 select SYS_SUPPORTS_MIPS16
>> 557 select SYS_SUPPORTS_MIPS_CPS
>> 558 select SYS_SUPPORTS_MULTITHREADING
>> 559 select SYS_SUPPORTS_RELOCATABLE
>> 560 select SYS_SUPPORTS_SMARTMIPS
>> 561 select SYS_SUPPORTS_VPE_LOADER
>> 562 select SYS_SUPPORTS_ZBOOT
>> 563 select USE_OF
>> 564 select WAR_ICACHE_REFILLS
>> 565 select ZONE_DMA32 if 64BIT
>> 566 help
>> 567 This enables support for the MIPS Technologies Malta evaluation
>> 568 board.
>> 569
>> 570 config MACH_PIC32
>> 571 bool "Microchip PIC32 Family"
>> 572 help
>> 573 This enables support for the Microchip PIC32 family of platforms.
>> 574
>> 575 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 576 microcontrollers.
>> 577
>> 578 config MACH_EYEQ5
>> 579 bool "Mobileye EyeQ5 SoC"
>> 580 select MACH_GENERIC_CORE
>> 581 select ARM_AMBA
>> 582 select PHYSICAL_START_BOOL
>> 583 select ARCH_SPARSEMEM_DEFAULT if 64BIT
>> 584 select BOOT_RAW
>> 585 select BUILTIN_DTB
>> 586 select CEVT_R4K
>> 587 select CLKSRC_MIPS_GIC
>> 588 select COMMON_CLK
>> 589 select CPU_MIPSR2_IRQ_EI
>> 590 select CPU_MIPSR2_IRQ_VI
>> 591 select CSRC_R4K
>> 592 select DMA_NONCOHERENT
>> 593 select HAVE_PCI
>> 594 select IRQ_MIPS_CPU
>> 595 select MIPS_AUTO_PFN_OFFSET
>> 596 select MIPS_CPU_SCACHE
>> 597 select MIPS_GIC
>> 598 select MIPS_L1_CACHE_SHIFT_7
>> 599 select PCI_DRIVERS_GENERIC
>> 600 select SMP_UP if SMP
>> 601 select SWAP_IO_SPACE
>> 602 select SYS_HAS_CPU_MIPS64_R6
>> 603 select SYS_SUPPORTS_64BIT_KERNEL
>> 604 select SYS_SUPPORTS_HIGHMEM
>> 605 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 606 select SYS_SUPPORTS_MIPS_CPS
>> 607 select SYS_SUPPORTS_RELOCATABLE
>> 608 select SYS_SUPPORTS_ZBOOT
>> 609 select UHI_BOOT
>> 610 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 611 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 612 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 613 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 614 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 615 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 616 select USE_OF
>> 617 help
>> 618 Select this to build a kernel supporting EyeQ5 SoC from Mobileye.
>> 619
>> 620 bool
>> 621
>> 622 config MACH_NINTENDO64
>> 623 bool "Nintendo 64 console"
>> 624 select CEVT_R4K
>> 625 select CSRC_R4K
>> 626 select SYS_HAS_CPU_R4300
>> 627 select SYS_SUPPORTS_BIG_ENDIAN
>> 628 select SYS_SUPPORTS_ZBOOT
>> 629 select SYS_SUPPORTS_32BIT_KERNEL
>> 630 select SYS_SUPPORTS_64BIT_KERNEL
>> 631 select DMA_NONCOHERENT
>> 632 select IRQ_MIPS_CPU
>> 633
>> 634 config RALINK
>> 635 bool "Ralink based machines"
>> 636 select CEVT_R4K
>> 637 select COMMON_CLK
>> 638 select CSRC_R4K
>> 639 select BOOT_RAW
>> 640 select DMA_NONCOHERENT
>> 641 select IRQ_MIPS_CPU
>> 642 select USE_OF
>> 643 select SYS_HAS_CPU_MIPS32_R2
>> 644 select SYS_SUPPORTS_32BIT_KERNEL
>> 645 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 646 select SYS_SUPPORTS_MIPS16
>> 647 select SYS_SUPPORTS_ZBOOT
>> 648 select SYS_HAS_EARLY_PRINTK
>> 649 select ARCH_HAS_RESET_CONTROLLER
>> 650 select RESET_CONTROLLER
>> 651
>> 652 config MACH_REALTEK_RTL
>> 653 bool "Realtek RTL838x/RTL839x based machines"
>> 654 select MIPS_GENERIC
>> 655 select MACH_GENERIC_CORE
>> 656 select DMA_NONCOHERENT
>> 657 select IRQ_MIPS_CPU
>> 658 select CSRC_R4K
>> 659 select CEVT_R4K
>> 660 select SYS_HAS_CPU_MIPS32_R1
>> 661 select SYS_HAS_CPU_MIPS32_R2
>> 662 select SYS_SUPPORTS_BIG_ENDIAN
>> 663 select SYS_SUPPORTS_32BIT_KERNEL
>> 664 select SYS_SUPPORTS_MIPS16
>> 665 select SYS_SUPPORTS_MULTITHREADING
>> 666 select SYS_SUPPORTS_VPE_LOADER
>> 667 select BOOT_RAW
>> 668 select PINCTRL
>> 669 select USE_OF
>> 670
>> 671 config SGI_IP22
>> 672 bool "SGI IP22 (Indy/Indigo2)"
>> 673 select ARC_MEMORY
>> 674 select ARC_PROMLIB
>> 675 select FW_ARC
>> 676 select FW_ARC32
>> 677 select ARCH_MIGHT_HAVE_PC_SERIO
>> 678 select BOOT_ELF32
>> 679 select CEVT_R4K
>> 680 select CSRC_R4K
>> 681 select DEFAULT_SGI_PARTITION
>> 682 select DMA_NONCOHERENT
>> 683 select HAVE_EISA
>> 684 select I8253
>> 685 select I8259
>> 686 select IP22_CPU_SCACHE
>> 687 select IRQ_MIPS_CPU
>> 688 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 689 select SGI_HAS_I8042
>> 690 select SGI_HAS_INDYDOG
>> 691 select SGI_HAS_HAL2
>> 692 select SGI_HAS_SEEQ
>> 693 select SGI_HAS_WD93
>> 694 select SGI_HAS_ZILOG
>> 695 select SWAP_IO_SPACE
>> 696 select SYS_HAS_CPU_R4X00
>> 697 select SYS_HAS_CPU_R5000
>> 698 select SYS_HAS_EARLY_PRINTK
>> 699 select SYS_SUPPORTS_32BIT_KERNEL
>> 700 select SYS_SUPPORTS_64BIT_KERNEL
>> 701 select SYS_SUPPORTS_BIG_ENDIAN
>> 702 select WAR_R4600_V1_INDEX_ICACHEOP
>> 703 select WAR_R4600_V1_HIT_CACHEOP
>> 704 select WAR_R4600_V2_HIT_CACHEOP
>> 705 select MIPS_L1_CACHE_SHIFT_7
>> 706 help
>> 707 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 708 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 709 that runs on these, say Y here.
>> 710
>> 711 config SGI_IP27
>> 712 bool "SGI IP27 (Origin200/2000)"
>> 713 select ARCH_HAS_PHYS_TO_DMA
>> 714 select ARCH_SPARSEMEM_ENABLE
>> 715 select FW_ARC
>> 716 select FW_ARC64
>> 717 select ARC_CMDLINE_ONLY
>> 718 select BOOT_ELF64
>> 719 select DEFAULT_SGI_PARTITION
>> 720 select FORCE_PCI
>> 721 select SYS_HAS_EARLY_PRINTK
>> 722 select HAVE_PCI
>> 723 select IRQ_MIPS_CPU
>> 724 select IRQ_DOMAIN_HIERARCHY
>> 725 select NR_CPUS_DEFAULT_64
>> 726 select PCI_DRIVERS_GENERIC
>> 727 select PCI_XTALK_BRIDGE
>> 728 select SYS_HAS_CPU_R10000
>> 729 select SYS_SUPPORTS_64BIT_KERNEL
>> 730 select SYS_SUPPORTS_BIG_ENDIAN
>> 731 select SYS_SUPPORTS_NUMA
>> 732 select SYS_SUPPORTS_SMP
>> 733 select WAR_R10000_LLSC
>> 734 select MIPS_L1_CACHE_SHIFT_7
>> 735 select NUMA
>> 736 select HAVE_ARCH_NODEDATA_EXTENSION
>> 737 help
>> 738 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 739 workstations. To compile a Linux kernel that runs on these, say Y
>> 740 here.
>> 741
>> 742 config SGI_IP28
>> 743 bool "SGI IP28 (Indigo2 R10k)"
>> 744 select ARC_MEMORY
>> 745 select ARC_PROMLIB
>> 746 select FW_ARC
>> 747 select FW_ARC64
>> 748 select ARCH_MIGHT_HAVE_PC_SERIO
>> 749 select BOOT_ELF64
>> 750 select CEVT_R4K
>> 751 select CSRC_R4K
>> 752 select DEFAULT_SGI_PARTITION
>> 753 select DMA_NONCOHERENT
>> 754 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 755 select IRQ_MIPS_CPU
>> 756 select HAVE_EISA
>> 757 select I8253
>> 758 select I8259
>> 759 select SGI_HAS_I8042
>> 760 select SGI_HAS_INDYDOG
>> 761 select SGI_HAS_HAL2
>> 762 select SGI_HAS_SEEQ
>> 763 select SGI_HAS_WD93
>> 764 select SGI_HAS_ZILOG
>> 765 select SWAP_IO_SPACE
>> 766 select SYS_HAS_CPU_R10000
>> 767 select SYS_HAS_EARLY_PRINTK
>> 768 select SYS_SUPPORTS_64BIT_KERNEL
>> 769 select SYS_SUPPORTS_BIG_ENDIAN
>> 770 select WAR_R10000_LLSC
>> 771 select MIPS_L1_CACHE_SHIFT_7
>> 772 help
>> 773 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 774 kernel that runs on these, say Y here.
>> 775
>> 776 config SGI_IP30
>> 777 bool "SGI IP30 (Octane/Octane2)"
>> 778 select ARCH_HAS_PHYS_TO_DMA
>> 779 select FW_ARC
>> 780 select FW_ARC64
>> 781 select BOOT_ELF64
>> 782 select CEVT_R4K
>> 783 select CSRC_R4K
>> 784 select FORCE_PCI
>> 785 select SYNC_R4K if SMP
>> 786 select ZONE_DMA32
>> 787 select HAVE_PCI
>> 788 select IRQ_MIPS_CPU
>> 789 select IRQ_DOMAIN_HIERARCHY
>> 790 select PCI_DRIVERS_GENERIC
>> 791 select PCI_XTALK_BRIDGE
>> 792 select SYS_HAS_EARLY_PRINTK
>> 793 select SYS_HAS_CPU_R10000
>> 794 select SYS_SUPPORTS_64BIT_KERNEL
>> 795 select SYS_SUPPORTS_BIG_ENDIAN
>> 796 select SYS_SUPPORTS_SMP
>> 797 select WAR_R10000_LLSC
>> 798 select MIPS_L1_CACHE_SHIFT_7
>> 799 select ARC_MEMORY
>> 800 help
>> 801 These are the SGI Octane and Octane2 graphics workstations. To
>> 802 compile a Linux kernel that runs on these, say Y here.
>> 803
>> 804 config SGI_IP32
>> 805 bool "SGI IP32 (O2)"
>> 806 select ARC_MEMORY
>> 807 select ARC_PROMLIB
>> 808 select ARCH_HAS_PHYS_TO_DMA
>> 809 select FW_ARC
>> 810 select FW_ARC32
>> 811 select BOOT_ELF32
>> 812 select CEVT_R4K
>> 813 select CSRC_R4K
>> 814 select DMA_NONCOHERENT
>> 815 select HAVE_PCI
>> 816 select IRQ_MIPS_CPU
>> 817 select R5000_CPU_SCACHE
>> 818 select RM7000_CPU_SCACHE
>> 819 select SYS_HAS_CPU_R5000
>> 820 select SYS_HAS_CPU_R10000 if BROKEN
>> 821 select SYS_HAS_CPU_RM7000
>> 822 select SYS_HAS_CPU_NEVADA
>> 823 select SYS_SUPPORTS_64BIT_KERNEL
>> 824 select SYS_SUPPORTS_BIG_ENDIAN
>> 825 select WAR_ICACHE_REFILLS
>> 826 help
>> 827 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 828
>> 829 config SIBYTE_CRHONE
>> 830 bool "Sibyte BCM91125C-CRhone"
>> 831 select BOOT_ELF32
>> 832 select SIBYTE_BCM1125
>> 833 select SWAP_IO_SPACE
>> 834 select SYS_HAS_CPU_SB1
>> 835 select SYS_SUPPORTS_BIG_ENDIAN
>> 836 select SYS_SUPPORTS_HIGHMEM
>> 837 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 838
>> 839 config SIBYTE_RHONE
>> 840 bool "Sibyte BCM91125E-Rhone"
>> 841 select BOOT_ELF32
>> 842 select SIBYTE_SB1250
>> 843 select SWAP_IO_SPACE
>> 844 select SYS_HAS_CPU_SB1
>> 845 select SYS_SUPPORTS_BIG_ENDIAN
>> 846 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 847
>> 848 config SIBYTE_SWARM
>> 849 bool "Sibyte BCM91250A-SWARM"
>> 850 select BOOT_ELF32
>> 851 select HAVE_PATA_PLATFORM
>> 852 select SIBYTE_SB1250
>> 853 select SWAP_IO_SPACE
>> 854 select SYS_HAS_CPU_SB1
>> 855 select SYS_SUPPORTS_BIG_ENDIAN
>> 856 select SYS_SUPPORTS_HIGHMEM
>> 857 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 858 select ZONE_DMA32 if 64BIT
>> 859 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 860
>> 861 config SIBYTE_LITTLESUR
>> 862 bool "Sibyte BCM91250C2-LittleSur"
>> 863 select BOOT_ELF32
>> 864 select HAVE_PATA_PLATFORM
>> 865 select SIBYTE_SB1250
>> 866 select SWAP_IO_SPACE
>> 867 select SYS_HAS_CPU_SB1
>> 868 select SYS_SUPPORTS_BIG_ENDIAN
>> 869 select SYS_SUPPORTS_HIGHMEM
>> 870 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 871 select ZONE_DMA32 if 64BIT
>> 872
>> 873 config SIBYTE_SENTOSA
>> 874 bool "Sibyte BCM91250E-Sentosa"
>> 875 select BOOT_ELF32
>> 876 select SIBYTE_SB1250
>> 877 select SWAP_IO_SPACE
>> 878 select SYS_HAS_CPU_SB1
>> 879 select SYS_SUPPORTS_BIG_ENDIAN
>> 880 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 881 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 882
>> 883 config SIBYTE_BIGSUR
>> 884 bool "Sibyte BCM91480B-BigSur"
>> 885 select BOOT_ELF32
>> 886 select NR_CPUS_DEFAULT_4
>> 887 select SIBYTE_BCM1x80
>> 888 select SWAP_IO_SPACE
>> 889 select SYS_HAS_CPU_SB1
>> 890 select SYS_SUPPORTS_BIG_ENDIAN
>> 891 select SYS_SUPPORTS_HIGHMEM
>> 892 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 893 select ZONE_DMA32 if 64BIT
>> 894 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 895
>> 896 config SNI_RM
>> 897 bool "SNI RM200/300/400"
>> 898 select ARC_MEMORY
>> 899 select ARC_PROMLIB
>> 900 select FW_ARC if CPU_LITTLE_ENDIAN
>> 901 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 902 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 903 select ARCH_MAY_HAVE_PC_FDC
>> 904 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 905 select ARCH_MIGHT_HAVE_PC_SERIO
>> 906 select BOOT_ELF32
>> 907 select CEVT_R4K
>> 908 select CSRC_R4K
>> 909 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 910 select DMA_NONCOHERENT
>> 911 select GENERIC_ISA_DMA
>> 912 select HAVE_EISA
>> 913 select HAVE_PCSPKR_PLATFORM
>> 914 select HAVE_PCI
>> 915 select IRQ_MIPS_CPU
>> 916 select I8253
>> 917 select I8259
>> 918 select ISA
>> 919 select MIPS_L1_CACHE_SHIFT_6
>> 920 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 921 select SYS_HAS_CPU_R4X00
>> 922 select SYS_HAS_CPU_R5000
>> 923 select SYS_HAS_CPU_R10000
>> 924 select R5000_CPU_SCACHE
>> 925 select SYS_HAS_EARLY_PRINTK
>> 926 select SYS_SUPPORTS_32BIT_KERNEL
>> 927 select SYS_SUPPORTS_64BIT_KERNEL
>> 928 select SYS_SUPPORTS_BIG_ENDIAN
>> 929 select SYS_SUPPORTS_HIGHMEM
>> 930 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 931 select WAR_R4600_V2_HIT_CACHEOP
>> 932 help
>> 933 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 934 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 935 Technology and now in turn merged with Fujitsu. Say Y here to
>> 936 support this machine type.
>> 937
>> 938 config MACH_TX49XX
>> 939 bool "Toshiba TX49 series based machines"
>> 940 select WAR_TX49XX_ICACHE_INDEX_INV
>> 941
>> 942 config MIKROTIK_RB532
>> 943 bool "Mikrotik RB532 boards"
>> 944 select CEVT_R4K
>> 945 select CSRC_R4K
>> 946 select DMA_NONCOHERENT
>> 947 select HAVE_PCI
>> 948 select IRQ_MIPS_CPU
>> 949 select SYS_HAS_CPU_MIPS32_R1
>> 950 select SYS_SUPPORTS_32BIT_KERNEL
>> 951 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 952 select SWAP_IO_SPACE
>> 953 select BOOT_RAW
>> 954 select GPIOLIB
>> 955 select MIPS_L1_CACHE_SHIFT_4
>> 956 help
>> 957 Support the Mikrotik(tm) RouterBoard 532 series,
>> 958 based on the IDT RC32434 SoC.
>> 959
>> 960 config CAVIUM_OCTEON_SOC
>> 961 bool "Cavium Networks Octeon SoC based boards"
>> 962 select CEVT_R4K
>> 963 select ARCH_HAS_PHYS_TO_DMA
>> 964 select HAVE_RAPIDIO
>> 965 select PHYS_ADDR_T_64BIT
>> 966 select SYS_SUPPORTS_64BIT_KERNEL
>> 967 select SYS_SUPPORTS_BIG_ENDIAN
>> 968 select EDAC_SUPPORT
>> 969 select EDAC_ATOMIC_SCRUB
>> 970 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 971 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 972 select SYS_HAS_EARLY_PRINTK
>> 973 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 974 select HAVE_PCI
>> 975 select HAVE_PLAT_DELAY
>> 976 select HAVE_PLAT_FW_INIT_CMDLINE
>> 977 select HAVE_PLAT_MEMCPY
>> 978 select ZONE_DMA32
>> 979 select GPIOLIB
>> 980 select USE_OF
>> 981 select ARCH_SPARSEMEM_ENABLE
>> 982 select SYS_SUPPORTS_SMP
>> 983 select NR_CPUS_DEFAULT_64
>> 984 select MIPS_NR_CPU_NR_MAP_1024
>> 985 select BUILTIN_DTB
>> 986 select MTD
>> 987 select MTD_COMPLEX_MAPPINGS
>> 988 select SWIOTLB
>> 989 select SYS_SUPPORTS_RELOCATABLE
>> 990 help
>> 991 This option supports all of the Octeon reference boards from Cavium
>> 992 Networks. It builds a kernel that dynamically determines the Octeon
>> 993 CPU type and supports all known board reference implementations.
>> 994 Some of the supported boards are:
>> 995 EBT3000
>> 996 EBH3000
>> 997 EBH3100
>> 998 Thunder
>> 999 Kodama
>> 1000 Hikari
>> 1001 Say Y here for most Octeon reference boards.
>> 1002
>> 1003 endchoice
>> 1004
>> 1005 config FIT_IMAGE_FDT_EPM5
>> 1006 bool "Include FDT for Mobileye EyeQ5 development platforms"
>> 1007 depends on MACH_EYEQ5
>> 1008 default n
>> 1009 help
>> 1010 Enable this to include the FDT for the EyeQ5 development platforms
>> 1011 from Mobileye in the FIT kernel image.
>> 1012 This requires u-boot on the platform.
>> 1013
>> 1014 source "arch/mips/alchemy/Kconfig"
>> 1015 source "arch/mips/ath25/Kconfig"
>> 1016 source "arch/mips/ath79/Kconfig"
>> 1017 source "arch/mips/bcm47xx/Kconfig"
>> 1018 source "arch/mips/bcm63xx/Kconfig"
>> 1019 source "arch/mips/bmips/Kconfig"
>> 1020 source "arch/mips/generic/Kconfig"
>> 1021 source "arch/mips/ingenic/Kconfig"
>> 1022 source "arch/mips/jazz/Kconfig"
>> 1023 source "arch/mips/lantiq/Kconfig"
>> 1024 source "arch/mips/pic32/Kconfig"
>> 1025 source "arch/mips/ralink/Kconfig"
>> 1026 source "arch/mips/sgi-ip27/Kconfig"
>> 1027 source "arch/mips/sibyte/Kconfig"
>> 1028 source "arch/mips/txx9/Kconfig"
>> 1029 source "arch/mips/cavium-octeon/Kconfig"
>> 1030 source "arch/mips/loongson2ef/Kconfig"
>> 1031 source "arch/mips/loongson32/Kconfig"
>> 1032 source "arch/mips/loongson64/Kconfig"
>> 1033
>> 1034 endmenu
67 1035
68 config GENERIC_HWEIGHT 1036 config GENERIC_HWEIGHT
69 def_bool y !! 1037 bool
>> 1038 default y
70 1039
71 config ARCH_HAS_ILOG2_U32 !! 1040 config GENERIC_CALIBRATE_DELAY
72 def_bool n !! 1041 bool
>> 1042 default y
73 1043
74 config ARCH_HAS_ILOG2_U64 !! 1044 config SCHED_OMIT_FRAME_POINTER
75 def_bool n !! 1045 bool
>> 1046 default y
>> 1047
>> 1048 #
>> 1049 # Select some configuration options automatically based on user selections.
>> 1050 #
>> 1051 config FW_ARC
>> 1052 bool
>> 1053
>> 1054 config ARCH_MAY_HAVE_PC_FDC
>> 1055 bool
>> 1056
>> 1057 config BOOT_RAW
>> 1058 bool
76 1059
77 config ARCH_MTD_XIP !! 1060 config CEVT_BCM1480
>> 1061 bool
>> 1062
>> 1063 config CEVT_DS1287
>> 1064 bool
>> 1065
>> 1066 config CEVT_GT641XX
>> 1067 bool
>> 1068
>> 1069 config CEVT_R4K
>> 1070 bool
>> 1071
>> 1072 config CEVT_SB1250
>> 1073 bool
>> 1074
>> 1075 config CEVT_TXX9
>> 1076 bool
>> 1077
>> 1078 config CSRC_BCM1480
>> 1079 bool
>> 1080
>> 1081 config CSRC_IOASIC
>> 1082 bool
>> 1083
>> 1084 config CSRC_R4K
>> 1085 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1086 bool
>> 1087
>> 1088 config CSRC_SB1250
>> 1089 bool
>> 1090
>> 1091 config MIPS_CLOCK_VSYSCALL
>> 1092 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1093
>> 1094 config GPIO_TXX9
>> 1095 select GPIOLIB
>> 1096 bool
>> 1097
>> 1098 config FW_CFE
>> 1099 bool
>> 1100
>> 1101 config ARCH_SUPPORTS_UPROBES
78 def_bool y 1102 def_bool y
79 1103
>> 1104 config DMA_NONCOHERENT
>> 1105 bool
>> 1106 #
>> 1107 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1108 # Attribute bits. It is believed that the uncached access through
>> 1109 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1110 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1111 # significant advantages.
>> 1112 #
>> 1113 select ARCH_HAS_SETUP_DMA_OPS
>> 1114 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1115 select ARCH_HAS_DMA_PREP_COHERENT
>> 1116 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 1117 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1118 select ARCH_HAS_DMA_SET_UNCACHED
>> 1119 select DMA_NONCOHERENT_MMAP
>> 1120 select NEED_DMA_MAP_STATE
>> 1121
>> 1122 config SYS_HAS_EARLY_PRINTK
>> 1123 bool
>> 1124
>> 1125 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1126 bool
>> 1127
>> 1128 config MIPS_BONITO64
>> 1129 bool
>> 1130
>> 1131 config MIPS_MSC
>> 1132 bool
>> 1133
>> 1134 config SYNC_R4K
>> 1135 bool
>> 1136
80 config NO_IOPORT_MAP 1137 config NO_IOPORT_MAP
81 def_bool n 1138 def_bool n
82 1139
83 config HZ !! 1140 config GENERIC_CSUM
84 int !! 1141 def_bool CPU_NO_LOAD_STORE_LR
85 default 100 <<
86 1142
87 config LOCKDEP_SUPPORT !! 1143 config GENERIC_ISA_DMA
88 def_bool y !! 1144 bool
>> 1145 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1146 select ISA_DMA_API
89 1147
90 config STACKTRACE_SUPPORT !! 1148 config GENERIC_ISA_DMA_SUPPORT_BROKEN
91 def_bool y !! 1149 bool
>> 1150 select GENERIC_ISA_DMA
92 1151
93 config MMU !! 1152 config HAVE_PLAT_DELAY
94 def_bool n !! 1153 bool
95 select PFAULT <<
96 1154
97 config HAVE_XTENSA_GPIO32 !! 1155 config HAVE_PLAT_FW_INIT_CMDLINE
98 def_bool n !! 1156 bool
>> 1157
>> 1158 config HAVE_PLAT_MEMCPY
>> 1159 bool
>> 1160
>> 1161 config ISA_DMA_API
>> 1162 bool
99 1163
100 config KASAN_SHADOW_OFFSET !! 1164 config SYS_SUPPORTS_RELOCATABLE
101 hex !! 1165 bool
102 default 0x6e400000 !! 1166 help
>> 1167 Selected if the platform supports relocating the kernel.
>> 1168 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1169 to allow access to command line and entropy sources.
>> 1170
>> 1171 #
>> 1172 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1173 # answer,so we try hard to limit the available choices. Also the use of a
>> 1174 # choice statement should be more obvious to the user.
>> 1175 #
>> 1176 choice
>> 1177 prompt "Endianness selection"
>> 1178 help
>> 1179 Some MIPS machines can be configured for either little or big endian
>> 1180 byte order. These modes require different kernels and a different
>> 1181 Linux distribution. In general there is one preferred byteorder for a
>> 1182 particular system but some systems are just as commonly used in the
>> 1183 one or the other endianness.
103 1184
104 config CPU_BIG_ENDIAN 1185 config CPU_BIG_ENDIAN
105 def_bool $(success,test "$(shell,echo !! 1186 bool "Big endian"
>> 1187 depends on SYS_SUPPORTS_BIG_ENDIAN
106 1188
107 config CPU_LITTLE_ENDIAN 1189 config CPU_LITTLE_ENDIAN
108 def_bool !CPU_BIG_ENDIAN !! 1190 bool "Little endian"
>> 1191 depends on SYS_SUPPORTS_LITTLE_ENDIAN
109 1192
110 config CC_HAVE_CALL0_ABI !! 1193 endchoice
111 def_bool $(success,test "$(shell,echo <<
112 1194
113 menu "Processor type and features" !! 1195 config EXPORT_UASM
>> 1196 bool
114 1197
115 choice !! 1198 config SYS_SUPPORTS_APM_EMULATION
116 prompt "Xtensa Processor Configuration !! 1199 bool
117 default XTENSA_VARIANT_FSF !! 1200
>> 1201 config SYS_SUPPORTS_BIG_ENDIAN
>> 1202 bool
118 1203
119 config XTENSA_VARIANT_FSF !! 1204 config SYS_SUPPORTS_LITTLE_ENDIAN
120 bool "fsf - default (not generic) conf !! 1205 bool
121 select MMU <<
122 1206
123 config XTENSA_VARIANT_DC232B !! 1207 config MIPS_HUGE_TLB_SUPPORT
124 bool "dc232b - Diamond 232L Standard C !! 1208 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
125 select MMU <<
126 select HAVE_XTENSA_GPIO32 <<
127 help <<
128 This variant refers to Tensilica's D <<
129 1209
130 config XTENSA_VARIANT_DC233C !! 1210 config IRQ_TXX9
131 bool "dc233c - Diamond 233L Standard C !! 1211 bool
132 select MMU !! 1212
133 select HAVE_XTENSA_GPIO32 !! 1213 config IRQ_GT641XX
134 help !! 1214 bool
135 This variant refers to Tensilica's D !! 1215
>> 1216 config PCI_GT64XXX_PCI0
>> 1217 bool
>> 1218
>> 1219 config PCI_XTALK_BRIDGE
>> 1220 bool
>> 1221
>> 1222 config NO_EXCEPT_FILL
>> 1223 bool
>> 1224
>> 1225 config MIPS_SPRAM
>> 1226 bool
>> 1227
>> 1228 config SWAP_IO_SPACE
>> 1229 bool
>> 1230
>> 1231 config SGI_HAS_INDYDOG
>> 1232 bool
>> 1233
>> 1234 config SGI_HAS_HAL2
>> 1235 bool
>> 1236
>> 1237 config SGI_HAS_SEEQ
>> 1238 bool
>> 1239
>> 1240 config SGI_HAS_WD93
>> 1241 bool
>> 1242
>> 1243 config SGI_HAS_ZILOG
>> 1244 bool
>> 1245
>> 1246 config SGI_HAS_I8042
>> 1247 bool
>> 1248
>> 1249 config DEFAULT_SGI_PARTITION
>> 1250 bool
>> 1251
>> 1252 config FW_ARC32
>> 1253 bool
>> 1254
>> 1255 config FW_SNIPROM
>> 1256 bool
>> 1257
>> 1258 config BOOT_ELF32
>> 1259 bool
>> 1260
>> 1261 config MIPS_L1_CACHE_SHIFT_4
>> 1262 bool
>> 1263
>> 1264 config MIPS_L1_CACHE_SHIFT_5
>> 1265 bool
>> 1266
>> 1267 config MIPS_L1_CACHE_SHIFT_6
>> 1268 bool
>> 1269
>> 1270 config MIPS_L1_CACHE_SHIFT_7
>> 1271 bool
>> 1272
>> 1273 config MIPS_L1_CACHE_SHIFT
>> 1274 int
>> 1275 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1276 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1277 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1278 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1279 default "5"
>> 1280
>> 1281 config ARC_CMDLINE_ONLY
>> 1282 bool
>> 1283
>> 1284 config ARC_CONSOLE
>> 1285 bool "ARC console support"
>> 1286 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
>> 1287
>> 1288 config ARC_MEMORY
>> 1289 bool
>> 1290
>> 1291 config ARC_PROMLIB
>> 1292 bool
136 1293
137 config XTENSA_VARIANT_CUSTOM !! 1294 config FW_ARC64
138 bool "Custom Xtensa processor configur !! 1295 bool
139 select HAVE_XTENSA_GPIO32 !! 1296
>> 1297 config BOOT_ELF64
>> 1298 bool
>> 1299
>> 1300 menu "CPU selection"
>> 1301
>> 1302 choice
>> 1303 prompt "CPU type"
>> 1304 default CPU_R4X00
>> 1305
>> 1306 config CPU_LOONGSON64
>> 1307 bool "Loongson 64-bit CPU"
>> 1308 depends on SYS_HAS_CPU_LOONGSON64
>> 1309 select ARCH_HAS_PHYS_TO_DMA
>> 1310 select CPU_MIPSR2
>> 1311 select CPU_HAS_PREFETCH
>> 1312 select CPU_SUPPORTS_64BIT_KERNEL
>> 1313 select CPU_SUPPORTS_HIGHMEM
>> 1314 select CPU_SUPPORTS_HUGEPAGES
>> 1315 select CPU_SUPPORTS_MSA
>> 1316 select CPU_SUPPORTS_VZ
>> 1317 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1318 select CPU_MIPSR2_IRQ_VI
>> 1319 select DMA_NONCOHERENT
>> 1320 select WEAK_ORDERING
>> 1321 select WEAK_REORDERING_BEYOND_LLSC
>> 1322 select MIPS_ASID_BITS_VARIABLE
>> 1323 select MIPS_PGD_C0_CONTEXT
>> 1324 select MIPS_L1_CACHE_SHIFT_6
>> 1325 select MIPS_FP_SUPPORT
>> 1326 select GPIOLIB
>> 1327 select SWIOTLB
>> 1328 help
>> 1329 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1330 cores implements the MIPS64R2 instruction set with many extensions,
>> 1331 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1332 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1333 Loongson-2E/2F is not covered here and will be removed in future.
>> 1334
>> 1335 config CPU_LOONGSON2E
>> 1336 bool "Loongson 2E"
>> 1337 depends on SYS_HAS_CPU_LOONGSON2E
>> 1338 select CPU_LOONGSON2EF
>> 1339 help
>> 1340 The Loongson 2E processor implements the MIPS III instruction set
>> 1341 with many extensions.
>> 1342
>> 1343 It has an internal FPGA northbridge, which is compatible to
>> 1344 bonito64.
>> 1345
>> 1346 config CPU_LOONGSON2F
>> 1347 bool "Loongson 2F"
>> 1348 depends on SYS_HAS_CPU_LOONGSON2F
>> 1349 select CPU_LOONGSON2EF
>> 1350 help
>> 1351 The Loongson 2F processor implements the MIPS III instruction set
>> 1352 with many extensions.
>> 1353
>> 1354 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1355 have a similar programming interface with FPGA northbridge used in
>> 1356 Loongson2E.
>> 1357
>> 1358 config CPU_LOONGSON1B
>> 1359 bool "Loongson 1B"
>> 1360 depends on SYS_HAS_CPU_LOONGSON1B
>> 1361 select CPU_LOONGSON32
>> 1362 select LEDS_GPIO_REGISTER
>> 1363 help
>> 1364 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1365 Release 1 instruction set and part of the MIPS32 Release 2
>> 1366 instruction set.
>> 1367
>> 1368 config CPU_LOONGSON1C
>> 1369 bool "Loongson 1C"
>> 1370 depends on SYS_HAS_CPU_LOONGSON1C
>> 1371 select CPU_LOONGSON32
>> 1372 select LEDS_GPIO_REGISTER
>> 1373 help
>> 1374 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1375 Release 1 instruction set and part of the MIPS32 Release 2
>> 1376 instruction set.
>> 1377
>> 1378 config CPU_MIPS32_R1
>> 1379 bool "MIPS32 Release 1"
>> 1380 depends on SYS_HAS_CPU_MIPS32_R1
>> 1381 select CPU_HAS_PREFETCH
>> 1382 select CPU_SUPPORTS_32BIT_KERNEL
>> 1383 select CPU_SUPPORTS_HIGHMEM
>> 1384 help
>> 1385 Choose this option to build a kernel for release 1 or later of the
>> 1386 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1387 MIPS processor are based on a MIPS32 processor. If you know the
>> 1388 specific type of processor in your system, choose those that one
>> 1389 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1390 Release 2 of the MIPS32 architecture is available since several
>> 1391 years so chances are you even have a MIPS32 Release 2 processor
>> 1392 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1393 performance.
>> 1394
>> 1395 config CPU_MIPS32_R2
>> 1396 bool "MIPS32 Release 2"
>> 1397 depends on SYS_HAS_CPU_MIPS32_R2
>> 1398 select CPU_HAS_PREFETCH
>> 1399 select CPU_SUPPORTS_32BIT_KERNEL
>> 1400 select CPU_SUPPORTS_HIGHMEM
>> 1401 select CPU_SUPPORTS_MSA
>> 1402 help
>> 1403 Choose this option to build a kernel for release 2 or later of the
>> 1404 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1405 MIPS processor are based on a MIPS32 processor. If you know the
>> 1406 specific type of processor in your system, choose those that one
>> 1407 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1408
>> 1409 config CPU_MIPS32_R5
>> 1410 bool "MIPS32 Release 5"
>> 1411 depends on SYS_HAS_CPU_MIPS32_R5
>> 1412 select CPU_HAS_PREFETCH
>> 1413 select CPU_SUPPORTS_32BIT_KERNEL
>> 1414 select CPU_SUPPORTS_HIGHMEM
>> 1415 select CPU_SUPPORTS_MSA
>> 1416 select CPU_SUPPORTS_VZ
>> 1417 select MIPS_O32_FP64_SUPPORT
>> 1418 help
>> 1419 Choose this option to build a kernel for release 5 or later of the
>> 1420 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1421 family, are based on a MIPS32r5 processor. If you own an older
>> 1422 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1423
>> 1424 config CPU_MIPS32_R6
>> 1425 bool "MIPS32 Release 6"
>> 1426 depends on SYS_HAS_CPU_MIPS32_R6
>> 1427 select CPU_HAS_PREFETCH
>> 1428 select CPU_NO_LOAD_STORE_LR
>> 1429 select CPU_SUPPORTS_32BIT_KERNEL
>> 1430 select CPU_SUPPORTS_HIGHMEM
>> 1431 select CPU_SUPPORTS_MSA
>> 1432 select CPU_SUPPORTS_VZ
>> 1433 select MIPS_O32_FP64_SUPPORT
>> 1434 help
>> 1435 Choose this option to build a kernel for release 6 or later of the
>> 1436 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1437 family, are based on a MIPS32r6 processor. If you own an older
>> 1438 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1439
>> 1440 config CPU_MIPS64_R1
>> 1441 bool "MIPS64 Release 1"
>> 1442 depends on SYS_HAS_CPU_MIPS64_R1
>> 1443 select CPU_HAS_PREFETCH
>> 1444 select CPU_SUPPORTS_32BIT_KERNEL
>> 1445 select CPU_SUPPORTS_64BIT_KERNEL
>> 1446 select CPU_SUPPORTS_HIGHMEM
>> 1447 select CPU_SUPPORTS_HUGEPAGES
>> 1448 help
>> 1449 Choose this option to build a kernel for release 1 or later of the
>> 1450 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1451 MIPS processor are based on a MIPS64 processor. If you know the
>> 1452 specific type of processor in your system, choose those that one
>> 1453 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1454 Release 2 of the MIPS64 architecture is available since several
>> 1455 years so chances are you even have a MIPS64 Release 2 processor
>> 1456 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1457 performance.
>> 1458
>> 1459 config CPU_MIPS64_R2
>> 1460 bool "MIPS64 Release 2"
>> 1461 depends on SYS_HAS_CPU_MIPS64_R2
>> 1462 select CPU_HAS_PREFETCH
>> 1463 select CPU_SUPPORTS_32BIT_KERNEL
>> 1464 select CPU_SUPPORTS_64BIT_KERNEL
>> 1465 select CPU_SUPPORTS_HIGHMEM
>> 1466 select CPU_SUPPORTS_HUGEPAGES
>> 1467 select CPU_SUPPORTS_MSA
>> 1468 help
>> 1469 Choose this option to build a kernel for release 2 or later of the
>> 1470 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1471 MIPS processor are based on a MIPS64 processor. If you know the
>> 1472 specific type of processor in your system, choose those that one
>> 1473 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1474
>> 1475 config CPU_MIPS64_R5
>> 1476 bool "MIPS64 Release 5"
>> 1477 depends on SYS_HAS_CPU_MIPS64_R5
>> 1478 select CPU_HAS_PREFETCH
>> 1479 select CPU_SUPPORTS_32BIT_KERNEL
>> 1480 select CPU_SUPPORTS_64BIT_KERNEL
>> 1481 select CPU_SUPPORTS_HIGHMEM
>> 1482 select CPU_SUPPORTS_HUGEPAGES
>> 1483 select CPU_SUPPORTS_MSA
>> 1484 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1485 select CPU_SUPPORTS_VZ
>> 1486 help
>> 1487 Choose this option to build a kernel for release 5 or later of the
>> 1488 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1489 release partly implementing release 6 features. Though there is no
>> 1490 any hardware known to be based on this release.
>> 1491
>> 1492 config CPU_MIPS64_R6
>> 1493 bool "MIPS64 Release 6"
>> 1494 depends on SYS_HAS_CPU_MIPS64_R6
>> 1495 select CPU_HAS_PREFETCH
>> 1496 select CPU_NO_LOAD_STORE_LR
>> 1497 select CPU_SUPPORTS_32BIT_KERNEL
>> 1498 select CPU_SUPPORTS_64BIT_KERNEL
>> 1499 select CPU_SUPPORTS_HIGHMEM
>> 1500 select CPU_SUPPORTS_HUGEPAGES
>> 1501 select CPU_SUPPORTS_MSA
>> 1502 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1503 select CPU_SUPPORTS_VZ
>> 1504 help
>> 1505 Choose this option to build a kernel for release 6 or later of the
>> 1506 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1507 family, are based on a MIPS64r6 processor. If you own an older
>> 1508 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1509
>> 1510 config CPU_P5600
>> 1511 bool "MIPS Warrior P5600"
>> 1512 depends on SYS_HAS_CPU_P5600
>> 1513 select CPU_HAS_PREFETCH
>> 1514 select CPU_SUPPORTS_32BIT_KERNEL
>> 1515 select CPU_SUPPORTS_HIGHMEM
>> 1516 select CPU_SUPPORTS_MSA
>> 1517 select CPU_SUPPORTS_CPUFREQ
>> 1518 select CPU_SUPPORTS_VZ
>> 1519 select CPU_MIPSR2_IRQ_VI
>> 1520 select CPU_MIPSR2_IRQ_EI
>> 1521 select MIPS_O32_FP64_SUPPORT
>> 1522 help
>> 1523 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1524 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1525 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1526 level features like up to six P5600 calculation cores, CM2 with L2
>> 1527 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1528 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1529 eJTAG and PDtrace.
>> 1530
>> 1531 config CPU_R3000
>> 1532 bool "R3000"
>> 1533 depends on SYS_HAS_CPU_R3000
>> 1534 select CPU_HAS_WB
>> 1535 select CPU_R3K_TLB
>> 1536 select CPU_SUPPORTS_32BIT_KERNEL
>> 1537 select CPU_SUPPORTS_HIGHMEM
>> 1538 help
>> 1539 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1540 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1541 *not* work on R4000 machines and vice versa. However, since most
>> 1542 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1543 might be a safe bet. If the resulting kernel does not work,
>> 1544 try to recompile with R3000.
>> 1545
>> 1546 config CPU_R4300
>> 1547 bool "R4300"
>> 1548 depends on SYS_HAS_CPU_R4300
>> 1549 select CPU_SUPPORTS_32BIT_KERNEL
>> 1550 select CPU_SUPPORTS_64BIT_KERNEL
>> 1551 help
>> 1552 MIPS Technologies R4300-series processors.
>> 1553
>> 1554 config CPU_R4X00
>> 1555 bool "R4x00"
>> 1556 depends on SYS_HAS_CPU_R4X00
>> 1557 select CPU_SUPPORTS_32BIT_KERNEL
>> 1558 select CPU_SUPPORTS_64BIT_KERNEL
>> 1559 select CPU_SUPPORTS_HUGEPAGES
>> 1560 help
>> 1561 MIPS Technologies R4000-series processors other than 4300, including
>> 1562 the R4000, R4400, R4600, and 4700.
>> 1563
>> 1564 config CPU_TX49XX
>> 1565 bool "R49XX"
>> 1566 depends on SYS_HAS_CPU_TX49XX
>> 1567 select CPU_HAS_PREFETCH
>> 1568 select CPU_SUPPORTS_32BIT_KERNEL
>> 1569 select CPU_SUPPORTS_64BIT_KERNEL
>> 1570 select CPU_SUPPORTS_HUGEPAGES
>> 1571
>> 1572 config CPU_R5000
>> 1573 bool "R5000"
>> 1574 depends on SYS_HAS_CPU_R5000
>> 1575 select CPU_SUPPORTS_32BIT_KERNEL
>> 1576 select CPU_SUPPORTS_64BIT_KERNEL
>> 1577 select CPU_SUPPORTS_HUGEPAGES
>> 1578 help
>> 1579 MIPS Technologies R5000-series processors other than the Nevada.
>> 1580
>> 1581 config CPU_R5500
>> 1582 bool "R5500"
>> 1583 depends on SYS_HAS_CPU_R5500
>> 1584 select CPU_SUPPORTS_32BIT_KERNEL
>> 1585 select CPU_SUPPORTS_64BIT_KERNEL
>> 1586 select CPU_SUPPORTS_HUGEPAGES
>> 1587 help
>> 1588 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1589 instruction set.
>> 1590
>> 1591 config CPU_NEVADA
>> 1592 bool "RM52xx"
>> 1593 depends on SYS_HAS_CPU_NEVADA
>> 1594 select CPU_SUPPORTS_32BIT_KERNEL
>> 1595 select CPU_SUPPORTS_64BIT_KERNEL
>> 1596 select CPU_SUPPORTS_HUGEPAGES
>> 1597 help
>> 1598 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1599
>> 1600 config CPU_R10000
>> 1601 bool "R10000"
>> 1602 depends on SYS_HAS_CPU_R10000
>> 1603 select CPU_HAS_PREFETCH
>> 1604 select CPU_SUPPORTS_32BIT_KERNEL
>> 1605 select CPU_SUPPORTS_64BIT_KERNEL
>> 1606 select CPU_SUPPORTS_HIGHMEM
>> 1607 select CPU_SUPPORTS_HUGEPAGES
>> 1608 help
>> 1609 MIPS Technologies R10000-series processors.
>> 1610
>> 1611 config CPU_RM7000
>> 1612 bool "RM7000"
>> 1613 depends on SYS_HAS_CPU_RM7000
>> 1614 select CPU_HAS_PREFETCH
>> 1615 select CPU_SUPPORTS_32BIT_KERNEL
>> 1616 select CPU_SUPPORTS_64BIT_KERNEL
>> 1617 select CPU_SUPPORTS_HIGHMEM
>> 1618 select CPU_SUPPORTS_HUGEPAGES
>> 1619
>> 1620 config CPU_SB1
>> 1621 bool "SB1"
>> 1622 depends on SYS_HAS_CPU_SB1
>> 1623 select CPU_SUPPORTS_32BIT_KERNEL
>> 1624 select CPU_SUPPORTS_64BIT_KERNEL
>> 1625 select CPU_SUPPORTS_HIGHMEM
>> 1626 select CPU_SUPPORTS_HUGEPAGES
>> 1627 select WEAK_ORDERING
>> 1628
>> 1629 config CPU_CAVIUM_OCTEON
>> 1630 bool "Cavium Octeon processor"
>> 1631 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1632 select CPU_HAS_PREFETCH
>> 1633 select CPU_SUPPORTS_64BIT_KERNEL
>> 1634 select HAVE_PAGE_SIZE_8KB if !MIPS_VA_BITS_48
>> 1635 select HAVE_PAGE_SIZE_32KB if !MIPS_VA_BITS_48
>> 1636 select WEAK_ORDERING
>> 1637 select CPU_SUPPORTS_HIGHMEM
>> 1638 select CPU_SUPPORTS_HUGEPAGES
>> 1639 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1640 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1641 select MIPS_L1_CACHE_SHIFT_7
>> 1642 select CPU_SUPPORTS_VZ
>> 1643 help
>> 1644 The Cavium Octeon processor is a highly integrated chip containing
>> 1645 many ethernet hardware widgets for networking tasks. The processor
>> 1646 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1647 Full details can be found at http://www.caviumnetworks.com.
>> 1648
>> 1649 config CPU_BMIPS
>> 1650 bool "Broadcom BMIPS"
>> 1651 depends on SYS_HAS_CPU_BMIPS
>> 1652 select CPU_MIPS32
>> 1653 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1654 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1655 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1656 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1657 select CPU_SUPPORTS_32BIT_KERNEL
>> 1658 select DMA_NONCOHERENT
>> 1659 select IRQ_MIPS_CPU
>> 1660 select SWAP_IO_SPACE
>> 1661 select WEAK_ORDERING
>> 1662 select CPU_SUPPORTS_HIGHMEM
>> 1663 select CPU_HAS_PREFETCH
>> 1664 select CPU_SUPPORTS_CPUFREQ
>> 1665 select MIPS_EXTERNAL_TIMER
>> 1666 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
140 help 1667 help
141 Select this variant to use a custom !! 1668 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
142 You will be prompted for a processor !! 1669
143 endchoice 1670 endchoice
144 1671
145 config XTENSA_VARIANT_CUSTOM_NAME !! 1672 config LOONGSON3_ENHANCEMENT
146 string "Xtensa Processor Custom Core V !! 1673 bool "New Loongson-3 CPU Enhancements"
147 depends on XTENSA_VARIANT_CUSTOM <<
148 help <<
149 Provide the name of a custom Xtensa <<
150 This CORENAME selects arch/xtensa/va <<
151 Don't forget you have to select MMU <<
152 <<
153 config XTENSA_VARIANT_NAME <<
154 string <<
155 default "dc232b" <<
156 default "dc233c" <<
157 default "fsf" <<
158 default XTENSA_VARIANT_CUSTOM_NAME <<
159 <<
160 config XTENSA_VARIANT_MMU <<
161 bool "Core variant has a Full MMU (TLB <<
162 depends on XTENSA_VARIANT_CUSTOM <<
163 default y <<
164 select MMU <<
165 help <<
166 Build a Conventional Kernel with ful <<
167 ie: it supports a TLB with auto-load <<
168 <<
169 config XTENSA_VARIANT_HAVE_PERF_EVENTS <<
170 bool "Core variant has Performance Mon <<
171 depends on XTENSA_VARIANT_CUSTOM <<
172 default n 1674 default n
>> 1675 depends on CPU_LOONGSON64
173 help 1676 help
174 Enable if core variant has Performan !! 1677 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
175 External Registers Interface. !! 1678 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1679 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1680 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1681 Fast TLB refill support, etc.
>> 1682
>> 1683 This option enable those enhancements which are not probed at run
>> 1684 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1685 please say 'N' here. If you want a high-performance kernel to run on
>> 1686 new Loongson-3 machines only, please say 'Y' here.
>> 1687
>> 1688 config CPU_LOONGSON3_WORKAROUNDS
>> 1689 bool "Loongson-3 LLSC Workarounds"
>> 1690 default y if SMP
>> 1691 depends on CPU_LOONGSON64
>> 1692 help
>> 1693 Loongson-3 processors have the llsc issues which require workarounds.
>> 1694 Without workarounds the system may hang unexpectedly.
176 1695
177 If unsure, say N. !! 1696 Say Y, unless you know what you are doing.
178 1697
179 config XTENSA_FAKE_NMI !! 1698 config CPU_LOONGSON3_CPUCFG_EMULATION
180 bool "Treat PMM IRQ as NMI" !! 1699 bool "Emulate the CPUCFG instruction on older Loongson cores"
181 depends on XTENSA_VARIANT_HAVE_PERF_EV !! 1700 default y
>> 1701 depends on CPU_LOONGSON64
>> 1702 help
>> 1703 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1704 userland to query CPU capabilities, much like CPUID on x86. This
>> 1705 option provides emulation of the instruction on older Loongson
>> 1706 cores, back to Loongson-3A1000.
>> 1707
>> 1708 If unsure, please say Y.
>> 1709
>> 1710 config CPU_MIPS32_3_5_FEATURES
>> 1711 bool "MIPS32 Release 3.5 Features"
>> 1712 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1713 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1714 CPU_P5600
>> 1715 help
>> 1716 Choose this option to build a kernel for release 2 or later of the
>> 1717 MIPS32 architecture including features from the 3.5 release such as
>> 1718 support for Enhanced Virtual Addressing (EVA).
>> 1719
>> 1720 config CPU_MIPS32_3_5_EVA
>> 1721 bool "Enhanced Virtual Addressing (EVA)"
>> 1722 depends on CPU_MIPS32_3_5_FEATURES
>> 1723 select EVA
>> 1724 default y
>> 1725 help
>> 1726 Choose this option if you want to enable the Enhanced Virtual
>> 1727 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1728 One of its primary benefits is an increase in the maximum size
>> 1729 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1730
>> 1731 config CPU_MIPS32_R5_FEATURES
>> 1732 bool "MIPS32 Release 5 Features"
>> 1733 depends on SYS_HAS_CPU_MIPS32_R5
>> 1734 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1735 help
>> 1736 Choose this option to build a kernel for release 2 or later of the
>> 1737 MIPS32 architecture including features from release 5 such as
>> 1738 support for Extended Physical Addressing (XPA).
>> 1739
>> 1740 config CPU_MIPS32_R5_XPA
>> 1741 bool "Extended Physical Addressing (XPA)"
>> 1742 depends on CPU_MIPS32_R5_FEATURES
>> 1743 depends on !EVA
>> 1744 depends on !PAGE_SIZE_4KB
>> 1745 depends on SYS_SUPPORTS_HIGHMEM
>> 1746 select XPA
>> 1747 select HIGHMEM
>> 1748 select PHYS_ADDR_T_64BIT
182 default n 1749 default n
183 help 1750 help
184 If PMM IRQ is the only IRQ at EXCM l !! 1751 Choose this option if you want to enable the Extended Physical
185 treat it as NMI, which improves accu !! 1752 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1753 benefit is to increase physical addressing equal to or greater
>> 1754 than 40 bits. Note that this has the side effect of turning on
>> 1755 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1756 If unsure, say 'N' here.
186 1757
187 If there are other interrupts at or !! 1758 if CPU_LOONGSON2F
188 but not above the EXCM level, PMM IR !! 1759 config CPU_NOP_WORKAROUNDS
189 but only if these IRQs are not used. !! 1760 bool
190 saying that this is not safe, and a <<
191 actually fire. <<
192 1761
193 If unsure, say N. !! 1762 config CPU_JUMP_WORKAROUNDS
>> 1763 bool
194 1764
195 config PFAULT !! 1765 config CPU_LOONGSON2F_WORKAROUNDS
196 bool "Handle protection faults" if EXP !! 1766 bool "Loongson 2F Workarounds"
197 default y 1767 default y
>> 1768 select CPU_NOP_WORKAROUNDS
>> 1769 select CPU_JUMP_WORKAROUNDS
198 help 1770 help
199 Handle protection faults. MMU config !! 1771 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
200 noMMU configurations may disable it !! 1772 require workarounds. Without workarounds the system may hang
201 generates protection faults or fault !! 1773 unexpectedly. For more information please refer to the gas
>> 1774 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1775
>> 1776 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1777 are needed. The workarounds have no significant side effect on them
>> 1778 but may decrease the performance of the system so this option should
>> 1779 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1780 systems.
202 1781
203 If unsure, say Y. !! 1782 If unsure, please say Y.
>> 1783 endif # CPU_LOONGSON2F
>> 1784
>> 1785 config SYS_SUPPORTS_ZBOOT
>> 1786 bool
>> 1787 select HAVE_KERNEL_GZIP
>> 1788 select HAVE_KERNEL_BZIP2
>> 1789 select HAVE_KERNEL_LZ4
>> 1790 select HAVE_KERNEL_LZMA
>> 1791 select HAVE_KERNEL_LZO
>> 1792 select HAVE_KERNEL_XZ
>> 1793 select HAVE_KERNEL_ZSTD
>> 1794
>> 1795 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1796 bool
>> 1797 select SYS_SUPPORTS_ZBOOT
>> 1798
>> 1799 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1800 bool
>> 1801 select SYS_SUPPORTS_ZBOOT
>> 1802
>> 1803 config CPU_LOONGSON2EF
>> 1804 bool
>> 1805 select CPU_SUPPORTS_32BIT_KERNEL
>> 1806 select CPU_SUPPORTS_64BIT_KERNEL
>> 1807 select CPU_SUPPORTS_HIGHMEM
>> 1808 select CPU_SUPPORTS_HUGEPAGES
>> 1809
>> 1810 config CPU_LOONGSON32
>> 1811 bool
>> 1812 select CPU_MIPS32
>> 1813 select CPU_MIPSR2
>> 1814 select CPU_HAS_PREFETCH
>> 1815 select CPU_SUPPORTS_32BIT_KERNEL
>> 1816 select CPU_SUPPORTS_HIGHMEM
>> 1817 select CPU_SUPPORTS_CPUFREQ
>> 1818
>> 1819 config CPU_BMIPS32_3300
>> 1820 select SMP_UP if SMP
>> 1821 bool
204 1822
205 config XTENSA_UNALIGNED_USER !! 1823 config CPU_BMIPS4350
206 bool "Unaligned memory access in user !! 1824 bool
>> 1825 select SYS_SUPPORTS_SMP
>> 1826 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1827
>> 1828 config CPU_BMIPS4380
>> 1829 bool
>> 1830 select MIPS_L1_CACHE_SHIFT_6
>> 1831 select SYS_SUPPORTS_SMP
>> 1832 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1833 select CPU_HAS_RIXI
>> 1834
>> 1835 config CPU_BMIPS5000
>> 1836 bool
>> 1837 select MIPS_CPU_SCACHE
>> 1838 select MIPS_L1_CACHE_SHIFT_7
>> 1839 select SYS_SUPPORTS_SMP
>> 1840 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1841 select CPU_HAS_RIXI
>> 1842
>> 1843 config SYS_HAS_CPU_LOONGSON64
>> 1844 bool
>> 1845 select CPU_SUPPORTS_CPUFREQ
>> 1846 select CPU_HAS_RIXI
>> 1847
>> 1848 config SYS_HAS_CPU_LOONGSON2E
>> 1849 bool
>> 1850
>> 1851 config SYS_HAS_CPU_LOONGSON2F
>> 1852 bool
>> 1853 select CPU_SUPPORTS_CPUFREQ
>> 1854 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1855
>> 1856 config SYS_HAS_CPU_LOONGSON1B
>> 1857 bool
>> 1858
>> 1859 config SYS_HAS_CPU_LOONGSON1C
>> 1860 bool
>> 1861
>> 1862 config SYS_HAS_CPU_MIPS32_R1
>> 1863 bool
>> 1864
>> 1865 config SYS_HAS_CPU_MIPS32_R2
>> 1866 bool
>> 1867
>> 1868 config SYS_HAS_CPU_MIPS32_R3_5
>> 1869 bool
>> 1870
>> 1871 config SYS_HAS_CPU_MIPS32_R5
>> 1872 bool
>> 1873
>> 1874 config SYS_HAS_CPU_MIPS32_R6
>> 1875 bool
>> 1876
>> 1877 config SYS_HAS_CPU_MIPS64_R1
>> 1878 bool
>> 1879
>> 1880 config SYS_HAS_CPU_MIPS64_R2
>> 1881 bool
>> 1882
>> 1883 config SYS_HAS_CPU_MIPS64_R5
>> 1884 bool
>> 1885
>> 1886 config SYS_HAS_CPU_MIPS64_R6
>> 1887 bool
>> 1888
>> 1889 config SYS_HAS_CPU_P5600
>> 1890 bool
>> 1891
>> 1892 config SYS_HAS_CPU_R3000
>> 1893 bool
>> 1894
>> 1895 config SYS_HAS_CPU_R4300
>> 1896 bool
>> 1897
>> 1898 config SYS_HAS_CPU_R4X00
>> 1899 bool
>> 1900
>> 1901 config SYS_HAS_CPU_TX49XX
>> 1902 bool
>> 1903
>> 1904 config SYS_HAS_CPU_R5000
>> 1905 bool
>> 1906
>> 1907 config SYS_HAS_CPU_R5500
>> 1908 bool
>> 1909
>> 1910 config SYS_HAS_CPU_NEVADA
>> 1911 bool
>> 1912
>> 1913 config SYS_HAS_CPU_R10000
>> 1914 bool
>> 1915
>> 1916 config SYS_HAS_CPU_RM7000
>> 1917 bool
>> 1918
>> 1919 config SYS_HAS_CPU_SB1
>> 1920 bool
>> 1921
>> 1922 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1923 bool
>> 1924
>> 1925 config SYS_HAS_CPU_BMIPS
>> 1926 bool
>> 1927
>> 1928 config SYS_HAS_CPU_BMIPS32_3300
>> 1929 bool
>> 1930 select SYS_HAS_CPU_BMIPS
>> 1931
>> 1932 config SYS_HAS_CPU_BMIPS4350
>> 1933 bool
>> 1934 select SYS_HAS_CPU_BMIPS
>> 1935
>> 1936 config SYS_HAS_CPU_BMIPS4380
>> 1937 bool
>> 1938 select SYS_HAS_CPU_BMIPS
>> 1939
>> 1940 config SYS_HAS_CPU_BMIPS5000
>> 1941 bool
>> 1942 select SYS_HAS_CPU_BMIPS
>> 1943
>> 1944 #
>> 1945 # CPU may reorder R->R, R->W, W->R, W->W
>> 1946 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1947 #
>> 1948 config WEAK_ORDERING
>> 1949 bool
>> 1950
>> 1951 #
>> 1952 # CPU may reorder reads and writes beyond LL/SC
>> 1953 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 1954 #
>> 1955 config WEAK_REORDERING_BEYOND_LLSC
>> 1956 bool
>> 1957 endmenu
>> 1958
>> 1959 #
>> 1960 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1961 #
>> 1962 config CPU_MIPS32
>> 1963 bool
>> 1964 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1965 CPU_MIPS32_R6 || CPU_P5600
>> 1966
>> 1967 config CPU_MIPS64
>> 1968 bool
>> 1969 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1970 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
>> 1971
>> 1972 #
>> 1973 # These indicate the revision of the architecture
>> 1974 #
>> 1975 config CPU_MIPSR1
>> 1976 bool
>> 1977 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 1978
>> 1979 config CPU_MIPSR2
>> 1980 bool
>> 1981 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 1982 select CPU_HAS_RIXI
>> 1983 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1984 select MIPS_SPRAM
>> 1985
>> 1986 config CPU_MIPSR5
>> 1987 bool
>> 1988 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 1989 select CPU_HAS_RIXI
>> 1990 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1991 select MIPS_SPRAM
>> 1992
>> 1993 config CPU_MIPSR6
>> 1994 bool
>> 1995 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 1996 select CPU_HAS_RIXI
>> 1997 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1998 select HAVE_ARCH_BITREVERSE
>> 1999 select MIPS_ASID_BITS_VARIABLE
>> 2000 select MIPS_CRC_SUPPORT
>> 2001 select MIPS_SPRAM
>> 2002
>> 2003 config TARGET_ISA_REV
>> 2004 int
>> 2005 default 1 if CPU_MIPSR1
>> 2006 default 2 if CPU_MIPSR2
>> 2007 default 5 if CPU_MIPSR5
>> 2008 default 6 if CPU_MIPSR6
>> 2009 default 0
207 help 2010 help
208 The Xtensa architecture currently do !! 2011 Reflects the ISA revision being targeted by the kernel build. This
209 memory accesses in hardware but thro !! 2012 is effectively the Kconfig equivalent of MIPS_ISA_REV.
210 Per default, unaligned memory access <<
211 2013
212 Say Y here to enable unaligned memor !! 2014 config EVA
>> 2015 bool
213 2016
214 config XTENSA_LOAD_STORE !! 2017 config XPA
215 bool "Load/store exception handler for !! 2018 bool
>> 2019
>> 2020 config SYS_SUPPORTS_32BIT_KERNEL
>> 2021 bool
>> 2022 config SYS_SUPPORTS_64BIT_KERNEL
>> 2023 bool
>> 2024 config CPU_SUPPORTS_32BIT_KERNEL
>> 2025 bool
>> 2026 config CPU_SUPPORTS_64BIT_KERNEL
>> 2027 bool
>> 2028 config CPU_SUPPORTS_CPUFREQ
>> 2029 bool
>> 2030 config CPU_SUPPORTS_ADDRWINCFG
>> 2031 bool
>> 2032 config CPU_SUPPORTS_HUGEPAGES
>> 2033 bool
>> 2034 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2035 config CPU_SUPPORTS_VZ
>> 2036 bool
>> 2037 config MIPS_PGD_C0_CONTEXT
>> 2038 bool
>> 2039 depends on 64BIT
>> 2040 default y if (CPU_MIPSR2 || CPU_MIPSR6)
>> 2041
>> 2042 #
>> 2043 # Set to y for ptrace access to watch registers.
>> 2044 #
>> 2045 config HARDWARE_WATCHPOINTS
>> 2046 bool
>> 2047 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
>> 2048
>> 2049 menu "Kernel type"
>> 2050
>> 2051 choice
>> 2052 prompt "Kernel code model"
216 help 2053 help
217 The Xtensa architecture only allows !! 2054 You should only select this option if you have a workload that
218 instruction bus with l32r and l32i i !! 2055 actually benefits from 64-bit processing or if your machine has
219 instructions raise an exception with !! 2056 large memory. You will only be presented a single option in this
220 This makes it hard to use some confi !! 2057 menu if your system does not support both 32-bit and 64-bit kernels.
221 literals in FLASH memory attached to <<
222 2058
223 Say Y here to enable exception handl !! 2059 config 32BIT
224 byte and 2-byte access to memory att !! 2060 bool "32-bit kernel"
>> 2061 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2062 select TRAD_SIGNALS
>> 2063 help
>> 2064 Select this option if you want to build a 32-bit kernel.
225 2065
226 config HAVE_SMP !! 2066 config 64BIT
227 bool "System Supports SMP (MX)" !! 2067 bool "64-bit kernel"
228 depends on XTENSA_VARIANT_CUSTOM !! 2068 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
229 select XTENSA_MX <<
230 help 2069 help
231 This option is used to indicate that !! 2070 Select this option if you want to build a 64-bit kernel.
232 supports Multiprocessing. Multiproce <<
233 the CPU core definition and currentl <<
234 2071
235 Multiprocessor support is implemente !! 2072 endchoice
236 interrupt controllers. <<
237 2073
238 The MX interrupt distributer adds In !! 2074 config MIPS_VA_BITS_48
239 and causes the IRQ numbers to be inc !! 2075 bool "48 bits virtual memory"
240 like the open cores ethernet driver !! 2076 depends on 64BIT
>> 2077 help
>> 2078 Support a maximum at least 48 bits of application virtual
>> 2079 memory. Default is 40 bits or less, depending on the CPU.
>> 2080 For page sizes 16k and above, this option results in a small
>> 2081 memory overhead for page tables. For 4k page size, a fourth
>> 2082 level of page tables is added which imposes both a memory
>> 2083 overhead as well as slower TLB fault handling.
241 2084
242 You still have to select "Enable SMP !! 2085 If unsure, say N.
243 2086
244 config SMP !! 2087 config ZBOOT_LOAD_ADDRESS
245 bool "Enable Symmetric multi-processin !! 2088 hex "Compressed kernel load address"
246 depends on HAVE_SMP !! 2089 default 0xffffffff80400000 if BCM47XX
247 select GENERIC_SMP_IDLE_THREAD !! 2090 default 0x0
>> 2091 depends on SYS_SUPPORTS_ZBOOT
248 help 2092 help
249 Enabled SMP Software; allows more th !! 2093 The address to load compressed kernel, aka vmlinuz.
250 to be activated during startup. <<
251 2094
252 config NR_CPUS !! 2095 This is only used if non-zero.
253 depends on SMP <<
254 int "Maximum number of CPUs (2-32)" <<
255 range 2 32 <<
256 default "4" <<
257 2096
258 config HOTPLUG_CPU !! 2097 config ARCH_FORCE_MAX_ORDER
259 bool "Enable CPU hotplug support" !! 2098 int "Maximum zone order"
260 depends on SMP !! 2099 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2100 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2101 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2102 default "10"
261 help 2103 help
262 Say Y here to allow turning CPUs off !! 2104 The kernel memory allocator divides physically contiguous memory
263 controlled through /sys/devices/syst !! 2105 blocks into "zones", where each zone is a power of two number of
>> 2106 pages. This option selects the largest power of two that the kernel
>> 2107 keeps in the memory allocator. If you need to allocate very large
>> 2108 blocks of physically contiguous memory, then you may need to
>> 2109 increase this value.
264 2110
265 Say N if you want to disable CPU hot !! 2111 The page size is not necessarily 4KB. Keep this in mind
>> 2112 when choosing a value for this option.
266 2113
267 config SECONDARY_RESET_VECTOR !! 2114 config BOARD_SCACHE
268 bool "Secondary cores use alternative !! 2115 bool
269 default y !! 2116
270 depends on HAVE_SMP !! 2117 config IP22_CPU_SCACHE
>> 2118 bool
>> 2119 select BOARD_SCACHE
>> 2120
>> 2121 #
>> 2122 # Support for a MIPS32 / MIPS64 style S-caches
>> 2123 #
>> 2124 config MIPS_CPU_SCACHE
>> 2125 bool
>> 2126 select BOARD_SCACHE
>> 2127
>> 2128 config R5000_CPU_SCACHE
>> 2129 bool
>> 2130 select BOARD_SCACHE
>> 2131
>> 2132 config RM7000_CPU_SCACHE
>> 2133 bool
>> 2134 select BOARD_SCACHE
>> 2135
>> 2136 config SIBYTE_DMA_PAGEOPS
>> 2137 bool "Use DMA to clear/copy pages"
>> 2138 depends on CPU_SB1
271 help 2139 help
272 Secondary cores may be configured to !! 2140 Instead of using the CPU to zero and copy pages, use a Data Mover
273 or all cores may use primary reset v !! 2141 channel. These DMA channels are otherwise unused by the standard
274 Say Y here to supply handler for the !! 2142 SiByte Linux port. Seems to give a small performance benefit.
275 2143
276 config FAST_SYSCALL_XTENSA !! 2144 config CPU_HAS_PREFETCH
277 bool "Enable fast atomic syscalls" !! 2145 bool
278 default n !! 2146
>> 2147 config CPU_GENERIC_DUMP_TLB
>> 2148 bool
>> 2149 default y if !CPU_R3000
>> 2150
>> 2151 config MIPS_FP_SUPPORT
>> 2152 bool "Floating Point support" if EXPERT
>> 2153 default y
279 help 2154 help
280 fast_syscall_xtensa is a syscall tha !! 2155 Select y to include support for floating point in the kernel
281 on UP kernel when processor has no s !! 2156 including initialization of FPU hardware, FP context save & restore
>> 2157 and emulation of an FPU where necessary. Without this support any
>> 2158 userland program attempting to use floating point instructions will
>> 2159 receive a SIGILL.
282 2160
283 This syscall is deprecated. It may h !! 2161 If you know that your userland will not attempt to use floating point
284 invalid arguments. It is provided on !! 2162 instructions then you can say n here to shrink the kernel a little.
285 Only enable it if your userspace sof <<
286 2163
287 If unsure, say N. !! 2164 If unsure, say y.
288 2165
289 config FAST_SYSCALL_SPILL_REGISTERS !! 2166 config CPU_R2300_FPU
290 bool "Enable spill registers syscall" !! 2167 bool
>> 2168 depends on MIPS_FP_SUPPORT
>> 2169 default y if CPU_R3000
>> 2170
>> 2171 config CPU_R3K_TLB
>> 2172 bool
>> 2173
>> 2174 config CPU_R4K_FPU
>> 2175 bool
>> 2176 depends on MIPS_FP_SUPPORT
>> 2177 default y if !CPU_R2300_FPU
>> 2178
>> 2179 config CPU_R4K_CACHE_TLB
>> 2180 bool
>> 2181 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2182
>> 2183 config MIPS_MT_SMP
>> 2184 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2185 default y
>> 2186 depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
>> 2187 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
>> 2188 select CPU_MIPSR2_IRQ_VI
>> 2189 select CPU_MIPSR2_IRQ_EI
>> 2190 select SYNC_R4K
>> 2191 select MIPS_MT
>> 2192 select SMP
>> 2193 select SMP_UP
>> 2194 select SYS_SUPPORTS_SMP
>> 2195 select SYS_SUPPORTS_SCHED_SMT
>> 2196 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2197 help
>> 2198 This is a kernel model which is known as SMVP. This is supported
>> 2199 on cores with the MT ASE and uses the available VPEs to implement
>> 2200 virtual processors which supports SMP. This is equivalent to the
>> 2201 Intel Hyperthreading feature. For further information go to
>> 2202 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2203
>> 2204 config MIPS_MT
>> 2205 bool
>> 2206
>> 2207 config SCHED_SMT
>> 2208 bool "SMT (multithreading) scheduler support"
>> 2209 depends on SYS_SUPPORTS_SCHED_SMT
291 default n 2210 default n
292 help 2211 help
293 fast_syscall_spill_registers is a sy !! 2212 SMT scheduler support improves the CPU scheduler's decision making
294 register windows of a calling usersp !! 2213 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2214 increased overhead in some places. If unsure say N here.
295 2215
296 This syscall is deprecated. It may h !! 2216 config SYS_SUPPORTS_SCHED_SMT
297 invalid arguments. It is provided on !! 2217 bool
298 Only enable it if your userspace sof <<
299 2218
300 If unsure, say N. !! 2219 config SYS_SUPPORTS_MULTITHREADING
>> 2220 bool
301 2221
302 choice !! 2222 config MIPS_MT_FPAFF
303 prompt "Kernel ABI" !! 2223 bool "Dynamic FPU affinity for FP-intensive threads"
304 default KERNEL_ABI_DEFAULT !! 2224 default y
>> 2225 depends on MIPS_MT_SMP
>> 2226
>> 2227 config MIPSR2_TO_R6_EMULATOR
>> 2228 bool "MIPS R2-to-R6 emulator"
>> 2229 depends on CPU_MIPSR6
>> 2230 depends on MIPS_FP_SUPPORT
>> 2231 default y
305 help 2232 help
306 Select ABI for the kernel code. This !! 2233 Choose this option if you want to run non-R6 MIPS userland code.
307 supported userspace ABI and any comb !! 2234 Even if you say 'Y' here, the emulator will still be disabled by
308 kernel/userspace ABI is possible and !! 2235 default. You can enable it using the 'mipsr2emu' kernel option.
309 !! 2236 The only reason this is a build-time option is to save ~14K from the
310 In case both kernel and userspace su !! 2237 final kernel image.
311 all register windows support code wi <<
312 build. <<
313 <<
314 If unsure, choose the default ABI. <<
315 <<
316 config KERNEL_ABI_DEFAULT <<
317 bool "Default ABI" <<
318 help <<
319 Select this option to compile kernel <<
320 selected for the toolchain. <<
321 Normally cores with windowed registe <<
322 cores without it use call0 ABI. <<
323 <<
324 config KERNEL_ABI_CALL0 <<
325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI <<
326 help <<
327 Select this option to compile kernel <<
328 toolchain that defaults to windowed <<
329 When this option is not selected the <<
330 be used for the kernel code. <<
331 2238
332 endchoice !! 2239 config SYS_SUPPORTS_VPE_LOADER
>> 2240 bool
>> 2241 depends on SYS_SUPPORTS_MULTITHREADING
>> 2242 help
>> 2243 Indicates that the platform supports the VPE loader, and provides
>> 2244 physical_memsize.
>> 2245
>> 2246 config MIPS_VPE_LOADER
>> 2247 bool "VPE loader support."
>> 2248 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2249 select CPU_MIPSR2_IRQ_VI
>> 2250 select CPU_MIPSR2_IRQ_EI
>> 2251 select MIPS_MT
>> 2252 help
>> 2253 Includes a loader for loading an elf relocatable object
>> 2254 onto another VPE and running it.
333 2255
334 config USER_ABI_CALL0 !! 2256 config MIPS_VPE_LOADER_MT
335 bool 2257 bool
>> 2258 default "y"
>> 2259 depends on MIPS_VPE_LOADER
336 2260
337 choice !! 2261 config MIPS_VPE_LOADER_TOM
338 prompt "Userspace ABI" !! 2262 bool "Load VPE program into memory hidden from linux"
339 default USER_ABI_DEFAULT !! 2263 depends on MIPS_VPE_LOADER
>> 2264 default y
340 help 2265 help
341 Select supported userspace ABI. !! 2266 The loader can use memory that is present but has been hidden from
>> 2267 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2268 you to ensure the amount you put in the option and the space your
>> 2269 program requires is less or equal to the amount physically present.
>> 2270
>> 2271 config MIPS_VPE_APSP_API
>> 2272 bool "Enable support for AP/SP API (RTLX)"
>> 2273 depends on MIPS_VPE_LOADER
>> 2274
>> 2275 config MIPS_VPE_APSP_API_MT
>> 2276 bool
>> 2277 default "y"
>> 2278 depends on MIPS_VPE_APSP_API
>> 2279
>> 2280 config MIPS_CPS
>> 2281 bool "MIPS Coherent Processing System support"
>> 2282 depends on SYS_SUPPORTS_MIPS_CPS
>> 2283 select MIPS_CM
>> 2284 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2285 select SMP
>> 2286 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
>> 2287 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2288 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2289 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2290 select SYS_SUPPORTS_SMP
>> 2291 select WEAK_ORDERING
>> 2292 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2293 help
>> 2294 Select this if you wish to run an SMP kernel across multiple cores
>> 2295 within a MIPS Coherent Processing System. When this option is
>> 2296 enabled the kernel will probe for other cores and boot them with
>> 2297 no external assistance. It is safe to enable this when hardware
>> 2298 support is unavailable.
>> 2299
>> 2300 config MIPS_CPS_PM
>> 2301 depends on MIPS_CPS
>> 2302 bool
342 2303
343 If unsure, choose the default ABI. !! 2304 config MIPS_CM
>> 2305 bool
>> 2306 select MIPS_CPC
>> 2307
>> 2308 config MIPS_CPC
>> 2309 bool
>> 2310
>> 2311 config SB1_PASS_2_WORKAROUNDS
>> 2312 bool
>> 2313 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2314 default y
>> 2315
>> 2316 config SB1_PASS_2_1_WORKAROUNDS
>> 2317 bool
>> 2318 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2319 default y
344 2320
345 config USER_ABI_DEFAULT !! 2321 choice
346 bool "Default ABI only" !! 2322 prompt "SmartMIPS or microMIPS ASE support"
>> 2323
>> 2324 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
>> 2325 bool "None"
347 help 2326 help
348 Assume default userspace ABI. For XE !! 2327 Select this if you want neither microMIPS nor SmartMIPS support
349 call0 ABI binaries may be run on suc <<
350 will not work correctly for them. <<
351 2328
352 config USER_ABI_CALL0_ONLY !! 2329 config CPU_HAS_SMARTMIPS
353 bool "Call0 ABI only" !! 2330 depends on SYS_SUPPORTS_SMARTMIPS
354 select USER_ABI_CALL0 !! 2331 bool "SmartMIPS"
>> 2332 help
>> 2333 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2334 increased security at both hardware and software level for
>> 2335 smartcards. Enabling this option will allow proper use of the
>> 2336 SmartMIPS instructions by Linux applications. However a kernel with
>> 2337 this option will not work on a MIPS core without SmartMIPS core. If
>> 2338 you don't know you probably don't have SmartMIPS and should say N
>> 2339 here.
>> 2340
>> 2341 config CPU_MICROMIPS
>> 2342 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2343 bool "microMIPS"
355 help 2344 help
356 Select this option to support only c !! 2345 When this option is enabled the kernel will be built using the
357 Windowed ABI binaries will crash wit !! 2346 microMIPS ISA
358 an illegal instruction exception on <<
359 2347
360 Choose this option if you're plannin !! 2348 endchoice
361 built with call0 ABI. <<
362 2349
363 config USER_ABI_CALL0_PROBE !! 2350 config CPU_HAS_MSA
364 bool "Support both windowed and call0 !! 2351 bool "Support for the MIPS SIMD Architecture"
365 select USER_ABI_CALL0 !! 2352 depends on CPU_SUPPORTS_MSA
366 help !! 2353 depends on MIPS_FP_SUPPORT
367 Select this option to support both w !! 2354 depends on 64BIT || MIPS_O32_FP64_SUPPORT
368 ABIs. When enabled all processes are !! 2355 help
369 and a fast user exception handler fo !! 2356 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
370 used to turn on PS.WOE bit on the fi !! 2357 and a set of SIMD instructions to operate on them. When this option
371 the userspace. !! 2358 is enabled the kernel will support allocating & switching MSA
>> 2359 vector register contexts. If you know that your kernel will only be
>> 2360 running on CPUs which do not support MSA or that your userland will
>> 2361 not be making use of it then you may wish to say N here to reduce
>> 2362 the size & complexity of your kernel.
372 2363
373 This option should be enabled for th !! 2364 If unsure, say Y.
374 both call0 and windowed ABIs in user <<
375 2365
376 Note that Xtensa ISA does not guaran !! 2366 config CPU_HAS_WB
377 raise an illegal instruction excepti !! 2367 bool
378 PS.WOE is disabled, check whether th <<
379 2368
380 endchoice !! 2369 config XKS01
>> 2370 bool
381 2371
382 endmenu !! 2372 config CPU_HAS_DIEI
>> 2373 depends on !CPU_DIEI_BROKEN
>> 2374 bool
383 2375
384 config XTENSA_CALIBRATE_CCOUNT !! 2376 config CPU_DIEI_BROKEN
385 def_bool n !! 2377 bool
>> 2378
>> 2379 config CPU_HAS_RIXI
>> 2380 bool
>> 2381
>> 2382 config CPU_NO_LOAD_STORE_LR
>> 2383 bool
386 help 2384 help
387 On some platforms (XT2000, for examp !! 2385 CPU lacks support for unaligned load and store instructions:
388 vary. The frequency can be determin !! 2386 LWL, LWR, SWL, SWR (Load/store word left/right).
389 against a well known, fixed frequenc !! 2387 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2388 systems).
>> 2389
>> 2390 #
>> 2391 # Vectored interrupt mode is an R2 feature
>> 2392 #
>> 2393 config CPU_MIPSR2_IRQ_VI
>> 2394 bool
390 2395
391 config SERIAL_CONSOLE !! 2396 #
392 def_bool n !! 2397 # Extended interrupt mode is an R2 feature
>> 2398 #
>> 2399 config CPU_MIPSR2_IRQ_EI
>> 2400 bool
393 2401
394 config PLATFORM_HAVE_XIP !! 2402 config CPU_HAS_SYNC
395 def_bool n !! 2403 bool
>> 2404 depends on !CPU_R3000
>> 2405 default y
396 2406
397 menu "Platform options" !! 2407 #
>> 2408 # CPU non-features
>> 2409 #
>> 2410
>> 2411 # Work around the "daddi" and "daddiu" CPU errata:
>> 2412 #
>> 2413 # - The `daddi' instruction fails to trap on overflow.
>> 2414 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2415 # erratum #23
>> 2416 #
>> 2417 # - The `daddiu' instruction can produce an incorrect result.
>> 2418 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2419 # erratum #41
>> 2420 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2421 # #15
>> 2422 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2423 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2424 config CPU_DADDI_WORKAROUNDS
>> 2425 bool
398 2426
399 choice !! 2427 # Work around certain R4000 CPU errata (as implemented by GCC):
400 prompt "Xtensa System Type" !! 2428 #
401 default XTENSA_PLATFORM_ISS !! 2429 # - A double-word or a variable shift may give an incorrect result
>> 2430 # if executed immediately after starting an integer division:
>> 2431 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2432 # erratum #28
>> 2433 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2434 # #19
>> 2435 #
>> 2436 # - A double-word or a variable shift may give an incorrect result
>> 2437 # if executed while an integer multiplication is in progress:
>> 2438 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2439 # errata #16 & #28
>> 2440 #
>> 2441 # - An integer division may give an incorrect result if started in
>> 2442 # a delay slot of a taken branch or a jump:
>> 2443 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2444 # erratum #52
>> 2445 config CPU_R4000_WORKAROUNDS
>> 2446 bool
>> 2447 select CPU_R4400_WORKAROUNDS
402 2448
403 config XTENSA_PLATFORM_ISS !! 2449 # Work around certain R4400 CPU errata (as implemented by GCC):
404 bool "ISS" !! 2450 #
405 select XTENSA_CALIBRATE_CCOUNT !! 2451 # - A double-word or a variable shift may give an incorrect result
406 select SERIAL_CONSOLE !! 2452 # if executed immediately after starting an integer division:
407 help !! 2453 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
408 ISS is an acronym for Tensilica's In !! 2454 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
409 !! 2455 config CPU_R4400_WORKAROUNDS
410 config XTENSA_PLATFORM_XT2000 !! 2456 bool
411 bool "XT2000" <<
412 help <<
413 XT2000 is the name of Tensilica's fe <<
414 This hardware is capable of running <<
415 <<
416 config XTENSA_PLATFORM_XTFPGA <<
417 bool "XTFPGA" <<
418 select ETHOC if ETHERNET <<
419 select PLATFORM_WANT_DEFAULT_MEM if !M <<
420 select SERIAL_CONSOLE <<
421 select XTENSA_CALIBRATE_CCOUNT <<
422 select PLATFORM_HAVE_XIP <<
423 help <<
424 XTFPGA is the name of Tensilica boar <<
425 This hardware is capable of running <<
426 2457
427 endchoice !! 2458 config CPU_R4X00_BUGS64
>> 2459 bool
>> 2460 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
428 2461
429 config PLATFORM_NR_IRQS !! 2462 config MIPS_ASID_SHIFT
430 int 2463 int
431 default 3 if XTENSA_PLATFORM_XT2000 !! 2464 default 6 if CPU_R3000
432 default 0 2465 default 0
433 2466
434 config XTENSA_CPU_CLOCK !! 2467 config MIPS_ASID_BITS
435 int "CPU clock rate [MHz]" !! 2468 int
436 depends on !XTENSA_CALIBRATE_CCOUNT !! 2469 default 0 if MIPS_ASID_BITS_VARIABLE
437 default 16 !! 2470 default 6 if CPU_R3000
>> 2471 default 8
438 2472
439 config GENERIC_CALIBRATE_DELAY !! 2473 config MIPS_ASID_BITS_VARIABLE
440 bool "Auto calibration of the BogoMIPS !! 2474 bool
441 help <<
442 The BogoMIPS value can easily be der <<
443 2475
444 config CMDLINE_BOOL !! 2476 config MIPS_CRC_SUPPORT
445 bool "Default bootloader kernel argume !! 2477 bool
446 2478
447 config CMDLINE !! 2479 # R4600 erratum. Due to the lack of errata information the exact
448 string "Initial kernel command string" !! 2480 # technical details aren't known. I've experimentally found that disabling
449 depends on CMDLINE_BOOL !! 2481 # interrupts during indexed I-cache flushes seems to be sufficient to deal
450 default "console=ttyS0,38400 root=/dev !! 2482 # with the issue.
451 help !! 2483 config WAR_R4600_V1_INDEX_ICACHEOP
452 On some architectures (EBSA110 and C !! 2484 bool
453 for the boot loader to pass argument <<
454 architectures, you should supply som <<
455 time by entering them here. As a min <<
456 memory size and the root device (e.g <<
457 2485
458 config USE_OF !! 2486 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
459 bool "Flattened Device Tree support" !! 2487 #
460 select OF !! 2488 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
461 select OF_EARLY_FLATTREE !! 2489 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
462 help !! 2490 # executed if there is no other dcache activity. If the dcache is
463 Include support for flattened device !! 2491 # accessed for another instruction immediately preceding when these
>> 2492 # cache instructions are executing, it is possible that the dcache
>> 2493 # tag match outputs used by these cache instructions will be
>> 2494 # incorrect. These cache instructions should be preceded by at least
>> 2495 # four instructions that are not any kind of load or store
>> 2496 # instruction.
>> 2497 #
>> 2498 # This is not allowed: lw
>> 2499 # nop
>> 2500 # nop
>> 2501 # nop
>> 2502 # cache Hit_Writeback_Invalidate_D
>> 2503 #
>> 2504 # This is allowed: lw
>> 2505 # nop
>> 2506 # nop
>> 2507 # nop
>> 2508 # nop
>> 2509 # cache Hit_Writeback_Invalidate_D
>> 2510 config WAR_R4600_V1_HIT_CACHEOP
>> 2511 bool
464 2512
465 config BUILTIN_DTB_SOURCE !! 2513 # Writeback and invalidate the primary cache dcache before DMA.
466 string "DTB to build into the kernel i !! 2514 #
467 depends on OF !! 2515 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2516 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2517 # operate correctly if the internal data cache refill buffer is empty. These
>> 2518 # CACHE instructions should be separated from any potential data cache miss
>> 2519 # by a load instruction to an uncached address to empty the response buffer."
>> 2520 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2521 # in .pdf format.)
>> 2522 config WAR_R4600_V2_HIT_CACHEOP
>> 2523 bool
468 2524
469 config PARSE_BOOTPARAM !! 2525 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
470 bool "Parse bootparam block" !! 2526 # the line which this instruction itself exists, the following
471 default y !! 2527 # operation is not guaranteed."
472 help !! 2528 #
473 Parse parameters passed to the kerne !! 2529 # Workaround: do two phase flushing for Index_Invalidate_I
474 be disabled if the kernel is known t !! 2530 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2531 bool
475 2532
476 If unsure, say Y. !! 2533 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2534 # opposes it being called that) where invalid instructions in the same
>> 2535 # I-cache line worth of instructions being fetched may case spurious
>> 2536 # exceptions.
>> 2537 config WAR_ICACHE_REFILLS
>> 2538 bool
477 2539
478 choice !! 2540 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
479 prompt "Semihosting interface" !! 2541 # may cause ll / sc and lld / scd sequences to execute non-atomically.
480 default XTENSA_SIMCALL_ISS !! 2542 config WAR_R10000_LLSC
481 depends on XTENSA_PLATFORM_ISS !! 2543 bool
482 help <<
483 Choose semihosting interface that wi <<
484 block device and networking. <<
485 2544
486 config XTENSA_SIMCALL_ISS !! 2545 # 34K core erratum: "Problems Executing the TLBR Instruction"
487 bool "simcall" !! 2546 config WAR_MIPS34K_MISSED_ITLB
488 help !! 2547 bool
489 Use simcall instruction. simcall is !! 2548
490 it does nothing on hardware. !! 2549 #
>> 2550 # - Highmem only makes sense for the 32-bit kernel.
>> 2551 # - The current highmem code will only work properly on physically indexed
>> 2552 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2553 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2554 # moment we protect the user and offer the highmem option only on machines
>> 2555 # where it's known to be safe. This will not offer highmem on a few systems
>> 2556 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2557 # indexed CPUs but we're playing safe.
>> 2558 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2559 # know they might have memory configurations that could make use of highmem
>> 2560 # support.
>> 2561 #
>> 2562 config HIGHMEM
>> 2563 bool "High Memory Support"
>> 2564 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2565 select KMAP_LOCAL
>> 2566
>> 2567 config CPU_SUPPORTS_HIGHMEM
>> 2568 bool
>> 2569
>> 2570 config SYS_SUPPORTS_HIGHMEM
>> 2571 bool
491 2572
492 config XTENSA_SIMCALL_GDBIO !! 2573 config SYS_SUPPORTS_SMARTMIPS
493 bool "GDBIO" !! 2574 bool
>> 2575
>> 2576 config SYS_SUPPORTS_MICROMIPS
>> 2577 bool
>> 2578
>> 2579 config SYS_SUPPORTS_MIPS16
>> 2580 bool
494 help 2581 help
495 Use break instruction. It is availab !! 2582 This option must be set if a kernel might be executed on a MIPS16-
496 is attached to it via JTAG. !! 2583 enabled CPU even if MIPS16 is not actually being used. In other
>> 2584 words, it makes the kernel MIPS16-tolerant.
497 2585
498 endchoice !! 2586 config CPU_SUPPORTS_MSA
>> 2587 bool
499 2588
500 config BLK_DEV_SIMDISK !! 2589 config ARCH_FLATMEM_ENABLE
501 tristate "Host file-based simulated bl !! 2590 def_bool y
502 default n !! 2591 depends on !NUMA && !CPU_LOONGSON2EF
503 depends on XTENSA_PLATFORM_ISS && BLOC !! 2592
>> 2593 config ARCH_SPARSEMEM_ENABLE
>> 2594 bool
>> 2595
>> 2596 config NUMA
>> 2597 bool "NUMA Support"
>> 2598 depends on SYS_SUPPORTS_NUMA
>> 2599 select SMP
>> 2600 select HAVE_SETUP_PER_CPU_AREA
>> 2601 select NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2602 help
>> 2603 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2604 Access). This option improves performance on systems with more
>> 2605 than two nodes; on two node systems it is generally better to
>> 2606 leave it disabled; on single node systems leave this option
>> 2607 disabled.
>> 2608
>> 2609 config SYS_SUPPORTS_NUMA
>> 2610 bool
>> 2611
>> 2612 config HAVE_ARCH_NODEDATA_EXTENSION
>> 2613 bool
>> 2614
>> 2615 config RELOCATABLE
>> 2616 bool "Relocatable kernel"
>> 2617 depends on SYS_SUPPORTS_RELOCATABLE
>> 2618 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2619 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2620 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2621 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2622 CPU_LOONGSON64
>> 2623 help
>> 2624 This builds a kernel image that retains relocation information
>> 2625 so it can be loaded someplace besides the default 1MB.
>> 2626 The relocations make the kernel binary about 15% larger,
>> 2627 but are discarded at runtime
>> 2628
>> 2629 config RELOCATION_TABLE_SIZE
>> 2630 hex "Relocation table size"
>> 2631 depends on RELOCATABLE
>> 2632 range 0x0 0x01000000
>> 2633 default "0x00200000" if CPU_LOONGSON64
>> 2634 default "0x00100000"
>> 2635 help
>> 2636 A table of relocation data will be appended to the kernel binary
>> 2637 and parsed at boot to fix up the relocated kernel.
>> 2638
>> 2639 This option allows the amount of space reserved for the table to be
>> 2640 adjusted, although the default of 1Mb should be ok in most cases.
>> 2641
>> 2642 The build will fail and a valid size suggested if this is too small.
>> 2643
>> 2644 If unsure, leave at the default value.
>> 2645
>> 2646 config RANDOMIZE_BASE
>> 2647 bool "Randomize the address of the kernel image"
>> 2648 depends on RELOCATABLE
>> 2649 help
>> 2650 Randomizes the physical and virtual address at which the
>> 2651 kernel image is loaded, as a security feature that
>> 2652 deters exploit attempts relying on knowledge of the location
>> 2653 of kernel internals.
>> 2654
>> 2655 Entropy is generated using any coprocessor 0 registers available.
>> 2656
>> 2657 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2658
>> 2659 If unsure, say N.
>> 2660
>> 2661 config RANDOMIZE_BASE_MAX_OFFSET
>> 2662 hex "Maximum kASLR offset" if EXPERT
>> 2663 depends on RANDOMIZE_BASE
>> 2664 range 0x0 0x40000000 if EVA || 64BIT
>> 2665 range 0x0 0x08000000
>> 2666 default "0x01000000"
>> 2667 help
>> 2668 When kASLR is active, this provides the maximum offset that will
>> 2669 be applied to the kernel image. It should be set according to the
>> 2670 amount of physical RAM available in the target system minus
>> 2671 PHYSICAL_START and must be a power of 2.
>> 2672
>> 2673 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2674 EVA or 64-bit. The default is 16Mb.
>> 2675
>> 2676 config NODES_SHIFT
>> 2677 int
>> 2678 default "6"
>> 2679 depends on NUMA
>> 2680
>> 2681 config HW_PERF_EVENTS
>> 2682 bool "Enable hardware performance counter support for perf events"
>> 2683 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
>> 2684 default y
504 help 2685 help
505 Create block devices that map to fil !! 2686 Enable hardware performance counter support for perf events. If
506 Device binding to host file may be c !! 2687 disabled, perf events will use software events only.
507 interface provided the device is not !! 2688
508 !! 2689 config DMI
509 config BLK_DEV_SIMDISK_COUNT !! 2690 bool "Enable DMI scanning"
510 int "Number of host file-based simulat !! 2691 depends on MACH_LOONGSON64
511 range 1 10 !! 2692 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
512 depends on BLK_DEV_SIMDISK !! 2693 default y
513 default 2 <<
514 help 2694 help
515 This is the default minimal number o !! 2695 Enabled scanning of DMI to identify machine quirks. Say Y
516 Kernel/module parameter 'simdisk_cou !! 2696 here unless you have verified that your setup is not
517 value at runtime. More file names (b !! 2697 affected by entries in the DMI blacklist. Required by PNP
518 specified as parameters, simdisk_cou !! 2698 BIOS code.
519 !! 2699
520 config SIMDISK0_FILENAME !! 2700 config SMP
521 string "Host filename for the first si !! 2701 bool "Multi-Processing support"
522 depends on BLK_DEV_SIMDISK = y !! 2702 depends on SYS_SUPPORTS_SMP
523 default "" <<
524 help <<
525 Attach a first simdisk to a host fil <<
526 contains a root file system. <<
527 <<
528 config SIMDISK1_FILENAME <<
529 string "Host filename for the second s <<
530 depends on BLK_DEV_SIMDISK = y && BLK_ <<
531 default "" <<
532 help <<
533 Another simulated disk in a host fil <<
534 storage. <<
535 <<
536 config XTFPGA_LCD <<
537 bool "Enable XTFPGA LCD driver" <<
538 depends on XTENSA_PLATFORM_XTFPGA <<
539 default n <<
540 help 2703 help
541 There's a 2x16 LCD on most of XTFPGA !! 2704 This enables support for systems with more than one CPU. If you have
542 progress messages there during bootu !! 2705 a system with only one CPU, say N. If you have a system with more
543 during board bringup. !! 2706 than one CPU, say Y.
>> 2707
>> 2708 If you say N here, the kernel will run on uni- and multiprocessor
>> 2709 machines, but will use only one CPU of a multiprocessor machine. If
>> 2710 you say Y here, the kernel will run on many, but not all,
>> 2711 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2712 will run faster if you say N here.
544 2713
545 If unsure, say N. !! 2714 People using multiprocessor machines who say Y here should also say
>> 2715 Y to "Enhanced Real Time Clock Support", below.
546 2716
547 config XTFPGA_LCD_BASE_ADDR !! 2717 See also the SMP-HOWTO available at
548 hex "XTFPGA LCD base address" !! 2718 <https://www.tldp.org/docs.html#howto>.
549 depends on XTFPGA_LCD !! 2719
550 default "0x0d0c0000" !! 2720 If you don't know what to do here, say N.
551 help !! 2721
552 Base address of the LCD controller i !! 2722 config HOTPLUG_CPU
553 Different boards from XTFPGA family !! 2723 bool "Support for hot-pluggable CPUs"
554 addresses. Please consult prototypin !! 2724 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
555 the correct address. Wrong address h <<
556 <<
557 config XTFPGA_LCD_8BIT_ACCESS <<
558 bool "Use 8-bit access to XTFPGA LCD" <<
559 depends on XTFPGA_LCD <<
560 default n <<
561 help 2725 help
562 LCD may be connected with 4- or 8-bi !! 2726 Say Y here to allow turning CPUs off and on. CPUs can be
563 only be used with 8-bit interface. P !! 2727 controlled through /sys/devices/system/cpu.
564 guide for your board for the correct !! 2728 (Note: power management support will enable this option
565 !! 2729 automatically on SMP systems. )
566 comment "Kernel memory layout" !! 2730 Say N if you want to disable CPU hotplug.
567 <<
568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX <<
569 bool "Initialize Xtensa MMU inside the <<
570 depends on !XTENSA_VARIANT_FSF && !XTE <<
571 default y if XTENSA_VARIANT_DC233C || <<
572 help <<
573 Earlier version initialized the MMU <<
574 before jumping to _startup in head.S <<
575 it was possible to place a software <<
576 then enter your normal kernel breakp <<
577 to the kernel mappings (0XC0000000). <<
578 <<
579 This unfortunately won't work for U- <<
580 work for using KEXEC to have a hot k <<
581 KDUMP. <<
582 <<
583 So now the MMU is initialized in hea <<
584 use hardware breakpoints (gdb 'hbrea <<
585 xt-gdb can't place a Software Breakp <<
586 to mapping the MMU and after mapping <<
587 was mapped gdb wouldn't remove the b <<
588 PC wouldn't match. Since Hardware Br <<
589 Linux configurations it seems reason <<
590 and leave this older mechanism for u <<
591 not to follow Tensilica's recommenda <<
592 <<
593 Selecting this will cause U-Boot to <<
594 address at 0x00003000 instead of the <<
595 <<
596 If in doubt, say Y. <<
597 <<
598 config XIP_KERNEL <<
599 bool "Kernel Execute-In-Place from ROM <<
600 depends on PLATFORM_HAVE_XIP <<
601 help <<
602 Execute-In-Place allows the kernel t <<
603 directly addressable by the CPU, suc <<
604 space since the text section of the <<
605 to RAM. Read-write sections, such as <<
606 are still copied to RAM. The XIP ker <<
607 it has to run directly from flash, s <<
608 store it. The flash address used to <<
609 and for storing it, is configuration <<
610 say Y here, you must know the proper <<
611 store the kernel image depending on <<
612 <<
613 Also note that the make target becom <<
614 "make Image" or "make uImage". The f <<
615 ROM memory will be arch/xtensa/boot/ <<
616 2731
617 If unsure, say N. !! 2732 config SMP_UP
>> 2733 bool
>> 2734
>> 2735 config SYS_SUPPORTS_MIPS_CPS
>> 2736 bool
>> 2737
>> 2738 config SYS_SUPPORTS_SMP
>> 2739 bool
>> 2740
>> 2741 config NR_CPUS_DEFAULT_4
>> 2742 bool
>> 2743
>> 2744 config NR_CPUS_DEFAULT_8
>> 2745 bool
>> 2746
>> 2747 config NR_CPUS_DEFAULT_16
>> 2748 bool
>> 2749
>> 2750 config NR_CPUS_DEFAULT_32
>> 2751 bool
>> 2752
>> 2753 config NR_CPUS_DEFAULT_64
>> 2754 bool
>> 2755
>> 2756 config NR_CPUS
>> 2757 int "Maximum number of CPUs (2-256)"
>> 2758 range 2 256
>> 2759 depends on SMP
>> 2760 default "4" if NR_CPUS_DEFAULT_4
>> 2761 default "8" if NR_CPUS_DEFAULT_8
>> 2762 default "16" if NR_CPUS_DEFAULT_16
>> 2763 default "32" if NR_CPUS_DEFAULT_32
>> 2764 default "64" if NR_CPUS_DEFAULT_64
>> 2765 help
>> 2766 This allows you to specify the maximum number of CPUs which this
>> 2767 kernel will support. The maximum supported value is 32 for 32-bit
>> 2768 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2769 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2770 and 2 for all others.
>> 2771
>> 2772 This is purely to save memory - each supported CPU adds
>> 2773 approximately eight kilobytes to the kernel image. For best
>> 2774 performance should round up your number of processors to the next
>> 2775 power of two.
>> 2776
>> 2777 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2778 bool
>> 2779
>> 2780 config MIPS_NR_CPU_NR_MAP_1024
>> 2781 bool
618 2782
619 config MEMMAP_CACHEATTR !! 2783 config MIPS_NR_CPU_NR_MAP
620 hex "Cache attributes for the memory a !! 2784 int
621 depends on !MMU !! 2785 depends on SMP
622 default 0x22222222 !! 2786 default 1024 if MIPS_NR_CPU_NR_MAP_1024
623 help !! 2787 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
624 These cache attributes are set up fo <<
625 specifies cache attributes for the c <<
626 region: bits 0..3 -- for addresses 0 <<
627 bits 4..7 -- for addresses 0x2000000 <<
628 <<
629 Cache attribute values are specific <<
630 For region protection MMUs: <<
631 1: WT cached, <<
632 2: cache bypass, <<
633 4: WB cached, <<
634 f: illegal. <<
635 For full MMU: <<
636 bit 0: executable, <<
637 bit 1: writable, <<
638 bits 2..3: <<
639 0: cache bypass, <<
640 1: WB cache, <<
641 2: WT cache, <<
642 3: special (c and e are illegal, <<
643 For MPU: <<
644 0: illegal, <<
645 1: WB cache, <<
646 2: WB, no-write-allocate cache, <<
647 3: WT cache, <<
648 4: cache bypass. <<
649 <<
650 config KSEG_PADDR <<
651 hex "Physical address of the KSEG mapp <<
652 depends on INITIALIZE_XTENSA_MMU_INSID <<
653 default 0x00000000 <<
654 help <<
655 This is the physical address where K <<
656 the chosen KSEG layout help for the <<
657 Unpacked kernel image (including vec <<
658 within KSEG. <<
659 Physical memory below this address i <<
660 <<
661 If unsure, leave the default value h <<
662 <<
663 config KERNEL_VIRTUAL_ADDRESS <<
664 hex "Kernel virtual address" <<
665 depends on MMU && XIP_KERNEL <<
666 default 0xd0003000 <<
667 help <<
668 This is the virtual address where th <<
669 XIP kernel may be mapped into KSEG o <<
670 provided here must match kernel load <<
671 KERNEL_LOAD_ADDRESS. <<
672 <<
673 config KERNEL_LOAD_ADDRESS <<
674 hex "Kernel load address" <<
675 default 0x60003000 if !MMU <<
676 default 0x00003000 if MMU && INITIALIZ <<
677 default 0xd0003000 if MMU && !INITIALI <<
678 help <<
679 This is the address where the kernel <<
680 It is virtual address for MMUv2 conf <<
681 for all other configurations. <<
682 2788
683 If unsure, leave the default value h !! 2789 #
>> 2790 # Timer Interrupt Frequency Configuration
>> 2791 #
684 2792
685 choice 2793 choice
686 prompt "Relocatable vectors location" !! 2794 prompt "Timer frequency"
687 default XTENSA_VECTORS_IN_TEXT !! 2795 default HZ_250
688 help 2796 help
689 Choose whether relocatable vectors a !! 2797 Allows the configuration of the timer frequency.
690 or placed separately at runtime. Thi !! 2798
691 configurations without VECBASE regis !! 2799 config HZ_24
692 placed at their hardware-defined loc !! 2800 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
693 !! 2801
694 config XTENSA_VECTORS_IN_TEXT !! 2802 config HZ_48
695 bool "Merge relocatable vectors into k !! 2803 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
696 depends on !MTD_XIP !! 2804
697 help !! 2805 config HZ_100
698 This option puts relocatable vectors !! 2806 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
699 with proper alignment. !! 2807
700 This is a safe choice for most confi !! 2808 config HZ_128
701 !! 2809 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
702 config XTENSA_VECTORS_SEPARATE !! 2810
703 bool "Put relocatable vectors at fixed !! 2811 config HZ_250
704 help !! 2812 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
705 This option puts relocatable vectors !! 2813
706 Vectors are merged with the .init da !! 2814 config HZ_256
707 are copied into their designated loc !! 2815 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
708 Use it to put vectors into IRAM or o !! 2816
709 XIP-aware MTD support. !! 2817 config HZ_1000
>> 2818 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2819
>> 2820 config HZ_1024
>> 2821 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
710 2822
711 endchoice 2823 endchoice
712 2824
713 config VECTORS_ADDR !! 2825 config SYS_SUPPORTS_24HZ
714 hex "Kernel vectors virtual address" !! 2826 bool
715 default 0x00000000 <<
716 depends on XTENSA_VECTORS_SEPARATE <<
717 help <<
718 This is the virtual address of the ( <<
719 It must be within KSEG if MMU is use <<
720 <<
721 config XIP_DATA_ADDR <<
722 hex "XIP kernel data virtual address" <<
723 depends on XIP_KERNEL <<
724 default 0x00000000 <<
725 help <<
726 This is the virtual address where XI <<
727 It must be within KSEG if MMU is use <<
728 2827
729 config PLATFORM_WANT_DEFAULT_MEM !! 2828 config SYS_SUPPORTS_48HZ
730 def_bool n !! 2829 bool
731 2830
732 config DEFAULT_MEM_START !! 2831 config SYS_SUPPORTS_100HZ
733 hex !! 2832 bool
734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !M !! 2833
735 default 0x60000000 if PLATFORM_WANT_DE !! 2834 config SYS_SUPPORTS_128HZ
736 default 0x00000000 !! 2835 bool
737 help !! 2836
738 This is the base address used for bo !! 2837 config SYS_SUPPORTS_250HZ
739 in noMMU configurations. !! 2838 bool
>> 2839
>> 2840 config SYS_SUPPORTS_256HZ
>> 2841 bool
>> 2842
>> 2843 config SYS_SUPPORTS_1000HZ
>> 2844 bool
>> 2845
>> 2846 config SYS_SUPPORTS_1024HZ
>> 2847 bool
>> 2848
>> 2849 config SYS_SUPPORTS_ARBIT_HZ
>> 2850 bool
>> 2851 default y if !SYS_SUPPORTS_24HZ && \
>> 2852 !SYS_SUPPORTS_48HZ && \
>> 2853 !SYS_SUPPORTS_100HZ && \
>> 2854 !SYS_SUPPORTS_128HZ && \
>> 2855 !SYS_SUPPORTS_250HZ && \
>> 2856 !SYS_SUPPORTS_256HZ && \
>> 2857 !SYS_SUPPORTS_1000HZ && \
>> 2858 !SYS_SUPPORTS_1024HZ
>> 2859
>> 2860 config HZ
>> 2861 int
>> 2862 default 24 if HZ_24
>> 2863 default 48 if HZ_48
>> 2864 default 100 if HZ_100
>> 2865 default 128 if HZ_128
>> 2866 default 250 if HZ_250
>> 2867 default 256 if HZ_256
>> 2868 default 1000 if HZ_1000
>> 2869 default 1024 if HZ_1024
>> 2870
>> 2871 config SCHED_HRTICK
>> 2872 def_bool HIGH_RES_TIMERS
>> 2873
>> 2874 config ARCH_SUPPORTS_KEXEC
>> 2875 def_bool y
>> 2876
>> 2877 config ARCH_SUPPORTS_CRASH_DUMP
>> 2878 def_bool y
>> 2879
>> 2880 config PHYSICAL_START
>> 2881 hex "Physical address where the kernel is loaded"
>> 2882 default "0xffffffff84000000"
>> 2883 depends on CRASH_DUMP
>> 2884 help
>> 2885 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2886 If you plan to use kernel for capturing the crash dump change
>> 2887 this value to start of the reserved region (the "X" value as
>> 2888 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2889 passed to the panic-ed kernel).
>> 2890
>> 2891 config MIPS_O32_FP64_SUPPORT
>> 2892 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2893 depends on 32BIT || MIPS32_O32
>> 2894 help
>> 2895 When this is enabled, the kernel will support use of 64-bit floating
>> 2896 point registers with binaries using the O32 ABI along with the
>> 2897 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2898 32-bit MIPS systems this support is at the cost of increasing the
>> 2899 size and complexity of the compiled FPU emulator. Thus if you are
>> 2900 running a MIPS32 system and know that none of your userland binaries
>> 2901 will require 64-bit floating point, you may wish to reduce the size
>> 2902 of your kernel & potentially improve FP emulation performance by
>> 2903 saying N here.
>> 2904
>> 2905 Although binutils currently supports use of this flag the details
>> 2906 concerning its effect upon the O32 ABI in userland are still being
>> 2907 worked on. In order to avoid userland becoming dependent upon current
>> 2908 behaviour before the details have been finalised, this option should
>> 2909 be considered experimental and only enabled by those working upon
>> 2910 said details.
>> 2911
>> 2912 If unsure, say N.
>> 2913
>> 2914 config USE_OF
>> 2915 bool
>> 2916 select OF
>> 2917 select OF_EARLY_FLATTREE
>> 2918 select IRQ_DOMAIN
740 2919
741 If unsure, leave the default value h !! 2920 config UHI_BOOT
>> 2921 bool
>> 2922
>> 2923 config BUILTIN_DTB
>> 2924 bool
742 2925
743 choice 2926 choice
744 prompt "KSEG layout" !! 2927 prompt "Kernel appended dtb support" if USE_OF
745 depends on MMU !! 2928 default MIPS_NO_APPENDED_DTB
746 default XTENSA_KSEG_MMU_V2 <<
747 <<
748 config XTENSA_KSEG_MMU_V2 <<
749 bool "MMUv2: 128MB cached + 128MB unca <<
750 help <<
751 MMUv2 compatible kernel memory map: <<
752 at KSEG_PADDR to 0xd0000000 with cac <<
753 without cache. <<
754 KSEG_PADDR must be aligned to 128MB. <<
755 <<
756 config XTENSA_KSEG_256M <<
757 bool "256MB cached + 256MB uncached" <<
758 depends on INITIALIZE_XTENSA_MMU_INSID <<
759 help <<
760 TLB way 6 maps 256MB starting at KSE <<
761 with cache and to 0xc0000000 without <<
762 KSEG_PADDR must be aligned to 256MB. <<
763 <<
764 config XTENSA_KSEG_512M <<
765 bool "512MB cached + 512MB uncached" <<
766 depends on INITIALIZE_XTENSA_MMU_INSID <<
767 help <<
768 TLB way 6 maps 512MB starting at KSE <<
769 with cache and to 0xc0000000 without <<
770 KSEG_PADDR must be aligned to 256MB. <<
771 2929
>> 2930 config MIPS_NO_APPENDED_DTB
>> 2931 bool "None"
>> 2932 help
>> 2933 Do not enable appended dtb support.
>> 2934
>> 2935 config MIPS_ELF_APPENDED_DTB
>> 2936 bool "vmlinux"
>> 2937 help
>> 2938 With this option, the boot code will look for a device tree binary
>> 2939 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2940 it is empty and the DTB can be appended using binutils command
>> 2941 objcopy:
>> 2942
>> 2943 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2944
>> 2945 This is meant as a backward compatibility convenience for those
>> 2946 systems with a bootloader that can't be upgraded to accommodate
>> 2947 the documented boot protocol using a device tree.
>> 2948
>> 2949 config MIPS_RAW_APPENDED_DTB
>> 2950 bool "vmlinux.bin or vmlinuz.bin"
>> 2951 help
>> 2952 With this option, the boot code will look for a device tree binary
>> 2953 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2954 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2955
>> 2956 This is meant as a backward compatibility convenience for those
>> 2957 systems with a bootloader that can't be upgraded to accommodate
>> 2958 the documented boot protocol using a device tree.
>> 2959
>> 2960 Beware that there is very little in terms of protection against
>> 2961 this option being confused by leftover garbage in memory that might
>> 2962 look like a DTB header after a reboot if no actual DTB is appended
>> 2963 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2964 if you don't intend to always append a DTB.
772 endchoice 2965 endchoice
773 2966
774 config HIGHMEM !! 2967 choice
775 bool "High Memory Support" !! 2968 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
776 depends on MMU !! 2969 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
777 select KMAP_LOCAL !! 2970 !MACH_LOONGSON64 && !MIPS_MALTA && \
778 help !! 2971 !CAVIUM_OCTEON_SOC
779 Linux can use the full amount of RAM !! 2972 default MIPS_CMDLINE_FROM_BOOTLOADER
780 default. However, the default MMUv2 !! 2973
781 lowermost 128 MB of memory linearly !! 2974 config MIPS_CMDLINE_FROM_DTB
782 at 0xd0000000 (cached) and 0xd800000 !! 2975 depends on USE_OF
783 When there are more than 128 MB memo !! 2976 bool "Dtb kernel arguments if available"
784 all of it can be "permanently mapped !! 2977
785 The physical memory that's not perma !! 2978 config MIPS_CMDLINE_DTB_EXTEND
786 "high memory". !! 2979 depends on USE_OF
787 !! 2980 bool "Extend dtb kernel arguments with bootloader arguments"
788 If you are compiling a kernel which !! 2981
789 machine with more than 128 MB total !! 2982 config MIPS_CMDLINE_FROM_BOOTLOADER
790 N here. !! 2983 bool "Bootloader kernel arguments if available"
>> 2984
>> 2985 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2986 depends on CMDLINE_BOOL
>> 2987 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2988 endchoice
791 2989
792 If unsure, say Y. !! 2990 endmenu
793 2991
794 config ARCH_FORCE_MAX_ORDER !! 2992 config LOCKDEP_SUPPORT
795 int "Order of maximal physically conti !! 2993 bool
796 default "10" !! 2994 default y
797 help !! 2995
798 The kernel page allocator limits the !! 2996 config STACKTRACE_SUPPORT
799 contiguous allocations. The limit is !! 2997 bool
800 defines the maximal power of two of !! 2998 default y
801 allocated as a single contiguous blo !! 2999
802 overriding the default setting when !! 3000 config PGTABLE_LEVELS
803 large blocks of physically contiguou !! 3001 int
>> 3002 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3003 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3004 default 2
>> 3005
>> 3006 config MIPS_AUTO_PFN_OFFSET
>> 3007 bool
>> 3008
>> 3009 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
804 3010
805 Don't change if unsure. !! 3011 config PCI_DRIVERS_GENERIC
>> 3012 select PCI_DOMAINS_GENERIC if PCI
>> 3013 bool
>> 3014
>> 3015 config PCI_DRIVERS_LEGACY
>> 3016 def_bool !PCI_DRIVERS_GENERIC
>> 3017 select NO_GENERIC_PCI_IOPORT_MAP
>> 3018 select PCI_DOMAINS if PCI
>> 3019
>> 3020 #
>> 3021 # ISA support is now enabled via select. Too many systems still have the one
>> 3022 # or other ISA chip on the board that users don't know about so don't expect
>> 3023 # users to choose the right thing ...
>> 3024 #
>> 3025 config ISA
>> 3026 bool
>> 3027
>> 3028 config TC
>> 3029 bool "TURBOchannel support"
>> 3030 depends on MACH_DECSTATION
>> 3031 help
>> 3032 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3033 processors. TURBOchannel programming specifications are available
>> 3034 at:
>> 3035 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3036 and:
>> 3037 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3038 Linux driver support status is documented at:
>> 3039 <http://www.linux-mips.org/wiki/DECstation>
>> 3040
>> 3041 config MMU
>> 3042 bool
>> 3043 default y
>> 3044
>> 3045 config ARCH_MMAP_RND_BITS_MIN
>> 3046 default 12 if 64BIT
>> 3047 default 8
>> 3048
>> 3049 config ARCH_MMAP_RND_BITS_MAX
>> 3050 default 18 if 64BIT
>> 3051 default 15
806 3052
>> 3053 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3054 default 8
>> 3055
>> 3056 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3057 default 15
>> 3058
>> 3059 config I8253
>> 3060 bool
>> 3061 select CLKSRC_I8253
>> 3062 select CLKEVT_I8253
>> 3063 select MIPS_EXTERNAL_TIMER
807 endmenu 3064 endmenu
808 3065
>> 3066 config TRAD_SIGNALS
>> 3067 bool
>> 3068
>> 3069 config MIPS32_COMPAT
>> 3070 bool
>> 3071
>> 3072 config COMPAT
>> 3073 bool
>> 3074
>> 3075 config MIPS32_O32
>> 3076 bool "Kernel support for o32 binaries"
>> 3077 depends on 64BIT
>> 3078 select ARCH_WANT_OLD_COMPAT_IPC
>> 3079 select COMPAT
>> 3080 select MIPS32_COMPAT
>> 3081 help
>> 3082 Select this option if you want to run o32 binaries. These are pure
>> 3083 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3084 existing binaries are in this format.
>> 3085
>> 3086 If unsure, say Y.
>> 3087
>> 3088 config MIPS32_N32
>> 3089 bool "Kernel support for n32 binaries"
>> 3090 depends on 64BIT
>> 3091 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3092 select COMPAT
>> 3093 select MIPS32_COMPAT
>> 3094 help
>> 3095 Select this option if you want to run n32 binaries. These are
>> 3096 64-bit binaries using 32-bit quantities for addressing and certain
>> 3097 data that would normally be 64-bit. They are used in special
>> 3098 cases.
>> 3099
>> 3100 If unsure, say N.
>> 3101
>> 3102 config CC_HAS_MNO_BRANCH_LIKELY
>> 3103 def_bool y
>> 3104 depends on $(cc-option,-mno-branch-likely)
>> 3105
>> 3106 # https://github.com/llvm/llvm-project/issues/61045
>> 3107 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>> 3108 def_bool y if CC_IS_CLANG
>> 3109
809 menu "Power management options" 3110 menu "Power management options"
810 3111
811 config ARCH_HIBERNATION_POSSIBLE 3112 config ARCH_HIBERNATION_POSSIBLE
812 def_bool y 3113 def_bool y
>> 3114 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3115
>> 3116 config ARCH_SUSPEND_POSSIBLE
>> 3117 def_bool y
>> 3118 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
813 3119
814 source "kernel/power/Kconfig" 3120 source "kernel/power/Kconfig"
815 3121
816 endmenu 3122 endmenu
>> 3123
>> 3124 config MIPS_EXTERNAL_TIMER
>> 3125 bool
>> 3126
>> 3127 menu "CPU Power Management"
>> 3128
>> 3129 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3130 source "drivers/cpufreq/Kconfig"
>> 3131 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3132
>> 3133 source "drivers/cpuidle/Kconfig"
>> 3134
>> 3135 endmenu
>> 3136
>> 3137 source "arch/mips/kvm/Kconfig"
>> 3138
>> 3139 source "arch/mips/vdso/Kconfig"
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