1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 config XTENSA !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ARCH_32BIT_OFF_T !! 4 default y
>> 5 select ARCH_32BIT_OFF_T if !64BIT
>> 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
5 select ARCH_HAS_CPU_CACHE_ALIASING 7 select ARCH_HAS_CPU_CACHE_ALIASING
6 select ARCH_HAS_BINFMT_FLAT if !MMU !! 8 select ARCH_HAS_CPU_FINALIZE_INIT
7 select ARCH_HAS_CURRENT_STACK_POINTER !! 9 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
8 select ARCH_HAS_DEBUG_VM_PGTABLE !! 10 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
9 select ARCH_HAS_DMA_PREP_COHERENT if M !! 11 select ARCH_HAS_FORTIFY_SOURCE
10 select ARCH_HAS_GCOV_PROFILE_ALL <<
11 select ARCH_HAS_KCOV 12 select ARCH_HAS_KCOV
12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MM !! 13 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if !! 14 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
14 select ARCH_HAS_DMA_SET_UNCACHED if MM !! 15 select ARCH_HAS_STRNCPY_FROM_USER
15 select ARCH_HAS_STRNCPY_FROM_USER if ! <<
16 select ARCH_HAS_STRNLEN_USER 16 select ARCH_HAS_STRNLEN_USER
17 select ARCH_NEED_CMPXCHG_1_EMU !! 17 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 18 select ARCH_HAS_UBSAN
>> 19 select ARCH_HAS_GCOV_PROFILE_ALL
>> 20 select ARCH_KEEP_MEMBLOCK
>> 21 select ARCH_USE_BUILTIN_BSWAP
>> 22 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
18 select ARCH_USE_MEMTEST 23 select ARCH_USE_MEMTEST
19 select ARCH_USE_QUEUED_RWLOCKS 24 select ARCH_USE_QUEUED_RWLOCKS
20 select ARCH_USE_QUEUED_SPINLOCKS 25 select ARCH_USE_QUEUED_SPINLOCKS
>> 26 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
>> 27 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
21 select ARCH_WANT_IPC_PARSE_VERSION 28 select ARCH_WANT_IPC_PARSE_VERSION
>> 29 select ARCH_WANT_LD_ORPHAN_WARN
22 select BUILDTIME_TABLE_SORT 30 select BUILDTIME_TABLE_SORT
23 select CLONE_BACKWARDS 31 select CLONE_BACKWARDS
24 select COMMON_CLK !! 32 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
25 select DMA_NONCOHERENT_MMAP if MMU !! 33 select CPU_PM if CPU_IDLE || SUSPEND
26 select GENERIC_ATOMIC64 !! 34 select GENERIC_ATOMIC64 if !64BIT
>> 35 select GENERIC_CMOS_UPDATE
>> 36 select GENERIC_CPU_AUTOPROBE
>> 37 select GENERIC_GETTIMEOFDAY
>> 38 select GENERIC_IOMAP
>> 39 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW 40 select GENERIC_IRQ_SHOW
>> 41 select GENERIC_ISA_DMA if EISA
>> 42 select GENERIC_LIB_ASHLDI3
>> 43 select GENERIC_LIB_ASHRDI3
28 select GENERIC_LIB_CMPDI2 44 select GENERIC_LIB_CMPDI2
29 select GENERIC_LIB_MULDI3 !! 45 select GENERIC_LIB_LSHRDI3
30 select GENERIC_LIB_UCMPDI2 46 select GENERIC_LIB_UCMPDI2
31 select GENERIC_PCI_IOMAP !! 47 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
32 select GENERIC_SCHED_CLOCK !! 48 select GENERIC_SMP_IDLE_THREAD
33 select GENERIC_IOREMAP if MMU !! 49 select GENERIC_IDLE_POLL_SETUP
34 select HAVE_ARCH_AUDITSYSCALL !! 50 select GENERIC_TIME_VSYSCALL
35 select HAVE_ARCH_JUMP_LABEL if !XIP_KE !! 51 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
36 select HAVE_ARCH_KASAN if MMU && !XIP_ !! 52 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
37 select HAVE_ARCH_KCSAN !! 53 select HAVE_ARCH_COMPILER_H
>> 54 select HAVE_ARCH_JUMP_LABEL
>> 55 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
>> 56 select HAVE_ARCH_MMAP_RND_BITS if MMU
>> 57 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
38 select HAVE_ARCH_SECCOMP_FILTER 58 select HAVE_ARCH_SECCOMP_FILTER
39 select HAVE_ARCH_TRACEHOOK 59 select HAVE_ARCH_TRACEHOOK
>> 60 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
40 select HAVE_ASM_MODVERSIONS 61 select HAVE_ASM_MODVERSIONS
41 select HAVE_CONTEXT_TRACKING_USER 62 select HAVE_CONTEXT_TRACKING_USER
>> 63 select HAVE_TIF_NOHZ
>> 64 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK 65 select HAVE_DEBUG_KMEMLEAK
>> 66 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_DMA_CONTIGUOUS 67 select HAVE_DMA_CONTIGUOUS
>> 68 select HAVE_DYNAMIC_FTRACE
>> 69 select HAVE_EBPF_JIT if !CPU_MICROMIPS
44 select HAVE_EXIT_THREAD 70 select HAVE_EXIT_THREAD
>> 71 select HAVE_GUP_FAST
>> 72 select HAVE_FTRACE_MCOUNT_RECORD
>> 73 select HAVE_FUNCTION_GRAPH_TRACER
45 select HAVE_FUNCTION_TRACER 74 select HAVE_FUNCTION_TRACER
46 select HAVE_GCC_PLUGINS if GCC_VERSION !! 75 select HAVE_GCC_PLUGINS
47 select HAVE_HW_BREAKPOINT if PERF_EVEN !! 76 select HAVE_GENERIC_VDSO
>> 77 select HAVE_IOREMAP_PROT
>> 78 select HAVE_IRQ_EXIT_ON_IRQ_STACK
48 select HAVE_IRQ_TIME_ACCOUNTING 79 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_PAGE_SIZE_4KB !! 80 select HAVE_KPROBES
50 select HAVE_PCI !! 81 select HAVE_KRETPROBES
>> 82 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 83 select HAVE_MOD_ARCH_SPECIFIC
>> 84 select HAVE_NMI
>> 85 select HAVE_PAGE_SIZE_4KB if !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 86 select HAVE_PAGE_SIZE_16KB if !CPU_R3000
>> 87 select HAVE_PAGE_SIZE_64KB if !CPU_R3000
51 select HAVE_PERF_EVENTS 88 select HAVE_PERF_EVENTS
>> 89 select HAVE_PERF_REGS
>> 90 select HAVE_PERF_USER_STACK_DUMP
>> 91 select HAVE_REGS_AND_STACK_ACCESS_API
>> 92 select HAVE_RSEQ
>> 93 select HAVE_SPARSE_SYSCALL_NR
52 select HAVE_STACKPROTECTOR 94 select HAVE_STACKPROTECTOR
53 select HAVE_SYSCALL_TRACEPOINTS 95 select HAVE_SYSCALL_TRACEPOINTS
54 select HAVE_VIRT_CPU_ACCOUNTING_GEN !! 96 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
55 select IRQ_DOMAIN !! 97 select IRQ_FORCED_THREADING
>> 98 select ISA if EISA
56 select LOCK_MM_AND_FIND_VMA 99 select LOCK_MM_AND_FIND_VMA
57 select MODULES_USE_ELF_RELA !! 100 select MODULES_USE_ELF_REL if MODULES
>> 101 select MODULES_USE_ELF_RELA if MODULES && 64BIT
58 select PERF_USE_VMALLOC 102 select PERF_USE_VMALLOC
>> 103 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
>> 104 select RTC_LIB
>> 105 select SYSCTL_EXCEPTION_TRACE
59 select TRACE_IRQFLAGS_SUPPORT 106 select TRACE_IRQFLAGS_SUPPORT
>> 107 select ARCH_HAS_ELFCORE_COMPAT
>> 108 select HAVE_ARCH_KCSAN if 64BIT
>> 109
>> 110 config MIPS_FIXUP_BIGPHYS_ADDR
>> 111 bool
>> 112
>> 113 config MIPS_GENERIC
>> 114 bool
>> 115
>> 116 config MACH_GENERIC_CORE
>> 117 bool
>> 118
>> 119 config MACH_INGENIC
>> 120 bool
>> 121 select SYS_SUPPORTS_32BIT_KERNEL
>> 122 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 123 select SYS_SUPPORTS_ZBOOT
>> 124 select DMA_NONCOHERENT
>> 125 select IRQ_MIPS_CPU
>> 126 select PINCTRL
>> 127 select GPIOLIB
>> 128 select COMMON_CLK
>> 129 select GENERIC_IRQ_CHIP
>> 130 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 131 select USE_OF
>> 132 select CPU_SUPPORTS_CPUFREQ
>> 133 select MIPS_EXTERNAL_TIMER
>> 134
>> 135 menu "Machine selection"
>> 136
>> 137 choice
>> 138 prompt "System type"
>> 139 default MIPS_GENERIC_KERNEL
>> 140
>> 141 config MIPS_GENERIC_KERNEL
>> 142 bool "Generic board-agnostic MIPS kernel"
>> 143 select MIPS_GENERIC
>> 144 select BOOT_RAW
>> 145 select BUILTIN_DTB
>> 146 select CEVT_R4K
>> 147 select CLKSRC_MIPS_GIC
>> 148 select COMMON_CLK
>> 149 select CPU_MIPSR2_IRQ_EI
>> 150 select CPU_MIPSR2_IRQ_VI
>> 151 select CSRC_R4K
>> 152 select DMA_NONCOHERENT
>> 153 select HAVE_PCI
>> 154 select IRQ_MIPS_CPU
>> 155 select MACH_GENERIC_CORE
>> 156 select MIPS_AUTO_PFN_OFFSET
>> 157 select MIPS_CPU_SCACHE
>> 158 select MIPS_GIC
>> 159 select MIPS_L1_CACHE_SHIFT_7
>> 160 select NO_EXCEPT_FILL
>> 161 select PCI_DRIVERS_GENERIC
>> 162 select SMP_UP if SMP
>> 163 select SWAP_IO_SPACE
>> 164 select SYS_HAS_CPU_MIPS32_R1
>> 165 select SYS_HAS_CPU_MIPS32_R2
>> 166 select SYS_HAS_CPU_MIPS32_R5
>> 167 select SYS_HAS_CPU_MIPS32_R6
>> 168 select SYS_HAS_CPU_MIPS64_R1
>> 169 select SYS_HAS_CPU_MIPS64_R2
>> 170 select SYS_HAS_CPU_MIPS64_R5
>> 171 select SYS_HAS_CPU_MIPS64_R6
>> 172 select SYS_SUPPORTS_32BIT_KERNEL
>> 173 select SYS_SUPPORTS_64BIT_KERNEL
>> 174 select SYS_SUPPORTS_BIG_ENDIAN
>> 175 select SYS_SUPPORTS_HIGHMEM
>> 176 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 177 select SYS_SUPPORTS_MICROMIPS
>> 178 select SYS_SUPPORTS_MIPS16
>> 179 select SYS_SUPPORTS_MIPS_CPS
>> 180 select SYS_SUPPORTS_MULTITHREADING
>> 181 select SYS_SUPPORTS_RELOCATABLE
>> 182 select SYS_SUPPORTS_SMARTMIPS
>> 183 select SYS_SUPPORTS_ZBOOT
>> 184 select UHI_BOOT
>> 185 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 186 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 187 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 188 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 189 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 190 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 191 select USE_OF
>> 192 help
>> 193 Select this to build a kernel which aims to support multiple boards,
>> 194 generally using a flattened device tree passed from the bootloader
>> 195 using the boot protocol defined in the UHI (Unified Hosting
>> 196 Interface) specification.
>> 197
>> 198 config MIPS_ALCHEMY
>> 199 bool "Alchemy processor based machines"
>> 200 select PHYS_ADDR_T_64BIT
>> 201 select CEVT_R4K
>> 202 select CSRC_R4K
>> 203 select IRQ_MIPS_CPU
>> 204 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 205 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 206 select SYS_HAS_CPU_MIPS32_R1
>> 207 select SYS_SUPPORTS_32BIT_KERNEL
>> 208 select SYS_SUPPORTS_APM_EMULATION
>> 209 select GPIOLIB
>> 210 select SYS_SUPPORTS_ZBOOT
>> 211 select COMMON_CLK
>> 212
>> 213 config ATH25
>> 214 bool "Atheros AR231x/AR531x SoC support"
>> 215 select CEVT_R4K
>> 216 select CSRC_R4K
>> 217 select DMA_NONCOHERENT
>> 218 select IRQ_MIPS_CPU
>> 219 select IRQ_DOMAIN
>> 220 select SYS_HAS_CPU_MIPS32_R1
>> 221 select SYS_SUPPORTS_BIG_ENDIAN
>> 222 select SYS_SUPPORTS_32BIT_KERNEL
>> 223 select SYS_HAS_EARLY_PRINTK
>> 224 help
>> 225 Support for Atheros AR231x and Atheros AR531x based boards
>> 226
>> 227 config ATH79
>> 228 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 229 select ARCH_HAS_RESET_CONTROLLER
>> 230 select BOOT_RAW
>> 231 select CEVT_R4K
>> 232 select CSRC_R4K
>> 233 select DMA_NONCOHERENT
>> 234 select GPIOLIB
>> 235 select PINCTRL
>> 236 select COMMON_CLK
>> 237 select IRQ_MIPS_CPU
>> 238 select SYS_HAS_CPU_MIPS32_R2
>> 239 select SYS_HAS_EARLY_PRINTK
>> 240 select SYS_SUPPORTS_32BIT_KERNEL
>> 241 select SYS_SUPPORTS_BIG_ENDIAN
>> 242 select SYS_SUPPORTS_MIPS16
>> 243 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 244 select USE_OF
>> 245 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 246 help
>> 247 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 248
>> 249 config BMIPS_GENERIC
>> 250 bool "Broadcom Generic BMIPS kernel"
>> 251 select ARCH_HAS_RESET_CONTROLLER
>> 252 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 253 select BOOT_RAW
>> 254 select NO_EXCEPT_FILL
>> 255 select USE_OF
>> 256 select CEVT_R4K
>> 257 select CSRC_R4K
>> 258 select SYNC_R4K
>> 259 select COMMON_CLK
>> 260 select BCM6345_L1_IRQ
>> 261 select BCM7038_L1_IRQ
>> 262 select BCM7120_L2_IRQ
>> 263 select BRCMSTB_L2_IRQ
>> 264 select IRQ_MIPS_CPU
>> 265 select DMA_NONCOHERENT
>> 266 select SYS_SUPPORTS_32BIT_KERNEL
>> 267 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 268 select SYS_SUPPORTS_BIG_ENDIAN
>> 269 select SYS_SUPPORTS_HIGHMEM
>> 270 select SYS_HAS_CPU_BMIPS32_3300
>> 271 select SYS_HAS_CPU_BMIPS4350
>> 272 select SYS_HAS_CPU_BMIPS4380
>> 273 select SYS_HAS_CPU_BMIPS5000
>> 274 select SWAP_IO_SPACE
>> 275 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 276 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 277 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 278 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 279 select HARDIRQS_SW_RESEND
>> 280 select HAVE_PCI
>> 281 select PCI_DRIVERS_GENERIC
>> 282 select FW_CFE
60 help 283 help
61 Xtensa processors are 32-bit RISC ma !! 284 Build a generic DT-based kernel image that boots on select
62 primarily for embedded systems. The !! 285 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
63 configurable and extensible. The Li !! 286 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
64 architecture supports all processor !! 287 must be set appropriately for your board.
65 with reasonable minimum requirements !! 288
66 a home page at <http://www.linux-xte !! 289 config BCM47XX
>> 290 bool "Broadcom BCM47XX based boards"
>> 291 select BOOT_RAW
>> 292 select CEVT_R4K
>> 293 select CSRC_R4K
>> 294 select DMA_NONCOHERENT
>> 295 select HAVE_PCI
>> 296 select IRQ_MIPS_CPU
>> 297 select SYS_HAS_CPU_MIPS32_R1
>> 298 select NO_EXCEPT_FILL
>> 299 select SYS_SUPPORTS_32BIT_KERNEL
>> 300 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 301 select SYS_SUPPORTS_MIPS16
>> 302 select SYS_SUPPORTS_ZBOOT
>> 303 select SYS_HAS_EARLY_PRINTK
>> 304 select USE_GENERIC_EARLY_PRINTK_8250
>> 305 select GPIOLIB
>> 306 select LEDS_GPIO_REGISTER
>> 307 select BCM47XX_NVRAM
>> 308 select BCM47XX_SPROM
>> 309 select BCM47XX_SSB if !BCM47XX_BCMA
>> 310 help
>> 311 Support for BCM47XX based boards
>> 312
>> 313 config BCM63XX
>> 314 bool "Broadcom BCM63XX based boards"
>> 315 select BOOT_RAW
>> 316 select CEVT_R4K
>> 317 select CSRC_R4K
>> 318 select SYNC_R4K
>> 319 select DMA_NONCOHERENT
>> 320 select IRQ_MIPS_CPU
>> 321 select SYS_SUPPORTS_32BIT_KERNEL
>> 322 select SYS_SUPPORTS_BIG_ENDIAN
>> 323 select SYS_HAS_EARLY_PRINTK
>> 324 select SYS_HAS_CPU_BMIPS32_3300
>> 325 select SYS_HAS_CPU_BMIPS4350
>> 326 select SYS_HAS_CPU_BMIPS4380
>> 327 select SWAP_IO_SPACE
>> 328 select GPIOLIB
>> 329 select MIPS_L1_CACHE_SHIFT_4
>> 330 select HAVE_LEGACY_CLK
>> 331 help
>> 332 Support for BCM63XX based boards
>> 333
>> 334 config MIPS_COBALT
>> 335 bool "Cobalt Server"
>> 336 select CEVT_R4K
>> 337 select CSRC_R4K
>> 338 select CEVT_GT641XX
>> 339 select DMA_NONCOHERENT
>> 340 select FORCE_PCI
>> 341 select I8253
>> 342 select I8259
>> 343 select IRQ_MIPS_CPU
>> 344 select IRQ_GT641XX
>> 345 select PCI_GT64XXX_PCI0
>> 346 select SYS_HAS_CPU_NEVADA
>> 347 select SYS_HAS_EARLY_PRINTK
>> 348 select SYS_SUPPORTS_32BIT_KERNEL
>> 349 select SYS_SUPPORTS_64BIT_KERNEL
>> 350 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 351 select USE_GENERIC_EARLY_PRINTK_8250
>> 352
>> 353 config MACH_DECSTATION
>> 354 bool "DECstations"
>> 355 select BOOT_ELF32
>> 356 select CEVT_DS1287
>> 357 select CEVT_R4K if CPU_R4X00
>> 358 select CSRC_IOASIC
>> 359 select CSRC_R4K if CPU_R4X00
>> 360 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 361 select CPU_R4000_WORKAROUNDS if 64BIT
>> 362 select CPU_R4400_WORKAROUNDS if 64BIT
>> 363 select DMA_NONCOHERENT
>> 364 select NO_IOPORT_MAP
>> 365 select IRQ_MIPS_CPU
>> 366 select SYS_HAS_CPU_R3000
>> 367 select SYS_HAS_CPU_R4X00
>> 368 select SYS_SUPPORTS_32BIT_KERNEL
>> 369 select SYS_SUPPORTS_64BIT_KERNEL
>> 370 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 371 select SYS_SUPPORTS_128HZ
>> 372 select SYS_SUPPORTS_256HZ
>> 373 select SYS_SUPPORTS_1024HZ
>> 374 select MIPS_L1_CACHE_SHIFT_4
>> 375 help
>> 376 This enables support for DEC's MIPS based workstations. For details
>> 377 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 378 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 379
>> 380 If you have one of the following DECstation Models you definitely
>> 381 want to choose R4xx0 for the CPU Type:
>> 382
>> 383 DECstation 5000/50
>> 384 DECstation 5000/150
>> 385 DECstation 5000/260
>> 386 DECsystem 5900/260
>> 387
>> 388 otherwise choose R3000.
>> 389
>> 390 config MACH_JAZZ
>> 391 bool "Jazz family of machines"
>> 392 select ARC_MEMORY
>> 393 select ARC_PROMLIB
>> 394 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 395 select ARCH_MIGHT_HAVE_PC_SERIO
>> 396 select DMA_OPS
>> 397 select FW_ARC
>> 398 select FW_ARC32
>> 399 select ARCH_MAY_HAVE_PC_FDC
>> 400 select CEVT_R4K
>> 401 select CSRC_R4K
>> 402 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 403 select GENERIC_ISA_DMA
>> 404 select HAVE_PCSPKR_PLATFORM
>> 405 select IRQ_MIPS_CPU
>> 406 select I8253
>> 407 select I8259
>> 408 select ISA
>> 409 select SYS_HAS_CPU_R4X00
>> 410 select SYS_SUPPORTS_32BIT_KERNEL
>> 411 select SYS_SUPPORTS_64BIT_KERNEL
>> 412 select SYS_SUPPORTS_100HZ
>> 413 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 414 help
>> 415 This a family of machines based on the MIPS R4030 chipset which was
>> 416 used by several vendors to build RISC/os and Windows NT workstations.
>> 417 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 418 Olivetti M700-10 workstations.
>> 419
>> 420 config MACH_INGENIC_SOC
>> 421 bool "Ingenic SoC based machines"
>> 422 select MIPS_GENERIC
>> 423 select MACH_INGENIC
>> 424 select MACH_GENERIC_CORE
>> 425 select SYS_SUPPORTS_ZBOOT_UART16550
>> 426 select CPU_SUPPORTS_CPUFREQ
>> 427 select MIPS_EXTERNAL_TIMER
>> 428
>> 429 config LANTIQ
>> 430 bool "Lantiq based platforms"
>> 431 select DMA_NONCOHERENT
>> 432 select IRQ_MIPS_CPU
>> 433 select CEVT_R4K
>> 434 select CSRC_R4K
>> 435 select NO_EXCEPT_FILL
>> 436 select SYS_HAS_CPU_MIPS32_R1
>> 437 select SYS_HAS_CPU_MIPS32_R2
>> 438 select SYS_SUPPORTS_BIG_ENDIAN
>> 439 select SYS_SUPPORTS_32BIT_KERNEL
>> 440 select SYS_SUPPORTS_MIPS16
>> 441 select SYS_SUPPORTS_MULTITHREADING
>> 442 select SYS_SUPPORTS_VPE_LOADER
>> 443 select SYS_HAS_EARLY_PRINTK
>> 444 select GPIOLIB
>> 445 select SWAP_IO_SPACE
>> 446 select BOOT_RAW
>> 447 select HAVE_LEGACY_CLK
>> 448 select USE_OF
>> 449 select PINCTRL
>> 450 select PINCTRL_LANTIQ
>> 451 select ARCH_HAS_RESET_CONTROLLER
>> 452 select RESET_CONTROLLER
>> 453
>> 454 config MACH_LOONGSON32
>> 455 bool "Loongson 32-bit family of machines"
>> 456 select SYS_SUPPORTS_ZBOOT
>> 457 help
>> 458 This enables support for the Loongson-1 family of machines.
>> 459
>> 460 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 461 the Institute of Computing Technology (ICT), Chinese Academy of
>> 462 Sciences (CAS).
>> 463
>> 464 config MACH_LOONGSON2EF
>> 465 bool "Loongson-2E/F family of machines"
>> 466 select SYS_SUPPORTS_ZBOOT
>> 467 help
>> 468 This enables the support of early Loongson-2E/F family of machines.
>> 469
>> 470 config MACH_LOONGSON64
>> 471 bool "Loongson 64-bit family of machines"
>> 472 select ARCH_DMA_DEFAULT_COHERENT
>> 473 select ARCH_SPARSEMEM_ENABLE
>> 474 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 475 select ARCH_MIGHT_HAVE_PC_SERIO
>> 476 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 477 select BOOT_ELF32
>> 478 select BOARD_SCACHE
>> 479 select CSRC_R4K
>> 480 select CEVT_R4K
>> 481 select SYNC_R4K
>> 482 select FORCE_PCI
>> 483 select ISA
>> 484 select I8259
>> 485 select IRQ_MIPS_CPU
>> 486 select NO_EXCEPT_FILL
>> 487 select NR_CPUS_DEFAULT_64
>> 488 select USE_GENERIC_EARLY_PRINTK_8250
>> 489 select PCI_DRIVERS_GENERIC
>> 490 select SYS_HAS_CPU_LOONGSON64
>> 491 select SYS_HAS_EARLY_PRINTK
>> 492 select SYS_SUPPORTS_SMP
>> 493 select SYS_SUPPORTS_HOTPLUG_CPU
>> 494 select SYS_SUPPORTS_NUMA
>> 495 select SYS_SUPPORTS_64BIT_KERNEL
>> 496 select SYS_SUPPORTS_HIGHMEM
>> 497 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 498 select SYS_SUPPORTS_ZBOOT
>> 499 select SYS_SUPPORTS_RELOCATABLE
>> 500 select ZONE_DMA32
>> 501 select COMMON_CLK
>> 502 select USE_OF
>> 503 select BUILTIN_DTB
>> 504 select PCI_HOST_GENERIC
>> 505 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 506 help
>> 507 This enables the support of Loongson-2/3 family of machines.
>> 508
>> 509 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 510 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 511 and Loongson-2F which will be removed), developed by the Institute
>> 512 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 513
>> 514 config MIPS_MALTA
>> 515 bool "MIPS Malta board"
>> 516 select ARCH_MAY_HAVE_PC_FDC
>> 517 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 518 select ARCH_MIGHT_HAVE_PC_SERIO
>> 519 select BOOT_ELF32
>> 520 select BOOT_RAW
>> 521 select BUILTIN_DTB
>> 522 select CEVT_R4K
>> 523 select CLKSRC_MIPS_GIC
>> 524 select COMMON_CLK
>> 525 select CSRC_R4K
>> 526 select DMA_NONCOHERENT
>> 527 select GENERIC_ISA_DMA
>> 528 select HAVE_PCSPKR_PLATFORM
>> 529 select HAVE_PCI
>> 530 select I8253
>> 531 select I8259
>> 532 select IRQ_MIPS_CPU
>> 533 select MIPS_BONITO64
>> 534 select MIPS_CPU_SCACHE
>> 535 select MIPS_GIC
>> 536 select MIPS_L1_CACHE_SHIFT_6
>> 537 select MIPS_MSC
>> 538 select PCI_GT64XXX_PCI0
>> 539 select SMP_UP if SMP
>> 540 select SWAP_IO_SPACE
>> 541 select SYS_HAS_CPU_MIPS32_R1
>> 542 select SYS_HAS_CPU_MIPS32_R2
>> 543 select SYS_HAS_CPU_MIPS32_R3_5
>> 544 select SYS_HAS_CPU_MIPS32_R5
>> 545 select SYS_HAS_CPU_MIPS32_R6
>> 546 select SYS_HAS_CPU_MIPS64_R1
>> 547 select SYS_HAS_CPU_MIPS64_R2
>> 548 select SYS_HAS_CPU_MIPS64_R6
>> 549 select SYS_HAS_CPU_NEVADA
>> 550 select SYS_HAS_CPU_RM7000
>> 551 select SYS_SUPPORTS_32BIT_KERNEL
>> 552 select SYS_SUPPORTS_64BIT_KERNEL
>> 553 select SYS_SUPPORTS_BIG_ENDIAN
>> 554 select SYS_SUPPORTS_HIGHMEM
>> 555 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 556 select SYS_SUPPORTS_MICROMIPS
>> 557 select SYS_SUPPORTS_MIPS16
>> 558 select SYS_SUPPORTS_MIPS_CPS
>> 559 select SYS_SUPPORTS_MULTITHREADING
>> 560 select SYS_SUPPORTS_RELOCATABLE
>> 561 select SYS_SUPPORTS_SMARTMIPS
>> 562 select SYS_SUPPORTS_VPE_LOADER
>> 563 select SYS_SUPPORTS_ZBOOT
>> 564 select USE_OF
>> 565 select WAR_ICACHE_REFILLS
>> 566 select ZONE_DMA32 if 64BIT
>> 567 help
>> 568 This enables support for the MIPS Technologies Malta evaluation
>> 569 board.
>> 570
>> 571 config MACH_PIC32
>> 572 bool "Microchip PIC32 Family"
>> 573 help
>> 574 This enables support for the Microchip PIC32 family of platforms.
>> 575
>> 576 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 577 microcontrollers.
>> 578
>> 579 config EYEQ
>> 580 bool "Mobileye EyeQ SoC"
>> 581 select MACH_GENERIC_CORE
>> 582 select ARM_AMBA
>> 583 select PHYSICAL_START_BOOL
>> 584 select ARCH_SPARSEMEM_DEFAULT if 64BIT
>> 585 select BOOT_RAW
>> 586 select BUILTIN_DTB
>> 587 select CEVT_R4K
>> 588 select CLKSRC_MIPS_GIC
>> 589 select COMMON_CLK
>> 590 select CPU_MIPSR2_IRQ_EI
>> 591 select CPU_MIPSR2_IRQ_VI
>> 592 select CSRC_R4K
>> 593 select DMA_NONCOHERENT
>> 594 select HAVE_PCI
>> 595 select IRQ_MIPS_CPU
>> 596 select MIPS_AUTO_PFN_OFFSET
>> 597 select MIPS_CPU_SCACHE
>> 598 select MIPS_GIC
>> 599 select MIPS_L1_CACHE_SHIFT_7
>> 600 select PCI_DRIVERS_GENERIC
>> 601 select SMP_UP if SMP
>> 602 select SWAP_IO_SPACE
>> 603 select SYS_HAS_CPU_MIPS64_R6
>> 604 select SYS_SUPPORTS_64BIT_KERNEL
>> 605 select SYS_SUPPORTS_HIGHMEM
>> 606 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 607 select SYS_SUPPORTS_MIPS_CPS
>> 608 select SYS_SUPPORTS_RELOCATABLE
>> 609 select SYS_SUPPORTS_ZBOOT
>> 610 select UHI_BOOT
>> 611 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 612 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 613 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 614 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 615 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 616 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 617 select USE_OF
>> 618 help
>> 619 Select this to build a kernel supporting EyeQ SoC from Mobileye.
>> 620
>> 621 bool
>> 622
>> 623 config MACH_NINTENDO64
>> 624 bool "Nintendo 64 console"
>> 625 select CEVT_R4K
>> 626 select CSRC_R4K
>> 627 select SYS_HAS_CPU_R4300
>> 628 select SYS_SUPPORTS_BIG_ENDIAN
>> 629 select SYS_SUPPORTS_ZBOOT
>> 630 select SYS_SUPPORTS_32BIT_KERNEL
>> 631 select SYS_SUPPORTS_64BIT_KERNEL
>> 632 select DMA_NONCOHERENT
>> 633 select IRQ_MIPS_CPU
>> 634
>> 635 config RALINK
>> 636 bool "Ralink based machines"
>> 637 select CEVT_R4K
>> 638 select COMMON_CLK
>> 639 select CSRC_R4K
>> 640 select BOOT_RAW
>> 641 select DMA_NONCOHERENT
>> 642 select IRQ_MIPS_CPU
>> 643 select USE_OF
>> 644 select SYS_HAS_CPU_MIPS32_R2
>> 645 select SYS_SUPPORTS_32BIT_KERNEL
>> 646 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 647 select SYS_SUPPORTS_MIPS16
>> 648 select SYS_SUPPORTS_ZBOOT
>> 649 select SYS_HAS_EARLY_PRINTK
>> 650 select ARCH_HAS_RESET_CONTROLLER
>> 651 select RESET_CONTROLLER
>> 652
>> 653 config MACH_REALTEK_RTL
>> 654 bool "Realtek RTL838x/RTL839x based machines"
>> 655 select MIPS_GENERIC
>> 656 select MACH_GENERIC_CORE
>> 657 select DMA_NONCOHERENT
>> 658 select IRQ_MIPS_CPU
>> 659 select CSRC_R4K
>> 660 select CEVT_R4K
>> 661 select SYS_HAS_CPU_MIPS32_R1
>> 662 select SYS_HAS_CPU_MIPS32_R2
>> 663 select SYS_SUPPORTS_BIG_ENDIAN
>> 664 select SYS_SUPPORTS_32BIT_KERNEL
>> 665 select SYS_SUPPORTS_MIPS16
>> 666 select SYS_SUPPORTS_MULTITHREADING
>> 667 select SYS_SUPPORTS_VPE_LOADER
>> 668 select BOOT_RAW
>> 669 select PINCTRL
>> 670 select USE_OF
>> 671 select REALTEK_OTTO_TIMER
>> 672
>> 673 config SGI_IP22
>> 674 bool "SGI IP22 (Indy/Indigo2)"
>> 675 select ARC_MEMORY
>> 676 select ARC_PROMLIB
>> 677 select FW_ARC
>> 678 select FW_ARC32
>> 679 select ARCH_MIGHT_HAVE_PC_SERIO
>> 680 select BOOT_ELF32
>> 681 select CEVT_R4K
>> 682 select CSRC_R4K
>> 683 select DEFAULT_SGI_PARTITION
>> 684 select DMA_NONCOHERENT
>> 685 select HAVE_EISA
>> 686 select I8253
>> 687 select I8259
>> 688 select IP22_CPU_SCACHE
>> 689 select IRQ_MIPS_CPU
>> 690 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 691 select SGI_HAS_I8042
>> 692 select SGI_HAS_INDYDOG
>> 693 select SGI_HAS_HAL2
>> 694 select SGI_HAS_SEEQ
>> 695 select SGI_HAS_WD93
>> 696 select SGI_HAS_ZILOG
>> 697 select SWAP_IO_SPACE
>> 698 select SYS_HAS_CPU_R4X00
>> 699 select SYS_HAS_CPU_R5000
>> 700 select SYS_HAS_EARLY_PRINTK
>> 701 select SYS_SUPPORTS_32BIT_KERNEL
>> 702 select SYS_SUPPORTS_64BIT_KERNEL
>> 703 select SYS_SUPPORTS_BIG_ENDIAN
>> 704 select WAR_R4600_V1_INDEX_ICACHEOP
>> 705 select WAR_R4600_V1_HIT_CACHEOP
>> 706 select WAR_R4600_V2_HIT_CACHEOP
>> 707 select MIPS_L1_CACHE_SHIFT_7
>> 708 help
>> 709 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 710 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 711 that runs on these, say Y here.
>> 712
>> 713 config SGI_IP27
>> 714 bool "SGI IP27 (Origin200/2000)"
>> 715 select ARCH_HAS_PHYS_TO_DMA
>> 716 select ARCH_SPARSEMEM_ENABLE
>> 717 select FW_ARC
>> 718 select FW_ARC64
>> 719 select ARC_CMDLINE_ONLY
>> 720 select BOOT_ELF64
>> 721 select DEFAULT_SGI_PARTITION
>> 722 select FORCE_PCI
>> 723 select SYS_HAS_EARLY_PRINTK
>> 724 select HAVE_PCI
>> 725 select IRQ_MIPS_CPU
>> 726 select IRQ_DOMAIN_HIERARCHY
>> 727 select NR_CPUS_DEFAULT_64
>> 728 select PCI_DRIVERS_GENERIC
>> 729 select PCI_XTALK_BRIDGE
>> 730 select SYS_HAS_CPU_R10000
>> 731 select SYS_SUPPORTS_64BIT_KERNEL
>> 732 select SYS_SUPPORTS_BIG_ENDIAN
>> 733 select SYS_SUPPORTS_NUMA
>> 734 select SYS_SUPPORTS_SMP
>> 735 select WAR_R10000_LLSC
>> 736 select MIPS_L1_CACHE_SHIFT_7
>> 737 select NUMA
>> 738 select HAVE_ARCH_NODEDATA_EXTENSION
>> 739 help
>> 740 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 741 workstations. To compile a Linux kernel that runs on these, say Y
>> 742 here.
>> 743
>> 744 config SGI_IP28
>> 745 bool "SGI IP28 (Indigo2 R10k)"
>> 746 select ARC_MEMORY
>> 747 select ARC_PROMLIB
>> 748 select FW_ARC
>> 749 select FW_ARC64
>> 750 select ARCH_MIGHT_HAVE_PC_SERIO
>> 751 select BOOT_ELF64
>> 752 select CEVT_R4K
>> 753 select CSRC_R4K
>> 754 select DEFAULT_SGI_PARTITION
>> 755 select DMA_NONCOHERENT
>> 756 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 757 select IRQ_MIPS_CPU
>> 758 select HAVE_EISA
>> 759 select I8253
>> 760 select I8259
>> 761 select SGI_HAS_I8042
>> 762 select SGI_HAS_INDYDOG
>> 763 select SGI_HAS_HAL2
>> 764 select SGI_HAS_SEEQ
>> 765 select SGI_HAS_WD93
>> 766 select SGI_HAS_ZILOG
>> 767 select SWAP_IO_SPACE
>> 768 select SYS_HAS_CPU_R10000
>> 769 select SYS_HAS_EARLY_PRINTK
>> 770 select SYS_SUPPORTS_64BIT_KERNEL
>> 771 select SYS_SUPPORTS_BIG_ENDIAN
>> 772 select WAR_R10000_LLSC
>> 773 select MIPS_L1_CACHE_SHIFT_7
>> 774 help
>> 775 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 776 kernel that runs on these, say Y here.
>> 777
>> 778 config SGI_IP30
>> 779 bool "SGI IP30 (Octane/Octane2)"
>> 780 select ARCH_HAS_PHYS_TO_DMA
>> 781 select FW_ARC
>> 782 select FW_ARC64
>> 783 select BOOT_ELF64
>> 784 select CEVT_R4K
>> 785 select CSRC_R4K
>> 786 select FORCE_PCI
>> 787 select SYNC_R4K if SMP
>> 788 select ZONE_DMA32
>> 789 select HAVE_PCI
>> 790 select IRQ_MIPS_CPU
>> 791 select IRQ_DOMAIN_HIERARCHY
>> 792 select PCI_DRIVERS_GENERIC
>> 793 select PCI_XTALK_BRIDGE
>> 794 select SYS_HAS_EARLY_PRINTK
>> 795 select SYS_HAS_CPU_R10000
>> 796 select SYS_SUPPORTS_64BIT_KERNEL
>> 797 select SYS_SUPPORTS_BIG_ENDIAN
>> 798 select SYS_SUPPORTS_SMP
>> 799 select WAR_R10000_LLSC
>> 800 select MIPS_L1_CACHE_SHIFT_7
>> 801 select ARC_MEMORY
>> 802 help
>> 803 These are the SGI Octane and Octane2 graphics workstations. To
>> 804 compile a Linux kernel that runs on these, say Y here.
>> 805
>> 806 config SGI_IP32
>> 807 bool "SGI IP32 (O2)"
>> 808 select ARC_MEMORY
>> 809 select ARC_PROMLIB
>> 810 select ARCH_HAS_PHYS_TO_DMA
>> 811 select FW_ARC
>> 812 select FW_ARC32
>> 813 select BOOT_ELF32
>> 814 select CEVT_R4K
>> 815 select CSRC_R4K
>> 816 select DMA_NONCOHERENT
>> 817 select HAVE_PCI
>> 818 select IRQ_MIPS_CPU
>> 819 select R5000_CPU_SCACHE
>> 820 select RM7000_CPU_SCACHE
>> 821 select SYS_HAS_CPU_R5000
>> 822 select SYS_HAS_CPU_R10000 if BROKEN
>> 823 select SYS_HAS_CPU_RM7000
>> 824 select SYS_HAS_CPU_NEVADA
>> 825 select SYS_SUPPORTS_64BIT_KERNEL
>> 826 select SYS_SUPPORTS_BIG_ENDIAN
>> 827 select WAR_ICACHE_REFILLS
>> 828 help
>> 829 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 830
>> 831 config SIBYTE_CRHONE
>> 832 bool "Sibyte BCM91125C-CRhone"
>> 833 select BOOT_ELF32
>> 834 select SIBYTE_BCM1125
>> 835 select SWAP_IO_SPACE
>> 836 select SYS_HAS_CPU_SB1
>> 837 select SYS_SUPPORTS_BIG_ENDIAN
>> 838 select SYS_SUPPORTS_HIGHMEM
>> 839 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 840
>> 841 config SIBYTE_RHONE
>> 842 bool "Sibyte BCM91125E-Rhone"
>> 843 select BOOT_ELF32
>> 844 select SIBYTE_SB1250
>> 845 select SWAP_IO_SPACE
>> 846 select SYS_HAS_CPU_SB1
>> 847 select SYS_SUPPORTS_BIG_ENDIAN
>> 848 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 849
>> 850 config SIBYTE_SWARM
>> 851 bool "Sibyte BCM91250A-SWARM"
>> 852 select BOOT_ELF32
>> 853 select HAVE_PATA_PLATFORM
>> 854 select SIBYTE_SB1250
>> 855 select SWAP_IO_SPACE
>> 856 select SYS_HAS_CPU_SB1
>> 857 select SYS_SUPPORTS_BIG_ENDIAN
>> 858 select SYS_SUPPORTS_HIGHMEM
>> 859 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 860 select ZONE_DMA32 if 64BIT
>> 861 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 862
>> 863 config SIBYTE_LITTLESUR
>> 864 bool "Sibyte BCM91250C2-LittleSur"
>> 865 select BOOT_ELF32
>> 866 select HAVE_PATA_PLATFORM
>> 867 select SIBYTE_SB1250
>> 868 select SWAP_IO_SPACE
>> 869 select SYS_HAS_CPU_SB1
>> 870 select SYS_SUPPORTS_BIG_ENDIAN
>> 871 select SYS_SUPPORTS_HIGHMEM
>> 872 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 873 select ZONE_DMA32 if 64BIT
>> 874
>> 875 config SIBYTE_SENTOSA
>> 876 bool "Sibyte BCM91250E-Sentosa"
>> 877 select BOOT_ELF32
>> 878 select SIBYTE_SB1250
>> 879 select SWAP_IO_SPACE
>> 880 select SYS_HAS_CPU_SB1
>> 881 select SYS_SUPPORTS_BIG_ENDIAN
>> 882 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 883 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 884
>> 885 config SIBYTE_BIGSUR
>> 886 bool "Sibyte BCM91480B-BigSur"
>> 887 select BOOT_ELF32
>> 888 select NR_CPUS_DEFAULT_4
>> 889 select SIBYTE_BCM1x80
>> 890 select SWAP_IO_SPACE
>> 891 select SYS_HAS_CPU_SB1
>> 892 select SYS_SUPPORTS_BIG_ENDIAN
>> 893 select SYS_SUPPORTS_HIGHMEM
>> 894 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 895 select ZONE_DMA32 if 64BIT
>> 896 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 897
>> 898 config SNI_RM
>> 899 bool "SNI RM200/300/400"
>> 900 select ARC_MEMORY
>> 901 select ARC_PROMLIB
>> 902 select FW_ARC if CPU_LITTLE_ENDIAN
>> 903 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 904 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 905 select ARCH_MAY_HAVE_PC_FDC
>> 906 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 907 select ARCH_MIGHT_HAVE_PC_SERIO
>> 908 select BOOT_ELF32
>> 909 select CEVT_R4K
>> 910 select CSRC_R4K
>> 911 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 912 select DMA_NONCOHERENT
>> 913 select GENERIC_ISA_DMA
>> 914 select HAVE_EISA
>> 915 select HAVE_PCSPKR_PLATFORM
>> 916 select HAVE_PCI
>> 917 select IRQ_MIPS_CPU
>> 918 select I8253
>> 919 select I8259
>> 920 select ISA
>> 921 select MIPS_L1_CACHE_SHIFT_6
>> 922 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 923 select SYS_HAS_CPU_R4X00
>> 924 select SYS_HAS_CPU_R5000
>> 925 select SYS_HAS_CPU_R10000
>> 926 select R5000_CPU_SCACHE
>> 927 select SYS_HAS_EARLY_PRINTK
>> 928 select SYS_SUPPORTS_32BIT_KERNEL
>> 929 select SYS_SUPPORTS_64BIT_KERNEL
>> 930 select SYS_SUPPORTS_BIG_ENDIAN
>> 931 select SYS_SUPPORTS_HIGHMEM
>> 932 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 933 select WAR_R4600_V2_HIT_CACHEOP
>> 934 help
>> 935 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 936 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 937 Technology and now in turn merged with Fujitsu. Say Y here to
>> 938 support this machine type.
>> 939
>> 940 config MACH_TX49XX
>> 941 bool "Toshiba TX49 series based machines"
>> 942 select WAR_TX49XX_ICACHE_INDEX_INV
>> 943
>> 944 config MIKROTIK_RB532
>> 945 bool "Mikrotik RB532 boards"
>> 946 select CEVT_R4K
>> 947 select CSRC_R4K
>> 948 select DMA_NONCOHERENT
>> 949 select HAVE_PCI
>> 950 select IRQ_MIPS_CPU
>> 951 select SYS_HAS_CPU_MIPS32_R1
>> 952 select SYS_SUPPORTS_32BIT_KERNEL
>> 953 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 954 select SWAP_IO_SPACE
>> 955 select BOOT_RAW
>> 956 select GPIOLIB
>> 957 select MIPS_L1_CACHE_SHIFT_4
>> 958 help
>> 959 Support the Mikrotik(tm) RouterBoard 532 series,
>> 960 based on the IDT RC32434 SoC.
>> 961
>> 962 config CAVIUM_OCTEON_SOC
>> 963 bool "Cavium Networks Octeon SoC based boards"
>> 964 select CEVT_R4K
>> 965 select ARCH_HAS_PHYS_TO_DMA
>> 966 select HAVE_RAPIDIO
>> 967 select PHYS_ADDR_T_64BIT
>> 968 select SYS_SUPPORTS_64BIT_KERNEL
>> 969 select SYS_SUPPORTS_BIG_ENDIAN
>> 970 select EDAC_SUPPORT
>> 971 select EDAC_ATOMIC_SCRUB
>> 972 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 973 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 974 select SYS_HAS_EARLY_PRINTK
>> 975 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 976 select HAVE_PCI
>> 977 select HAVE_PLAT_DELAY
>> 978 select HAVE_PLAT_FW_INIT_CMDLINE
>> 979 select HAVE_PLAT_MEMCPY
>> 980 select ZONE_DMA32
>> 981 select GPIOLIB
>> 982 select USE_OF
>> 983 select ARCH_SPARSEMEM_ENABLE
>> 984 select SYS_SUPPORTS_SMP
>> 985 select NR_CPUS_DEFAULT_64
>> 986 select MIPS_NR_CPU_NR_MAP_1024
>> 987 select BUILTIN_DTB
>> 988 select MTD
>> 989 select MTD_COMPLEX_MAPPINGS
>> 990 select SWIOTLB
>> 991 select SYS_SUPPORTS_RELOCATABLE
>> 992 help
>> 993 This option supports all of the Octeon reference boards from Cavium
>> 994 Networks. It builds a kernel that dynamically determines the Octeon
>> 995 CPU type and supports all known board reference implementations.
>> 996 Some of the supported boards are:
>> 997 EBT3000
>> 998 EBH3000
>> 999 EBH3100
>> 1000 Thunder
>> 1001 Kodama
>> 1002 Hikari
>> 1003 Say Y here for most Octeon reference boards.
>> 1004
>> 1005 endchoice
>> 1006
>> 1007 config FIT_IMAGE_FDT_EPM5
>> 1008 bool "Include FDT for Mobileye EyeQ5 development platforms"
>> 1009 depends on MACH_EYEQ5
>> 1010 default n
>> 1011 help
>> 1012 Enable this to include the FDT for the EyeQ5 development platforms
>> 1013 from Mobileye in the FIT kernel image.
>> 1014 This requires u-boot on the platform.
>> 1015
>> 1016 source "arch/mips/alchemy/Kconfig"
>> 1017 source "arch/mips/ath25/Kconfig"
>> 1018 source "arch/mips/ath79/Kconfig"
>> 1019 source "arch/mips/bcm47xx/Kconfig"
>> 1020 source "arch/mips/bcm63xx/Kconfig"
>> 1021 source "arch/mips/bmips/Kconfig"
>> 1022 source "arch/mips/generic/Kconfig"
>> 1023 source "arch/mips/ingenic/Kconfig"
>> 1024 source "arch/mips/jazz/Kconfig"
>> 1025 source "arch/mips/lantiq/Kconfig"
>> 1026 source "arch/mips/mobileye/Kconfig"
>> 1027 source "arch/mips/pic32/Kconfig"
>> 1028 source "arch/mips/ralink/Kconfig"
>> 1029 source "arch/mips/sgi-ip27/Kconfig"
>> 1030 source "arch/mips/sibyte/Kconfig"
>> 1031 source "arch/mips/txx9/Kconfig"
>> 1032 source "arch/mips/cavium-octeon/Kconfig"
>> 1033 source "arch/mips/loongson2ef/Kconfig"
>> 1034 source "arch/mips/loongson32/Kconfig"
>> 1035 source "arch/mips/loongson64/Kconfig"
>> 1036
>> 1037 endmenu
67 1038
68 config GENERIC_HWEIGHT 1039 config GENERIC_HWEIGHT
69 def_bool y !! 1040 bool
>> 1041 default y
70 1042
71 config ARCH_HAS_ILOG2_U32 !! 1043 config GENERIC_CALIBRATE_DELAY
72 def_bool n !! 1044 bool
>> 1045 default y
73 1046
74 config ARCH_HAS_ILOG2_U64 !! 1047 config SCHED_OMIT_FRAME_POINTER
75 def_bool n !! 1048 bool
>> 1049 default y
>> 1050
>> 1051 #
>> 1052 # Select some configuration options automatically based on user selections.
>> 1053 #
>> 1054 config FW_ARC
>> 1055 bool
>> 1056
>> 1057 config ARCH_MAY_HAVE_PC_FDC
>> 1058 bool
>> 1059
>> 1060 config BOOT_RAW
>> 1061 bool
76 1062
77 config ARCH_MTD_XIP !! 1063 config CEVT_BCM1480
>> 1064 bool
>> 1065
>> 1066 config CEVT_DS1287
>> 1067 bool
>> 1068
>> 1069 config CEVT_GT641XX
>> 1070 bool
>> 1071
>> 1072 config CEVT_R4K
>> 1073 bool
>> 1074
>> 1075 config CEVT_SB1250
>> 1076 bool
>> 1077
>> 1078 config CEVT_TXX9
>> 1079 bool
>> 1080
>> 1081 config CSRC_BCM1480
>> 1082 bool
>> 1083
>> 1084 config CSRC_IOASIC
>> 1085 bool
>> 1086
>> 1087 config CSRC_R4K
>> 1088 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1089 select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT
>> 1090 bool
>> 1091
>> 1092 config CSRC_SB1250
>> 1093 bool
>> 1094
>> 1095 config MIPS_CLOCK_VSYSCALL
>> 1096 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1097
>> 1098 config GPIO_TXX9
>> 1099 select GPIOLIB
>> 1100 bool
>> 1101
>> 1102 config FW_CFE
>> 1103 bool
>> 1104
>> 1105 config ARCH_SUPPORTS_UPROBES
78 def_bool y 1106 def_bool y
79 1107
>> 1108 config DMA_NONCOHERENT
>> 1109 bool
>> 1110 #
>> 1111 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1112 # Attribute bits. It is believed that the uncached access through
>> 1113 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1114 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1115 # significant advantages.
>> 1116 #
>> 1117 select ARCH_HAS_SETUP_DMA_OPS
>> 1118 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1119 select ARCH_HAS_DMA_PREP_COHERENT
>> 1120 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 1121 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1122 select ARCH_HAS_DMA_SET_UNCACHED
>> 1123 select DMA_NONCOHERENT_MMAP
>> 1124 select NEED_DMA_MAP_STATE
>> 1125
>> 1126 config SYS_HAS_EARLY_PRINTK
>> 1127 bool
>> 1128
>> 1129 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1130 bool
>> 1131
>> 1132 config MIPS_BONITO64
>> 1133 bool
>> 1134
>> 1135 config MIPS_MSC
>> 1136 bool
>> 1137
>> 1138 config SYNC_R4K
>> 1139 bool
>> 1140
80 config NO_IOPORT_MAP 1141 config NO_IOPORT_MAP
81 def_bool n 1142 def_bool n
82 1143
83 config HZ !! 1144 config GENERIC_CSUM
84 int !! 1145 def_bool CPU_NO_LOAD_STORE_LR
85 default 100 <<
86 1146
87 config LOCKDEP_SUPPORT !! 1147 config GENERIC_ISA_DMA
88 def_bool y !! 1148 bool
>> 1149 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1150 select ISA_DMA_API
89 1151
90 config STACKTRACE_SUPPORT !! 1152 config GENERIC_ISA_DMA_SUPPORT_BROKEN
91 def_bool y !! 1153 bool
>> 1154 select GENERIC_ISA_DMA
92 1155
93 config MMU !! 1156 config HAVE_PLAT_DELAY
94 def_bool n !! 1157 bool
95 select PFAULT <<
96 1158
97 config HAVE_XTENSA_GPIO32 !! 1159 config HAVE_PLAT_FW_INIT_CMDLINE
98 def_bool n !! 1160 bool
>> 1161
>> 1162 config HAVE_PLAT_MEMCPY
>> 1163 bool
>> 1164
>> 1165 config ISA_DMA_API
>> 1166 bool
99 1167
100 config KASAN_SHADOW_OFFSET !! 1168 config SYS_SUPPORTS_RELOCATABLE
101 hex !! 1169 bool
102 default 0x6e400000 !! 1170 help
>> 1171 Selected if the platform supports relocating the kernel.
>> 1172 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1173 to allow access to command line and entropy sources.
>> 1174
>> 1175 #
>> 1176 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1177 # answer,so we try hard to limit the available choices. Also the use of a
>> 1178 # choice statement should be more obvious to the user.
>> 1179 #
>> 1180 choice
>> 1181 prompt "Endianness selection"
>> 1182 help
>> 1183 Some MIPS machines can be configured for either little or big endian
>> 1184 byte order. These modes require different kernels and a different
>> 1185 Linux distribution. In general there is one preferred byteorder for a
>> 1186 particular system but some systems are just as commonly used in the
>> 1187 one or the other endianness.
103 1188
104 config CPU_BIG_ENDIAN 1189 config CPU_BIG_ENDIAN
105 def_bool $(success,test "$(shell,echo !! 1190 bool "Big endian"
>> 1191 depends on SYS_SUPPORTS_BIG_ENDIAN
106 1192
107 config CPU_LITTLE_ENDIAN 1193 config CPU_LITTLE_ENDIAN
108 def_bool !CPU_BIG_ENDIAN !! 1194 bool "Little endian"
>> 1195 depends on SYS_SUPPORTS_LITTLE_ENDIAN
109 1196
110 config CC_HAVE_CALL0_ABI !! 1197 endchoice
111 def_bool $(success,test "$(shell,echo <<
112 1198
113 menu "Processor type and features" !! 1199 config EXPORT_UASM
>> 1200 bool
114 1201
115 choice !! 1202 config SYS_SUPPORTS_APM_EMULATION
116 prompt "Xtensa Processor Configuration !! 1203 bool
117 default XTENSA_VARIANT_FSF !! 1204
>> 1205 config SYS_SUPPORTS_BIG_ENDIAN
>> 1206 bool
118 1207
119 config XTENSA_VARIANT_FSF !! 1208 config SYS_SUPPORTS_LITTLE_ENDIAN
120 bool "fsf - default (not generic) conf !! 1209 bool
121 select MMU <<
122 1210
123 config XTENSA_VARIANT_DC232B !! 1211 config MIPS_HUGE_TLB_SUPPORT
124 bool "dc232b - Diamond 232L Standard C !! 1212 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
125 select MMU <<
126 select HAVE_XTENSA_GPIO32 <<
127 help <<
128 This variant refers to Tensilica's D <<
129 1213
130 config XTENSA_VARIANT_DC233C !! 1214 config IRQ_TXX9
131 bool "dc233c - Diamond 233L Standard C !! 1215 bool
132 select MMU <<
133 select HAVE_XTENSA_GPIO32 <<
134 help <<
135 This variant refers to Tensilica's D <<
136 1216
137 config XTENSA_VARIANT_CUSTOM !! 1217 config IRQ_GT641XX
138 bool "Custom Xtensa processor configur !! 1218 bool
139 select HAVE_XTENSA_GPIO32 !! 1219
>> 1220 config PCI_GT64XXX_PCI0
>> 1221 bool
>> 1222
>> 1223 config PCI_XTALK_BRIDGE
>> 1224 bool
>> 1225
>> 1226 config NO_EXCEPT_FILL
>> 1227 bool
>> 1228
>> 1229 config MIPS_SPRAM
>> 1230 bool
>> 1231
>> 1232 config SWAP_IO_SPACE
>> 1233 bool
>> 1234
>> 1235 config SGI_HAS_INDYDOG
>> 1236 bool
>> 1237
>> 1238 config SGI_HAS_HAL2
>> 1239 bool
>> 1240
>> 1241 config SGI_HAS_SEEQ
>> 1242 bool
>> 1243
>> 1244 config SGI_HAS_WD93
>> 1245 bool
>> 1246
>> 1247 config SGI_HAS_ZILOG
>> 1248 bool
>> 1249
>> 1250 config SGI_HAS_I8042
>> 1251 bool
>> 1252
>> 1253 config DEFAULT_SGI_PARTITION
>> 1254 bool
>> 1255
>> 1256 config FW_ARC32
>> 1257 bool
>> 1258
>> 1259 config FW_SNIPROM
>> 1260 bool
>> 1261
>> 1262 config BOOT_ELF32
>> 1263 bool
>> 1264
>> 1265 config MIPS_L1_CACHE_SHIFT_4
>> 1266 bool
>> 1267
>> 1268 config MIPS_L1_CACHE_SHIFT_5
>> 1269 bool
>> 1270
>> 1271 config MIPS_L1_CACHE_SHIFT_6
>> 1272 bool
>> 1273
>> 1274 config MIPS_L1_CACHE_SHIFT_7
>> 1275 bool
>> 1276
>> 1277 config MIPS_L1_CACHE_SHIFT
>> 1278 int
>> 1279 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1280 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1281 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1282 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1283 default "5"
>> 1284
>> 1285 config ARC_CMDLINE_ONLY
>> 1286 bool
>> 1287
>> 1288 config ARC_CONSOLE
>> 1289 bool "ARC console support"
>> 1290 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
>> 1291
>> 1292 config ARC_MEMORY
>> 1293 bool
>> 1294
>> 1295 config ARC_PROMLIB
>> 1296 bool
>> 1297
>> 1298 config FW_ARC64
>> 1299 bool
>> 1300
>> 1301 config BOOT_ELF64
>> 1302 bool
>> 1303
>> 1304 menu "CPU selection"
>> 1305
>> 1306 choice
>> 1307 prompt "CPU type"
>> 1308 default CPU_R4X00
>> 1309
>> 1310 config CPU_LOONGSON64
>> 1311 bool "Loongson 64-bit CPU"
>> 1312 depends on SYS_HAS_CPU_LOONGSON64
>> 1313 select ARCH_HAS_PHYS_TO_DMA
>> 1314 select CPU_MIPSR2
>> 1315 select CPU_HAS_PREFETCH
>> 1316 select CPU_SUPPORTS_64BIT_KERNEL
>> 1317 select CPU_SUPPORTS_HIGHMEM
>> 1318 select CPU_SUPPORTS_HUGEPAGES
>> 1319 select CPU_SUPPORTS_MSA
>> 1320 select CPU_SUPPORTS_VZ
>> 1321 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1322 select CPU_MIPSR2_IRQ_VI
>> 1323 select DMA_NONCOHERENT
>> 1324 select WEAK_ORDERING
>> 1325 select WEAK_REORDERING_BEYOND_LLSC
>> 1326 select MIPS_ASID_BITS_VARIABLE
>> 1327 select MIPS_PGD_C0_CONTEXT
>> 1328 select MIPS_L1_CACHE_SHIFT_6
>> 1329 select MIPS_FP_SUPPORT
>> 1330 select GPIOLIB
>> 1331 select SWIOTLB
>> 1332 help
>> 1333 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1334 cores implements the MIPS64R2 instruction set with many extensions,
>> 1335 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1336 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1337 Loongson-2E/2F is not covered here and will be removed in future.
>> 1338
>> 1339 config CPU_LOONGSON2E
>> 1340 bool "Loongson 2E"
>> 1341 depends on SYS_HAS_CPU_LOONGSON2E
>> 1342 select CPU_LOONGSON2EF
>> 1343 help
>> 1344 The Loongson 2E processor implements the MIPS III instruction set
>> 1345 with many extensions.
>> 1346
>> 1347 It has an internal FPGA northbridge, which is compatible to
>> 1348 bonito64.
>> 1349
>> 1350 config CPU_LOONGSON2F
>> 1351 bool "Loongson 2F"
>> 1352 depends on SYS_HAS_CPU_LOONGSON2F
>> 1353 select CPU_LOONGSON2EF
>> 1354 help
>> 1355 The Loongson 2F processor implements the MIPS III instruction set
>> 1356 with many extensions.
>> 1357
>> 1358 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1359 have a similar programming interface with FPGA northbridge used in
>> 1360 Loongson2E.
>> 1361
>> 1362 config CPU_LOONGSON1B
>> 1363 bool "Loongson 1B"
>> 1364 depends on SYS_HAS_CPU_LOONGSON1B
>> 1365 select CPU_LOONGSON32
>> 1366 select LEDS_GPIO_REGISTER
>> 1367 help
>> 1368 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1369 Release 1 instruction set and part of the MIPS32 Release 2
>> 1370 instruction set.
>> 1371
>> 1372 config CPU_LOONGSON1C
>> 1373 bool "Loongson 1C"
>> 1374 depends on SYS_HAS_CPU_LOONGSON1C
>> 1375 select CPU_LOONGSON32
>> 1376 select LEDS_GPIO_REGISTER
>> 1377 help
>> 1378 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1379 Release 1 instruction set and part of the MIPS32 Release 2
>> 1380 instruction set.
>> 1381
>> 1382 config CPU_MIPS32_R1
>> 1383 bool "MIPS32 Release 1"
>> 1384 depends on SYS_HAS_CPU_MIPS32_R1
>> 1385 select CPU_HAS_PREFETCH
>> 1386 select CPU_SUPPORTS_32BIT_KERNEL
>> 1387 select CPU_SUPPORTS_HIGHMEM
>> 1388 help
>> 1389 Choose this option to build a kernel for release 1 or later of the
>> 1390 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1391 MIPS processor are based on a MIPS32 processor. If you know the
>> 1392 specific type of processor in your system, choose those that one
>> 1393 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1394 Release 2 of the MIPS32 architecture is available since several
>> 1395 years so chances are you even have a MIPS32 Release 2 processor
>> 1396 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1397 performance.
>> 1398
>> 1399 config CPU_MIPS32_R2
>> 1400 bool "MIPS32 Release 2"
>> 1401 depends on SYS_HAS_CPU_MIPS32_R2
>> 1402 select CPU_HAS_PREFETCH
>> 1403 select CPU_SUPPORTS_32BIT_KERNEL
>> 1404 select CPU_SUPPORTS_HIGHMEM
>> 1405 select CPU_SUPPORTS_MSA
>> 1406 help
>> 1407 Choose this option to build a kernel for release 2 or later of the
>> 1408 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1409 MIPS processor are based on a MIPS32 processor. If you know the
>> 1410 specific type of processor in your system, choose those that one
>> 1411 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1412
>> 1413 config CPU_MIPS32_R5
>> 1414 bool "MIPS32 Release 5"
>> 1415 depends on SYS_HAS_CPU_MIPS32_R5
>> 1416 select CPU_HAS_PREFETCH
>> 1417 select CPU_SUPPORTS_32BIT_KERNEL
>> 1418 select CPU_SUPPORTS_HIGHMEM
>> 1419 select CPU_SUPPORTS_MSA
>> 1420 select CPU_SUPPORTS_VZ
>> 1421 select MIPS_O32_FP64_SUPPORT
>> 1422 help
>> 1423 Choose this option to build a kernel for release 5 or later of the
>> 1424 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1425 family, are based on a MIPS32r5 processor. If you own an older
>> 1426 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1427
>> 1428 config CPU_MIPS32_R6
>> 1429 bool "MIPS32 Release 6"
>> 1430 depends on SYS_HAS_CPU_MIPS32_R6
>> 1431 select CPU_HAS_PREFETCH
>> 1432 select CPU_NO_LOAD_STORE_LR
>> 1433 select CPU_SUPPORTS_32BIT_KERNEL
>> 1434 select CPU_SUPPORTS_HIGHMEM
>> 1435 select CPU_SUPPORTS_MSA
>> 1436 select CPU_SUPPORTS_VZ
>> 1437 select MIPS_O32_FP64_SUPPORT
>> 1438 help
>> 1439 Choose this option to build a kernel for release 6 or later of the
>> 1440 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1441 family, are based on a MIPS32r6 processor. If you own an older
>> 1442 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1443
>> 1444 config CPU_MIPS64_R1
>> 1445 bool "MIPS64 Release 1"
>> 1446 depends on SYS_HAS_CPU_MIPS64_R1
>> 1447 select CPU_HAS_PREFETCH
>> 1448 select CPU_SUPPORTS_32BIT_KERNEL
>> 1449 select CPU_SUPPORTS_64BIT_KERNEL
>> 1450 select CPU_SUPPORTS_HIGHMEM
>> 1451 select CPU_SUPPORTS_HUGEPAGES
>> 1452 help
>> 1453 Choose this option to build a kernel for release 1 or later of the
>> 1454 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1455 MIPS processor are based on a MIPS64 processor. If you know the
>> 1456 specific type of processor in your system, choose those that one
>> 1457 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1458 Release 2 of the MIPS64 architecture is available since several
>> 1459 years so chances are you even have a MIPS64 Release 2 processor
>> 1460 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1461 performance.
>> 1462
>> 1463 config CPU_MIPS64_R2
>> 1464 bool "MIPS64 Release 2"
>> 1465 depends on SYS_HAS_CPU_MIPS64_R2
>> 1466 select CPU_HAS_PREFETCH
>> 1467 select CPU_SUPPORTS_32BIT_KERNEL
>> 1468 select CPU_SUPPORTS_64BIT_KERNEL
>> 1469 select CPU_SUPPORTS_HIGHMEM
>> 1470 select CPU_SUPPORTS_HUGEPAGES
>> 1471 select CPU_SUPPORTS_MSA
>> 1472 help
>> 1473 Choose this option to build a kernel for release 2 or later of the
>> 1474 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1475 MIPS processor are based on a MIPS64 processor. If you know the
>> 1476 specific type of processor in your system, choose those that one
>> 1477 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1478
>> 1479 config CPU_MIPS64_R5
>> 1480 bool "MIPS64 Release 5"
>> 1481 depends on SYS_HAS_CPU_MIPS64_R5
>> 1482 select CPU_HAS_PREFETCH
>> 1483 select CPU_SUPPORTS_32BIT_KERNEL
>> 1484 select CPU_SUPPORTS_64BIT_KERNEL
>> 1485 select CPU_SUPPORTS_HIGHMEM
>> 1486 select CPU_SUPPORTS_HUGEPAGES
>> 1487 select CPU_SUPPORTS_MSA
>> 1488 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1489 select CPU_SUPPORTS_VZ
>> 1490 help
>> 1491 Choose this option to build a kernel for release 5 or later of the
>> 1492 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1493 release partly implementing release 6 features. Though there is no
>> 1494 any hardware known to be based on this release.
>> 1495
>> 1496 config CPU_MIPS64_R6
>> 1497 bool "MIPS64 Release 6"
>> 1498 depends on SYS_HAS_CPU_MIPS64_R6
>> 1499 select CPU_HAS_PREFETCH
>> 1500 select CPU_NO_LOAD_STORE_LR
>> 1501 select CPU_SUPPORTS_32BIT_KERNEL
>> 1502 select CPU_SUPPORTS_64BIT_KERNEL
>> 1503 select CPU_SUPPORTS_HIGHMEM
>> 1504 select CPU_SUPPORTS_HUGEPAGES
>> 1505 select CPU_SUPPORTS_MSA
>> 1506 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1507 select CPU_SUPPORTS_VZ
>> 1508 help
>> 1509 Choose this option to build a kernel for release 6 or later of the
>> 1510 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1511 family, are based on a MIPS64r6 processor. If you own an older
>> 1512 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1513
>> 1514 config CPU_P5600
>> 1515 bool "MIPS Warrior P5600"
>> 1516 depends on SYS_HAS_CPU_P5600
>> 1517 select CPU_HAS_PREFETCH
>> 1518 select CPU_SUPPORTS_32BIT_KERNEL
>> 1519 select CPU_SUPPORTS_HIGHMEM
>> 1520 select CPU_SUPPORTS_MSA
>> 1521 select CPU_SUPPORTS_CPUFREQ
>> 1522 select CPU_SUPPORTS_VZ
>> 1523 select CPU_MIPSR2_IRQ_VI
>> 1524 select CPU_MIPSR2_IRQ_EI
>> 1525 select MIPS_O32_FP64_SUPPORT
>> 1526 help
>> 1527 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1528 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1529 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1530 level features like up to six P5600 calculation cores, CM2 with L2
>> 1531 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1532 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1533 eJTAG and PDtrace.
>> 1534
>> 1535 config CPU_R3000
>> 1536 bool "R3000"
>> 1537 depends on SYS_HAS_CPU_R3000
>> 1538 select CPU_HAS_WB
>> 1539 select CPU_R3K_TLB
>> 1540 select CPU_SUPPORTS_32BIT_KERNEL
>> 1541 select CPU_SUPPORTS_HIGHMEM
>> 1542 help
>> 1543 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1544 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1545 *not* work on R4000 machines and vice versa. However, since most
>> 1546 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1547 might be a safe bet. If the resulting kernel does not work,
>> 1548 try to recompile with R3000.
>> 1549
>> 1550 config CPU_R4300
>> 1551 bool "R4300"
>> 1552 depends on SYS_HAS_CPU_R4300
>> 1553 select CPU_SUPPORTS_32BIT_KERNEL
>> 1554 select CPU_SUPPORTS_64BIT_KERNEL
>> 1555 help
>> 1556 MIPS Technologies R4300-series processors.
>> 1557
>> 1558 config CPU_R4X00
>> 1559 bool "R4x00"
>> 1560 depends on SYS_HAS_CPU_R4X00
>> 1561 select CPU_SUPPORTS_32BIT_KERNEL
>> 1562 select CPU_SUPPORTS_64BIT_KERNEL
>> 1563 select CPU_SUPPORTS_HUGEPAGES
>> 1564 help
>> 1565 MIPS Technologies R4000-series processors other than 4300, including
>> 1566 the R4000, R4400, R4600, and 4700.
>> 1567
>> 1568 config CPU_TX49XX
>> 1569 bool "R49XX"
>> 1570 depends on SYS_HAS_CPU_TX49XX
>> 1571 select CPU_HAS_PREFETCH
>> 1572 select CPU_SUPPORTS_32BIT_KERNEL
>> 1573 select CPU_SUPPORTS_64BIT_KERNEL
>> 1574 select CPU_SUPPORTS_HUGEPAGES
>> 1575
>> 1576 config CPU_R5000
>> 1577 bool "R5000"
>> 1578 depends on SYS_HAS_CPU_R5000
>> 1579 select CPU_SUPPORTS_32BIT_KERNEL
>> 1580 select CPU_SUPPORTS_64BIT_KERNEL
>> 1581 select CPU_SUPPORTS_HUGEPAGES
>> 1582 help
>> 1583 MIPS Technologies R5000-series processors other than the Nevada.
>> 1584
>> 1585 config CPU_R5500
>> 1586 bool "R5500"
>> 1587 depends on SYS_HAS_CPU_R5500
>> 1588 select CPU_SUPPORTS_32BIT_KERNEL
>> 1589 select CPU_SUPPORTS_64BIT_KERNEL
>> 1590 select CPU_SUPPORTS_HUGEPAGES
>> 1591 help
>> 1592 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1593 instruction set.
>> 1594
>> 1595 config CPU_NEVADA
>> 1596 bool "RM52xx"
>> 1597 depends on SYS_HAS_CPU_NEVADA
>> 1598 select CPU_SUPPORTS_32BIT_KERNEL
>> 1599 select CPU_SUPPORTS_64BIT_KERNEL
>> 1600 select CPU_SUPPORTS_HUGEPAGES
>> 1601 help
>> 1602 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1603
>> 1604 config CPU_R10000
>> 1605 bool "R10000"
>> 1606 depends on SYS_HAS_CPU_R10000
>> 1607 select CPU_HAS_PREFETCH
>> 1608 select CPU_SUPPORTS_32BIT_KERNEL
>> 1609 select CPU_SUPPORTS_64BIT_KERNEL
>> 1610 select CPU_SUPPORTS_HIGHMEM
>> 1611 select CPU_SUPPORTS_HUGEPAGES
>> 1612 help
>> 1613 MIPS Technologies R10000-series processors.
>> 1614
>> 1615 config CPU_RM7000
>> 1616 bool "RM7000"
>> 1617 depends on SYS_HAS_CPU_RM7000
>> 1618 select CPU_HAS_PREFETCH
>> 1619 select CPU_SUPPORTS_32BIT_KERNEL
>> 1620 select CPU_SUPPORTS_64BIT_KERNEL
>> 1621 select CPU_SUPPORTS_HIGHMEM
>> 1622 select CPU_SUPPORTS_HUGEPAGES
>> 1623
>> 1624 config CPU_SB1
>> 1625 bool "SB1"
>> 1626 depends on SYS_HAS_CPU_SB1
>> 1627 select CPU_SUPPORTS_32BIT_KERNEL
>> 1628 select CPU_SUPPORTS_64BIT_KERNEL
>> 1629 select CPU_SUPPORTS_HIGHMEM
>> 1630 select CPU_SUPPORTS_HUGEPAGES
>> 1631 select WEAK_ORDERING
>> 1632
>> 1633 config CPU_CAVIUM_OCTEON
>> 1634 bool "Cavium Octeon processor"
>> 1635 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1636 select CPU_HAS_PREFETCH
>> 1637 select CPU_SUPPORTS_64BIT_KERNEL
>> 1638 select HAVE_PAGE_SIZE_8KB if !MIPS_VA_BITS_48
>> 1639 select HAVE_PAGE_SIZE_32KB if !MIPS_VA_BITS_48
>> 1640 select WEAK_ORDERING
>> 1641 select CPU_SUPPORTS_HIGHMEM
>> 1642 select CPU_SUPPORTS_HUGEPAGES
>> 1643 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1644 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1645 select MIPS_L1_CACHE_SHIFT_7
>> 1646 select CPU_SUPPORTS_VZ
>> 1647 help
>> 1648 The Cavium Octeon processor is a highly integrated chip containing
>> 1649 many ethernet hardware widgets for networking tasks. The processor
>> 1650 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1651 Full details can be found at http://www.caviumnetworks.com.
>> 1652
>> 1653 config CPU_BMIPS
>> 1654 bool "Broadcom BMIPS"
>> 1655 depends on SYS_HAS_CPU_BMIPS
>> 1656 select CPU_MIPS32
>> 1657 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1658 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1659 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1660 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1661 select CPU_SUPPORTS_32BIT_KERNEL
>> 1662 select DMA_NONCOHERENT
>> 1663 select IRQ_MIPS_CPU
>> 1664 select SWAP_IO_SPACE
>> 1665 select WEAK_ORDERING
>> 1666 select CPU_SUPPORTS_HIGHMEM
>> 1667 select CPU_HAS_PREFETCH
>> 1668 select CPU_SUPPORTS_CPUFREQ
>> 1669 select MIPS_EXTERNAL_TIMER
>> 1670 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
140 help 1671 help
141 Select this variant to use a custom !! 1672 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
142 You will be prompted for a processor !! 1673
143 endchoice 1674 endchoice
144 1675
145 config XTENSA_VARIANT_CUSTOM_NAME !! 1676 config LOONGSON3_ENHANCEMENT
146 string "Xtensa Processor Custom Core V !! 1677 bool "New Loongson-3 CPU Enhancements"
147 depends on XTENSA_VARIANT_CUSTOM <<
148 help <<
149 Provide the name of a custom Xtensa <<
150 This CORENAME selects arch/xtensa/va <<
151 Don't forget you have to select MMU <<
152 <<
153 config XTENSA_VARIANT_NAME <<
154 string <<
155 default "dc232b" <<
156 default "dc233c" <<
157 default "fsf" <<
158 default XTENSA_VARIANT_CUSTOM_NAME <<
159 <<
160 config XTENSA_VARIANT_MMU <<
161 bool "Core variant has a Full MMU (TLB <<
162 depends on XTENSA_VARIANT_CUSTOM <<
163 default y <<
164 select MMU <<
165 help <<
166 Build a Conventional Kernel with ful <<
167 ie: it supports a TLB with auto-load <<
168 <<
169 config XTENSA_VARIANT_HAVE_PERF_EVENTS <<
170 bool "Core variant has Performance Mon <<
171 depends on XTENSA_VARIANT_CUSTOM <<
172 default n 1678 default n
>> 1679 depends on CPU_LOONGSON64
>> 1680 help
>> 1681 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
>> 1682 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
>> 1683 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
>> 1684 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
>> 1685 Fast TLB refill support, etc.
>> 1686
>> 1687 This option enable those enhancements which are not probed at run
>> 1688 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1689 please say 'N' here. If you want a high-performance kernel to run on
>> 1690 new Loongson-3 machines only, please say 'Y' here.
>> 1691
>> 1692 config CPU_LOONGSON3_WORKAROUNDS
>> 1693 bool "Loongson-3 LLSC Workarounds"
>> 1694 default y if SMP
>> 1695 depends on CPU_LOONGSON64
173 help 1696 help
174 Enable if core variant has Performan !! 1697 Loongson-3 processors have the llsc issues which require workarounds.
175 External Registers Interface. !! 1698 Without workarounds the system may hang unexpectedly.
176 1699
177 If unsure, say N. !! 1700 Say Y, unless you know what you are doing.
178 1701
179 config XTENSA_FAKE_NMI !! 1702 config CPU_LOONGSON3_CPUCFG_EMULATION
180 bool "Treat PMM IRQ as NMI" !! 1703 bool "Emulate the CPUCFG instruction on older Loongson cores"
181 depends on XTENSA_VARIANT_HAVE_PERF_EV !! 1704 default y
>> 1705 depends on CPU_LOONGSON64
>> 1706 help
>> 1707 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1708 userland to query CPU capabilities, much like CPUID on x86. This
>> 1709 option provides emulation of the instruction on older Loongson
>> 1710 cores, back to Loongson-3A1000.
>> 1711
>> 1712 If unsure, please say Y.
>> 1713
>> 1714 config CPU_MIPS32_3_5_FEATURES
>> 1715 bool "MIPS32 Release 3.5 Features"
>> 1716 depends on SYS_HAS_CPU_MIPS32_R3_5
>> 1717 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
>> 1718 CPU_P5600
>> 1719 help
>> 1720 Choose this option to build a kernel for release 2 or later of the
>> 1721 MIPS32 architecture including features from the 3.5 release such as
>> 1722 support for Enhanced Virtual Addressing (EVA).
>> 1723
>> 1724 config CPU_MIPS32_3_5_EVA
>> 1725 bool "Enhanced Virtual Addressing (EVA)"
>> 1726 depends on CPU_MIPS32_3_5_FEATURES
>> 1727 select EVA
>> 1728 default y
>> 1729 help
>> 1730 Choose this option if you want to enable the Enhanced Virtual
>> 1731 Addressing (EVA) on your MIPS32 core (such as proAptiv).
>> 1732 One of its primary benefits is an increase in the maximum size
>> 1733 of lowmem (up to 3GB). If unsure, say 'N' here.
>> 1734
>> 1735 config CPU_MIPS32_R5_FEATURES
>> 1736 bool "MIPS32 Release 5 Features"
>> 1737 depends on SYS_HAS_CPU_MIPS32_R5
>> 1738 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>> 1739 help
>> 1740 Choose this option to build a kernel for release 2 or later of the
>> 1741 MIPS32 architecture including features from release 5 such as
>> 1742 support for Extended Physical Addressing (XPA).
>> 1743
>> 1744 config CPU_MIPS32_R5_XPA
>> 1745 bool "Extended Physical Addressing (XPA)"
>> 1746 depends on CPU_MIPS32_R5_FEATURES
>> 1747 depends on !EVA
>> 1748 depends on !PAGE_SIZE_4KB
>> 1749 depends on SYS_SUPPORTS_HIGHMEM
>> 1750 select XPA
>> 1751 select HIGHMEM
>> 1752 select PHYS_ADDR_T_64BIT
182 default n 1753 default n
183 help 1754 help
184 If PMM IRQ is the only IRQ at EXCM l !! 1755 Choose this option if you want to enable the Extended Physical
185 treat it as NMI, which improves accu !! 1756 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1757 benefit is to increase physical addressing equal to or greater
>> 1758 than 40 bits. Note that this has the side effect of turning on
>> 1759 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1760 If unsure, say 'N' here.
186 1761
187 If there are other interrupts at or !! 1762 if CPU_LOONGSON2F
188 but not above the EXCM level, PMM IR !! 1763 config CPU_NOP_WORKAROUNDS
189 but only if these IRQs are not used. !! 1764 bool
190 saying that this is not safe, and a <<
191 actually fire. <<
192 1765
193 If unsure, say N. !! 1766 config CPU_JUMP_WORKAROUNDS
>> 1767 bool
194 1768
195 config PFAULT !! 1769 config CPU_LOONGSON2F_WORKAROUNDS
196 bool "Handle protection faults" if EXP !! 1770 bool "Loongson 2F Workarounds"
197 default y 1771 default y
>> 1772 select CPU_NOP_WORKAROUNDS
>> 1773 select CPU_JUMP_WORKAROUNDS
198 help 1774 help
199 Handle protection faults. MMU config !! 1775 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
200 noMMU configurations may disable it !! 1776 require workarounds. Without workarounds the system may hang
201 generates protection faults or fault !! 1777 unexpectedly. For more information please refer to the gas
>> 1778 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1779
>> 1780 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1781 are needed. The workarounds have no significant side effect on them
>> 1782 but may decrease the performance of the system so this option should
>> 1783 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1784 systems.
202 1785
203 If unsure, say Y. !! 1786 If unsure, please say Y.
>> 1787 endif # CPU_LOONGSON2F
>> 1788
>> 1789 config SYS_SUPPORTS_ZBOOT
>> 1790 bool
>> 1791 select HAVE_KERNEL_GZIP
>> 1792 select HAVE_KERNEL_BZIP2
>> 1793 select HAVE_KERNEL_LZ4
>> 1794 select HAVE_KERNEL_LZMA
>> 1795 select HAVE_KERNEL_LZO
>> 1796 select HAVE_KERNEL_XZ
>> 1797 select HAVE_KERNEL_ZSTD
>> 1798
>> 1799 config SYS_SUPPORTS_ZBOOT_UART16550
>> 1800 bool
>> 1801 select SYS_SUPPORTS_ZBOOT
>> 1802
>> 1803 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1804 bool
>> 1805 select SYS_SUPPORTS_ZBOOT
>> 1806
>> 1807 config CPU_LOONGSON2EF
>> 1808 bool
>> 1809 select CPU_SUPPORTS_32BIT_KERNEL
>> 1810 select CPU_SUPPORTS_64BIT_KERNEL
>> 1811 select CPU_SUPPORTS_HIGHMEM
>> 1812 select CPU_SUPPORTS_HUGEPAGES
>> 1813
>> 1814 config CPU_LOONGSON32
>> 1815 bool
>> 1816 select CPU_MIPS32
>> 1817 select CPU_MIPSR2
>> 1818 select CPU_HAS_PREFETCH
>> 1819 select CPU_SUPPORTS_32BIT_KERNEL
>> 1820 select CPU_SUPPORTS_HIGHMEM
>> 1821 select CPU_SUPPORTS_CPUFREQ
>> 1822
>> 1823 config CPU_BMIPS32_3300
>> 1824 select SMP_UP if SMP
>> 1825 bool
>> 1826
>> 1827 config CPU_BMIPS4350
>> 1828 bool
>> 1829 select SYS_SUPPORTS_SMP
>> 1830 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1831
>> 1832 config CPU_BMIPS4380
>> 1833 bool
>> 1834 select MIPS_L1_CACHE_SHIFT_6
>> 1835 select SYS_SUPPORTS_SMP
>> 1836 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1837 select CPU_HAS_RIXI
>> 1838
>> 1839 config CPU_BMIPS5000
>> 1840 bool
>> 1841 select MIPS_CPU_SCACHE
>> 1842 select MIPS_L1_CACHE_SHIFT_7
>> 1843 select SYS_SUPPORTS_SMP
>> 1844 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1845 select CPU_HAS_RIXI
>> 1846
>> 1847 config SYS_HAS_CPU_LOONGSON64
>> 1848 bool
>> 1849 select CPU_SUPPORTS_CPUFREQ
>> 1850 select CPU_HAS_RIXI
>> 1851
>> 1852 config SYS_HAS_CPU_LOONGSON2E
>> 1853 bool
>> 1854
>> 1855 config SYS_HAS_CPU_LOONGSON2F
>> 1856 bool
>> 1857 select CPU_SUPPORTS_CPUFREQ
>> 1858 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1859
>> 1860 config SYS_HAS_CPU_LOONGSON1B
>> 1861 bool
>> 1862
>> 1863 config SYS_HAS_CPU_LOONGSON1C
>> 1864 bool
>> 1865
>> 1866 config SYS_HAS_CPU_MIPS32_R1
>> 1867 bool
204 1868
205 config XTENSA_UNALIGNED_USER !! 1869 config SYS_HAS_CPU_MIPS32_R2
206 bool "Unaligned memory access in user !! 1870 bool
>> 1871
>> 1872 config SYS_HAS_CPU_MIPS32_R3_5
>> 1873 bool
>> 1874
>> 1875 config SYS_HAS_CPU_MIPS32_R5
>> 1876 bool
>> 1877
>> 1878 config SYS_HAS_CPU_MIPS32_R6
>> 1879 bool
>> 1880
>> 1881 config SYS_HAS_CPU_MIPS64_R1
>> 1882 bool
>> 1883
>> 1884 config SYS_HAS_CPU_MIPS64_R2
>> 1885 bool
>> 1886
>> 1887 config SYS_HAS_CPU_MIPS64_R5
>> 1888 bool
>> 1889
>> 1890 config SYS_HAS_CPU_MIPS64_R6
>> 1891 bool
>> 1892
>> 1893 config SYS_HAS_CPU_P5600
>> 1894 bool
>> 1895
>> 1896 config SYS_HAS_CPU_R3000
>> 1897 bool
>> 1898
>> 1899 config SYS_HAS_CPU_R4300
>> 1900 bool
>> 1901
>> 1902 config SYS_HAS_CPU_R4X00
>> 1903 bool
>> 1904
>> 1905 config SYS_HAS_CPU_TX49XX
>> 1906 bool
>> 1907
>> 1908 config SYS_HAS_CPU_R5000
>> 1909 bool
>> 1910
>> 1911 config SYS_HAS_CPU_R5500
>> 1912 bool
>> 1913
>> 1914 config SYS_HAS_CPU_NEVADA
>> 1915 bool
>> 1916
>> 1917 config SYS_HAS_CPU_R10000
>> 1918 bool
>> 1919
>> 1920 config SYS_HAS_CPU_RM7000
>> 1921 bool
>> 1922
>> 1923 config SYS_HAS_CPU_SB1
>> 1924 bool
>> 1925
>> 1926 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1927 bool
>> 1928
>> 1929 config SYS_HAS_CPU_BMIPS
>> 1930 bool
>> 1931
>> 1932 config SYS_HAS_CPU_BMIPS32_3300
>> 1933 bool
>> 1934 select SYS_HAS_CPU_BMIPS
>> 1935
>> 1936 config SYS_HAS_CPU_BMIPS4350
>> 1937 bool
>> 1938 select SYS_HAS_CPU_BMIPS
>> 1939
>> 1940 config SYS_HAS_CPU_BMIPS4380
>> 1941 bool
>> 1942 select SYS_HAS_CPU_BMIPS
>> 1943
>> 1944 config SYS_HAS_CPU_BMIPS5000
>> 1945 bool
>> 1946 select SYS_HAS_CPU_BMIPS
>> 1947
>> 1948 #
>> 1949 # CPU may reorder R->R, R->W, W->R, W->W
>> 1950 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1951 #
>> 1952 config WEAK_ORDERING
>> 1953 bool
>> 1954
>> 1955 #
>> 1956 # CPU may reorder reads and writes beyond LL/SC
>> 1957 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 1958 #
>> 1959 config WEAK_REORDERING_BEYOND_LLSC
>> 1960 bool
>> 1961 endmenu
>> 1962
>> 1963 #
>> 1964 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1965 #
>> 1966 config CPU_MIPS32
>> 1967 bool
>> 1968 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1969 CPU_MIPS32_R6 || CPU_P5600
>> 1970
>> 1971 config CPU_MIPS64
>> 1972 bool
>> 1973 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1974 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
>> 1975
>> 1976 #
>> 1977 # These indicate the revision of the architecture
>> 1978 #
>> 1979 config CPU_MIPSR1
>> 1980 bool
>> 1981 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 1982
>> 1983 config CPU_MIPSR2
>> 1984 bool
>> 1985 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 1986 select CPU_HAS_RIXI
>> 1987 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1988 select MIPS_SPRAM
>> 1989
>> 1990 config CPU_MIPSR5
>> 1991 bool
>> 1992 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 1993 select CPU_HAS_RIXI
>> 1994 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1995 select MIPS_SPRAM
>> 1996
>> 1997 config CPU_MIPSR6
>> 1998 bool
>> 1999 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 2000 select CPU_HAS_RIXI
>> 2001 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 2002 select HAVE_ARCH_BITREVERSE
>> 2003 select MIPS_ASID_BITS_VARIABLE
>> 2004 select MIPS_CRC_SUPPORT
>> 2005 select MIPS_SPRAM
>> 2006
>> 2007 config TARGET_ISA_REV
>> 2008 int
>> 2009 default 1 if CPU_MIPSR1
>> 2010 default 2 if CPU_MIPSR2
>> 2011 default 5 if CPU_MIPSR5
>> 2012 default 6 if CPU_MIPSR6
>> 2013 default 0
207 help 2014 help
208 The Xtensa architecture currently do !! 2015 Reflects the ISA revision being targeted by the kernel build. This
209 memory accesses in hardware but thro !! 2016 is effectively the Kconfig equivalent of MIPS_ISA_REV.
210 Per default, unaligned memory access !! 2017
>> 2018 config EVA
>> 2019 bool
>> 2020
>> 2021 config XPA
>> 2022 bool
>> 2023
>> 2024 config SYS_SUPPORTS_32BIT_KERNEL
>> 2025 bool
>> 2026 config SYS_SUPPORTS_64BIT_KERNEL
>> 2027 bool
>> 2028 config CPU_SUPPORTS_32BIT_KERNEL
>> 2029 bool
>> 2030 config CPU_SUPPORTS_64BIT_KERNEL
>> 2031 bool
>> 2032 config CPU_SUPPORTS_CPUFREQ
>> 2033 bool
>> 2034 config CPU_SUPPORTS_ADDRWINCFG
>> 2035 bool
>> 2036 config CPU_SUPPORTS_HUGEPAGES
>> 2037 bool
>> 2038 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 2039 config CPU_SUPPORTS_VZ
>> 2040 bool
>> 2041 config MIPS_PGD_C0_CONTEXT
>> 2042 bool
>> 2043 depends on 64BIT
>> 2044 default y if (CPU_MIPSR2 || CPU_MIPSR6)
211 2045
212 Say Y here to enable unaligned memor !! 2046 #
>> 2047 # Set to y for ptrace access to watch registers.
>> 2048 #
>> 2049 config HARDWARE_WATCHPOINTS
>> 2050 bool
>> 2051 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
>> 2052
>> 2053 menu "Kernel type"
213 2054
214 config XTENSA_LOAD_STORE !! 2055 choice
215 bool "Load/store exception handler for !! 2056 prompt "Kernel code model"
216 help 2057 help
217 The Xtensa architecture only allows !! 2058 You should only select this option if you have a workload that
218 instruction bus with l32r and l32i i !! 2059 actually benefits from 64-bit processing or if your machine has
219 instructions raise an exception with !! 2060 large memory. You will only be presented a single option in this
220 This makes it hard to use some confi !! 2061 menu if your system does not support both 32-bit and 64-bit kernels.
221 literals in FLASH memory attached to <<
222 2062
223 Say Y here to enable exception handl !! 2063 config 32BIT
224 byte and 2-byte access to memory att !! 2064 bool "32-bit kernel"
>> 2065 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2066 select TRAD_SIGNALS
>> 2067 help
>> 2068 Select this option if you want to build a 32-bit kernel.
225 2069
226 config HAVE_SMP !! 2070 config 64BIT
227 bool "System Supports SMP (MX)" !! 2071 bool "64-bit kernel"
228 depends on XTENSA_VARIANT_CUSTOM !! 2072 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
229 select XTENSA_MX <<
230 help 2073 help
231 This option is used to indicate that !! 2074 Select this option if you want to build a 64-bit kernel.
232 supports Multiprocessing. Multiproce <<
233 the CPU core definition and currentl <<
234 2075
235 Multiprocessor support is implemente !! 2076 endchoice
236 interrupt controllers. <<
237 2077
238 The MX interrupt distributer adds In !! 2078 config MIPS_VA_BITS_48
239 and causes the IRQ numbers to be inc !! 2079 bool "48 bits virtual memory"
240 like the open cores ethernet driver !! 2080 depends on 64BIT
>> 2081 help
>> 2082 Support a maximum at least 48 bits of application virtual
>> 2083 memory. Default is 40 bits or less, depending on the CPU.
>> 2084 For page sizes 16k and above, this option results in a small
>> 2085 memory overhead for page tables. For 4k page size, a fourth
>> 2086 level of page tables is added which imposes both a memory
>> 2087 overhead as well as slower TLB fault handling.
241 2088
242 You still have to select "Enable SMP !! 2089 If unsure, say N.
243 2090
244 config SMP !! 2091 config ZBOOT_LOAD_ADDRESS
245 bool "Enable Symmetric multi-processin !! 2092 hex "Compressed kernel load address"
246 depends on HAVE_SMP !! 2093 default 0xffffffff80400000 if BCM47XX
247 select GENERIC_SMP_IDLE_THREAD !! 2094 default 0x0
>> 2095 depends on SYS_SUPPORTS_ZBOOT
248 help 2096 help
249 Enabled SMP Software; allows more th !! 2097 The address to load compressed kernel, aka vmlinuz.
250 to be activated during startup. <<
251 2098
252 config NR_CPUS !! 2099 This is only used if non-zero.
253 depends on SMP <<
254 int "Maximum number of CPUs (2-32)" <<
255 range 2 32 <<
256 default "4" <<
257 2100
258 config HOTPLUG_CPU !! 2101 config ARCH_FORCE_MAX_ORDER
259 bool "Enable CPU hotplug support" !! 2102 int "Maximum zone order"
260 depends on SMP !! 2103 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2104 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2105 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2106 default "10"
261 help 2107 help
262 Say Y here to allow turning CPUs off !! 2108 The kernel memory allocator divides physically contiguous memory
263 controlled through /sys/devices/syst !! 2109 blocks into "zones", where each zone is a power of two number of
>> 2110 pages. This option selects the largest power of two that the kernel
>> 2111 keeps in the memory allocator. If you need to allocate very large
>> 2112 blocks of physically contiguous memory, then you may need to
>> 2113 increase this value.
264 2114
265 Say N if you want to disable CPU hot !! 2115 The page size is not necessarily 4KB. Keep this in mind
>> 2116 when choosing a value for this option.
266 2117
267 config SECONDARY_RESET_VECTOR !! 2118 config BOARD_SCACHE
268 bool "Secondary cores use alternative !! 2119 bool
269 default y !! 2120
270 depends on HAVE_SMP !! 2121 config IP22_CPU_SCACHE
>> 2122 bool
>> 2123 select BOARD_SCACHE
>> 2124
>> 2125 #
>> 2126 # Support for a MIPS32 / MIPS64 style S-caches
>> 2127 #
>> 2128 config MIPS_CPU_SCACHE
>> 2129 bool
>> 2130 select BOARD_SCACHE
>> 2131
>> 2132 config R5000_CPU_SCACHE
>> 2133 bool
>> 2134 select BOARD_SCACHE
>> 2135
>> 2136 config RM7000_CPU_SCACHE
>> 2137 bool
>> 2138 select BOARD_SCACHE
>> 2139
>> 2140 config SIBYTE_DMA_PAGEOPS
>> 2141 bool "Use DMA to clear/copy pages"
>> 2142 depends on CPU_SB1
271 help 2143 help
272 Secondary cores may be configured to !! 2144 Instead of using the CPU to zero and copy pages, use a Data Mover
273 or all cores may use primary reset v !! 2145 channel. These DMA channels are otherwise unused by the standard
274 Say Y here to supply handler for the !! 2146 SiByte Linux port. Seems to give a small performance benefit.
275 2147
276 config FAST_SYSCALL_XTENSA !! 2148 config CPU_HAS_PREFETCH
277 bool "Enable fast atomic syscalls" !! 2149 bool
278 default n !! 2150
>> 2151 config CPU_GENERIC_DUMP_TLB
>> 2152 bool
>> 2153 default y if !CPU_R3000
>> 2154
>> 2155 config MIPS_FP_SUPPORT
>> 2156 bool "Floating Point support" if EXPERT
>> 2157 default y
279 help 2158 help
280 fast_syscall_xtensa is a syscall tha !! 2159 Select y to include support for floating point in the kernel
281 on UP kernel when processor has no s !! 2160 including initialization of FPU hardware, FP context save & restore
>> 2161 and emulation of an FPU where necessary. Without this support any
>> 2162 userland program attempting to use floating point instructions will
>> 2163 receive a SIGILL.
282 2164
283 This syscall is deprecated. It may h !! 2165 If you know that your userland will not attempt to use floating point
284 invalid arguments. It is provided on !! 2166 instructions then you can say n here to shrink the kernel a little.
285 Only enable it if your userspace sof <<
286 2167
287 If unsure, say N. !! 2168 If unsure, say y.
288 2169
289 config FAST_SYSCALL_SPILL_REGISTERS !! 2170 config CPU_R2300_FPU
290 bool "Enable spill registers syscall" !! 2171 bool
>> 2172 depends on MIPS_FP_SUPPORT
>> 2173 default y if CPU_R3000
>> 2174
>> 2175 config CPU_R3K_TLB
>> 2176 bool
>> 2177
>> 2178 config CPU_R4K_FPU
>> 2179 bool
>> 2180 depends on MIPS_FP_SUPPORT
>> 2181 default y if !CPU_R2300_FPU
>> 2182
>> 2183 config CPU_R4K_CACHE_TLB
>> 2184 bool
>> 2185 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2186
>> 2187 config MIPS_MT_SMP
>> 2188 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2189 default y
>> 2190 depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6
>> 2191 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS
>> 2192 select CPU_MIPSR2_IRQ_VI
>> 2193 select CPU_MIPSR2_IRQ_EI
>> 2194 select SYNC_R4K
>> 2195 select MIPS_MT
>> 2196 select SMP
>> 2197 select SMP_UP
>> 2198 select SYS_SUPPORTS_SMP
>> 2199 select SYS_SUPPORTS_SCHED_SMT
>> 2200 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2201 help
>> 2202 This is a kernel model which is known as SMVP. This is supported
>> 2203 on cores with the MT ASE and uses the available VPEs to implement
>> 2204 virtual processors which supports SMP. This is equivalent to the
>> 2205 Intel Hyperthreading feature. For further information go to
>> 2206 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2207
>> 2208 config MIPS_MT
>> 2209 bool
>> 2210
>> 2211 config SCHED_SMT
>> 2212 bool "SMT (multithreading) scheduler support"
>> 2213 depends on SYS_SUPPORTS_SCHED_SMT
291 default n 2214 default n
292 help 2215 help
293 fast_syscall_spill_registers is a sy !! 2216 SMT scheduler support improves the CPU scheduler's decision making
294 register windows of a calling usersp !! 2217 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2218 increased overhead in some places. If unsure say N here.
295 2219
296 This syscall is deprecated. It may h !! 2220 config SYS_SUPPORTS_SCHED_SMT
297 invalid arguments. It is provided on !! 2221 bool
298 Only enable it if your userspace sof <<
299 2222
300 If unsure, say N. !! 2223 config SYS_SUPPORTS_MULTITHREADING
>> 2224 bool
301 2225
302 choice !! 2226 config MIPS_MT_FPAFF
303 prompt "Kernel ABI" !! 2227 bool "Dynamic FPU affinity for FP-intensive threads"
304 default KERNEL_ABI_DEFAULT !! 2228 default y
>> 2229 depends on MIPS_MT_SMP
>> 2230
>> 2231 config MIPSR2_TO_R6_EMULATOR
>> 2232 bool "MIPS R2-to-R6 emulator"
>> 2233 depends on CPU_MIPSR6
>> 2234 depends on MIPS_FP_SUPPORT
>> 2235 default y
305 help 2236 help
306 Select ABI for the kernel code. This !! 2237 Choose this option if you want to run non-R6 MIPS userland code.
307 supported userspace ABI and any comb !! 2238 Even if you say 'Y' here, the emulator will still be disabled by
308 kernel/userspace ABI is possible and !! 2239 default. You can enable it using the 'mipsr2emu' kernel option.
309 !! 2240 The only reason this is a build-time option is to save ~14K from the
310 In case both kernel and userspace su !! 2241 final kernel image.
311 all register windows support code wi <<
312 build. <<
313 <<
314 If unsure, choose the default ABI. <<
315 <<
316 config KERNEL_ABI_DEFAULT <<
317 bool "Default ABI" <<
318 help <<
319 Select this option to compile kernel <<
320 selected for the toolchain. <<
321 Normally cores with windowed registe <<
322 cores without it use call0 ABI. <<
323 <<
324 config KERNEL_ABI_CALL0 <<
325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI <<
326 help <<
327 Select this option to compile kernel <<
328 toolchain that defaults to windowed <<
329 When this option is not selected the <<
330 be used for the kernel code. <<
331 2242
332 endchoice !! 2243 config SYS_SUPPORTS_VPE_LOADER
>> 2244 bool
>> 2245 depends on SYS_SUPPORTS_MULTITHREADING
>> 2246 help
>> 2247 Indicates that the platform supports the VPE loader, and provides
>> 2248 physical_memsize.
333 2249
334 config USER_ABI_CALL0 !! 2250 config MIPS_VPE_LOADER
>> 2251 bool "VPE loader support."
>> 2252 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2253 select CPU_MIPSR2_IRQ_VI
>> 2254 select CPU_MIPSR2_IRQ_EI
>> 2255 select MIPS_MT
>> 2256 help
>> 2257 Includes a loader for loading an elf relocatable object
>> 2258 onto another VPE and running it.
>> 2259
>> 2260 config MIPS_VPE_LOADER_MT
335 bool 2261 bool
>> 2262 default "y"
>> 2263 depends on MIPS_VPE_LOADER
336 2264
337 choice !! 2265 config MIPS_VPE_LOADER_TOM
338 prompt "Userspace ABI" !! 2266 bool "Load VPE program into memory hidden from linux"
339 default USER_ABI_DEFAULT !! 2267 depends on MIPS_VPE_LOADER
>> 2268 default y
340 help 2269 help
341 Select supported userspace ABI. !! 2270 The loader can use memory that is present but has been hidden from
>> 2271 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2272 you to ensure the amount you put in the option and the space your
>> 2273 program requires is less or equal to the amount physically present.
>> 2274
>> 2275 config MIPS_VPE_APSP_API
>> 2276 bool "Enable support for AP/SP API (RTLX)"
>> 2277 depends on MIPS_VPE_LOADER
>> 2278
>> 2279 config MIPS_VPE_APSP_API_MT
>> 2280 bool
>> 2281 default "y"
>> 2282 depends on MIPS_VPE_APSP_API
342 2283
343 If unsure, choose the default ABI. !! 2284 config MIPS_CPS
>> 2285 bool "MIPS Coherent Processing System support"
>> 2286 depends on SYS_SUPPORTS_MIPS_CPS
>> 2287 select MIPS_CM
>> 2288 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2289 select SMP
>> 2290 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
>> 2291 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2292 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2293 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2294 select SYS_SUPPORTS_SMP
>> 2295 select WEAK_ORDERING
>> 2296 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2297 help
>> 2298 Select this if you wish to run an SMP kernel across multiple cores
>> 2299 within a MIPS Coherent Processing System. When this option is
>> 2300 enabled the kernel will probe for other cores and boot them with
>> 2301 no external assistance. It is safe to enable this when hardware
>> 2302 support is unavailable.
>> 2303
>> 2304 config MIPS_CPS_PM
>> 2305 depends on MIPS_CPS
>> 2306 bool
344 2307
345 config USER_ABI_DEFAULT !! 2308 config MIPS_CM
346 bool "Default ABI only" !! 2309 bool
>> 2310 select MIPS_CPC
>> 2311
>> 2312 config MIPS_CPC
>> 2313 bool
>> 2314
>> 2315 config SB1_PASS_2_WORKAROUNDS
>> 2316 bool
>> 2317 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2318 default y
>> 2319
>> 2320 config SB1_PASS_2_1_WORKAROUNDS
>> 2321 bool
>> 2322 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2323 default y
>> 2324
>> 2325 choice
>> 2326 prompt "SmartMIPS or microMIPS ASE support"
>> 2327
>> 2328 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
>> 2329 bool "None"
347 help 2330 help
348 Assume default userspace ABI. For XE !! 2331 Select this if you want neither microMIPS nor SmartMIPS support
349 call0 ABI binaries may be run on suc <<
350 will not work correctly for them. <<
351 2332
352 config USER_ABI_CALL0_ONLY !! 2333 config CPU_HAS_SMARTMIPS
353 bool "Call0 ABI only" !! 2334 depends on SYS_SUPPORTS_SMARTMIPS
354 select USER_ABI_CALL0 !! 2335 bool "SmartMIPS"
>> 2336 help
>> 2337 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2338 increased security at both hardware and software level for
>> 2339 smartcards. Enabling this option will allow proper use of the
>> 2340 SmartMIPS instructions by Linux applications. However a kernel with
>> 2341 this option will not work on a MIPS core without SmartMIPS core. If
>> 2342 you don't know you probably don't have SmartMIPS and should say N
>> 2343 here.
>> 2344
>> 2345 config CPU_MICROMIPS
>> 2346 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2347 bool "microMIPS"
355 help 2348 help
356 Select this option to support only c !! 2349 When this option is enabled the kernel will be built using the
357 Windowed ABI binaries will crash wit !! 2350 microMIPS ISA
358 an illegal instruction exception on <<
359 2351
360 Choose this option if you're plannin !! 2352 endchoice
361 built with call0 ABI. <<
362 2353
363 config USER_ABI_CALL0_PROBE !! 2354 config CPU_HAS_MSA
364 bool "Support both windowed and call0 !! 2355 bool "Support for the MIPS SIMD Architecture"
365 select USER_ABI_CALL0 !! 2356 depends on CPU_SUPPORTS_MSA
366 help !! 2357 depends on MIPS_FP_SUPPORT
367 Select this option to support both w !! 2358 depends on 64BIT || MIPS_O32_FP64_SUPPORT
368 ABIs. When enabled all processes are !! 2359 help
369 and a fast user exception handler fo !! 2360 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
370 used to turn on PS.WOE bit on the fi !! 2361 and a set of SIMD instructions to operate on them. When this option
371 the userspace. !! 2362 is enabled the kernel will support allocating & switching MSA
>> 2363 vector register contexts. If you know that your kernel will only be
>> 2364 running on CPUs which do not support MSA or that your userland will
>> 2365 not be making use of it then you may wish to say N here to reduce
>> 2366 the size & complexity of your kernel.
372 2367
373 This option should be enabled for th !! 2368 If unsure, say Y.
374 both call0 and windowed ABIs in user <<
375 2369
376 Note that Xtensa ISA does not guaran !! 2370 config CPU_HAS_WB
377 raise an illegal instruction excepti !! 2371 bool
378 PS.WOE is disabled, check whether th <<
379 2372
380 endchoice !! 2373 config XKS01
>> 2374 bool
381 2375
382 endmenu !! 2376 config CPU_HAS_DIEI
>> 2377 depends on !CPU_DIEI_BROKEN
>> 2378 bool
383 2379
384 config XTENSA_CALIBRATE_CCOUNT !! 2380 config CPU_DIEI_BROKEN
385 def_bool n !! 2381 bool
>> 2382
>> 2383 config CPU_HAS_RIXI
>> 2384 bool
>> 2385
>> 2386 config CPU_NO_LOAD_STORE_LR
>> 2387 bool
386 help 2388 help
387 On some platforms (XT2000, for examp !! 2389 CPU lacks support for unaligned load and store instructions:
388 vary. The frequency can be determin !! 2390 LWL, LWR, SWL, SWR (Load/store word left/right).
389 against a well known, fixed frequenc !! 2391 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2392 systems).
>> 2393
>> 2394 #
>> 2395 # Vectored interrupt mode is an R2 feature
>> 2396 #
>> 2397 config CPU_MIPSR2_IRQ_VI
>> 2398 bool
390 2399
391 config SERIAL_CONSOLE !! 2400 #
392 def_bool n !! 2401 # Extended interrupt mode is an R2 feature
>> 2402 #
>> 2403 config CPU_MIPSR2_IRQ_EI
>> 2404 bool
393 2405
394 config PLATFORM_HAVE_XIP !! 2406 config CPU_HAS_SYNC
395 def_bool n !! 2407 bool
>> 2408 depends on !CPU_R3000
>> 2409 default y
396 2410
397 menu "Platform options" !! 2411 #
>> 2412 # CPU non-features
>> 2413 #
>> 2414
>> 2415 # Work around the "daddi" and "daddiu" CPU errata:
>> 2416 #
>> 2417 # - The `daddi' instruction fails to trap on overflow.
>> 2418 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2419 # erratum #23
>> 2420 #
>> 2421 # - The `daddiu' instruction can produce an incorrect result.
>> 2422 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2423 # erratum #41
>> 2424 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2425 # #15
>> 2426 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2427 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2428 config CPU_DADDI_WORKAROUNDS
>> 2429 bool
398 2430
399 choice !! 2431 # Work around certain R4000 CPU errata (as implemented by GCC):
400 prompt "Xtensa System Type" !! 2432 #
401 default XTENSA_PLATFORM_ISS !! 2433 # - A double-word or a variable shift may give an incorrect result
>> 2434 # if executed immediately after starting an integer division:
>> 2435 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2436 # erratum #28
>> 2437 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2438 # #19
>> 2439 #
>> 2440 # - A double-word or a variable shift may give an incorrect result
>> 2441 # if executed while an integer multiplication is in progress:
>> 2442 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2443 # errata #16 & #28
>> 2444 #
>> 2445 # - An integer division may give an incorrect result if started in
>> 2446 # a delay slot of a taken branch or a jump:
>> 2447 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2448 # erratum #52
>> 2449 config CPU_R4000_WORKAROUNDS
>> 2450 bool
>> 2451 select CPU_R4400_WORKAROUNDS
402 2452
403 config XTENSA_PLATFORM_ISS !! 2453 # Work around certain R4400 CPU errata (as implemented by GCC):
404 bool "ISS" !! 2454 #
405 select XTENSA_CALIBRATE_CCOUNT !! 2455 # - A double-word or a variable shift may give an incorrect result
406 select SERIAL_CONSOLE !! 2456 # if executed immediately after starting an integer division:
407 help !! 2457 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
408 ISS is an acronym for Tensilica's In !! 2458 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
409 !! 2459 config CPU_R4400_WORKAROUNDS
410 config XTENSA_PLATFORM_XT2000 !! 2460 bool
411 bool "XT2000" <<
412 help <<
413 XT2000 is the name of Tensilica's fe <<
414 This hardware is capable of running <<
415 <<
416 config XTENSA_PLATFORM_XTFPGA <<
417 bool "XTFPGA" <<
418 select ETHOC if ETHERNET <<
419 select PLATFORM_WANT_DEFAULT_MEM if !M <<
420 select SERIAL_CONSOLE <<
421 select XTENSA_CALIBRATE_CCOUNT <<
422 select PLATFORM_HAVE_XIP <<
423 help <<
424 XTFPGA is the name of Tensilica boar <<
425 This hardware is capable of running <<
426 2461
427 endchoice !! 2462 config CPU_R4X00_BUGS64
>> 2463 bool
>> 2464 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
428 2465
429 config PLATFORM_NR_IRQS !! 2466 config MIPS_ASID_SHIFT
430 int 2467 int
431 default 3 if XTENSA_PLATFORM_XT2000 !! 2468 default 6 if CPU_R3000
432 default 0 2469 default 0
433 2470
434 config XTENSA_CPU_CLOCK !! 2471 config MIPS_ASID_BITS
435 int "CPU clock rate [MHz]" !! 2472 int
436 depends on !XTENSA_CALIBRATE_CCOUNT !! 2473 default 0 if MIPS_ASID_BITS_VARIABLE
437 default 16 !! 2474 default 6 if CPU_R3000
>> 2475 default 8
438 2476
439 config GENERIC_CALIBRATE_DELAY !! 2477 config MIPS_ASID_BITS_VARIABLE
440 bool "Auto calibration of the BogoMIPS !! 2478 bool
441 help <<
442 The BogoMIPS value can easily be der <<
443 2479
444 config CMDLINE_BOOL !! 2480 config MIPS_CRC_SUPPORT
445 bool "Default bootloader kernel argume !! 2481 bool
446 2482
447 config CMDLINE !! 2483 # R4600 erratum. Due to the lack of errata information the exact
448 string "Initial kernel command string" !! 2484 # technical details aren't known. I've experimentally found that disabling
449 depends on CMDLINE_BOOL !! 2485 # interrupts during indexed I-cache flushes seems to be sufficient to deal
450 default "console=ttyS0,38400 root=/dev !! 2486 # with the issue.
451 help !! 2487 config WAR_R4600_V1_INDEX_ICACHEOP
452 On some architectures (EBSA110 and C !! 2488 bool
453 for the boot loader to pass argument <<
454 architectures, you should supply som <<
455 time by entering them here. As a min <<
456 memory size and the root device (e.g <<
457 2489
458 config USE_OF !! 2490 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
459 bool "Flattened Device Tree support" !! 2491 #
460 select OF !! 2492 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
461 select OF_EARLY_FLATTREE !! 2493 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
462 help !! 2494 # executed if there is no other dcache activity. If the dcache is
463 Include support for flattened device !! 2495 # accessed for another instruction immediately preceding when these
>> 2496 # cache instructions are executing, it is possible that the dcache
>> 2497 # tag match outputs used by these cache instructions will be
>> 2498 # incorrect. These cache instructions should be preceded by at least
>> 2499 # four instructions that are not any kind of load or store
>> 2500 # instruction.
>> 2501 #
>> 2502 # This is not allowed: lw
>> 2503 # nop
>> 2504 # nop
>> 2505 # nop
>> 2506 # cache Hit_Writeback_Invalidate_D
>> 2507 #
>> 2508 # This is allowed: lw
>> 2509 # nop
>> 2510 # nop
>> 2511 # nop
>> 2512 # nop
>> 2513 # cache Hit_Writeback_Invalidate_D
>> 2514 config WAR_R4600_V1_HIT_CACHEOP
>> 2515 bool
464 2516
465 config BUILTIN_DTB_SOURCE !! 2517 # Writeback and invalidate the primary cache dcache before DMA.
466 string "DTB to build into the kernel i !! 2518 #
467 depends on OF !! 2519 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2520 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2521 # operate correctly if the internal data cache refill buffer is empty. These
>> 2522 # CACHE instructions should be separated from any potential data cache miss
>> 2523 # by a load instruction to an uncached address to empty the response buffer."
>> 2524 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2525 # in .pdf format.)
>> 2526 config WAR_R4600_V2_HIT_CACHEOP
>> 2527 bool
468 2528
469 config PARSE_BOOTPARAM !! 2529 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
470 bool "Parse bootparam block" !! 2530 # the line which this instruction itself exists, the following
471 default y !! 2531 # operation is not guaranteed."
472 help !! 2532 #
473 Parse parameters passed to the kerne !! 2533 # Workaround: do two phase flushing for Index_Invalidate_I
474 be disabled if the kernel is known t !! 2534 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2535 bool
475 2536
476 If unsure, say Y. !! 2537 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2538 # opposes it being called that) where invalid instructions in the same
>> 2539 # I-cache line worth of instructions being fetched may case spurious
>> 2540 # exceptions.
>> 2541 config WAR_ICACHE_REFILLS
>> 2542 bool
477 2543
478 choice !! 2544 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
479 prompt "Semihosting interface" !! 2545 # may cause ll / sc and lld / scd sequences to execute non-atomically.
480 default XTENSA_SIMCALL_ISS !! 2546 config WAR_R10000_LLSC
481 depends on XTENSA_PLATFORM_ISS !! 2547 bool
482 help <<
483 Choose semihosting interface that wi <<
484 block device and networking. <<
485 2548
486 config XTENSA_SIMCALL_ISS !! 2549 # 34K core erratum: "Problems Executing the TLBR Instruction"
487 bool "simcall" !! 2550 config WAR_MIPS34K_MISSED_ITLB
488 help !! 2551 bool
489 Use simcall instruction. simcall is !! 2552
490 it does nothing on hardware. !! 2553 #
>> 2554 # - Highmem only makes sense for the 32-bit kernel.
>> 2555 # - The current highmem code will only work properly on physically indexed
>> 2556 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2557 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2558 # moment we protect the user and offer the highmem option only on machines
>> 2559 # where it's known to be safe. This will not offer highmem on a few systems
>> 2560 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2561 # indexed CPUs but we're playing safe.
>> 2562 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2563 # know they might have memory configurations that could make use of highmem
>> 2564 # support.
>> 2565 #
>> 2566 config HIGHMEM
>> 2567 bool "High Memory Support"
>> 2568 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2569 select KMAP_LOCAL
491 2570
492 config XTENSA_SIMCALL_GDBIO !! 2571 config CPU_SUPPORTS_HIGHMEM
493 bool "GDBIO" !! 2572 bool
>> 2573
>> 2574 config SYS_SUPPORTS_HIGHMEM
>> 2575 bool
>> 2576
>> 2577 config SYS_SUPPORTS_SMARTMIPS
>> 2578 bool
>> 2579
>> 2580 config SYS_SUPPORTS_MICROMIPS
>> 2581 bool
>> 2582
>> 2583 config SYS_SUPPORTS_MIPS16
>> 2584 bool
494 help 2585 help
495 Use break instruction. It is availab !! 2586 This option must be set if a kernel might be executed on a MIPS16-
496 is attached to it via JTAG. !! 2587 enabled CPU even if MIPS16 is not actually being used. In other
>> 2588 words, it makes the kernel MIPS16-tolerant.
497 2589
498 endchoice !! 2590 config CPU_SUPPORTS_MSA
>> 2591 bool
499 2592
500 config BLK_DEV_SIMDISK !! 2593 config ARCH_FLATMEM_ENABLE
501 tristate "Host file-based simulated bl !! 2594 def_bool y
502 default n !! 2595 depends on !NUMA && !CPU_LOONGSON2EF
503 depends on XTENSA_PLATFORM_ISS && BLOC !! 2596
>> 2597 config ARCH_SPARSEMEM_ENABLE
>> 2598 bool
>> 2599
>> 2600 config NUMA
>> 2601 bool "NUMA Support"
>> 2602 depends on SYS_SUPPORTS_NUMA
>> 2603 select SMP
>> 2604 select HAVE_SETUP_PER_CPU_AREA
>> 2605 select NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2606 help
>> 2607 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2608 Access). This option improves performance on systems with more
>> 2609 than two nodes; on two node systems it is generally better to
>> 2610 leave it disabled; on single node systems leave this option
>> 2611 disabled.
>> 2612
>> 2613 config SYS_SUPPORTS_NUMA
>> 2614 bool
>> 2615
>> 2616 config HAVE_ARCH_NODEDATA_EXTENSION
>> 2617 bool
>> 2618
>> 2619 config RELOCATABLE
>> 2620 bool "Relocatable kernel"
>> 2621 depends on SYS_SUPPORTS_RELOCATABLE
>> 2622 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2623 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2624 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2625 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2626 CPU_LOONGSON64
>> 2627 help
>> 2628 This builds a kernel image that retains relocation information
>> 2629 so it can be loaded someplace besides the default 1MB.
>> 2630 The relocations make the kernel binary about 15% larger,
>> 2631 but are discarded at runtime
>> 2632
>> 2633 config RELOCATION_TABLE_SIZE
>> 2634 hex "Relocation table size"
>> 2635 depends on RELOCATABLE
>> 2636 range 0x0 0x01000000
>> 2637 default "0x00200000" if CPU_LOONGSON64
>> 2638 default "0x00100000"
>> 2639 help
>> 2640 A table of relocation data will be appended to the kernel binary
>> 2641 and parsed at boot to fix up the relocated kernel.
>> 2642
>> 2643 This option allows the amount of space reserved for the table to be
>> 2644 adjusted, although the default of 1Mb should be ok in most cases.
>> 2645
>> 2646 The build will fail and a valid size suggested if this is too small.
>> 2647
>> 2648 If unsure, leave at the default value.
>> 2649
>> 2650 config RANDOMIZE_BASE
>> 2651 bool "Randomize the address of the kernel image"
>> 2652 depends on RELOCATABLE
>> 2653 help
>> 2654 Randomizes the physical and virtual address at which the
>> 2655 kernel image is loaded, as a security feature that
>> 2656 deters exploit attempts relying on knowledge of the location
>> 2657 of kernel internals.
>> 2658
>> 2659 Entropy is generated using any coprocessor 0 registers available.
>> 2660
>> 2661 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2662
>> 2663 If unsure, say N.
>> 2664
>> 2665 config RANDOMIZE_BASE_MAX_OFFSET
>> 2666 hex "Maximum kASLR offset" if EXPERT
>> 2667 depends on RANDOMIZE_BASE
>> 2668 range 0x0 0x40000000 if EVA || 64BIT
>> 2669 range 0x0 0x08000000
>> 2670 default "0x01000000"
>> 2671 help
>> 2672 When kASLR is active, this provides the maximum offset that will
>> 2673 be applied to the kernel image. It should be set according to the
>> 2674 amount of physical RAM available in the target system minus
>> 2675 PHYSICAL_START and must be a power of 2.
>> 2676
>> 2677 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2678 EVA or 64-bit. The default is 16Mb.
>> 2679
>> 2680 config NODES_SHIFT
>> 2681 int
>> 2682 default "6"
>> 2683 depends on NUMA
>> 2684
>> 2685 config HW_PERF_EVENTS
>> 2686 bool "Enable hardware performance counter support for perf events"
>> 2687 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
>> 2688 default y
504 help 2689 help
505 Create block devices that map to fil !! 2690 Enable hardware performance counter support for perf events. If
506 Device binding to host file may be c !! 2691 disabled, perf events will use software events only.
507 interface provided the device is not !! 2692
508 !! 2693 config DMI
509 config BLK_DEV_SIMDISK_COUNT !! 2694 bool "Enable DMI scanning"
510 int "Number of host file-based simulat !! 2695 depends on MACH_LOONGSON64
511 range 1 10 !! 2696 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
512 depends on BLK_DEV_SIMDISK !! 2697 default y
513 default 2 <<
514 help 2698 help
515 This is the default minimal number o !! 2699 Enabled scanning of DMI to identify machine quirks. Say Y
516 Kernel/module parameter 'simdisk_cou !! 2700 here unless you have verified that your setup is not
517 value at runtime. More file names (b !! 2701 affected by entries in the DMI blacklist. Required by PNP
518 specified as parameters, simdisk_cou !! 2702 BIOS code.
519 !! 2703
520 config SIMDISK0_FILENAME !! 2704 config SMP
521 string "Host filename for the first si !! 2705 bool "Multi-Processing support"
522 depends on BLK_DEV_SIMDISK = y !! 2706 depends on SYS_SUPPORTS_SMP
523 default "" <<
524 help <<
525 Attach a first simdisk to a host fil <<
526 contains a root file system. <<
527 <<
528 config SIMDISK1_FILENAME <<
529 string "Host filename for the second s <<
530 depends on BLK_DEV_SIMDISK = y && BLK_ <<
531 default "" <<
532 help <<
533 Another simulated disk in a host fil <<
534 storage. <<
535 <<
536 config XTFPGA_LCD <<
537 bool "Enable XTFPGA LCD driver" <<
538 depends on XTENSA_PLATFORM_XTFPGA <<
539 default n <<
540 help 2707 help
541 There's a 2x16 LCD on most of XTFPGA !! 2708 This enables support for systems with more than one CPU. If you have
542 progress messages there during bootu !! 2709 a system with only one CPU, say N. If you have a system with more
543 during board bringup. !! 2710 than one CPU, say Y.
>> 2711
>> 2712 If you say N here, the kernel will run on uni- and multiprocessor
>> 2713 machines, but will use only one CPU of a multiprocessor machine. If
>> 2714 you say Y here, the kernel will run on many, but not all,
>> 2715 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2716 will run faster if you say N here.
544 2717
545 If unsure, say N. !! 2718 People using multiprocessor machines who say Y here should also say
>> 2719 Y to "Enhanced Real Time Clock Support", below.
546 2720
547 config XTFPGA_LCD_BASE_ADDR !! 2721 See also the SMP-HOWTO available at
548 hex "XTFPGA LCD base address" !! 2722 <https://www.tldp.org/docs.html#howto>.
549 depends on XTFPGA_LCD !! 2723
550 default "0x0d0c0000" !! 2724 If you don't know what to do here, say N.
551 help !! 2725
552 Base address of the LCD controller i !! 2726 config HOTPLUG_CPU
553 Different boards from XTFPGA family !! 2727 bool "Support for hot-pluggable CPUs"
554 addresses. Please consult prototypin !! 2728 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
555 the correct address. Wrong address h <<
556 <<
557 config XTFPGA_LCD_8BIT_ACCESS <<
558 bool "Use 8-bit access to XTFPGA LCD" <<
559 depends on XTFPGA_LCD <<
560 default n <<
561 help 2729 help
562 LCD may be connected with 4- or 8-bi !! 2730 Say Y here to allow turning CPUs off and on. CPUs can be
563 only be used with 8-bit interface. P !! 2731 controlled through /sys/devices/system/cpu.
564 guide for your board for the correct !! 2732 (Note: power management support will enable this option
565 !! 2733 automatically on SMP systems. )
566 comment "Kernel memory layout" !! 2734 Say N if you want to disable CPU hotplug.
567 <<
568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX <<
569 bool "Initialize Xtensa MMU inside the <<
570 depends on !XTENSA_VARIANT_FSF && !XTE <<
571 default y if XTENSA_VARIANT_DC233C || <<
572 help <<
573 Earlier version initialized the MMU <<
574 before jumping to _startup in head.S <<
575 it was possible to place a software <<
576 then enter your normal kernel breakp <<
577 to the kernel mappings (0XC0000000). <<
578 <<
579 This unfortunately won't work for U- <<
580 work for using KEXEC to have a hot k <<
581 KDUMP. <<
582 <<
583 So now the MMU is initialized in hea <<
584 use hardware breakpoints (gdb 'hbrea <<
585 xt-gdb can't place a Software Breakp <<
586 to mapping the MMU and after mapping <<
587 was mapped gdb wouldn't remove the b <<
588 PC wouldn't match. Since Hardware Br <<
589 Linux configurations it seems reason <<
590 and leave this older mechanism for u <<
591 not to follow Tensilica's recommenda <<
592 <<
593 Selecting this will cause U-Boot to <<
594 address at 0x00003000 instead of the <<
595 <<
596 If in doubt, say Y. <<
597 <<
598 config XIP_KERNEL <<
599 bool "Kernel Execute-In-Place from ROM <<
600 depends on PLATFORM_HAVE_XIP <<
601 help <<
602 Execute-In-Place allows the kernel t <<
603 directly addressable by the CPU, suc <<
604 space since the text section of the <<
605 to RAM. Read-write sections, such as <<
606 are still copied to RAM. The XIP ker <<
607 it has to run directly from flash, s <<
608 store it. The flash address used to <<
609 and for storing it, is configuration <<
610 say Y here, you must know the proper <<
611 store the kernel image depending on <<
612 <<
613 Also note that the make target becom <<
614 "make Image" or "make uImage". The f <<
615 ROM memory will be arch/xtensa/boot/ <<
616 2735
617 If unsure, say N. !! 2736 config SMP_UP
>> 2737 bool
>> 2738
>> 2739 config SYS_SUPPORTS_MIPS_CPS
>> 2740 bool
>> 2741
>> 2742 config SYS_SUPPORTS_SMP
>> 2743 bool
>> 2744
>> 2745 config NR_CPUS_DEFAULT_4
>> 2746 bool
>> 2747
>> 2748 config NR_CPUS_DEFAULT_8
>> 2749 bool
>> 2750
>> 2751 config NR_CPUS_DEFAULT_16
>> 2752 bool
>> 2753
>> 2754 config NR_CPUS_DEFAULT_32
>> 2755 bool
>> 2756
>> 2757 config NR_CPUS_DEFAULT_64
>> 2758 bool
618 2759
619 config MEMMAP_CACHEATTR !! 2760 config NR_CPUS
620 hex "Cache attributes for the memory a !! 2761 int "Maximum number of CPUs (2-256)"
621 depends on !MMU !! 2762 range 2 256
622 default 0x22222222 !! 2763 depends on SMP
623 help !! 2764 default "4" if NR_CPUS_DEFAULT_4
624 These cache attributes are set up fo !! 2765 default "8" if NR_CPUS_DEFAULT_8
625 specifies cache attributes for the c !! 2766 default "16" if NR_CPUS_DEFAULT_16
626 region: bits 0..3 -- for addresses 0 !! 2767 default "32" if NR_CPUS_DEFAULT_32
627 bits 4..7 -- for addresses 0x2000000 !! 2768 default "64" if NR_CPUS_DEFAULT_64
628 !! 2769 help
629 Cache attribute values are specific !! 2770 This allows you to specify the maximum number of CPUs which this
630 For region protection MMUs: !! 2771 kernel will support. The maximum supported value is 32 for 32-bit
631 1: WT cached, !! 2772 kernel and 64 for 64-bit kernels; the minimum value which makes
632 2: cache bypass, !! 2773 sense is 1 for Qemu (useful only for kernel debugging purposes)
633 4: WB cached, !! 2774 and 2 for all others.
634 f: illegal. !! 2775
635 For full MMU: !! 2776 This is purely to save memory - each supported CPU adds
636 bit 0: executable, !! 2777 approximately eight kilobytes to the kernel image. For best
637 bit 1: writable, !! 2778 performance should round up your number of processors to the next
638 bits 2..3: !! 2779 power of two.
639 0: cache bypass, !! 2780
640 1: WB cache, !! 2781 config MIPS_PERF_SHARED_TC_COUNTERS
641 2: WT cache, !! 2782 bool
642 3: special (c and e are illegal, !! 2783
643 For MPU: !! 2784 config MIPS_NR_CPU_NR_MAP_1024
644 0: illegal, !! 2785 bool
645 1: WB cache, <<
646 2: WB, no-write-allocate cache, <<
647 3: WT cache, <<
648 4: cache bypass. <<
649 <<
650 config KSEG_PADDR <<
651 hex "Physical address of the KSEG mapp <<
652 depends on INITIALIZE_XTENSA_MMU_INSID <<
653 default 0x00000000 <<
654 help <<
655 This is the physical address where K <<
656 the chosen KSEG layout help for the <<
657 Unpacked kernel image (including vec <<
658 within KSEG. <<
659 Physical memory below this address i <<
660 <<
661 If unsure, leave the default value h <<
662 <<
663 config KERNEL_VIRTUAL_ADDRESS <<
664 hex "Kernel virtual address" <<
665 depends on MMU && XIP_KERNEL <<
666 default 0xd0003000 <<
667 help <<
668 This is the virtual address where th <<
669 XIP kernel may be mapped into KSEG o <<
670 provided here must match kernel load <<
671 KERNEL_LOAD_ADDRESS. <<
672 <<
673 config KERNEL_LOAD_ADDRESS <<
674 hex "Kernel load address" <<
675 default 0x60003000 if !MMU <<
676 default 0x00003000 if MMU && INITIALIZ <<
677 default 0xd0003000 if MMU && !INITIALI <<
678 help <<
679 This is the address where the kernel <<
680 It is virtual address for MMUv2 conf <<
681 for all other configurations. <<
682 2786
683 If unsure, leave the default value h !! 2787 config MIPS_NR_CPU_NR_MAP
>> 2788 int
>> 2789 depends on SMP
>> 2790 default 1024 if MIPS_NR_CPU_NR_MAP_1024
>> 2791 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
>> 2792
>> 2793 #
>> 2794 # Timer Interrupt Frequency Configuration
>> 2795 #
684 2796
685 choice 2797 choice
686 prompt "Relocatable vectors location" !! 2798 prompt "Timer frequency"
687 default XTENSA_VECTORS_IN_TEXT !! 2799 default HZ_250
688 help 2800 help
689 Choose whether relocatable vectors a !! 2801 Allows the configuration of the timer frequency.
690 or placed separately at runtime. Thi !! 2802
691 configurations without VECBASE regis !! 2803 config HZ_24
692 placed at their hardware-defined loc !! 2804 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
693 !! 2805
694 config XTENSA_VECTORS_IN_TEXT !! 2806 config HZ_48
695 bool "Merge relocatable vectors into k !! 2807 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
696 depends on !MTD_XIP !! 2808
697 help !! 2809 config HZ_100
698 This option puts relocatable vectors !! 2810 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
699 with proper alignment. !! 2811
700 This is a safe choice for most confi !! 2812 config HZ_128
701 !! 2813 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
702 config XTENSA_VECTORS_SEPARATE !! 2814
703 bool "Put relocatable vectors at fixed !! 2815 config HZ_250
704 help !! 2816 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
705 This option puts relocatable vectors !! 2817
706 Vectors are merged with the .init da !! 2818 config HZ_256
707 are copied into their designated loc !! 2819 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
708 Use it to put vectors into IRAM or o !! 2820
709 XIP-aware MTD support. !! 2821 config HZ_1000
>> 2822 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2823
>> 2824 config HZ_1024
>> 2825 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
710 2826
711 endchoice 2827 endchoice
712 2828
713 config VECTORS_ADDR !! 2829 config SYS_SUPPORTS_24HZ
714 hex "Kernel vectors virtual address" !! 2830 bool
715 default 0x00000000 <<
716 depends on XTENSA_VECTORS_SEPARATE <<
717 help <<
718 This is the virtual address of the ( <<
719 It must be within KSEG if MMU is use <<
720 <<
721 config XIP_DATA_ADDR <<
722 hex "XIP kernel data virtual address" <<
723 depends on XIP_KERNEL <<
724 default 0x00000000 <<
725 help <<
726 This is the virtual address where XI <<
727 It must be within KSEG if MMU is use <<
728 2831
729 config PLATFORM_WANT_DEFAULT_MEM !! 2832 config SYS_SUPPORTS_48HZ
730 def_bool n !! 2833 bool
731 2834
732 config DEFAULT_MEM_START !! 2835 config SYS_SUPPORTS_100HZ
733 hex !! 2836 bool
734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !M !! 2837
735 default 0x60000000 if PLATFORM_WANT_DE !! 2838 config SYS_SUPPORTS_128HZ
736 default 0x00000000 !! 2839 bool
737 help !! 2840
738 This is the base address used for bo !! 2841 config SYS_SUPPORTS_250HZ
739 in noMMU configurations. !! 2842 bool
>> 2843
>> 2844 config SYS_SUPPORTS_256HZ
>> 2845 bool
>> 2846
>> 2847 config SYS_SUPPORTS_1000HZ
>> 2848 bool
>> 2849
>> 2850 config SYS_SUPPORTS_1024HZ
>> 2851 bool
>> 2852
>> 2853 config SYS_SUPPORTS_ARBIT_HZ
>> 2854 bool
>> 2855 default y if !SYS_SUPPORTS_24HZ && \
>> 2856 !SYS_SUPPORTS_48HZ && \
>> 2857 !SYS_SUPPORTS_100HZ && \
>> 2858 !SYS_SUPPORTS_128HZ && \
>> 2859 !SYS_SUPPORTS_250HZ && \
>> 2860 !SYS_SUPPORTS_256HZ && \
>> 2861 !SYS_SUPPORTS_1000HZ && \
>> 2862 !SYS_SUPPORTS_1024HZ
>> 2863
>> 2864 config HZ
>> 2865 int
>> 2866 default 24 if HZ_24
>> 2867 default 48 if HZ_48
>> 2868 default 100 if HZ_100
>> 2869 default 128 if HZ_128
>> 2870 default 250 if HZ_250
>> 2871 default 256 if HZ_256
>> 2872 default 1000 if HZ_1000
>> 2873 default 1024 if HZ_1024
>> 2874
>> 2875 config SCHED_HRTICK
>> 2876 def_bool HIGH_RES_TIMERS
740 2877
741 If unsure, leave the default value h !! 2878 config ARCH_SUPPORTS_KEXEC
>> 2879 def_bool y
>> 2880
>> 2881 config ARCH_SUPPORTS_CRASH_DUMP
>> 2882 def_bool y
>> 2883
>> 2884 config PHYSICAL_START
>> 2885 hex "Physical address where the kernel is loaded"
>> 2886 default "0xffffffff84000000"
>> 2887 depends on CRASH_DUMP
>> 2888 help
>> 2889 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2890 If you plan to use kernel for capturing the crash dump change
>> 2891 this value to start of the reserved region (the "X" value as
>> 2892 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2893 passed to the panic-ed kernel).
>> 2894
>> 2895 config MIPS_O32_FP64_SUPPORT
>> 2896 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2897 depends on 32BIT || MIPS32_O32
>> 2898 help
>> 2899 When this is enabled, the kernel will support use of 64-bit floating
>> 2900 point registers with binaries using the O32 ABI along with the
>> 2901 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2902 32-bit MIPS systems this support is at the cost of increasing the
>> 2903 size and complexity of the compiled FPU emulator. Thus if you are
>> 2904 running a MIPS32 system and know that none of your userland binaries
>> 2905 will require 64-bit floating point, you may wish to reduce the size
>> 2906 of your kernel & potentially improve FP emulation performance by
>> 2907 saying N here.
>> 2908
>> 2909 Although binutils currently supports use of this flag the details
>> 2910 concerning its effect upon the O32 ABI in userland are still being
>> 2911 worked on. In order to avoid userland becoming dependent upon current
>> 2912 behaviour before the details have been finalised, this option should
>> 2913 be considered experimental and only enabled by those working upon
>> 2914 said details.
>> 2915
>> 2916 If unsure, say N.
>> 2917
>> 2918 config USE_OF
>> 2919 bool
>> 2920 select OF
>> 2921 select OF_EARLY_FLATTREE
>> 2922 select IRQ_DOMAIN
>> 2923
>> 2924 config UHI_BOOT
>> 2925 bool
>> 2926
>> 2927 config BUILTIN_DTB
>> 2928 bool
742 2929
743 choice 2930 choice
744 prompt "KSEG layout" !! 2931 prompt "Kernel appended dtb support"
745 depends on MMU !! 2932 depends on USE_OF
746 default XTENSA_KSEG_MMU_V2 !! 2933 default MIPS_NO_APPENDED_DTB
747 !! 2934
748 config XTENSA_KSEG_MMU_V2 !! 2935 config MIPS_NO_APPENDED_DTB
749 bool "MMUv2: 128MB cached + 128MB unca !! 2936 bool "None"
750 help !! 2937 help
751 MMUv2 compatible kernel memory map: !! 2938 Do not enable appended dtb support.
752 at KSEG_PADDR to 0xd0000000 with cac !! 2939
753 without cache. !! 2940 config MIPS_ELF_APPENDED_DTB
754 KSEG_PADDR must be aligned to 128MB. !! 2941 bool "vmlinux"
755 !! 2942 help
756 config XTENSA_KSEG_256M !! 2943 With this option, the boot code will look for a device tree binary
757 bool "256MB cached + 256MB uncached" !! 2944 DTB) included in the vmlinux ELF section .appended_dtb. By default
758 depends on INITIALIZE_XTENSA_MMU_INSID !! 2945 it is empty and the DTB can be appended using binutils command
759 help !! 2946 objcopy:
760 TLB way 6 maps 256MB starting at KSE !! 2947
761 with cache and to 0xc0000000 without !! 2948 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
762 KSEG_PADDR must be aligned to 256MB. !! 2949
763 !! 2950 This is meant as a backward compatibility convenience for those
764 config XTENSA_KSEG_512M !! 2951 systems with a bootloader that can't be upgraded to accommodate
765 bool "512MB cached + 512MB uncached" !! 2952 the documented boot protocol using a device tree.
766 depends on INITIALIZE_XTENSA_MMU_INSID !! 2953
767 help !! 2954 config MIPS_RAW_APPENDED_DTB
768 TLB way 6 maps 512MB starting at KSE !! 2955 bool "vmlinux.bin or vmlinuz.bin"
769 with cache and to 0xc0000000 without !! 2956 help
770 KSEG_PADDR must be aligned to 256MB. !! 2957 With this option, the boot code will look for a device tree binary
>> 2958 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2959 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2960
>> 2961 This is meant as a backward compatibility convenience for those
>> 2962 systems with a bootloader that can't be upgraded to accommodate
>> 2963 the documented boot protocol using a device tree.
>> 2964
>> 2965 Beware that there is very little in terms of protection against
>> 2966 this option being confused by leftover garbage in memory that might
>> 2967 look like a DTB header after a reboot if no actual DTB is appended
>> 2968 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2969 if you don't intend to always append a DTB.
>> 2970 endchoice
771 2971
>> 2972 choice
>> 2973 prompt "Kernel command line type"
>> 2974 depends on !CMDLINE_OVERRIDE
>> 2975 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
>> 2976 !MACH_LOONGSON64 && !MIPS_MALTA && \
>> 2977 !CAVIUM_OCTEON_SOC
>> 2978 default MIPS_CMDLINE_FROM_BOOTLOADER
>> 2979
>> 2980 config MIPS_CMDLINE_FROM_DTB
>> 2981 depends on USE_OF
>> 2982 bool "Dtb kernel arguments if available"
>> 2983
>> 2984 config MIPS_CMDLINE_DTB_EXTEND
>> 2985 depends on USE_OF
>> 2986 bool "Extend dtb kernel arguments with bootloader arguments"
>> 2987
>> 2988 config MIPS_CMDLINE_FROM_BOOTLOADER
>> 2989 bool "Bootloader kernel arguments if available"
>> 2990
>> 2991 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2992 depends on CMDLINE_BOOL
>> 2993 bool "Extend builtin kernel arguments with bootloader arguments"
772 endchoice 2994 endchoice
773 2995
774 config HIGHMEM !! 2996 endmenu
775 bool "High Memory Support" <<
776 depends on MMU <<
777 select KMAP_LOCAL <<
778 help <<
779 Linux can use the full amount of RAM <<
780 default. However, the default MMUv2 <<
781 lowermost 128 MB of memory linearly <<
782 at 0xd0000000 (cached) and 0xd800000 <<
783 When there are more than 128 MB memo <<
784 all of it can be "permanently mapped <<
785 The physical memory that's not perma <<
786 "high memory". <<
787 <<
788 If you are compiling a kernel which <<
789 machine with more than 128 MB total <<
790 N here. <<
791 2997
792 If unsure, say Y. !! 2998 config LOCKDEP_SUPPORT
>> 2999 bool
>> 3000 default y
793 3001
794 config ARCH_FORCE_MAX_ORDER !! 3002 config STACKTRACE_SUPPORT
795 int "Order of maximal physically conti !! 3003 bool
796 default "10" !! 3004 default y
797 help !! 3005
798 The kernel page allocator limits the !! 3006 config PGTABLE_LEVELS
799 contiguous allocations. The limit is !! 3007 int
800 defines the maximal power of two of !! 3008 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
801 allocated as a single contiguous blo !! 3009 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
802 overriding the default setting when !! 3010 default 2
803 large blocks of physically contiguou !! 3011
>> 3012 config MIPS_AUTO_PFN_OFFSET
>> 3013 bool
>> 3014
>> 3015 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
804 3016
805 Don't change if unsure. !! 3017 config PCI_DRIVERS_GENERIC
>> 3018 select PCI_DOMAINS_GENERIC if PCI
>> 3019 bool
>> 3020
>> 3021 config PCI_DRIVERS_LEGACY
>> 3022 def_bool !PCI_DRIVERS_GENERIC
>> 3023 select NO_GENERIC_PCI_IOPORT_MAP
>> 3024 select PCI_DOMAINS if PCI
>> 3025
>> 3026 #
>> 3027 # ISA support is now enabled via select. Too many systems still have the one
>> 3028 # or other ISA chip on the board that users don't know about so don't expect
>> 3029 # users to choose the right thing ...
>> 3030 #
>> 3031 config ISA
>> 3032 bool
>> 3033
>> 3034 config TC
>> 3035 bool "TURBOchannel support"
>> 3036 depends on MACH_DECSTATION
>> 3037 help
>> 3038 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3039 processors. TURBOchannel programming specifications are available
>> 3040 at:
>> 3041 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3042 and:
>> 3043 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3044 Linux driver support status is documented at:
>> 3045 <http://www.linux-mips.org/wiki/DECstation>
>> 3046
>> 3047 config MMU
>> 3048 bool
>> 3049 default y
>> 3050
>> 3051 config ARCH_MMAP_RND_BITS_MIN
>> 3052 default 12 if 64BIT
>> 3053 default 8
>> 3054
>> 3055 config ARCH_MMAP_RND_BITS_MAX
>> 3056 default 18 if 64BIT
>> 3057 default 15
806 3058
>> 3059 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3060 default 8
>> 3061
>> 3062 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3063 default 15
>> 3064
>> 3065 config I8253
>> 3066 bool
>> 3067 select CLKSRC_I8253
>> 3068 select CLKEVT_I8253
>> 3069 select MIPS_EXTERNAL_TIMER
807 endmenu 3070 endmenu
808 3071
>> 3072 config TRAD_SIGNALS
>> 3073 bool
>> 3074
>> 3075 config MIPS32_COMPAT
>> 3076 bool
>> 3077
>> 3078 config COMPAT
>> 3079 bool
>> 3080
>> 3081 config MIPS32_O32
>> 3082 bool "Kernel support for o32 binaries"
>> 3083 depends on 64BIT
>> 3084 select ARCH_WANT_OLD_COMPAT_IPC
>> 3085 select COMPAT
>> 3086 select MIPS32_COMPAT
>> 3087 help
>> 3088 Select this option if you want to run o32 binaries. These are pure
>> 3089 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3090 existing binaries are in this format.
>> 3091
>> 3092 If unsure, say Y.
>> 3093
>> 3094 config MIPS32_N32
>> 3095 bool "Kernel support for n32 binaries"
>> 3096 depends on 64BIT
>> 3097 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3098 select COMPAT
>> 3099 select MIPS32_COMPAT
>> 3100 help
>> 3101 Select this option if you want to run n32 binaries. These are
>> 3102 64-bit binaries using 32-bit quantities for addressing and certain
>> 3103 data that would normally be 64-bit. They are used in special
>> 3104 cases.
>> 3105
>> 3106 If unsure, say N.
>> 3107
>> 3108 config CC_HAS_MNO_BRANCH_LIKELY
>> 3109 def_bool y
>> 3110 depends on $(cc-option,-mno-branch-likely)
>> 3111
>> 3112 # https://github.com/llvm/llvm-project/issues/61045
>> 3113 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>> 3114 def_bool y if CC_IS_CLANG
>> 3115
809 menu "Power management options" 3116 menu "Power management options"
810 3117
811 config ARCH_HIBERNATION_POSSIBLE 3118 config ARCH_HIBERNATION_POSSIBLE
812 def_bool y 3119 def_bool y
>> 3120 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3121
>> 3122 config ARCH_SUSPEND_POSSIBLE
>> 3123 def_bool y
>> 3124 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
813 3125
814 source "kernel/power/Kconfig" 3126 source "kernel/power/Kconfig"
815 3127
816 endmenu 3128 endmenu
>> 3129
>> 3130 config MIPS_EXTERNAL_TIMER
>> 3131 bool
>> 3132
>> 3133 menu "CPU Power Management"
>> 3134
>> 3135 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3136 source "drivers/cpufreq/Kconfig"
>> 3137 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3138
>> 3139 source "drivers/cpuidle/Kconfig"
>> 3140
>> 3141 endmenu
>> 3142
>> 3143 source "arch/mips/kvm/Kconfig"
>> 3144
>> 3145 source "arch/mips/vdso/Kconfig"
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