1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 config XTENSA !! 2 config MIPS
3 def_bool y !! 3 bool
4 select ARCH_32BIT_OFF_T !! 4 default y
5 select ARCH_HAS_CPU_CACHE_ALIASING !! 5 select ARCH_32BIT_OFF_T if !64BIT
6 select ARCH_HAS_BINFMT_FLAT if !MMU !! 6 select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
7 select ARCH_HAS_CURRENT_STACK_POINTER !! 7 select ARCH_HAS_CPU_FINALIZE_INIT
8 select ARCH_HAS_DEBUG_VM_PGTABLE !! 8 select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
9 select ARCH_HAS_DMA_PREP_COHERENT if M !! 9 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
10 select ARCH_HAS_GCOV_PROFILE_ALL !! 10 select ARCH_HAS_FORTIFY_SOURCE
11 select ARCH_HAS_KCOV 11 select ARCH_HAS_KCOV
12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MM !! 12 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if !! 13 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
14 select ARCH_HAS_DMA_SET_UNCACHED if MM !! 14 select ARCH_HAS_STRNCPY_FROM_USER
15 select ARCH_HAS_STRNCPY_FROM_USER if ! <<
16 select ARCH_HAS_STRNLEN_USER 15 select ARCH_HAS_STRNLEN_USER
17 select ARCH_NEED_CMPXCHG_1_EMU !! 16 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
>> 17 select ARCH_HAS_UBSAN_SANITIZE_ALL
>> 18 select ARCH_HAS_GCOV_PROFILE_ALL
>> 19 select ARCH_KEEP_MEMBLOCK
>> 20 select ARCH_USE_BUILTIN_BSWAP
>> 21 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
18 select ARCH_USE_MEMTEST 22 select ARCH_USE_MEMTEST
19 select ARCH_USE_QUEUED_RWLOCKS 23 select ARCH_USE_QUEUED_RWLOCKS
20 select ARCH_USE_QUEUED_SPINLOCKS 24 select ARCH_USE_QUEUED_SPINLOCKS
>> 25 select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
>> 26 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
21 select ARCH_WANT_IPC_PARSE_VERSION 27 select ARCH_WANT_IPC_PARSE_VERSION
>> 28 select ARCH_WANT_LD_ORPHAN_WARN
22 select BUILDTIME_TABLE_SORT 29 select BUILDTIME_TABLE_SORT
23 select CLONE_BACKWARDS 30 select CLONE_BACKWARDS
24 select COMMON_CLK !! 31 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
25 select DMA_NONCOHERENT_MMAP if MMU !! 32 select CPU_PM if CPU_IDLE
26 select GENERIC_ATOMIC64 !! 33 select GENERIC_ATOMIC64 if !64BIT
>> 34 select GENERIC_CMOS_UPDATE
>> 35 select GENERIC_CPU_AUTOPROBE
>> 36 select GENERIC_GETTIMEOFDAY
>> 37 select GENERIC_IOMAP
>> 38 select GENERIC_IRQ_PROBE
27 select GENERIC_IRQ_SHOW 39 select GENERIC_IRQ_SHOW
>> 40 select GENERIC_ISA_DMA if EISA
>> 41 select GENERIC_LIB_ASHLDI3
>> 42 select GENERIC_LIB_ASHRDI3
28 select GENERIC_LIB_CMPDI2 43 select GENERIC_LIB_CMPDI2
29 select GENERIC_LIB_MULDI3 !! 44 select GENERIC_LIB_LSHRDI3
30 select GENERIC_LIB_UCMPDI2 45 select GENERIC_LIB_UCMPDI2
31 select GENERIC_PCI_IOMAP !! 46 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
32 select GENERIC_SCHED_CLOCK !! 47 select GENERIC_SMP_IDLE_THREAD
33 select GENERIC_IOREMAP if MMU !! 48 select GENERIC_IDLE_POLL_SETUP
34 select HAVE_ARCH_AUDITSYSCALL !! 49 select GENERIC_TIME_VSYSCALL
35 select HAVE_ARCH_JUMP_LABEL if !XIP_KE !! 50 select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
36 select HAVE_ARCH_KASAN if MMU && !XIP_ !! 51 select HAS_IOPORT if !NO_IOPORT_MAP || ISA
37 select HAVE_ARCH_KCSAN !! 52 select HAVE_ARCH_COMPILER_H
>> 53 select HAVE_ARCH_JUMP_LABEL
>> 54 select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT
>> 55 select HAVE_ARCH_MMAP_RND_BITS if MMU
>> 56 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
38 select HAVE_ARCH_SECCOMP_FILTER 57 select HAVE_ARCH_SECCOMP_FILTER
39 select HAVE_ARCH_TRACEHOOK 58 select HAVE_ARCH_TRACEHOOK
>> 59 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
40 select HAVE_ASM_MODVERSIONS 60 select HAVE_ASM_MODVERSIONS
41 select HAVE_CONTEXT_TRACKING_USER 61 select HAVE_CONTEXT_TRACKING_USER
>> 62 select HAVE_TIF_NOHZ
>> 63 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK 64 select HAVE_DEBUG_KMEMLEAK
>> 65 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_DMA_CONTIGUOUS 66 select HAVE_DMA_CONTIGUOUS
>> 67 select HAVE_DYNAMIC_FTRACE
>> 68 select HAVE_EBPF_JIT if !CPU_MICROMIPS
44 select HAVE_EXIT_THREAD 69 select HAVE_EXIT_THREAD
>> 70 select HAVE_FAST_GUP
>> 71 select HAVE_FTRACE_MCOUNT_RECORD
>> 72 select HAVE_FUNCTION_GRAPH_TRACER
45 select HAVE_FUNCTION_TRACER 73 select HAVE_FUNCTION_TRACER
46 select HAVE_GCC_PLUGINS if GCC_VERSION !! 74 select HAVE_GCC_PLUGINS
47 select HAVE_HW_BREAKPOINT if PERF_EVEN !! 75 select HAVE_GENERIC_VDSO
>> 76 select HAVE_IOREMAP_PROT
>> 77 select HAVE_IRQ_EXIT_ON_IRQ_STACK
48 select HAVE_IRQ_TIME_ACCOUNTING 78 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_PAGE_SIZE_4KB !! 79 select HAVE_KPROBES
50 select HAVE_PCI !! 80 select HAVE_KRETPROBES
>> 81 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
>> 82 select HAVE_MOD_ARCH_SPECIFIC
>> 83 select HAVE_NMI
51 select HAVE_PERF_EVENTS 84 select HAVE_PERF_EVENTS
>> 85 select HAVE_PERF_REGS
>> 86 select HAVE_PERF_USER_STACK_DUMP
>> 87 select HAVE_REGS_AND_STACK_ACCESS_API
>> 88 select HAVE_RSEQ
>> 89 select HAVE_SPARSE_SYSCALL_NR
52 select HAVE_STACKPROTECTOR 90 select HAVE_STACKPROTECTOR
53 select HAVE_SYSCALL_TRACEPOINTS 91 select HAVE_SYSCALL_TRACEPOINTS
54 select HAVE_VIRT_CPU_ACCOUNTING_GEN !! 92 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
55 select IRQ_DOMAIN !! 93 select IRQ_FORCED_THREADING
>> 94 select ISA if EISA
56 select LOCK_MM_AND_FIND_VMA 95 select LOCK_MM_AND_FIND_VMA
57 select MODULES_USE_ELF_RELA !! 96 select MODULES_USE_ELF_REL if MODULES
>> 97 select MODULES_USE_ELF_RELA if MODULES && 64BIT
58 select PERF_USE_VMALLOC 98 select PERF_USE_VMALLOC
>> 99 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
>> 100 select RTC_LIB
>> 101 select SYSCTL_EXCEPTION_TRACE
59 select TRACE_IRQFLAGS_SUPPORT 102 select TRACE_IRQFLAGS_SUPPORT
>> 103 select ARCH_HAS_ELFCORE_COMPAT
>> 104 select HAVE_ARCH_KCSAN if 64BIT
>> 105
>> 106 config MIPS_FIXUP_BIGPHYS_ADDR
>> 107 bool
>> 108
>> 109 config MIPS_GENERIC
>> 110 bool
>> 111
>> 112 config MACH_INGENIC
>> 113 bool
>> 114 select SYS_SUPPORTS_32BIT_KERNEL
>> 115 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 116 select SYS_SUPPORTS_ZBOOT
>> 117 select DMA_NONCOHERENT
>> 118 select IRQ_MIPS_CPU
>> 119 select PINCTRL
>> 120 select GPIOLIB
>> 121 select COMMON_CLK
>> 122 select GENERIC_IRQ_CHIP
>> 123 select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
>> 124 select USE_OF
>> 125 select CPU_SUPPORTS_CPUFREQ
>> 126 select MIPS_EXTERNAL_TIMER
>> 127
>> 128 menu "Machine selection"
>> 129
>> 130 choice
>> 131 prompt "System type"
>> 132 default MIPS_GENERIC_KERNEL
>> 133
>> 134 config MIPS_GENERIC_KERNEL
>> 135 bool "Generic board-agnostic MIPS kernel"
>> 136 select MIPS_GENERIC
>> 137 select BOOT_RAW
>> 138 select BUILTIN_DTB
>> 139 select CEVT_R4K
>> 140 select CLKSRC_MIPS_GIC
>> 141 select COMMON_CLK
>> 142 select CPU_MIPSR2_IRQ_EI
>> 143 select CPU_MIPSR2_IRQ_VI
>> 144 select CSRC_R4K
>> 145 select DMA_NONCOHERENT
>> 146 select HAVE_PCI
>> 147 select IRQ_MIPS_CPU
>> 148 select MIPS_AUTO_PFN_OFFSET
>> 149 select MIPS_CPU_SCACHE
>> 150 select MIPS_GIC
>> 151 select MIPS_L1_CACHE_SHIFT_7
>> 152 select NO_EXCEPT_FILL
>> 153 select PCI_DRIVERS_GENERIC
>> 154 select SMP_UP if SMP
>> 155 select SWAP_IO_SPACE
>> 156 select SYS_HAS_CPU_MIPS32_R1
>> 157 select SYS_HAS_CPU_MIPS32_R2
>> 158 select SYS_HAS_CPU_MIPS32_R5
>> 159 select SYS_HAS_CPU_MIPS32_R6
>> 160 select SYS_HAS_CPU_MIPS64_R1
>> 161 select SYS_HAS_CPU_MIPS64_R2
>> 162 select SYS_HAS_CPU_MIPS64_R5
>> 163 select SYS_HAS_CPU_MIPS64_R6
>> 164 select SYS_SUPPORTS_32BIT_KERNEL
>> 165 select SYS_SUPPORTS_64BIT_KERNEL
>> 166 select SYS_SUPPORTS_BIG_ENDIAN
>> 167 select SYS_SUPPORTS_HIGHMEM
>> 168 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 169 select SYS_SUPPORTS_MICROMIPS
>> 170 select SYS_SUPPORTS_MIPS16
>> 171 select SYS_SUPPORTS_MIPS_CPS
>> 172 select SYS_SUPPORTS_MULTITHREADING
>> 173 select SYS_SUPPORTS_RELOCATABLE
>> 174 select SYS_SUPPORTS_SMARTMIPS
>> 175 select SYS_SUPPORTS_ZBOOT
>> 176 select UHI_BOOT
>> 177 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 178 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 179 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 180 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 181 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 182 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 183 select USE_OF
>> 184 help
>> 185 Select this to build a kernel which aims to support multiple boards,
>> 186 generally using a flattened device tree passed from the bootloader
>> 187 using the boot protocol defined in the UHI (Unified Hosting
>> 188 Interface) specification.
>> 189
>> 190 config MIPS_ALCHEMY
>> 191 bool "Alchemy processor based machines"
>> 192 select PHYS_ADDR_T_64BIT
>> 193 select CEVT_R4K
>> 194 select CSRC_R4K
>> 195 select IRQ_MIPS_CPU
>> 196 select DMA_NONCOHERENT # Au1000,1500,1100 aren't, rest is
>> 197 select MIPS_FIXUP_BIGPHYS_ADDR if PCI
>> 198 select SYS_HAS_CPU_MIPS32_R1
>> 199 select SYS_SUPPORTS_32BIT_KERNEL
>> 200 select SYS_SUPPORTS_APM_EMULATION
>> 201 select GPIOLIB
>> 202 select SYS_SUPPORTS_ZBOOT
>> 203 select COMMON_CLK
>> 204
>> 205 config AR7
>> 206 bool "Texas Instruments AR7"
>> 207 select BOOT_ELF32
>> 208 select COMMON_CLK
>> 209 select DMA_NONCOHERENT
>> 210 select CEVT_R4K
>> 211 select CSRC_R4K
>> 212 select IRQ_MIPS_CPU
>> 213 select NO_EXCEPT_FILL
>> 214 select SWAP_IO_SPACE
>> 215 select SYS_HAS_CPU_MIPS32_R1
>> 216 select SYS_HAS_EARLY_PRINTK
>> 217 select SYS_SUPPORTS_32BIT_KERNEL
>> 218 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 219 select SYS_SUPPORTS_MIPS16
>> 220 select SYS_SUPPORTS_ZBOOT_UART16550
>> 221 select GPIOLIB
>> 222 select VLYNQ
>> 223 help
>> 224 Support for the Texas Instruments AR7 System-on-a-Chip
>> 225 family: TNETD7100, 7200 and 7300.
>> 226
>> 227 config ATH25
>> 228 bool "Atheros AR231x/AR531x SoC support"
>> 229 select CEVT_R4K
>> 230 select CSRC_R4K
>> 231 select DMA_NONCOHERENT
>> 232 select IRQ_MIPS_CPU
>> 233 select IRQ_DOMAIN
>> 234 select SYS_HAS_CPU_MIPS32_R1
>> 235 select SYS_SUPPORTS_BIG_ENDIAN
>> 236 select SYS_SUPPORTS_32BIT_KERNEL
>> 237 select SYS_HAS_EARLY_PRINTK
>> 238 help
>> 239 Support for Atheros AR231x and Atheros AR531x based boards
>> 240
>> 241 config ATH79
>> 242 bool "Atheros AR71XX/AR724X/AR913X based boards"
>> 243 select ARCH_HAS_RESET_CONTROLLER
>> 244 select BOOT_RAW
>> 245 select CEVT_R4K
>> 246 select CSRC_R4K
>> 247 select DMA_NONCOHERENT
>> 248 select GPIOLIB
>> 249 select PINCTRL
>> 250 select COMMON_CLK
>> 251 select IRQ_MIPS_CPU
>> 252 select SYS_HAS_CPU_MIPS32_R2
>> 253 select SYS_HAS_EARLY_PRINTK
>> 254 select SYS_SUPPORTS_32BIT_KERNEL
>> 255 select SYS_SUPPORTS_BIG_ENDIAN
>> 256 select SYS_SUPPORTS_MIPS16
>> 257 select SYS_SUPPORTS_ZBOOT_UART_PROM
>> 258 select USE_OF
>> 259 select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
>> 260 help
>> 261 Support for the Atheros AR71XX/AR724X/AR913X SoCs.
>> 262
>> 263 config BMIPS_GENERIC
>> 264 bool "Broadcom Generic BMIPS kernel"
>> 265 select ARCH_HAS_RESET_CONTROLLER
>> 266 select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
>> 267 select BOOT_RAW
>> 268 select NO_EXCEPT_FILL
>> 269 select USE_OF
>> 270 select CEVT_R4K
>> 271 select CSRC_R4K
>> 272 select SYNC_R4K
>> 273 select COMMON_CLK
>> 274 select BCM6345_L1_IRQ
>> 275 select BCM7038_L1_IRQ
>> 276 select BCM7120_L2_IRQ
>> 277 select BRCMSTB_L2_IRQ
>> 278 select IRQ_MIPS_CPU
>> 279 select DMA_NONCOHERENT
>> 280 select SYS_SUPPORTS_32BIT_KERNEL
>> 281 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 282 select SYS_SUPPORTS_BIG_ENDIAN
>> 283 select SYS_SUPPORTS_HIGHMEM
>> 284 select SYS_HAS_CPU_BMIPS32_3300
>> 285 select SYS_HAS_CPU_BMIPS4350
>> 286 select SYS_HAS_CPU_BMIPS4380
>> 287 select SYS_HAS_CPU_BMIPS5000
>> 288 select SWAP_IO_SPACE
>> 289 select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 290 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 291 select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
>> 292 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 293 select HARDIRQS_SW_RESEND
>> 294 select HAVE_PCI
>> 295 select PCI_DRIVERS_GENERIC
>> 296 select FW_CFE
60 help 297 help
61 Xtensa processors are 32-bit RISC ma !! 298 Build a generic DT-based kernel image that boots on select
62 primarily for embedded systems. The !! 299 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
63 configurable and extensible. The Li !! 300 box chips. Note that CONFIG_CPU_BIG_ENDIAN/CONFIG_CPU_LITTLE_ENDIAN
64 architecture supports all processor !! 301 must be set appropriately for your board.
65 with reasonable minimum requirements !! 302
66 a home page at <http://www.linux-xte !! 303 config BCM47XX
>> 304 bool "Broadcom BCM47XX based boards"
>> 305 select BOOT_RAW
>> 306 select CEVT_R4K
>> 307 select CSRC_R4K
>> 308 select DMA_NONCOHERENT
>> 309 select HAVE_PCI
>> 310 select IRQ_MIPS_CPU
>> 311 select SYS_HAS_CPU_MIPS32_R1
>> 312 select NO_EXCEPT_FILL
>> 313 select SYS_SUPPORTS_32BIT_KERNEL
>> 314 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 315 select SYS_SUPPORTS_MIPS16
>> 316 select SYS_SUPPORTS_ZBOOT
>> 317 select SYS_HAS_EARLY_PRINTK
>> 318 select USE_GENERIC_EARLY_PRINTK_8250
>> 319 select GPIOLIB
>> 320 select LEDS_GPIO_REGISTER
>> 321 select BCM47XX_NVRAM
>> 322 select BCM47XX_SPROM
>> 323 select BCM47XX_SSB if !BCM47XX_BCMA
>> 324 help
>> 325 Support for BCM47XX based boards
>> 326
>> 327 config BCM63XX
>> 328 bool "Broadcom BCM63XX based boards"
>> 329 select BOOT_RAW
>> 330 select CEVT_R4K
>> 331 select CSRC_R4K
>> 332 select SYNC_R4K
>> 333 select DMA_NONCOHERENT
>> 334 select IRQ_MIPS_CPU
>> 335 select SYS_SUPPORTS_32BIT_KERNEL
>> 336 select SYS_SUPPORTS_BIG_ENDIAN
>> 337 select SYS_HAS_EARLY_PRINTK
>> 338 select SYS_HAS_CPU_BMIPS32_3300
>> 339 select SYS_HAS_CPU_BMIPS4350
>> 340 select SYS_HAS_CPU_BMIPS4380
>> 341 select SWAP_IO_SPACE
>> 342 select GPIOLIB
>> 343 select MIPS_L1_CACHE_SHIFT_4
>> 344 select HAVE_LEGACY_CLK
>> 345 help
>> 346 Support for BCM63XX based boards
>> 347
>> 348 config MIPS_COBALT
>> 349 bool "Cobalt Server"
>> 350 select CEVT_R4K
>> 351 select CSRC_R4K
>> 352 select CEVT_GT641XX
>> 353 select DMA_NONCOHERENT
>> 354 select FORCE_PCI
>> 355 select I8253
>> 356 select I8259
>> 357 select IRQ_MIPS_CPU
>> 358 select IRQ_GT641XX
>> 359 select PCI_GT64XXX_PCI0
>> 360 select SYS_HAS_CPU_NEVADA
>> 361 select SYS_HAS_EARLY_PRINTK
>> 362 select SYS_SUPPORTS_32BIT_KERNEL
>> 363 select SYS_SUPPORTS_64BIT_KERNEL
>> 364 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 365 select USE_GENERIC_EARLY_PRINTK_8250
>> 366
>> 367 config MACH_DECSTATION
>> 368 bool "DECstations"
>> 369 select BOOT_ELF32
>> 370 select CEVT_DS1287
>> 371 select CEVT_R4K if CPU_R4X00
>> 372 select CSRC_IOASIC
>> 373 select CSRC_R4K if CPU_R4X00
>> 374 select CPU_DADDI_WORKAROUNDS if 64BIT
>> 375 select CPU_R4000_WORKAROUNDS if 64BIT
>> 376 select CPU_R4400_WORKAROUNDS if 64BIT
>> 377 select DMA_NONCOHERENT
>> 378 select NO_IOPORT_MAP
>> 379 select IRQ_MIPS_CPU
>> 380 select SYS_HAS_CPU_R3000
>> 381 select SYS_HAS_CPU_R4X00
>> 382 select SYS_SUPPORTS_32BIT_KERNEL
>> 383 select SYS_SUPPORTS_64BIT_KERNEL
>> 384 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 385 select SYS_SUPPORTS_128HZ
>> 386 select SYS_SUPPORTS_256HZ
>> 387 select SYS_SUPPORTS_1024HZ
>> 388 select MIPS_L1_CACHE_SHIFT_4
>> 389 help
>> 390 This enables support for DEC's MIPS based workstations. For details
>> 391 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
>> 392 DECstation porting pages on <http://decstation.unix-ag.org/>.
>> 393
>> 394 If you have one of the following DECstation Models you definitely
>> 395 want to choose R4xx0 for the CPU Type:
>> 396
>> 397 DECstation 5000/50
>> 398 DECstation 5000/150
>> 399 DECstation 5000/260
>> 400 DECsystem 5900/260
>> 401
>> 402 otherwise choose R3000.
>> 403
>> 404 config MACH_JAZZ
>> 405 bool "Jazz family of machines"
>> 406 select ARC_MEMORY
>> 407 select ARC_PROMLIB
>> 408 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 409 select ARCH_MIGHT_HAVE_PC_SERIO
>> 410 select DMA_OPS
>> 411 select FW_ARC
>> 412 select FW_ARC32
>> 413 select ARCH_MAY_HAVE_PC_FDC
>> 414 select CEVT_R4K
>> 415 select CSRC_R4K
>> 416 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 417 select GENERIC_ISA_DMA
>> 418 select HAVE_PCSPKR_PLATFORM
>> 419 select IRQ_MIPS_CPU
>> 420 select I8253
>> 421 select I8259
>> 422 select ISA
>> 423 select SYS_HAS_CPU_R4X00
>> 424 select SYS_SUPPORTS_32BIT_KERNEL
>> 425 select SYS_SUPPORTS_64BIT_KERNEL
>> 426 select SYS_SUPPORTS_100HZ
>> 427 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 428 help
>> 429 This a family of machines based on the MIPS R4030 chipset which was
>> 430 used by several vendors to build RISC/os and Windows NT workstations.
>> 431 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
>> 432 Olivetti M700-10 workstations.
>> 433
>> 434 config MACH_INGENIC_SOC
>> 435 bool "Ingenic SoC based machines"
>> 436 select MIPS_GENERIC
>> 437 select MACH_INGENIC
>> 438 select SYS_SUPPORTS_ZBOOT_UART16550
>> 439 select CPU_SUPPORTS_CPUFREQ
>> 440 select MIPS_EXTERNAL_TIMER
>> 441
>> 442 config LANTIQ
>> 443 bool "Lantiq based platforms"
>> 444 select DMA_NONCOHERENT
>> 445 select IRQ_MIPS_CPU
>> 446 select CEVT_R4K
>> 447 select CSRC_R4K
>> 448 select NO_EXCEPT_FILL
>> 449 select SYS_HAS_CPU_MIPS32_R1
>> 450 select SYS_HAS_CPU_MIPS32_R2
>> 451 select SYS_SUPPORTS_BIG_ENDIAN
>> 452 select SYS_SUPPORTS_32BIT_KERNEL
>> 453 select SYS_SUPPORTS_MIPS16
>> 454 select SYS_SUPPORTS_MULTITHREADING
>> 455 select SYS_SUPPORTS_VPE_LOADER
>> 456 select SYS_HAS_EARLY_PRINTK
>> 457 select GPIOLIB
>> 458 select SWAP_IO_SPACE
>> 459 select BOOT_RAW
>> 460 select HAVE_LEGACY_CLK
>> 461 select USE_OF
>> 462 select PINCTRL
>> 463 select PINCTRL_LANTIQ
>> 464 select ARCH_HAS_RESET_CONTROLLER
>> 465 select RESET_CONTROLLER
>> 466
>> 467 config MACH_LOONGSON32
>> 468 bool "Loongson 32-bit family of machines"
>> 469 select SYS_SUPPORTS_ZBOOT
>> 470 help
>> 471 This enables support for the Loongson-1 family of machines.
>> 472
>> 473 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
>> 474 the Institute of Computing Technology (ICT), Chinese Academy of
>> 475 Sciences (CAS).
>> 476
>> 477 config MACH_LOONGSON2EF
>> 478 bool "Loongson-2E/F family of machines"
>> 479 select SYS_SUPPORTS_ZBOOT
>> 480 help
>> 481 This enables the support of early Loongson-2E/F family of machines.
>> 482
>> 483 config MACH_LOONGSON64
>> 484 bool "Loongson 64-bit family of machines"
>> 485 select ARCH_DMA_DEFAULT_COHERENT
>> 486 select ARCH_SPARSEMEM_ENABLE
>> 487 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 488 select ARCH_MIGHT_HAVE_PC_SERIO
>> 489 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 490 select BOOT_ELF32
>> 491 select BOARD_SCACHE
>> 492 select CSRC_R4K
>> 493 select CEVT_R4K
>> 494 select FORCE_PCI
>> 495 select ISA
>> 496 select I8259
>> 497 select IRQ_MIPS_CPU
>> 498 select NO_EXCEPT_FILL
>> 499 select NR_CPUS_DEFAULT_64
>> 500 select USE_GENERIC_EARLY_PRINTK_8250
>> 501 select PCI_DRIVERS_GENERIC
>> 502 select SYS_HAS_CPU_LOONGSON64
>> 503 select SYS_HAS_EARLY_PRINTK
>> 504 select SYS_SUPPORTS_SMP
>> 505 select SYS_SUPPORTS_HOTPLUG_CPU
>> 506 select SYS_SUPPORTS_NUMA
>> 507 select SYS_SUPPORTS_64BIT_KERNEL
>> 508 select SYS_SUPPORTS_HIGHMEM
>> 509 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 510 select SYS_SUPPORTS_ZBOOT
>> 511 select SYS_SUPPORTS_RELOCATABLE
>> 512 select ZONE_DMA32
>> 513 select COMMON_CLK
>> 514 select USE_OF
>> 515 select BUILTIN_DTB
>> 516 select PCI_HOST_GENERIC
>> 517 select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
>> 518 help
>> 519 This enables the support of Loongson-2/3 family of machines.
>> 520
>> 521 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
>> 522 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
>> 523 and Loongson-2F which will be removed), developed by the Institute
>> 524 of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
>> 525
>> 526 config MIPS_MALTA
>> 527 bool "MIPS Malta board"
>> 528 select ARCH_MAY_HAVE_PC_FDC
>> 529 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 530 select ARCH_MIGHT_HAVE_PC_SERIO
>> 531 select BOOT_ELF32
>> 532 select BOOT_RAW
>> 533 select BUILTIN_DTB
>> 534 select CEVT_R4K
>> 535 select CLKSRC_MIPS_GIC
>> 536 select COMMON_CLK
>> 537 select CSRC_R4K
>> 538 select DMA_NONCOHERENT
>> 539 select GENERIC_ISA_DMA
>> 540 select HAVE_PCSPKR_PLATFORM
>> 541 select HAVE_PCI
>> 542 select I8253
>> 543 select I8259
>> 544 select IRQ_MIPS_CPU
>> 545 select MIPS_BONITO64
>> 546 select MIPS_CPU_SCACHE
>> 547 select MIPS_GIC
>> 548 select MIPS_L1_CACHE_SHIFT_6
>> 549 select MIPS_MSC
>> 550 select PCI_GT64XXX_PCI0
>> 551 select SMP_UP if SMP
>> 552 select SWAP_IO_SPACE
>> 553 select SYS_HAS_CPU_MIPS32_R1
>> 554 select SYS_HAS_CPU_MIPS32_R2
>> 555 select SYS_HAS_CPU_MIPS32_R3_5
>> 556 select SYS_HAS_CPU_MIPS32_R5
>> 557 select SYS_HAS_CPU_MIPS32_R6
>> 558 select SYS_HAS_CPU_MIPS64_R1
>> 559 select SYS_HAS_CPU_MIPS64_R2
>> 560 select SYS_HAS_CPU_MIPS64_R6
>> 561 select SYS_HAS_CPU_NEVADA
>> 562 select SYS_HAS_CPU_RM7000
>> 563 select SYS_SUPPORTS_32BIT_KERNEL
>> 564 select SYS_SUPPORTS_64BIT_KERNEL
>> 565 select SYS_SUPPORTS_BIG_ENDIAN
>> 566 select SYS_SUPPORTS_HIGHMEM
>> 567 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 568 select SYS_SUPPORTS_MICROMIPS
>> 569 select SYS_SUPPORTS_MIPS16
>> 570 select SYS_SUPPORTS_MIPS_CPS
>> 571 select SYS_SUPPORTS_MULTITHREADING
>> 572 select SYS_SUPPORTS_RELOCATABLE
>> 573 select SYS_SUPPORTS_SMARTMIPS
>> 574 select SYS_SUPPORTS_VPE_LOADER
>> 575 select SYS_SUPPORTS_ZBOOT
>> 576 select USE_OF
>> 577 select WAR_ICACHE_REFILLS
>> 578 select ZONE_DMA32 if 64BIT
>> 579 help
>> 580 This enables support for the MIPS Technologies Malta evaluation
>> 581 board.
>> 582
>> 583 config MACH_PIC32
>> 584 bool "Microchip PIC32 Family"
>> 585 help
>> 586 This enables support for the Microchip PIC32 family of platforms.
>> 587
>> 588 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
>> 589 microcontrollers.
>> 590
>> 591 config MACH_NINTENDO64
>> 592 bool "Nintendo 64 console"
>> 593 select CEVT_R4K
>> 594 select CSRC_R4K
>> 595 select SYS_HAS_CPU_R4300
>> 596 select SYS_SUPPORTS_BIG_ENDIAN
>> 597 select SYS_SUPPORTS_ZBOOT
>> 598 select SYS_SUPPORTS_32BIT_KERNEL
>> 599 select SYS_SUPPORTS_64BIT_KERNEL
>> 600 select DMA_NONCOHERENT
>> 601 select IRQ_MIPS_CPU
>> 602
>> 603 config RALINK
>> 604 bool "Ralink based machines"
>> 605 select CEVT_R4K
>> 606 select COMMON_CLK
>> 607 select CSRC_R4K
>> 608 select BOOT_RAW
>> 609 select DMA_NONCOHERENT
>> 610 select IRQ_MIPS_CPU
>> 611 select USE_OF
>> 612 select SYS_HAS_CPU_MIPS32_R2
>> 613 select SYS_SUPPORTS_32BIT_KERNEL
>> 614 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 615 select SYS_SUPPORTS_MIPS16
>> 616 select SYS_SUPPORTS_ZBOOT
>> 617 select SYS_HAS_EARLY_PRINTK
>> 618 select ARCH_HAS_RESET_CONTROLLER
>> 619 select RESET_CONTROLLER
>> 620
>> 621 config MACH_REALTEK_RTL
>> 622 bool "Realtek RTL838x/RTL839x based machines"
>> 623 select MIPS_GENERIC
>> 624 select DMA_NONCOHERENT
>> 625 select IRQ_MIPS_CPU
>> 626 select CSRC_R4K
>> 627 select CEVT_R4K
>> 628 select SYS_HAS_CPU_MIPS32_R1
>> 629 select SYS_HAS_CPU_MIPS32_R2
>> 630 select SYS_SUPPORTS_BIG_ENDIAN
>> 631 select SYS_SUPPORTS_32BIT_KERNEL
>> 632 select SYS_SUPPORTS_MIPS16
>> 633 select SYS_SUPPORTS_MULTITHREADING
>> 634 select SYS_SUPPORTS_VPE_LOADER
>> 635 select BOOT_RAW
>> 636 select PINCTRL
>> 637 select USE_OF
>> 638
>> 639 config SGI_IP22
>> 640 bool "SGI IP22 (Indy/Indigo2)"
>> 641 select ARC_MEMORY
>> 642 select ARC_PROMLIB
>> 643 select FW_ARC
>> 644 select FW_ARC32
>> 645 select ARCH_MIGHT_HAVE_PC_SERIO
>> 646 select BOOT_ELF32
>> 647 select CEVT_R4K
>> 648 select CSRC_R4K
>> 649 select DEFAULT_SGI_PARTITION
>> 650 select DMA_NONCOHERENT
>> 651 select HAVE_EISA
>> 652 select I8253
>> 653 select I8259
>> 654 select IP22_CPU_SCACHE
>> 655 select IRQ_MIPS_CPU
>> 656 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 657 select SGI_HAS_I8042
>> 658 select SGI_HAS_INDYDOG
>> 659 select SGI_HAS_HAL2
>> 660 select SGI_HAS_SEEQ
>> 661 select SGI_HAS_WD93
>> 662 select SGI_HAS_ZILOG
>> 663 select SWAP_IO_SPACE
>> 664 select SYS_HAS_CPU_R4X00
>> 665 select SYS_HAS_CPU_R5000
>> 666 select SYS_HAS_EARLY_PRINTK
>> 667 select SYS_SUPPORTS_32BIT_KERNEL
>> 668 select SYS_SUPPORTS_64BIT_KERNEL
>> 669 select SYS_SUPPORTS_BIG_ENDIAN
>> 670 select WAR_R4600_V1_INDEX_ICACHEOP
>> 671 select WAR_R4600_V1_HIT_CACHEOP
>> 672 select WAR_R4600_V2_HIT_CACHEOP
>> 673 select MIPS_L1_CACHE_SHIFT_7
>> 674 help
>> 675 This are the SGI Indy, Challenge S and Indigo2, as well as certain
>> 676 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
>> 677 that runs on these, say Y here.
>> 678
>> 679 config SGI_IP27
>> 680 bool "SGI IP27 (Origin200/2000)"
>> 681 select ARCH_HAS_PHYS_TO_DMA
>> 682 select ARCH_SPARSEMEM_ENABLE
>> 683 select FW_ARC
>> 684 select FW_ARC64
>> 685 select ARC_CMDLINE_ONLY
>> 686 select BOOT_ELF64
>> 687 select DEFAULT_SGI_PARTITION
>> 688 select FORCE_PCI
>> 689 select SYS_HAS_EARLY_PRINTK
>> 690 select HAVE_PCI
>> 691 select IRQ_MIPS_CPU
>> 692 select IRQ_DOMAIN_HIERARCHY
>> 693 select NR_CPUS_DEFAULT_64
>> 694 select PCI_DRIVERS_GENERIC
>> 695 select PCI_XTALK_BRIDGE
>> 696 select SYS_HAS_CPU_R10000
>> 697 select SYS_SUPPORTS_64BIT_KERNEL
>> 698 select SYS_SUPPORTS_BIG_ENDIAN
>> 699 select SYS_SUPPORTS_NUMA
>> 700 select SYS_SUPPORTS_SMP
>> 701 select WAR_R10000_LLSC
>> 702 select MIPS_L1_CACHE_SHIFT_7
>> 703 select NUMA
>> 704 select HAVE_ARCH_NODEDATA_EXTENSION
>> 705 help
>> 706 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>> 707 workstations. To compile a Linux kernel that runs on these, say Y
>> 708 here.
>> 709
>> 710 config SGI_IP28
>> 711 bool "SGI IP28 (Indigo2 R10k)"
>> 712 select ARC_MEMORY
>> 713 select ARC_PROMLIB
>> 714 select FW_ARC
>> 715 select FW_ARC64
>> 716 select ARCH_MIGHT_HAVE_PC_SERIO
>> 717 select BOOT_ELF64
>> 718 select CEVT_R4K
>> 719 select CSRC_R4K
>> 720 select DEFAULT_SGI_PARTITION
>> 721 select DMA_NONCOHERENT
>> 722 select GENERIC_ISA_DMA_SUPPORT_BROKEN
>> 723 select IRQ_MIPS_CPU
>> 724 select HAVE_EISA
>> 725 select I8253
>> 726 select I8259
>> 727 select SGI_HAS_I8042
>> 728 select SGI_HAS_INDYDOG
>> 729 select SGI_HAS_HAL2
>> 730 select SGI_HAS_SEEQ
>> 731 select SGI_HAS_WD93
>> 732 select SGI_HAS_ZILOG
>> 733 select SWAP_IO_SPACE
>> 734 select SYS_HAS_CPU_R10000
>> 735 select SYS_HAS_EARLY_PRINTK
>> 736 select SYS_SUPPORTS_64BIT_KERNEL
>> 737 select SYS_SUPPORTS_BIG_ENDIAN
>> 738 select WAR_R10000_LLSC
>> 739 select MIPS_L1_CACHE_SHIFT_7
>> 740 help
>> 741 This is the SGI Indigo2 with R10000 processor. To compile a Linux
>> 742 kernel that runs on these, say Y here.
>> 743
>> 744 config SGI_IP30
>> 745 bool "SGI IP30 (Octane/Octane2)"
>> 746 select ARCH_HAS_PHYS_TO_DMA
>> 747 select FW_ARC
>> 748 select FW_ARC64
>> 749 select BOOT_ELF64
>> 750 select CEVT_R4K
>> 751 select CSRC_R4K
>> 752 select FORCE_PCI
>> 753 select SYNC_R4K if SMP
>> 754 select ZONE_DMA32
>> 755 select HAVE_PCI
>> 756 select IRQ_MIPS_CPU
>> 757 select IRQ_DOMAIN_HIERARCHY
>> 758 select PCI_DRIVERS_GENERIC
>> 759 select PCI_XTALK_BRIDGE
>> 760 select SYS_HAS_EARLY_PRINTK
>> 761 select SYS_HAS_CPU_R10000
>> 762 select SYS_SUPPORTS_64BIT_KERNEL
>> 763 select SYS_SUPPORTS_BIG_ENDIAN
>> 764 select SYS_SUPPORTS_SMP
>> 765 select WAR_R10000_LLSC
>> 766 select MIPS_L1_CACHE_SHIFT_7
>> 767 select ARC_MEMORY
>> 768 help
>> 769 These are the SGI Octane and Octane2 graphics workstations. To
>> 770 compile a Linux kernel that runs on these, say Y here.
>> 771
>> 772 config SGI_IP32
>> 773 bool "SGI IP32 (O2)"
>> 774 select ARC_MEMORY
>> 775 select ARC_PROMLIB
>> 776 select ARCH_HAS_PHYS_TO_DMA
>> 777 select FW_ARC
>> 778 select FW_ARC32
>> 779 select BOOT_ELF32
>> 780 select CEVT_R4K
>> 781 select CSRC_R4K
>> 782 select DMA_NONCOHERENT
>> 783 select HAVE_PCI
>> 784 select IRQ_MIPS_CPU
>> 785 select R5000_CPU_SCACHE
>> 786 select RM7000_CPU_SCACHE
>> 787 select SYS_HAS_CPU_R5000
>> 788 select SYS_HAS_CPU_R10000 if BROKEN
>> 789 select SYS_HAS_CPU_RM7000
>> 790 select SYS_HAS_CPU_NEVADA
>> 791 select SYS_SUPPORTS_64BIT_KERNEL
>> 792 select SYS_SUPPORTS_BIG_ENDIAN
>> 793 select WAR_ICACHE_REFILLS
>> 794 help
>> 795 If you want this kernel to run on SGI O2 workstation, say Y here.
>> 796
>> 797 config SIBYTE_CRHONE
>> 798 bool "Sibyte BCM91125C-CRhone"
>> 799 select BOOT_ELF32
>> 800 select SIBYTE_BCM1125
>> 801 select SWAP_IO_SPACE
>> 802 select SYS_HAS_CPU_SB1
>> 803 select SYS_SUPPORTS_BIG_ENDIAN
>> 804 select SYS_SUPPORTS_HIGHMEM
>> 805 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 806
>> 807 config SIBYTE_RHONE
>> 808 bool "Sibyte BCM91125E-Rhone"
>> 809 select BOOT_ELF32
>> 810 select SIBYTE_SB1250
>> 811 select SWAP_IO_SPACE
>> 812 select SYS_HAS_CPU_SB1
>> 813 select SYS_SUPPORTS_BIG_ENDIAN
>> 814 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 815
>> 816 config SIBYTE_SWARM
>> 817 bool "Sibyte BCM91250A-SWARM"
>> 818 select BOOT_ELF32
>> 819 select HAVE_PATA_PLATFORM
>> 820 select SIBYTE_SB1250
>> 821 select SWAP_IO_SPACE
>> 822 select SYS_HAS_CPU_SB1
>> 823 select SYS_SUPPORTS_BIG_ENDIAN
>> 824 select SYS_SUPPORTS_HIGHMEM
>> 825 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 826 select ZONE_DMA32 if 64BIT
>> 827 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 828
>> 829 config SIBYTE_LITTLESUR
>> 830 bool "Sibyte BCM91250C2-LittleSur"
>> 831 select BOOT_ELF32
>> 832 select HAVE_PATA_PLATFORM
>> 833 select SIBYTE_SB1250
>> 834 select SWAP_IO_SPACE
>> 835 select SYS_HAS_CPU_SB1
>> 836 select SYS_SUPPORTS_BIG_ENDIAN
>> 837 select SYS_SUPPORTS_HIGHMEM
>> 838 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 839 select ZONE_DMA32 if 64BIT
>> 840
>> 841 config SIBYTE_SENTOSA
>> 842 bool "Sibyte BCM91250E-Sentosa"
>> 843 select BOOT_ELF32
>> 844 select SIBYTE_SB1250
>> 845 select SWAP_IO_SPACE
>> 846 select SYS_HAS_CPU_SB1
>> 847 select SYS_SUPPORTS_BIG_ENDIAN
>> 848 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 849 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 850
>> 851 config SIBYTE_BIGSUR
>> 852 bool "Sibyte BCM91480B-BigSur"
>> 853 select BOOT_ELF32
>> 854 select NR_CPUS_DEFAULT_4
>> 855 select SIBYTE_BCM1x80
>> 856 select SWAP_IO_SPACE
>> 857 select SYS_HAS_CPU_SB1
>> 858 select SYS_SUPPORTS_BIG_ENDIAN
>> 859 select SYS_SUPPORTS_HIGHMEM
>> 860 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 861 select ZONE_DMA32 if 64BIT
>> 862 select SWIOTLB if ARCH_DMA_ADDR_T_64BIT && PCI
>> 863
>> 864 config SNI_RM
>> 865 bool "SNI RM200/300/400"
>> 866 select ARC_MEMORY
>> 867 select ARC_PROMLIB
>> 868 select FW_ARC if CPU_LITTLE_ENDIAN
>> 869 select FW_ARC32 if CPU_LITTLE_ENDIAN
>> 870 select FW_SNIPROM if CPU_BIG_ENDIAN
>> 871 select ARCH_MAY_HAVE_PC_FDC
>> 872 select ARCH_MIGHT_HAVE_PC_PARPORT
>> 873 select ARCH_MIGHT_HAVE_PC_SERIO
>> 874 select BOOT_ELF32
>> 875 select CEVT_R4K
>> 876 select CSRC_R4K
>> 877 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
>> 878 select DMA_NONCOHERENT
>> 879 select GENERIC_ISA_DMA
>> 880 select HAVE_EISA
>> 881 select HAVE_PCSPKR_PLATFORM
>> 882 select HAVE_PCI
>> 883 select IRQ_MIPS_CPU
>> 884 select I8253
>> 885 select I8259
>> 886 select ISA
>> 887 select MIPS_L1_CACHE_SHIFT_6
>> 888 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
>> 889 select SYS_HAS_CPU_R4X00
>> 890 select SYS_HAS_CPU_R5000
>> 891 select SYS_HAS_CPU_R10000
>> 892 select R5000_CPU_SCACHE
>> 893 select SYS_HAS_EARLY_PRINTK
>> 894 select SYS_SUPPORTS_32BIT_KERNEL
>> 895 select SYS_SUPPORTS_64BIT_KERNEL
>> 896 select SYS_SUPPORTS_BIG_ENDIAN
>> 897 select SYS_SUPPORTS_HIGHMEM
>> 898 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 899 select WAR_R4600_V2_HIT_CACHEOP
>> 900 help
>> 901 The SNI RM200/300/400 are MIPS-based machines manufactured by
>> 902 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
>> 903 Technology and now in turn merged with Fujitsu. Say Y here to
>> 904 support this machine type.
>> 905
>> 906 config MACH_TX49XX
>> 907 bool "Toshiba TX49 series based machines"
>> 908 select WAR_TX49XX_ICACHE_INDEX_INV
>> 909
>> 910 config MIKROTIK_RB532
>> 911 bool "Mikrotik RB532 boards"
>> 912 select CEVT_R4K
>> 913 select CSRC_R4K
>> 914 select DMA_NONCOHERENT
>> 915 select HAVE_PCI
>> 916 select IRQ_MIPS_CPU
>> 917 select SYS_HAS_CPU_MIPS32_R1
>> 918 select SYS_SUPPORTS_32BIT_KERNEL
>> 919 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 920 select SWAP_IO_SPACE
>> 921 select BOOT_RAW
>> 922 select GPIOLIB
>> 923 select MIPS_L1_CACHE_SHIFT_4
>> 924 help
>> 925 Support the Mikrotik(tm) RouterBoard 532 series,
>> 926 based on the IDT RC32434 SoC.
>> 927
>> 928 config CAVIUM_OCTEON_SOC
>> 929 bool "Cavium Networks Octeon SoC based boards"
>> 930 select CEVT_R4K
>> 931 select ARCH_HAS_PHYS_TO_DMA
>> 932 select HAVE_RAPIDIO
>> 933 select PHYS_ADDR_T_64BIT
>> 934 select SYS_SUPPORTS_64BIT_KERNEL
>> 935 select SYS_SUPPORTS_BIG_ENDIAN
>> 936 select EDAC_SUPPORT
>> 937 select EDAC_ATOMIC_SCRUB
>> 938 select SYS_SUPPORTS_LITTLE_ENDIAN
>> 939 select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
>> 940 select SYS_HAS_EARLY_PRINTK
>> 941 select SYS_HAS_CPU_CAVIUM_OCTEON
>> 942 select HAVE_PCI
>> 943 select HAVE_PLAT_DELAY
>> 944 select HAVE_PLAT_FW_INIT_CMDLINE
>> 945 select HAVE_PLAT_MEMCPY
>> 946 select ZONE_DMA32
>> 947 select GPIOLIB
>> 948 select USE_OF
>> 949 select ARCH_SPARSEMEM_ENABLE
>> 950 select SYS_SUPPORTS_SMP
>> 951 select NR_CPUS_DEFAULT_64
>> 952 select MIPS_NR_CPU_NR_MAP_1024
>> 953 select BUILTIN_DTB
>> 954 select MTD
>> 955 select MTD_COMPLEX_MAPPINGS
>> 956 select SWIOTLB
>> 957 select SYS_SUPPORTS_RELOCATABLE
>> 958 help
>> 959 This option supports all of the Octeon reference boards from Cavium
>> 960 Networks. It builds a kernel that dynamically determines the Octeon
>> 961 CPU type and supports all known board reference implementations.
>> 962 Some of the supported boards are:
>> 963 EBT3000
>> 964 EBH3000
>> 965 EBH3100
>> 966 Thunder
>> 967 Kodama
>> 968 Hikari
>> 969 Say Y here for most Octeon reference boards.
>> 970
>> 971 endchoice
>> 972
>> 973 source "arch/mips/alchemy/Kconfig"
>> 974 source "arch/mips/ath25/Kconfig"
>> 975 source "arch/mips/ath79/Kconfig"
>> 976 source "arch/mips/bcm47xx/Kconfig"
>> 977 source "arch/mips/bcm63xx/Kconfig"
>> 978 source "arch/mips/bmips/Kconfig"
>> 979 source "arch/mips/generic/Kconfig"
>> 980 source "arch/mips/ingenic/Kconfig"
>> 981 source "arch/mips/jazz/Kconfig"
>> 982 source "arch/mips/lantiq/Kconfig"
>> 983 source "arch/mips/pic32/Kconfig"
>> 984 source "arch/mips/ralink/Kconfig"
>> 985 source "arch/mips/sgi-ip27/Kconfig"
>> 986 source "arch/mips/sibyte/Kconfig"
>> 987 source "arch/mips/txx9/Kconfig"
>> 988 source "arch/mips/cavium-octeon/Kconfig"
>> 989 source "arch/mips/loongson2ef/Kconfig"
>> 990 source "arch/mips/loongson32/Kconfig"
>> 991 source "arch/mips/loongson64/Kconfig"
>> 992
>> 993 endmenu
67 994
68 config GENERIC_HWEIGHT 995 config GENERIC_HWEIGHT
69 def_bool y !! 996 bool
>> 997 default y
70 998
71 config ARCH_HAS_ILOG2_U32 !! 999 config GENERIC_CALIBRATE_DELAY
72 def_bool n !! 1000 bool
>> 1001 default y
73 1002
74 config ARCH_HAS_ILOG2_U64 !! 1003 config SCHED_OMIT_FRAME_POINTER
75 def_bool n !! 1004 bool
>> 1005 default y
>> 1006
>> 1007 #
>> 1008 # Select some configuration options automatically based on user selections.
>> 1009 #
>> 1010 config FW_ARC
>> 1011 bool
>> 1012
>> 1013 config ARCH_MAY_HAVE_PC_FDC
>> 1014 bool
>> 1015
>> 1016 config BOOT_RAW
>> 1017 bool
>> 1018
>> 1019 config CEVT_BCM1480
>> 1020 bool
>> 1021
>> 1022 config CEVT_DS1287
>> 1023 bool
>> 1024
>> 1025 config CEVT_GT641XX
>> 1026 bool
>> 1027
>> 1028 config CEVT_R4K
>> 1029 bool
>> 1030
>> 1031 config CEVT_SB1250
>> 1032 bool
>> 1033
>> 1034 config CEVT_TXX9
>> 1035 bool
>> 1036
>> 1037 config CSRC_BCM1480
>> 1038 bool
>> 1039
>> 1040 config CSRC_IOASIC
>> 1041 bool
>> 1042
>> 1043 config CSRC_R4K
>> 1044 select CLOCKSOURCE_WATCHDOG if CPU_FREQ
>> 1045 bool
>> 1046
>> 1047 config CSRC_SB1250
>> 1048 bool
>> 1049
>> 1050 config MIPS_CLOCK_VSYSCALL
>> 1051 def_bool CSRC_R4K || CLKSRC_MIPS_GIC
>> 1052
>> 1053 config GPIO_TXX9
>> 1054 select GPIOLIB
>> 1055 bool
>> 1056
>> 1057 config FW_CFE
>> 1058 bool
76 1059
77 config ARCH_MTD_XIP !! 1060 config ARCH_SUPPORTS_UPROBES
78 def_bool y 1061 def_bool y
79 1062
>> 1063 config DMA_NONCOHERENT
>> 1064 bool
>> 1065 #
>> 1066 # MIPS allows mixing "slightly different" Cacheability and Coherency
>> 1067 # Attribute bits. It is believed that the uncached access through
>> 1068 # KSEG1 and the implementation specific "uncached accelerated" used
>> 1069 # by pgprot_writcombine can be mixed, and the latter sometimes provides
>> 1070 # significant advantages.
>> 1071 #
>> 1072 select ARCH_HAS_SETUP_DMA_OPS
>> 1073 select ARCH_HAS_DMA_WRITE_COMBINE
>> 1074 select ARCH_HAS_DMA_PREP_COHERENT
>> 1075 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 1076 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
>> 1077 select ARCH_HAS_DMA_SET_UNCACHED
>> 1078 select DMA_NONCOHERENT_MMAP
>> 1079 select NEED_DMA_MAP_STATE
>> 1080
>> 1081 config SYS_HAS_EARLY_PRINTK
>> 1082 bool
>> 1083
>> 1084 config SYS_SUPPORTS_HOTPLUG_CPU
>> 1085 bool
>> 1086
>> 1087 config MIPS_BONITO64
>> 1088 bool
>> 1089
>> 1090 config MIPS_MSC
>> 1091 bool
>> 1092
>> 1093 config SYNC_R4K
>> 1094 bool
>> 1095
80 config NO_IOPORT_MAP 1096 config NO_IOPORT_MAP
81 def_bool n 1097 def_bool n
82 1098
83 config HZ !! 1099 config GENERIC_CSUM
84 int !! 1100 def_bool CPU_NO_LOAD_STORE_LR
85 default 100 <<
86 1101
87 config LOCKDEP_SUPPORT !! 1102 config GENERIC_ISA_DMA
88 def_bool y !! 1103 bool
>> 1104 select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
>> 1105 select ISA_DMA_API
89 1106
90 config STACKTRACE_SUPPORT !! 1107 config GENERIC_ISA_DMA_SUPPORT_BROKEN
91 def_bool y !! 1108 bool
>> 1109 select GENERIC_ISA_DMA
92 1110
93 config MMU !! 1111 config HAVE_PLAT_DELAY
94 def_bool n !! 1112 bool
95 select PFAULT <<
96 1113
97 config HAVE_XTENSA_GPIO32 !! 1114 config HAVE_PLAT_FW_INIT_CMDLINE
98 def_bool n !! 1115 bool
>> 1116
>> 1117 config HAVE_PLAT_MEMCPY
>> 1118 bool
99 1119
100 config KASAN_SHADOW_OFFSET !! 1120 config ISA_DMA_API
101 hex !! 1121 bool
102 default 0x6e400000 !! 1122
>> 1123 config SYS_SUPPORTS_RELOCATABLE
>> 1124 bool
>> 1125 help
>> 1126 Selected if the platform supports relocating the kernel.
>> 1127 The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
>> 1128 to allow access to command line and entropy sources.
>> 1129
>> 1130 #
>> 1131 # Endianness selection. Sufficiently obscure so many users don't know what to
>> 1132 # answer,so we try hard to limit the available choices. Also the use of a
>> 1133 # choice statement should be more obvious to the user.
>> 1134 #
>> 1135 choice
>> 1136 prompt "Endianness selection"
>> 1137 help
>> 1138 Some MIPS machines can be configured for either little or big endian
>> 1139 byte order. These modes require different kernels and a different
>> 1140 Linux distribution. In general there is one preferred byteorder for a
>> 1141 particular system but some systems are just as commonly used in the
>> 1142 one or the other endianness.
103 1143
104 config CPU_BIG_ENDIAN 1144 config CPU_BIG_ENDIAN
105 def_bool $(success,test "$(shell,echo !! 1145 bool "Big endian"
>> 1146 depends on SYS_SUPPORTS_BIG_ENDIAN
106 1147
107 config CPU_LITTLE_ENDIAN 1148 config CPU_LITTLE_ENDIAN
108 def_bool !CPU_BIG_ENDIAN !! 1149 bool "Little endian"
>> 1150 depends on SYS_SUPPORTS_LITTLE_ENDIAN
>> 1151
>> 1152 endchoice
>> 1153
>> 1154 config EXPORT_UASM
>> 1155 bool
>> 1156
>> 1157 config SYS_SUPPORTS_APM_EMULATION
>> 1158 bool
>> 1159
>> 1160 config SYS_SUPPORTS_BIG_ENDIAN
>> 1161 bool
>> 1162
>> 1163 config SYS_SUPPORTS_LITTLE_ENDIAN
>> 1164 bool
>> 1165
>> 1166 config MIPS_HUGE_TLB_SUPPORT
>> 1167 def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
>> 1168
>> 1169 config IRQ_TXX9
>> 1170 bool
>> 1171
>> 1172 config IRQ_GT641XX
>> 1173 bool
>> 1174
>> 1175 config PCI_GT64XXX_PCI0
>> 1176 bool
>> 1177
>> 1178 config PCI_XTALK_BRIDGE
>> 1179 bool
>> 1180
>> 1181 config NO_EXCEPT_FILL
>> 1182 bool
>> 1183
>> 1184 config MIPS_SPRAM
>> 1185 bool
>> 1186
>> 1187 config SWAP_IO_SPACE
>> 1188 bool
>> 1189
>> 1190 config SGI_HAS_INDYDOG
>> 1191 bool
>> 1192
>> 1193 config SGI_HAS_HAL2
>> 1194 bool
>> 1195
>> 1196 config SGI_HAS_SEEQ
>> 1197 bool
>> 1198
>> 1199 config SGI_HAS_WD93
>> 1200 bool
>> 1201
>> 1202 config SGI_HAS_ZILOG
>> 1203 bool
>> 1204
>> 1205 config SGI_HAS_I8042
>> 1206 bool
109 1207
110 config CC_HAVE_CALL0_ABI !! 1208 config DEFAULT_SGI_PARTITION
111 def_bool $(success,test "$(shell,echo !! 1209 bool
>> 1210
>> 1211 config FW_ARC32
>> 1212 bool
>> 1213
>> 1214 config FW_SNIPROM
>> 1215 bool
>> 1216
>> 1217 config BOOT_ELF32
>> 1218 bool
>> 1219
>> 1220 config MIPS_L1_CACHE_SHIFT_4
>> 1221 bool
>> 1222
>> 1223 config MIPS_L1_CACHE_SHIFT_5
>> 1224 bool
>> 1225
>> 1226 config MIPS_L1_CACHE_SHIFT_6
>> 1227 bool
>> 1228
>> 1229 config MIPS_L1_CACHE_SHIFT_7
>> 1230 bool
112 1231
113 menu "Processor type and features" !! 1232 config MIPS_L1_CACHE_SHIFT
>> 1233 int
>> 1234 default "7" if MIPS_L1_CACHE_SHIFT_7
>> 1235 default "6" if MIPS_L1_CACHE_SHIFT_6
>> 1236 default "5" if MIPS_L1_CACHE_SHIFT_5
>> 1237 default "4" if MIPS_L1_CACHE_SHIFT_4
>> 1238 default "5"
>> 1239
>> 1240 config ARC_CMDLINE_ONLY
>> 1241 bool
>> 1242
>> 1243 config ARC_CONSOLE
>> 1244 bool "ARC console support"
>> 1245 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
>> 1246
>> 1247 config ARC_MEMORY
>> 1248 bool
>> 1249
>> 1250 config ARC_PROMLIB
>> 1251 bool
>> 1252
>> 1253 config FW_ARC64
>> 1254 bool
>> 1255
>> 1256 config BOOT_ELF64
>> 1257 bool
>> 1258
>> 1259 menu "CPU selection"
114 1260
115 choice 1261 choice
116 prompt "Xtensa Processor Configuration !! 1262 prompt "CPU type"
117 default XTENSA_VARIANT_FSF !! 1263 default CPU_R4X00
118 1264
119 config XTENSA_VARIANT_FSF !! 1265 config CPU_LOONGSON64
120 bool "fsf - default (not generic) conf !! 1266 bool "Loongson 64-bit CPU"
121 select MMU !! 1267 depends on SYS_HAS_CPU_LOONGSON64
>> 1268 select ARCH_HAS_PHYS_TO_DMA
>> 1269 select CPU_MIPSR2
>> 1270 select CPU_HAS_PREFETCH
>> 1271 select CPU_SUPPORTS_64BIT_KERNEL
>> 1272 select CPU_SUPPORTS_HIGHMEM
>> 1273 select CPU_SUPPORTS_HUGEPAGES
>> 1274 select CPU_SUPPORTS_MSA
>> 1275 select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
>> 1276 select CPU_MIPSR2_IRQ_VI
>> 1277 select DMA_NONCOHERENT
>> 1278 select WEAK_ORDERING
>> 1279 select WEAK_REORDERING_BEYOND_LLSC
>> 1280 select MIPS_ASID_BITS_VARIABLE
>> 1281 select MIPS_PGD_C0_CONTEXT
>> 1282 select MIPS_L1_CACHE_SHIFT_6
>> 1283 select MIPS_FP_SUPPORT
>> 1284 select GPIOLIB
>> 1285 select SWIOTLB
>> 1286 select HAVE_KVM
>> 1287 help
>> 1288 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
>> 1289 cores implements the MIPS64R2 instruction set with many extensions,
>> 1290 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
>> 1291 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
>> 1292 Loongson-2E/2F is not covered here and will be removed in future.
122 1293
123 config XTENSA_VARIANT_DC232B !! 1294 config LOONGSON3_ENHANCEMENT
124 bool "dc232b - Diamond 232L Standard C !! 1295 bool "New Loongson-3 CPU Enhancements"
125 select MMU !! 1296 default n
126 select HAVE_XTENSA_GPIO32 !! 1297 depends on CPU_LOONGSON64
127 help 1298 help
128 This variant refers to Tensilica's D !! 1299 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
129 !! 1300 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
130 config XTENSA_VARIANT_DC233C !! 1301 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
131 bool "dc233c - Diamond 233L Standard C !! 1302 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
132 select MMU !! 1303 Fast TLB refill support, etc.
133 select HAVE_XTENSA_GPIO32 !! 1304
>> 1305 This option enable those enhancements which are not probed at run
>> 1306 time. If you want a generic kernel to run on all Loongson 3 machines,
>> 1307 please say 'N' here. If you want a high-performance kernel to run on
>> 1308 new Loongson-3 machines only, please say 'Y' here.
>> 1309
>> 1310 config CPU_LOONGSON3_WORKAROUNDS
>> 1311 bool "Loongson-3 LLSC Workarounds"
>> 1312 default y if SMP
>> 1313 depends on CPU_LOONGSON64
134 help 1314 help
135 This variant refers to Tensilica's D !! 1315 Loongson-3 processors have the llsc issues which require workarounds.
>> 1316 Without workarounds the system may hang unexpectedly.
136 1317
137 config XTENSA_VARIANT_CUSTOM !! 1318 Say Y, unless you know what you are doing.
138 bool "Custom Xtensa processor configur !! 1319
139 select HAVE_XTENSA_GPIO32 !! 1320 config CPU_LOONGSON3_CPUCFG_EMULATION
>> 1321 bool "Emulate the CPUCFG instruction on older Loongson cores"
>> 1322 default y
>> 1323 depends on CPU_LOONGSON64
>> 1324 help
>> 1325 Loongson-3A R4 and newer have the CPUCFG instruction available for
>> 1326 userland to query CPU capabilities, much like CPUID on x86. This
>> 1327 option provides emulation of the instruction on older Loongson
>> 1328 cores, back to Loongson-3A1000.
>> 1329
>> 1330 If unsure, please say Y.
>> 1331
>> 1332 config CPU_LOONGSON2E
>> 1333 bool "Loongson 2E"
>> 1334 depends on SYS_HAS_CPU_LOONGSON2E
>> 1335 select CPU_LOONGSON2EF
>> 1336 help
>> 1337 The Loongson 2E processor implements the MIPS III instruction set
>> 1338 with many extensions.
>> 1339
>> 1340 It has an internal FPGA northbridge, which is compatible to
>> 1341 bonito64.
>> 1342
>> 1343 config CPU_LOONGSON2F
>> 1344 bool "Loongson 2F"
>> 1345 depends on SYS_HAS_CPU_LOONGSON2F
>> 1346 select CPU_LOONGSON2EF
>> 1347 help
>> 1348 The Loongson 2F processor implements the MIPS III instruction set
>> 1349 with many extensions.
>> 1350
>> 1351 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
>> 1352 have a similar programming interface with FPGA northbridge used in
>> 1353 Loongson2E.
>> 1354
>> 1355 config CPU_LOONGSON1B
>> 1356 bool "Loongson 1B"
>> 1357 depends on SYS_HAS_CPU_LOONGSON1B
>> 1358 select CPU_LOONGSON32
>> 1359 select LEDS_GPIO_REGISTER
>> 1360 help
>> 1361 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
>> 1362 Release 1 instruction set and part of the MIPS32 Release 2
>> 1363 instruction set.
>> 1364
>> 1365 config CPU_LOONGSON1C
>> 1366 bool "Loongson 1C"
>> 1367 depends on SYS_HAS_CPU_LOONGSON1C
>> 1368 select CPU_LOONGSON32
>> 1369 select LEDS_GPIO_REGISTER
>> 1370 help
>> 1371 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
>> 1372 Release 1 instruction set and part of the MIPS32 Release 2
>> 1373 instruction set.
>> 1374
>> 1375 config CPU_MIPS32_R1
>> 1376 bool "MIPS32 Release 1"
>> 1377 depends on SYS_HAS_CPU_MIPS32_R1
>> 1378 select CPU_HAS_PREFETCH
>> 1379 select CPU_SUPPORTS_32BIT_KERNEL
>> 1380 select CPU_SUPPORTS_HIGHMEM
>> 1381 help
>> 1382 Choose this option to build a kernel for release 1 or later of the
>> 1383 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1384 MIPS processor are based on a MIPS32 processor. If you know the
>> 1385 specific type of processor in your system, choose those that one
>> 1386 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1387 Release 2 of the MIPS32 architecture is available since several
>> 1388 years so chances are you even have a MIPS32 Release 2 processor
>> 1389 in which case you should choose CPU_MIPS32_R2 instead for better
>> 1390 performance.
>> 1391
>> 1392 config CPU_MIPS32_R2
>> 1393 bool "MIPS32 Release 2"
>> 1394 depends on SYS_HAS_CPU_MIPS32_R2
>> 1395 select CPU_HAS_PREFETCH
>> 1396 select CPU_SUPPORTS_32BIT_KERNEL
>> 1397 select CPU_SUPPORTS_HIGHMEM
>> 1398 select CPU_SUPPORTS_MSA
>> 1399 select HAVE_KVM
>> 1400 help
>> 1401 Choose this option to build a kernel for release 2 or later of the
>> 1402 MIPS32 architecture. Most modern embedded systems with a 32-bit
>> 1403 MIPS processor are based on a MIPS32 processor. If you know the
>> 1404 specific type of processor in your system, choose those that one
>> 1405 otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
>> 1406
>> 1407 config CPU_MIPS32_R5
>> 1408 bool "MIPS32 Release 5"
>> 1409 depends on SYS_HAS_CPU_MIPS32_R5
>> 1410 select CPU_HAS_PREFETCH
>> 1411 select CPU_SUPPORTS_32BIT_KERNEL
>> 1412 select CPU_SUPPORTS_HIGHMEM
>> 1413 select CPU_SUPPORTS_MSA
>> 1414 select HAVE_KVM
>> 1415 select MIPS_O32_FP64_SUPPORT
>> 1416 help
>> 1417 Choose this option to build a kernel for release 5 or later of the
>> 1418 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1419 family, are based on a MIPS32r5 processor. If you own an older
>> 1420 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1421
>> 1422 config CPU_MIPS32_R6
>> 1423 bool "MIPS32 Release 6"
>> 1424 depends on SYS_HAS_CPU_MIPS32_R6
>> 1425 select CPU_HAS_PREFETCH
>> 1426 select CPU_NO_LOAD_STORE_LR
>> 1427 select CPU_SUPPORTS_32BIT_KERNEL
>> 1428 select CPU_SUPPORTS_HIGHMEM
>> 1429 select CPU_SUPPORTS_MSA
>> 1430 select HAVE_KVM
>> 1431 select MIPS_O32_FP64_SUPPORT
>> 1432 help
>> 1433 Choose this option to build a kernel for release 6 or later of the
>> 1434 MIPS32 architecture. New MIPS processors, starting with the Warrior
>> 1435 family, are based on a MIPS32r6 processor. If you own an older
>> 1436 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
>> 1437
>> 1438 config CPU_MIPS64_R1
>> 1439 bool "MIPS64 Release 1"
>> 1440 depends on SYS_HAS_CPU_MIPS64_R1
>> 1441 select CPU_HAS_PREFETCH
>> 1442 select CPU_SUPPORTS_32BIT_KERNEL
>> 1443 select CPU_SUPPORTS_64BIT_KERNEL
>> 1444 select CPU_SUPPORTS_HIGHMEM
>> 1445 select CPU_SUPPORTS_HUGEPAGES
>> 1446 help
>> 1447 Choose this option to build a kernel for release 1 or later of the
>> 1448 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1449 MIPS processor are based on a MIPS64 processor. If you know the
>> 1450 specific type of processor in your system, choose those that one
>> 1451 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1452 Release 2 of the MIPS64 architecture is available since several
>> 1453 years so chances are you even have a MIPS64 Release 2 processor
>> 1454 in which case you should choose CPU_MIPS64_R2 instead for better
>> 1455 performance.
>> 1456
>> 1457 config CPU_MIPS64_R2
>> 1458 bool "MIPS64 Release 2"
>> 1459 depends on SYS_HAS_CPU_MIPS64_R2
>> 1460 select CPU_HAS_PREFETCH
>> 1461 select CPU_SUPPORTS_32BIT_KERNEL
>> 1462 select CPU_SUPPORTS_64BIT_KERNEL
>> 1463 select CPU_SUPPORTS_HIGHMEM
>> 1464 select CPU_SUPPORTS_HUGEPAGES
>> 1465 select CPU_SUPPORTS_MSA
>> 1466 select HAVE_KVM
>> 1467 help
>> 1468 Choose this option to build a kernel for release 2 or later of the
>> 1469 MIPS64 architecture. Many modern embedded systems with a 64-bit
>> 1470 MIPS processor are based on a MIPS64 processor. If you know the
>> 1471 specific type of processor in your system, choose those that one
>> 1472 otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
>> 1473
>> 1474 config CPU_MIPS64_R5
>> 1475 bool "MIPS64 Release 5"
>> 1476 depends on SYS_HAS_CPU_MIPS64_R5
>> 1477 select CPU_HAS_PREFETCH
>> 1478 select CPU_SUPPORTS_32BIT_KERNEL
>> 1479 select CPU_SUPPORTS_64BIT_KERNEL
>> 1480 select CPU_SUPPORTS_HIGHMEM
>> 1481 select CPU_SUPPORTS_HUGEPAGES
>> 1482 select CPU_SUPPORTS_MSA
>> 1483 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1484 select HAVE_KVM
>> 1485 help
>> 1486 Choose this option to build a kernel for release 5 or later of the
>> 1487 MIPS64 architecture. This is a intermediate MIPS architecture
>> 1488 release partly implementing release 6 features. Though there is no
>> 1489 any hardware known to be based on this release.
>> 1490
>> 1491 config CPU_MIPS64_R6
>> 1492 bool "MIPS64 Release 6"
>> 1493 depends on SYS_HAS_CPU_MIPS64_R6
>> 1494 select CPU_HAS_PREFETCH
>> 1495 select CPU_NO_LOAD_STORE_LR
>> 1496 select CPU_SUPPORTS_32BIT_KERNEL
>> 1497 select CPU_SUPPORTS_64BIT_KERNEL
>> 1498 select CPU_SUPPORTS_HIGHMEM
>> 1499 select CPU_SUPPORTS_HUGEPAGES
>> 1500 select CPU_SUPPORTS_MSA
>> 1501 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
>> 1502 select HAVE_KVM
>> 1503 help
>> 1504 Choose this option to build a kernel for release 6 or later of the
>> 1505 MIPS64 architecture. New MIPS processors, starting with the Warrior
>> 1506 family, are based on a MIPS64r6 processor. If you own an older
>> 1507 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
>> 1508
>> 1509 config CPU_P5600
>> 1510 bool "MIPS Warrior P5600"
>> 1511 depends on SYS_HAS_CPU_P5600
>> 1512 select CPU_HAS_PREFETCH
>> 1513 select CPU_SUPPORTS_32BIT_KERNEL
>> 1514 select CPU_SUPPORTS_HIGHMEM
>> 1515 select CPU_SUPPORTS_MSA
>> 1516 select CPU_SUPPORTS_CPUFREQ
>> 1517 select CPU_MIPSR2_IRQ_VI
>> 1518 select CPU_MIPSR2_IRQ_EI
>> 1519 select HAVE_KVM
>> 1520 select MIPS_O32_FP64_SUPPORT
>> 1521 help
>> 1522 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
>> 1523 It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
>> 1524 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
>> 1525 level features like up to six P5600 calculation cores, CM2 with L2
>> 1526 cache, IOCU/IOMMU (though might be unused depending on the system-
>> 1527 specific IP core configuration), GIC, CPC, virtualisation module,
>> 1528 eJTAG and PDtrace.
>> 1529
>> 1530 config CPU_R3000
>> 1531 bool "R3000"
>> 1532 depends on SYS_HAS_CPU_R3000
>> 1533 select CPU_HAS_WB
>> 1534 select CPU_R3K_TLB
>> 1535 select CPU_SUPPORTS_32BIT_KERNEL
>> 1536 select CPU_SUPPORTS_HIGHMEM
>> 1537 help
>> 1538 Please make sure to pick the right CPU type. Linux/MIPS is not
>> 1539 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
>> 1540 *not* work on R4000 machines and vice versa. However, since most
>> 1541 of the supported machines have an R4000 (or similar) CPU, R4x00
>> 1542 might be a safe bet. If the resulting kernel does not work,
>> 1543 try to recompile with R3000.
>> 1544
>> 1545 config CPU_R4300
>> 1546 bool "R4300"
>> 1547 depends on SYS_HAS_CPU_R4300
>> 1548 select CPU_SUPPORTS_32BIT_KERNEL
>> 1549 select CPU_SUPPORTS_64BIT_KERNEL
>> 1550 help
>> 1551 MIPS Technologies R4300-series processors.
>> 1552
>> 1553 config CPU_R4X00
>> 1554 bool "R4x00"
>> 1555 depends on SYS_HAS_CPU_R4X00
>> 1556 select CPU_SUPPORTS_32BIT_KERNEL
>> 1557 select CPU_SUPPORTS_64BIT_KERNEL
>> 1558 select CPU_SUPPORTS_HUGEPAGES
>> 1559 help
>> 1560 MIPS Technologies R4000-series processors other than 4300, including
>> 1561 the R4000, R4400, R4600, and 4700.
>> 1562
>> 1563 config CPU_TX49XX
>> 1564 bool "R49XX"
>> 1565 depends on SYS_HAS_CPU_TX49XX
>> 1566 select CPU_HAS_PREFETCH
>> 1567 select CPU_SUPPORTS_32BIT_KERNEL
>> 1568 select CPU_SUPPORTS_64BIT_KERNEL
>> 1569 select CPU_SUPPORTS_HUGEPAGES
>> 1570
>> 1571 config CPU_R5000
>> 1572 bool "R5000"
>> 1573 depends on SYS_HAS_CPU_R5000
>> 1574 select CPU_SUPPORTS_32BIT_KERNEL
>> 1575 select CPU_SUPPORTS_64BIT_KERNEL
>> 1576 select CPU_SUPPORTS_HUGEPAGES
>> 1577 help
>> 1578 MIPS Technologies R5000-series processors other than the Nevada.
>> 1579
>> 1580 config CPU_R5500
>> 1581 bool "R5500"
>> 1582 depends on SYS_HAS_CPU_R5500
>> 1583 select CPU_SUPPORTS_32BIT_KERNEL
>> 1584 select CPU_SUPPORTS_64BIT_KERNEL
>> 1585 select CPU_SUPPORTS_HUGEPAGES
>> 1586 help
>> 1587 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
>> 1588 instruction set.
>> 1589
>> 1590 config CPU_NEVADA
>> 1591 bool "RM52xx"
>> 1592 depends on SYS_HAS_CPU_NEVADA
>> 1593 select CPU_SUPPORTS_32BIT_KERNEL
>> 1594 select CPU_SUPPORTS_64BIT_KERNEL
>> 1595 select CPU_SUPPORTS_HUGEPAGES
>> 1596 help
>> 1597 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
>> 1598
>> 1599 config CPU_R10000
>> 1600 bool "R10000"
>> 1601 depends on SYS_HAS_CPU_R10000
>> 1602 select CPU_HAS_PREFETCH
>> 1603 select CPU_SUPPORTS_32BIT_KERNEL
>> 1604 select CPU_SUPPORTS_64BIT_KERNEL
>> 1605 select CPU_SUPPORTS_HIGHMEM
>> 1606 select CPU_SUPPORTS_HUGEPAGES
>> 1607 help
>> 1608 MIPS Technologies R10000-series processors.
>> 1609
>> 1610 config CPU_RM7000
>> 1611 bool "RM7000"
>> 1612 depends on SYS_HAS_CPU_RM7000
>> 1613 select CPU_HAS_PREFETCH
>> 1614 select CPU_SUPPORTS_32BIT_KERNEL
>> 1615 select CPU_SUPPORTS_64BIT_KERNEL
>> 1616 select CPU_SUPPORTS_HIGHMEM
>> 1617 select CPU_SUPPORTS_HUGEPAGES
>> 1618
>> 1619 config CPU_SB1
>> 1620 bool "SB1"
>> 1621 depends on SYS_HAS_CPU_SB1
>> 1622 select CPU_SUPPORTS_32BIT_KERNEL
>> 1623 select CPU_SUPPORTS_64BIT_KERNEL
>> 1624 select CPU_SUPPORTS_HIGHMEM
>> 1625 select CPU_SUPPORTS_HUGEPAGES
>> 1626 select WEAK_ORDERING
>> 1627
>> 1628 config CPU_CAVIUM_OCTEON
>> 1629 bool "Cavium Octeon processor"
>> 1630 depends on SYS_HAS_CPU_CAVIUM_OCTEON
>> 1631 select CPU_HAS_PREFETCH
>> 1632 select CPU_SUPPORTS_64BIT_KERNEL
>> 1633 select WEAK_ORDERING
>> 1634 select CPU_SUPPORTS_HIGHMEM
>> 1635 select CPU_SUPPORTS_HUGEPAGES
>> 1636 select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1637 select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
>> 1638 select MIPS_L1_CACHE_SHIFT_7
>> 1639 select HAVE_KVM
>> 1640 help
>> 1641 The Cavium Octeon processor is a highly integrated chip containing
>> 1642 many ethernet hardware widgets for networking tasks. The processor
>> 1643 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
>> 1644 Full details can be found at http://www.caviumnetworks.com.
>> 1645
>> 1646 config CPU_BMIPS
>> 1647 bool "Broadcom BMIPS"
>> 1648 depends on SYS_HAS_CPU_BMIPS
>> 1649 select CPU_MIPS32
>> 1650 select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
>> 1651 select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
>> 1652 select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
>> 1653 select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
>> 1654 select CPU_SUPPORTS_32BIT_KERNEL
>> 1655 select DMA_NONCOHERENT
>> 1656 select IRQ_MIPS_CPU
>> 1657 select SWAP_IO_SPACE
>> 1658 select WEAK_ORDERING
>> 1659 select CPU_SUPPORTS_HIGHMEM
>> 1660 select CPU_HAS_PREFETCH
>> 1661 select CPU_SUPPORTS_CPUFREQ
>> 1662 select MIPS_EXTERNAL_TIMER
>> 1663 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
140 help 1664 help
141 Select this variant to use a custom !! 1665 Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
142 You will be prompted for a processor !! 1666
143 endchoice 1667 endchoice
144 1668
145 config XTENSA_VARIANT_CUSTOM_NAME !! 1669 config CPU_MIPS32_3_5_FEATURES
146 string "Xtensa Processor Custom Core V !! 1670 bool "MIPS32 Release 3.5 Features"
147 depends on XTENSA_VARIANT_CUSTOM !! 1671 depends on SYS_HAS_CPU_MIPS32_R3_5
148 help !! 1672 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
149 Provide the name of a custom Xtensa !! 1673 CPU_P5600
150 This CORENAME selects arch/xtensa/va !! 1674 help
151 Don't forget you have to select MMU !! 1675 Choose this option to build a kernel for release 2 or later of the
152 !! 1676 MIPS32 architecture including features from the 3.5 release such as
153 config XTENSA_VARIANT_NAME !! 1677 support for Enhanced Virtual Addressing (EVA).
154 string !! 1678
155 default "dc232b" !! 1679 config CPU_MIPS32_3_5_EVA
156 default "dc233c" !! 1680 bool "Enhanced Virtual Addressing (EVA)"
157 default "fsf" !! 1681 depends on CPU_MIPS32_3_5_FEATURES
158 default XTENSA_VARIANT_CUSTOM_NAME !! 1682 select EVA
159 !! 1683 default y
160 config XTENSA_VARIANT_MMU !! 1684 help
161 bool "Core variant has a Full MMU (TLB !! 1685 Choose this option if you want to enable the Enhanced Virtual
162 depends on XTENSA_VARIANT_CUSTOM !! 1686 Addressing (EVA) on your MIPS32 core (such as proAptiv).
163 default y !! 1687 One of its primary benefits is an increase in the maximum size
164 select MMU !! 1688 of lowmem (up to 3GB). If unsure, say 'N' here.
165 help !! 1689
166 Build a Conventional Kernel with ful !! 1690 config CPU_MIPS32_R5_FEATURES
167 ie: it supports a TLB with auto-load !! 1691 bool "MIPS32 Release 5 Features"
168 !! 1692 depends on SYS_HAS_CPU_MIPS32_R5
169 config XTENSA_VARIANT_HAVE_PERF_EVENTS !! 1693 depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
170 bool "Core variant has Performance Mon !! 1694 help
171 depends on XTENSA_VARIANT_CUSTOM !! 1695 Choose this option to build a kernel for release 2 or later of the
>> 1696 MIPS32 architecture including features from release 5 such as
>> 1697 support for Extended Physical Addressing (XPA).
>> 1698
>> 1699 config CPU_MIPS32_R5_XPA
>> 1700 bool "Extended Physical Addressing (XPA)"
>> 1701 depends on CPU_MIPS32_R5_FEATURES
>> 1702 depends on !EVA
>> 1703 depends on !PAGE_SIZE_4KB
>> 1704 depends on SYS_SUPPORTS_HIGHMEM
>> 1705 select XPA
>> 1706 select HIGHMEM
>> 1707 select PHYS_ADDR_T_64BIT
172 default n 1708 default n
173 help 1709 help
174 Enable if core variant has Performan !! 1710 Choose this option if you want to enable the Extended Physical
175 External Registers Interface. !! 1711 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
>> 1712 benefit is to increase physical addressing equal to or greater
>> 1713 than 40 bits. Note that this has the side effect of turning on
>> 1714 64-bit addressing which in turn makes the PTEs 64-bit in size.
>> 1715 If unsure, say 'N' here.
176 1716
177 If unsure, say N. !! 1717 if CPU_LOONGSON2F
>> 1718 config CPU_NOP_WORKAROUNDS
>> 1719 bool
178 1720
179 config XTENSA_FAKE_NMI !! 1721 config CPU_JUMP_WORKAROUNDS
180 bool "Treat PMM IRQ as NMI" !! 1722 bool
181 depends on XTENSA_VARIANT_HAVE_PERF_EV !! 1723
182 default n !! 1724 config CPU_LOONGSON2F_WORKAROUNDS
>> 1725 bool "Loongson 2F Workarounds"
>> 1726 default y
>> 1727 select CPU_NOP_WORKAROUNDS
>> 1728 select CPU_JUMP_WORKAROUNDS
183 help 1729 help
184 If PMM IRQ is the only IRQ at EXCM l !! 1730 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
185 treat it as NMI, which improves accu !! 1731 require workarounds. Without workarounds the system may hang
>> 1732 unexpectedly. For more information please refer to the gas
>> 1733 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
>> 1734
>> 1735 Loongson 2F03 and later have fixed these issues and no workarounds
>> 1736 are needed. The workarounds have no significant side effect on them
>> 1737 but may decrease the performance of the system so this option should
>> 1738 be disabled unless the kernel is intended to be run on 2F01 or 2F02
>> 1739 systems.
186 1740
187 If there are other interrupts at or !! 1741 If unsure, please say Y.
188 but not above the EXCM level, PMM IR !! 1742 endif # CPU_LOONGSON2F
189 but only if these IRQs are not used. <<
190 saying that this is not safe, and a <<
191 actually fire. <<
192 1743
193 If unsure, say N. !! 1744 config SYS_SUPPORTS_ZBOOT
>> 1745 bool
>> 1746 select HAVE_KERNEL_GZIP
>> 1747 select HAVE_KERNEL_BZIP2
>> 1748 select HAVE_KERNEL_LZ4
>> 1749 select HAVE_KERNEL_LZMA
>> 1750 select HAVE_KERNEL_LZO
>> 1751 select HAVE_KERNEL_XZ
>> 1752 select HAVE_KERNEL_ZSTD
194 1753
195 config PFAULT !! 1754 config SYS_SUPPORTS_ZBOOT_UART16550
196 bool "Handle protection faults" if EXP !! 1755 bool
197 default y !! 1756 select SYS_SUPPORTS_ZBOOT
>> 1757
>> 1758 config SYS_SUPPORTS_ZBOOT_UART_PROM
>> 1759 bool
>> 1760 select SYS_SUPPORTS_ZBOOT
>> 1761
>> 1762 config CPU_LOONGSON2EF
>> 1763 bool
>> 1764 select CPU_SUPPORTS_32BIT_KERNEL
>> 1765 select CPU_SUPPORTS_64BIT_KERNEL
>> 1766 select CPU_SUPPORTS_HIGHMEM
>> 1767 select CPU_SUPPORTS_HUGEPAGES
>> 1768
>> 1769 config CPU_LOONGSON32
>> 1770 bool
>> 1771 select CPU_MIPS32
>> 1772 select CPU_MIPSR2
>> 1773 select CPU_HAS_PREFETCH
>> 1774 select CPU_SUPPORTS_32BIT_KERNEL
>> 1775 select CPU_SUPPORTS_HIGHMEM
>> 1776 select CPU_SUPPORTS_CPUFREQ
>> 1777
>> 1778 config CPU_BMIPS32_3300
>> 1779 select SMP_UP if SMP
>> 1780 bool
>> 1781
>> 1782 config CPU_BMIPS4350
>> 1783 bool
>> 1784 select SYS_SUPPORTS_SMP
>> 1785 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1786
>> 1787 config CPU_BMIPS4380
>> 1788 bool
>> 1789 select MIPS_L1_CACHE_SHIFT_6
>> 1790 select SYS_SUPPORTS_SMP
>> 1791 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1792 select CPU_HAS_RIXI
>> 1793
>> 1794 config CPU_BMIPS5000
>> 1795 bool
>> 1796 select MIPS_CPU_SCACHE
>> 1797 select MIPS_L1_CACHE_SHIFT_7
>> 1798 select SYS_SUPPORTS_SMP
>> 1799 select SYS_SUPPORTS_HOTPLUG_CPU
>> 1800 select CPU_HAS_RIXI
>> 1801
>> 1802 config SYS_HAS_CPU_LOONGSON64
>> 1803 bool
>> 1804 select CPU_SUPPORTS_CPUFREQ
>> 1805 select CPU_HAS_RIXI
>> 1806
>> 1807 config SYS_HAS_CPU_LOONGSON2E
>> 1808 bool
>> 1809
>> 1810 config SYS_HAS_CPU_LOONGSON2F
>> 1811 bool
>> 1812 select CPU_SUPPORTS_CPUFREQ
>> 1813 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
>> 1814
>> 1815 config SYS_HAS_CPU_LOONGSON1B
>> 1816 bool
>> 1817
>> 1818 config SYS_HAS_CPU_LOONGSON1C
>> 1819 bool
>> 1820
>> 1821 config SYS_HAS_CPU_MIPS32_R1
>> 1822 bool
>> 1823
>> 1824 config SYS_HAS_CPU_MIPS32_R2
>> 1825 bool
>> 1826
>> 1827 config SYS_HAS_CPU_MIPS32_R3_5
>> 1828 bool
>> 1829
>> 1830 config SYS_HAS_CPU_MIPS32_R5
>> 1831 bool
>> 1832
>> 1833 config SYS_HAS_CPU_MIPS32_R6
>> 1834 bool
>> 1835
>> 1836 config SYS_HAS_CPU_MIPS64_R1
>> 1837 bool
>> 1838
>> 1839 config SYS_HAS_CPU_MIPS64_R2
>> 1840 bool
>> 1841
>> 1842 config SYS_HAS_CPU_MIPS64_R5
>> 1843 bool
>> 1844
>> 1845 config SYS_HAS_CPU_MIPS64_R6
>> 1846 bool
>> 1847
>> 1848 config SYS_HAS_CPU_P5600
>> 1849 bool
>> 1850
>> 1851 config SYS_HAS_CPU_R3000
>> 1852 bool
>> 1853
>> 1854 config SYS_HAS_CPU_R4300
>> 1855 bool
>> 1856
>> 1857 config SYS_HAS_CPU_R4X00
>> 1858 bool
>> 1859
>> 1860 config SYS_HAS_CPU_TX49XX
>> 1861 bool
>> 1862
>> 1863 config SYS_HAS_CPU_R5000
>> 1864 bool
>> 1865
>> 1866 config SYS_HAS_CPU_R5500
>> 1867 bool
>> 1868
>> 1869 config SYS_HAS_CPU_NEVADA
>> 1870 bool
>> 1871
>> 1872 config SYS_HAS_CPU_R10000
>> 1873 bool
>> 1874
>> 1875 config SYS_HAS_CPU_RM7000
>> 1876 bool
>> 1877
>> 1878 config SYS_HAS_CPU_SB1
>> 1879 bool
>> 1880
>> 1881 config SYS_HAS_CPU_CAVIUM_OCTEON
>> 1882 bool
>> 1883
>> 1884 config SYS_HAS_CPU_BMIPS
>> 1885 bool
>> 1886
>> 1887 config SYS_HAS_CPU_BMIPS32_3300
>> 1888 bool
>> 1889 select SYS_HAS_CPU_BMIPS
>> 1890
>> 1891 config SYS_HAS_CPU_BMIPS4350
>> 1892 bool
>> 1893 select SYS_HAS_CPU_BMIPS
>> 1894
>> 1895 config SYS_HAS_CPU_BMIPS4380
>> 1896 bool
>> 1897 select SYS_HAS_CPU_BMIPS
>> 1898
>> 1899 config SYS_HAS_CPU_BMIPS5000
>> 1900 bool
>> 1901 select SYS_HAS_CPU_BMIPS
>> 1902
>> 1903 #
>> 1904 # CPU may reorder R->R, R->W, W->R, W->W
>> 1905 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
>> 1906 #
>> 1907 config WEAK_ORDERING
>> 1908 bool
>> 1909
>> 1910 #
>> 1911 # CPU may reorder reads and writes beyond LL/SC
>> 1912 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
>> 1913 #
>> 1914 config WEAK_REORDERING_BEYOND_LLSC
>> 1915 bool
>> 1916 endmenu
>> 1917
>> 1918 #
>> 1919 # These two indicate any level of the MIPS32 and MIPS64 architecture
>> 1920 #
>> 1921 config CPU_MIPS32
>> 1922 bool
>> 1923 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
>> 1924 CPU_MIPS32_R6 || CPU_P5600
>> 1925
>> 1926 config CPU_MIPS64
>> 1927 bool
>> 1928 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \
>> 1929 CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
>> 1930
>> 1931 #
>> 1932 # These indicate the revision of the architecture
>> 1933 #
>> 1934 config CPU_MIPSR1
>> 1935 bool
>> 1936 default y if CPU_MIPS32_R1 || CPU_MIPS64_R1
>> 1937
>> 1938 config CPU_MIPSR2
>> 1939 bool
>> 1940 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
>> 1941 select CPU_HAS_RIXI
>> 1942 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1943 select MIPS_SPRAM
>> 1944
>> 1945 config CPU_MIPSR5
>> 1946 bool
>> 1947 default y if CPU_MIPS32_R5 || CPU_MIPS64_R5 || CPU_P5600
>> 1948 select CPU_HAS_RIXI
>> 1949 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1950 select MIPS_SPRAM
>> 1951
>> 1952 config CPU_MIPSR6
>> 1953 bool
>> 1954 default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
>> 1955 select CPU_HAS_RIXI
>> 1956 select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
>> 1957 select HAVE_ARCH_BITREVERSE
>> 1958 select MIPS_ASID_BITS_VARIABLE
>> 1959 select MIPS_CRC_SUPPORT
>> 1960 select MIPS_SPRAM
>> 1961
>> 1962 config TARGET_ISA_REV
>> 1963 int
>> 1964 default 1 if CPU_MIPSR1
>> 1965 default 2 if CPU_MIPSR2
>> 1966 default 5 if CPU_MIPSR5
>> 1967 default 6 if CPU_MIPSR6
>> 1968 default 0
198 help 1969 help
199 Handle protection faults. MMU config !! 1970 Reflects the ISA revision being targeted by the kernel build. This
200 noMMU configurations may disable it !! 1971 is effectively the Kconfig equivalent of MIPS_ISA_REV.
201 generates protection faults or fault <<
202 1972
203 If unsure, say Y. !! 1973 config EVA
>> 1974 bool
204 1975
205 config XTENSA_UNALIGNED_USER !! 1976 config XPA
206 bool "Unaligned memory access in user !! 1977 bool
>> 1978
>> 1979 config SYS_SUPPORTS_32BIT_KERNEL
>> 1980 bool
>> 1981 config SYS_SUPPORTS_64BIT_KERNEL
>> 1982 bool
>> 1983 config CPU_SUPPORTS_32BIT_KERNEL
>> 1984 bool
>> 1985 config CPU_SUPPORTS_64BIT_KERNEL
>> 1986 bool
>> 1987 config CPU_SUPPORTS_CPUFREQ
>> 1988 bool
>> 1989 config CPU_SUPPORTS_ADDRWINCFG
>> 1990 bool
>> 1991 config CPU_SUPPORTS_HUGEPAGES
>> 1992 bool
>> 1993 depends on !(32BIT && (PHYS_ADDR_T_64BIT || EVA))
>> 1994 config MIPS_PGD_C0_CONTEXT
>> 1995 bool
>> 1996 depends on 64BIT
>> 1997 default y if (CPU_MIPSR2 || CPU_MIPSR6)
>> 1998
>> 1999 #
>> 2000 # Set to y for ptrace access to watch registers.
>> 2001 #
>> 2002 config HARDWARE_WATCHPOINTS
>> 2003 bool
>> 2004 default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
>> 2005
>> 2006 menu "Kernel type"
>> 2007
>> 2008 choice
>> 2009 prompt "Kernel code model"
207 help 2010 help
208 The Xtensa architecture currently do !! 2011 You should only select this option if you have a workload that
209 memory accesses in hardware but thro !! 2012 actually benefits from 64-bit processing or if your machine has
210 Per default, unaligned memory access !! 2013 large memory. You will only be presented a single option in this
>> 2014 menu if your system does not support both 32-bit and 64-bit kernels.
211 2015
212 Say Y here to enable unaligned memor !! 2016 config 32BIT
>> 2017 bool "32-bit kernel"
>> 2018 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
>> 2019 select TRAD_SIGNALS
>> 2020 help
>> 2021 Select this option if you want to build a 32-bit kernel.
213 2022
214 config XTENSA_LOAD_STORE !! 2023 config 64BIT
215 bool "Load/store exception handler for !! 2024 bool "64-bit kernel"
>> 2025 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
216 help 2026 help
217 The Xtensa architecture only allows !! 2027 Select this option if you want to build a 64-bit kernel.
218 instruction bus with l32r and l32i i !! 2028
219 instructions raise an exception with !! 2029 endchoice
220 This makes it hard to use some confi !! 2030
221 literals in FLASH memory attached to !! 2031 config MIPS_VA_BITS_48
>> 2032 bool "48 bits virtual memory"
>> 2033 depends on 64BIT
>> 2034 help
>> 2035 Support a maximum at least 48 bits of application virtual
>> 2036 memory. Default is 40 bits or less, depending on the CPU.
>> 2037 For page sizes 16k and above, this option results in a small
>> 2038 memory overhead for page tables. For 4k page size, a fourth
>> 2039 level of page tables is added which imposes both a memory
>> 2040 overhead as well as slower TLB fault handling.
222 2041
223 Say Y here to enable exception handl !! 2042 If unsure, say N.
224 byte and 2-byte access to memory att <<
225 2043
226 config HAVE_SMP !! 2044 config ZBOOT_LOAD_ADDRESS
227 bool "System Supports SMP (MX)" !! 2045 hex "Compressed kernel load address"
228 depends on XTENSA_VARIANT_CUSTOM !! 2046 default 0xffffffff80400000 if BCM47XX
229 select XTENSA_MX !! 2047 default 0x0
>> 2048 depends on SYS_SUPPORTS_ZBOOT
230 help 2049 help
231 This option is used to indicate that !! 2050 The address to load compressed kernel, aka vmlinuz.
232 supports Multiprocessing. Multiproce <<
233 the CPU core definition and currentl <<
234 2051
235 Multiprocessor support is implemente !! 2052 This is only used if non-zero.
236 interrupt controllers. <<
237 2053
238 The MX interrupt distributer adds In !! 2054 choice
239 and causes the IRQ numbers to be inc !! 2055 prompt "Kernel page size"
240 like the open cores ethernet driver !! 2056 default PAGE_SIZE_4KB
241 2057
242 You still have to select "Enable SMP !! 2058 config PAGE_SIZE_4KB
>> 2059 bool "4kB"
>> 2060 depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
>> 2061 help
>> 2062 This option select the standard 4kB Linux page size. On some
>> 2063 R3000-family processors this is the only available page size. Using
>> 2064 4kB page size will minimize memory consumption and is therefore
>> 2065 recommended for low memory systems.
>> 2066
>> 2067 config PAGE_SIZE_8KB
>> 2068 bool "8kB"
>> 2069 depends on CPU_CAVIUM_OCTEON
>> 2070 depends on !MIPS_VA_BITS_48
>> 2071 help
>> 2072 Using 8kB page size will result in higher performance kernel at
>> 2073 the price of higher memory consumption. This option is available
>> 2074 only on cnMIPS processors. Note that you will need a suitable Linux
>> 2075 distribution to support this.
>> 2076
>> 2077 config PAGE_SIZE_16KB
>> 2078 bool "16kB"
>> 2079 depends on !CPU_R3000
>> 2080 help
>> 2081 Using 16kB page size will result in higher performance kernel at
>> 2082 the price of higher memory consumption. This option is available on
>> 2083 all non-R3000 family processors. Note that you will need a suitable
>> 2084 Linux distribution to support this.
>> 2085
>> 2086 config PAGE_SIZE_32KB
>> 2087 bool "32kB"
>> 2088 depends on CPU_CAVIUM_OCTEON
>> 2089 depends on !MIPS_VA_BITS_48
>> 2090 help
>> 2091 Using 32kB page size will result in higher performance kernel at
>> 2092 the price of higher memory consumption. This option is available
>> 2093 only on cnMIPS cores. Note that you will need a suitable Linux
>> 2094 distribution to support this.
>> 2095
>> 2096 config PAGE_SIZE_64KB
>> 2097 bool "64kB"
>> 2098 depends on !CPU_R3000
>> 2099 help
>> 2100 Using 64kB page size will result in higher performance kernel at
>> 2101 the price of higher memory consumption. This option is available on
>> 2102 all non-R3000 family processor. Not that at the time of this
>> 2103 writing this option is still high experimental.
243 2104
244 config SMP !! 2105 endchoice
245 bool "Enable Symmetric multi-processin !! 2106
246 depends on HAVE_SMP !! 2107 config ARCH_FORCE_MAX_ORDER
247 select GENERIC_SMP_IDLE_THREAD !! 2108 int "Maximum zone order"
>> 2109 default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
>> 2110 default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
>> 2111 default "11" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
>> 2112 default "10"
248 help 2113 help
249 Enabled SMP Software; allows more th !! 2114 The kernel memory allocator divides physically contiguous memory
250 to be activated during startup. !! 2115 blocks into "zones", where each zone is a power of two number of
>> 2116 pages. This option selects the largest power of two that the kernel
>> 2117 keeps in the memory allocator. If you need to allocate very large
>> 2118 blocks of physically contiguous memory, then you may need to
>> 2119 increase this value.
251 2120
252 config NR_CPUS !! 2121 The page size is not necessarily 4KB. Keep this in mind
253 depends on SMP !! 2122 when choosing a value for this option.
254 int "Maximum number of CPUs (2-32)" <<
255 range 2 32 <<
256 default "4" <<
257 2123
258 config HOTPLUG_CPU !! 2124 config BOARD_SCACHE
259 bool "Enable CPU hotplug support" !! 2125 bool
260 depends on SMP !! 2126
>> 2127 config IP22_CPU_SCACHE
>> 2128 bool
>> 2129 select BOARD_SCACHE
>> 2130
>> 2131 #
>> 2132 # Support for a MIPS32 / MIPS64 style S-caches
>> 2133 #
>> 2134 config MIPS_CPU_SCACHE
>> 2135 bool
>> 2136 select BOARD_SCACHE
>> 2137
>> 2138 config R5000_CPU_SCACHE
>> 2139 bool
>> 2140 select BOARD_SCACHE
>> 2141
>> 2142 config RM7000_CPU_SCACHE
>> 2143 bool
>> 2144 select BOARD_SCACHE
>> 2145
>> 2146 config SIBYTE_DMA_PAGEOPS
>> 2147 bool "Use DMA to clear/copy pages"
>> 2148 depends on CPU_SB1
261 help 2149 help
262 Say Y here to allow turning CPUs off !! 2150 Instead of using the CPU to zero and copy pages, use a Data Mover
263 controlled through /sys/devices/syst !! 2151 channel. These DMA channels are otherwise unused by the standard
>> 2152 SiByte Linux port. Seems to give a small performance benefit.
264 2153
265 Say N if you want to disable CPU hot !! 2154 config CPU_HAS_PREFETCH
>> 2155 bool
>> 2156
>> 2157 config CPU_GENERIC_DUMP_TLB
>> 2158 bool
>> 2159 default y if !CPU_R3000
266 2160
267 config SECONDARY_RESET_VECTOR !! 2161 config MIPS_FP_SUPPORT
268 bool "Secondary cores use alternative !! 2162 bool "Floating Point support" if EXPERT
269 default y 2163 default y
270 depends on HAVE_SMP <<
271 help 2164 help
272 Secondary cores may be configured to !! 2165 Select y to include support for floating point in the kernel
273 or all cores may use primary reset v !! 2166 including initialization of FPU hardware, FP context save & restore
274 Say Y here to supply handler for the !! 2167 and emulation of an FPU where necessary. Without this support any
>> 2168 userland program attempting to use floating point instructions will
>> 2169 receive a SIGILL.
275 2170
276 config FAST_SYSCALL_XTENSA !! 2171 If you know that your userland will not attempt to use floating point
277 bool "Enable fast atomic syscalls" !! 2172 instructions then you can say n here to shrink the kernel a little.
278 default n <<
279 help <<
280 fast_syscall_xtensa is a syscall tha <<
281 on UP kernel when processor has no s <<
282 2173
283 This syscall is deprecated. It may h !! 2174 If unsure, say y.
284 invalid arguments. It is provided on <<
285 Only enable it if your userspace sof <<
286 2175
287 If unsure, say N. !! 2176 config CPU_R2300_FPU
>> 2177 bool
>> 2178 depends on MIPS_FP_SUPPORT
>> 2179 default y if CPU_R3000
288 2180
289 config FAST_SYSCALL_SPILL_REGISTERS !! 2181 config CPU_R3K_TLB
290 bool "Enable spill registers syscall" !! 2182 bool
>> 2183
>> 2184 config CPU_R4K_FPU
>> 2185 bool
>> 2186 depends on MIPS_FP_SUPPORT
>> 2187 default y if !CPU_R2300_FPU
>> 2188
>> 2189 config CPU_R4K_CACHE_TLB
>> 2190 bool
>> 2191 default y if !(CPU_R3K_TLB || CPU_SB1 || CPU_CAVIUM_OCTEON)
>> 2192
>> 2193 config MIPS_MT_SMP
>> 2194 bool "MIPS MT SMP support (1 TC on each available VPE)"
>> 2195 default y
>> 2196 depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
>> 2197 select CPU_MIPSR2_IRQ_VI
>> 2198 select CPU_MIPSR2_IRQ_EI
>> 2199 select SYNC_R4K
>> 2200 select MIPS_MT
>> 2201 select SMP
>> 2202 select SMP_UP
>> 2203 select SYS_SUPPORTS_SMP
>> 2204 select SYS_SUPPORTS_SCHED_SMT
>> 2205 select MIPS_PERF_SHARED_TC_COUNTERS
>> 2206 help
>> 2207 This is a kernel model which is known as SMVP. This is supported
>> 2208 on cores with the MT ASE and uses the available VPEs to implement
>> 2209 virtual processors which supports SMP. This is equivalent to the
>> 2210 Intel Hyperthreading feature. For further information go to
>> 2211 <http://www.imgtec.com/mips/mips-multithreading.asp>.
>> 2212
>> 2213 config MIPS_MT
>> 2214 bool
>> 2215
>> 2216 config SCHED_SMT
>> 2217 bool "SMT (multithreading) scheduler support"
>> 2218 depends on SYS_SUPPORTS_SCHED_SMT
291 default n 2219 default n
292 help 2220 help
293 fast_syscall_spill_registers is a sy !! 2221 SMT scheduler support improves the CPU scheduler's decision making
294 register windows of a calling usersp !! 2222 when dealing with MIPS MT enabled cores at a cost of slightly
>> 2223 increased overhead in some places. If unsure say N here.
295 2224
296 This syscall is deprecated. It may h !! 2225 config SYS_SUPPORTS_SCHED_SMT
297 invalid arguments. It is provided on !! 2226 bool
298 Only enable it if your userspace sof <<
299 2227
300 If unsure, say N. !! 2228 config SYS_SUPPORTS_MULTITHREADING
>> 2229 bool
301 2230
302 choice !! 2231 config MIPS_MT_FPAFF
303 prompt "Kernel ABI" !! 2232 bool "Dynamic FPU affinity for FP-intensive threads"
304 default KERNEL_ABI_DEFAULT !! 2233 default y
>> 2234 depends on MIPS_MT_SMP
>> 2235
>> 2236 config MIPSR2_TO_R6_EMULATOR
>> 2237 bool "MIPS R2-to-R6 emulator"
>> 2238 depends on CPU_MIPSR6
>> 2239 depends on MIPS_FP_SUPPORT
>> 2240 default y
305 help 2241 help
306 Select ABI for the kernel code. This !! 2242 Choose this option if you want to run non-R6 MIPS userland code.
307 supported userspace ABI and any comb !! 2243 Even if you say 'Y' here, the emulator will still be disabled by
308 kernel/userspace ABI is possible and !! 2244 default. You can enable it using the 'mipsr2emu' kernel option.
309 !! 2245 The only reason this is a build-time option is to save ~14K from the
310 In case both kernel and userspace su !! 2246 final kernel image.
311 all register windows support code wi <<
312 build. <<
313 <<
314 If unsure, choose the default ABI. <<
315 <<
316 config KERNEL_ABI_DEFAULT <<
317 bool "Default ABI" <<
318 help <<
319 Select this option to compile kernel <<
320 selected for the toolchain. <<
321 Normally cores with windowed registe <<
322 cores without it use call0 ABI. <<
323 <<
324 config KERNEL_ABI_CALL0 <<
325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI <<
326 help <<
327 Select this option to compile kernel <<
328 toolchain that defaults to windowed <<
329 When this option is not selected the <<
330 be used for the kernel code. <<
331 2247
332 endchoice !! 2248 config SYS_SUPPORTS_VPE_LOADER
>> 2249 bool
>> 2250 depends on SYS_SUPPORTS_MULTITHREADING
>> 2251 help
>> 2252 Indicates that the platform supports the VPE loader, and provides
>> 2253 physical_memsize.
333 2254
334 config USER_ABI_CALL0 !! 2255 config MIPS_VPE_LOADER
>> 2256 bool "VPE loader support."
>> 2257 depends on SYS_SUPPORTS_VPE_LOADER && MODULES
>> 2258 select CPU_MIPSR2_IRQ_VI
>> 2259 select CPU_MIPSR2_IRQ_EI
>> 2260 select MIPS_MT
>> 2261 help
>> 2262 Includes a loader for loading an elf relocatable object
>> 2263 onto another VPE and running it.
>> 2264
>> 2265 config MIPS_VPE_LOADER_MT
335 bool 2266 bool
>> 2267 default "y"
>> 2268 depends on MIPS_VPE_LOADER
336 2269
337 choice !! 2270 config MIPS_VPE_LOADER_TOM
338 prompt "Userspace ABI" !! 2271 bool "Load VPE program into memory hidden from linux"
339 default USER_ABI_DEFAULT !! 2272 depends on MIPS_VPE_LOADER
>> 2273 default y
340 help 2274 help
341 Select supported userspace ABI. !! 2275 The loader can use memory that is present but has been hidden from
>> 2276 Linux using the kernel command line option "mem=xxMB". It's up to
>> 2277 you to ensure the amount you put in the option and the space your
>> 2278 program requires is less or equal to the amount physically present.
>> 2279
>> 2280 config MIPS_VPE_APSP_API
>> 2281 bool "Enable support for AP/SP API (RTLX)"
>> 2282 depends on MIPS_VPE_LOADER
>> 2283
>> 2284 config MIPS_VPE_APSP_API_MT
>> 2285 bool
>> 2286 default "y"
>> 2287 depends on MIPS_VPE_APSP_API
>> 2288
>> 2289 config MIPS_CPS
>> 2290 bool "MIPS Coherent Processing System support"
>> 2291 depends on SYS_SUPPORTS_MIPS_CPS
>> 2292 select MIPS_CM
>> 2293 select MIPS_CPS_PM if HOTPLUG_CPU
>> 2294 select SMP
>> 2295 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
>> 2296 select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
>> 2297 select SYS_SUPPORTS_HOTPLUG_CPU
>> 2298 select SYS_SUPPORTS_SCHED_SMT if CPU_MIPSR6
>> 2299 select SYS_SUPPORTS_SMP
>> 2300 select WEAK_ORDERING
>> 2301 select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU
>> 2302 help
>> 2303 Select this if you wish to run an SMP kernel across multiple cores
>> 2304 within a MIPS Coherent Processing System. When this option is
>> 2305 enabled the kernel will probe for other cores and boot them with
>> 2306 no external assistance. It is safe to enable this when hardware
>> 2307 support is unavailable.
>> 2308
>> 2309 config MIPS_CPS_PM
>> 2310 depends on MIPS_CPS
>> 2311 bool
>> 2312
>> 2313 config MIPS_CM
>> 2314 bool
>> 2315 select MIPS_CPC
>> 2316
>> 2317 config MIPS_CPC
>> 2318 bool
>> 2319
>> 2320 config SB1_PASS_2_WORKAROUNDS
>> 2321 bool
>> 2322 depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
>> 2323 default y
>> 2324
>> 2325 config SB1_PASS_2_1_WORKAROUNDS
>> 2326 bool
>> 2327 depends on CPU_SB1 && CPU_SB1_PASS_2
>> 2328 default y
342 2329
343 If unsure, choose the default ABI. !! 2330 choice
>> 2331 prompt "SmartMIPS or microMIPS ASE support"
344 2332
345 config USER_ABI_DEFAULT !! 2333 config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
346 bool "Default ABI only" !! 2334 bool "None"
347 help 2335 help
348 Assume default userspace ABI. For XE !! 2336 Select this if you want neither microMIPS nor SmartMIPS support
349 call0 ABI binaries may be run on suc <<
350 will not work correctly for them. <<
351 2337
352 config USER_ABI_CALL0_ONLY !! 2338 config CPU_HAS_SMARTMIPS
353 bool "Call0 ABI only" !! 2339 depends on SYS_SUPPORTS_SMARTMIPS
354 select USER_ABI_CALL0 !! 2340 bool "SmartMIPS"
>> 2341 help
>> 2342 SmartMIPS is a extension of the MIPS32 architecture aimed at
>> 2343 increased security at both hardware and software level for
>> 2344 smartcards. Enabling this option will allow proper use of the
>> 2345 SmartMIPS instructions by Linux applications. However a kernel with
>> 2346 this option will not work on a MIPS core without SmartMIPS core. If
>> 2347 you don't know you probably don't have SmartMIPS and should say N
>> 2348 here.
>> 2349
>> 2350 config CPU_MICROMIPS
>> 2351 depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
>> 2352 bool "microMIPS"
355 help 2353 help
356 Select this option to support only c !! 2354 When this option is enabled the kernel will be built using the
357 Windowed ABI binaries will crash wit !! 2355 microMIPS ISA
358 an illegal instruction exception on <<
359 2356
360 Choose this option if you're plannin !! 2357 endchoice
361 built with call0 ABI. <<
362 2358
363 config USER_ABI_CALL0_PROBE !! 2359 config CPU_HAS_MSA
364 bool "Support both windowed and call0 !! 2360 bool "Support for the MIPS SIMD Architecture"
365 select USER_ABI_CALL0 !! 2361 depends on CPU_SUPPORTS_MSA
366 help !! 2362 depends on MIPS_FP_SUPPORT
367 Select this option to support both w !! 2363 depends on 64BIT || MIPS_O32_FP64_SUPPORT
368 ABIs. When enabled all processes are !! 2364 help
369 and a fast user exception handler fo !! 2365 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
370 used to turn on PS.WOE bit on the fi !! 2366 and a set of SIMD instructions to operate on them. When this option
371 the userspace. !! 2367 is enabled the kernel will support allocating & switching MSA
>> 2368 vector register contexts. If you know that your kernel will only be
>> 2369 running on CPUs which do not support MSA or that your userland will
>> 2370 not be making use of it then you may wish to say N here to reduce
>> 2371 the size & complexity of your kernel.
372 2372
373 This option should be enabled for th !! 2373 If unsure, say Y.
374 both call0 and windowed ABIs in user <<
375 2374
376 Note that Xtensa ISA does not guaran !! 2375 config CPU_HAS_WB
377 raise an illegal instruction excepti !! 2376 bool
378 PS.WOE is disabled, check whether th <<
379 2377
380 endchoice !! 2378 config XKS01
>> 2379 bool
381 2380
382 endmenu !! 2381 config CPU_HAS_DIEI
>> 2382 depends on !CPU_DIEI_BROKEN
>> 2383 bool
383 2384
384 config XTENSA_CALIBRATE_CCOUNT !! 2385 config CPU_DIEI_BROKEN
385 def_bool n !! 2386 bool
>> 2387
>> 2388 config CPU_HAS_RIXI
>> 2389 bool
>> 2390
>> 2391 config CPU_NO_LOAD_STORE_LR
>> 2392 bool
386 help 2393 help
387 On some platforms (XT2000, for examp !! 2394 CPU lacks support for unaligned load and store instructions:
388 vary. The frequency can be determin !! 2395 LWL, LWR, SWL, SWR (Load/store word left/right).
389 against a well known, fixed frequenc !! 2396 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
>> 2397 systems).
>> 2398
>> 2399 #
>> 2400 # Vectored interrupt mode is an R2 feature
>> 2401 #
>> 2402 config CPU_MIPSR2_IRQ_VI
>> 2403 bool
390 2404
391 config SERIAL_CONSOLE !! 2405 #
392 def_bool n !! 2406 # Extended interrupt mode is an R2 feature
>> 2407 #
>> 2408 config CPU_MIPSR2_IRQ_EI
>> 2409 bool
393 2410
394 config PLATFORM_HAVE_XIP !! 2411 config CPU_HAS_SYNC
395 def_bool n !! 2412 bool
>> 2413 depends on !CPU_R3000
>> 2414 default y
396 2415
397 menu "Platform options" !! 2416 #
>> 2417 # CPU non-features
>> 2418 #
>> 2419
>> 2420 # Work around the "daddi" and "daddiu" CPU errata:
>> 2421 #
>> 2422 # - The `daddi' instruction fails to trap on overflow.
>> 2423 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2424 # erratum #23
>> 2425 #
>> 2426 # - The `daddiu' instruction can produce an incorrect result.
>> 2427 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2428 # erratum #41
>> 2429 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2430 # #15
>> 2431 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
>> 2432 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
>> 2433 config CPU_DADDI_WORKAROUNDS
>> 2434 bool
398 2435
399 choice !! 2436 # Work around certain R4000 CPU errata (as implemented by GCC):
400 prompt "Xtensa System Type" !! 2437 #
401 default XTENSA_PLATFORM_ISS !! 2438 # - A double-word or a variable shift may give an incorrect result
>> 2439 # if executed immediately after starting an integer division:
>> 2440 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2441 # erratum #28
>> 2442 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
>> 2443 # #19
>> 2444 #
>> 2445 # - A double-word or a variable shift may give an incorrect result
>> 2446 # if executed while an integer multiplication is in progress:
>> 2447 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2448 # errata #16 & #28
>> 2449 #
>> 2450 # - An integer division may give an incorrect result if started in
>> 2451 # a delay slot of a taken branch or a jump:
>> 2452 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
>> 2453 # erratum #52
>> 2454 config CPU_R4000_WORKAROUNDS
>> 2455 bool
>> 2456 select CPU_R4400_WORKAROUNDS
402 2457
403 config XTENSA_PLATFORM_ISS !! 2458 # Work around certain R4400 CPU errata (as implemented by GCC):
404 bool "ISS" !! 2459 #
405 select XTENSA_CALIBRATE_CCOUNT !! 2460 # - A double-word or a variable shift may give an incorrect result
406 select SERIAL_CONSOLE !! 2461 # if executed immediately after starting an integer division:
407 help !! 2462 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
408 ISS is an acronym for Tensilica's In !! 2463 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
409 !! 2464 config CPU_R4400_WORKAROUNDS
410 config XTENSA_PLATFORM_XT2000 !! 2465 bool
411 bool "XT2000" <<
412 help <<
413 XT2000 is the name of Tensilica's fe <<
414 This hardware is capable of running <<
415 <<
416 config XTENSA_PLATFORM_XTFPGA <<
417 bool "XTFPGA" <<
418 select ETHOC if ETHERNET <<
419 select PLATFORM_WANT_DEFAULT_MEM if !M <<
420 select SERIAL_CONSOLE <<
421 select XTENSA_CALIBRATE_CCOUNT <<
422 select PLATFORM_HAVE_XIP <<
423 help <<
424 XTFPGA is the name of Tensilica boar <<
425 This hardware is capable of running <<
426 2466
427 endchoice !! 2467 config CPU_R4X00_BUGS64
>> 2468 bool
>> 2469 default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
428 2470
429 config PLATFORM_NR_IRQS !! 2471 config MIPS_ASID_SHIFT
430 int 2472 int
431 default 3 if XTENSA_PLATFORM_XT2000 !! 2473 default 6 if CPU_R3000
432 default 0 2474 default 0
433 2475
434 config XTENSA_CPU_CLOCK !! 2476 config MIPS_ASID_BITS
435 int "CPU clock rate [MHz]" !! 2477 int
436 depends on !XTENSA_CALIBRATE_CCOUNT !! 2478 default 0 if MIPS_ASID_BITS_VARIABLE
437 default 16 !! 2479 default 6 if CPU_R3000
>> 2480 default 8
438 2481
439 config GENERIC_CALIBRATE_DELAY !! 2482 config MIPS_ASID_BITS_VARIABLE
440 bool "Auto calibration of the BogoMIPS !! 2483 bool
441 help <<
442 The BogoMIPS value can easily be der <<
443 2484
444 config CMDLINE_BOOL !! 2485 config MIPS_CRC_SUPPORT
445 bool "Default bootloader kernel argume !! 2486 bool
446 2487
447 config CMDLINE !! 2488 # R4600 erratum. Due to the lack of errata information the exact
448 string "Initial kernel command string" !! 2489 # technical details aren't known. I've experimentally found that disabling
449 depends on CMDLINE_BOOL !! 2490 # interrupts during indexed I-cache flushes seems to be sufficient to deal
450 default "console=ttyS0,38400 root=/dev !! 2491 # with the issue.
451 help !! 2492 config WAR_R4600_V1_INDEX_ICACHEOP
452 On some architectures (EBSA110 and C !! 2493 bool
453 for the boot loader to pass argument <<
454 architectures, you should supply som <<
455 time by entering them here. As a min <<
456 memory size and the root device (e.g <<
457 2494
458 config USE_OF !! 2495 # Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
459 bool "Flattened Device Tree support" !! 2496 #
460 select OF !! 2497 # 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
461 select OF_EARLY_FLATTREE !! 2498 # Hit_Invalidate_D and Create_Dirty_Excl_D should only be
462 help !! 2499 # executed if there is no other dcache activity. If the dcache is
463 Include support for flattened device !! 2500 # accessed for another instruction immediately preceding when these
>> 2501 # cache instructions are executing, it is possible that the dcache
>> 2502 # tag match outputs used by these cache instructions will be
>> 2503 # incorrect. These cache instructions should be preceded by at least
>> 2504 # four instructions that are not any kind of load or store
>> 2505 # instruction.
>> 2506 #
>> 2507 # This is not allowed: lw
>> 2508 # nop
>> 2509 # nop
>> 2510 # nop
>> 2511 # cache Hit_Writeback_Invalidate_D
>> 2512 #
>> 2513 # This is allowed: lw
>> 2514 # nop
>> 2515 # nop
>> 2516 # nop
>> 2517 # nop
>> 2518 # cache Hit_Writeback_Invalidate_D
>> 2519 config WAR_R4600_V1_HIT_CACHEOP
>> 2520 bool
464 2521
465 config BUILTIN_DTB_SOURCE !! 2522 # Writeback and invalidate the primary cache dcache before DMA.
466 string "DTB to build into the kernel i !! 2523 #
467 depends on OF !! 2524 # R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
>> 2525 # Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
>> 2526 # operate correctly if the internal data cache refill buffer is empty. These
>> 2527 # CACHE instructions should be separated from any potential data cache miss
>> 2528 # by a load instruction to an uncached address to empty the response buffer."
>> 2529 # (Revision 2.0 device errata from IDT available on https://www.idt.com/
>> 2530 # in .pdf format.)
>> 2531 config WAR_R4600_V2_HIT_CACHEOP
>> 2532 bool
468 2533
469 config PARSE_BOOTPARAM !! 2534 # From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
470 bool "Parse bootparam block" !! 2535 # the line which this instruction itself exists, the following
471 default y !! 2536 # operation is not guaranteed."
472 help !! 2537 #
473 Parse parameters passed to the kerne !! 2538 # Workaround: do two phase flushing for Index_Invalidate_I
474 be disabled if the kernel is known t !! 2539 config WAR_TX49XX_ICACHE_INDEX_INV
>> 2540 bool
475 2541
476 If unsure, say Y. !! 2542 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
>> 2543 # opposes it being called that) where invalid instructions in the same
>> 2544 # I-cache line worth of instructions being fetched may case spurious
>> 2545 # exceptions.
>> 2546 config WAR_ICACHE_REFILLS
>> 2547 bool
477 2548
478 choice !! 2549 # On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
479 prompt "Semihosting interface" !! 2550 # may cause ll / sc and lld / scd sequences to execute non-atomically.
480 default XTENSA_SIMCALL_ISS !! 2551 config WAR_R10000_LLSC
481 depends on XTENSA_PLATFORM_ISS !! 2552 bool
482 help <<
483 Choose semihosting interface that wi <<
484 block device and networking. <<
485 2553
486 config XTENSA_SIMCALL_ISS !! 2554 # 34K core erratum: "Problems Executing the TLBR Instruction"
487 bool "simcall" !! 2555 config WAR_MIPS34K_MISSED_ITLB
488 help !! 2556 bool
489 Use simcall instruction. simcall is !! 2557
490 it does nothing on hardware. !! 2558 #
>> 2559 # - Highmem only makes sense for the 32-bit kernel.
>> 2560 # - The current highmem code will only work properly on physically indexed
>> 2561 # caches such as R3000, SB1, R7000 or those that look like they're virtually
>> 2562 # indexed such as R4000/R4400 SC and MC versions or R10000. So for the
>> 2563 # moment we protect the user and offer the highmem option only on machines
>> 2564 # where it's known to be safe. This will not offer highmem on a few systems
>> 2565 # such as MIPS32 and MIPS64 CPUs which may have virtual and physically
>> 2566 # indexed CPUs but we're playing safe.
>> 2567 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
>> 2568 # know they might have memory configurations that could make use of highmem
>> 2569 # support.
>> 2570 #
>> 2571 config HIGHMEM
>> 2572 bool "High Memory Support"
>> 2573 depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
>> 2574 select KMAP_LOCAL
491 2575
492 config XTENSA_SIMCALL_GDBIO !! 2576 config CPU_SUPPORTS_HIGHMEM
493 bool "GDBIO" !! 2577 bool
>> 2578
>> 2579 config SYS_SUPPORTS_HIGHMEM
>> 2580 bool
>> 2581
>> 2582 config SYS_SUPPORTS_SMARTMIPS
>> 2583 bool
>> 2584
>> 2585 config SYS_SUPPORTS_MICROMIPS
>> 2586 bool
>> 2587
>> 2588 config SYS_SUPPORTS_MIPS16
>> 2589 bool
494 help 2590 help
495 Use break instruction. It is availab !! 2591 This option must be set if a kernel might be executed on a MIPS16-
496 is attached to it via JTAG. !! 2592 enabled CPU even if MIPS16 is not actually being used. In other
>> 2593 words, it makes the kernel MIPS16-tolerant.
497 2594
498 endchoice !! 2595 config CPU_SUPPORTS_MSA
>> 2596 bool
499 2597
500 config BLK_DEV_SIMDISK !! 2598 config ARCH_FLATMEM_ENABLE
501 tristate "Host file-based simulated bl !! 2599 def_bool y
502 default n !! 2600 depends on !NUMA && !CPU_LOONGSON2EF
503 depends on XTENSA_PLATFORM_ISS && BLOC !! 2601
>> 2602 config ARCH_SPARSEMEM_ENABLE
>> 2603 bool
>> 2604
>> 2605 config NUMA
>> 2606 bool "NUMA Support"
>> 2607 depends on SYS_SUPPORTS_NUMA
>> 2608 select SMP
>> 2609 select HAVE_SETUP_PER_CPU_AREA
>> 2610 select NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 2611 help
>> 2612 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
>> 2613 Access). This option improves performance on systems with more
>> 2614 than two nodes; on two node systems it is generally better to
>> 2615 leave it disabled; on single node systems leave this option
>> 2616 disabled.
>> 2617
>> 2618 config SYS_SUPPORTS_NUMA
>> 2619 bool
>> 2620
>> 2621 config HAVE_ARCH_NODEDATA_EXTENSION
>> 2622 bool
>> 2623
>> 2624 config RELOCATABLE
>> 2625 bool "Relocatable kernel"
>> 2626 depends on SYS_SUPPORTS_RELOCATABLE
>> 2627 depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || \
>> 2628 CPU_MIPS32_R5 || CPU_MIPS64_R5 || \
>> 2629 CPU_MIPS32_R6 || CPU_MIPS64_R6 || \
>> 2630 CPU_P5600 || CAVIUM_OCTEON_SOC || \
>> 2631 CPU_LOONGSON64
>> 2632 help
>> 2633 This builds a kernel image that retains relocation information
>> 2634 so it can be loaded someplace besides the default 1MB.
>> 2635 The relocations make the kernel binary about 15% larger,
>> 2636 but are discarded at runtime
>> 2637
>> 2638 config RELOCATION_TABLE_SIZE
>> 2639 hex "Relocation table size"
>> 2640 depends on RELOCATABLE
>> 2641 range 0x0 0x01000000
>> 2642 default "0x00200000" if CPU_LOONGSON64
>> 2643 default "0x00100000"
>> 2644 help
>> 2645 A table of relocation data will be appended to the kernel binary
>> 2646 and parsed at boot to fix up the relocated kernel.
>> 2647
>> 2648 This option allows the amount of space reserved for the table to be
>> 2649 adjusted, although the default of 1Mb should be ok in most cases.
>> 2650
>> 2651 The build will fail and a valid size suggested if this is too small.
>> 2652
>> 2653 If unsure, leave at the default value.
>> 2654
>> 2655 config RANDOMIZE_BASE
>> 2656 bool "Randomize the address of the kernel image"
>> 2657 depends on RELOCATABLE
>> 2658 help
>> 2659 Randomizes the physical and virtual address at which the
>> 2660 kernel image is loaded, as a security feature that
>> 2661 deters exploit attempts relying on knowledge of the location
>> 2662 of kernel internals.
>> 2663
>> 2664 Entropy is generated using any coprocessor 0 registers available.
>> 2665
>> 2666 The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
>> 2667
>> 2668 If unsure, say N.
>> 2669
>> 2670 config RANDOMIZE_BASE_MAX_OFFSET
>> 2671 hex "Maximum kASLR offset" if EXPERT
>> 2672 depends on RANDOMIZE_BASE
>> 2673 range 0x0 0x40000000 if EVA || 64BIT
>> 2674 range 0x0 0x08000000
>> 2675 default "0x01000000"
>> 2676 help
>> 2677 When kASLR is active, this provides the maximum offset that will
>> 2678 be applied to the kernel image. It should be set according to the
>> 2679 amount of physical RAM available in the target system minus
>> 2680 PHYSICAL_START and must be a power of 2.
>> 2681
>> 2682 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
>> 2683 EVA or 64-bit. The default is 16Mb.
>> 2684
>> 2685 config NODES_SHIFT
>> 2686 int
>> 2687 default "6"
>> 2688 depends on NUMA
>> 2689
>> 2690 config HW_PERF_EVENTS
>> 2691 bool "Enable hardware performance counter support for perf events"
>> 2692 depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
>> 2693 default y
504 help 2694 help
505 Create block devices that map to fil !! 2695 Enable hardware performance counter support for perf events. If
506 Device binding to host file may be c !! 2696 disabled, perf events will use software events only.
507 interface provided the device is not !! 2697
508 !! 2698 config DMI
509 config BLK_DEV_SIMDISK_COUNT !! 2699 bool "Enable DMI scanning"
510 int "Number of host file-based simulat !! 2700 depends on MACH_LOONGSON64
511 range 1 10 !! 2701 select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
512 depends on BLK_DEV_SIMDISK !! 2702 default y
513 default 2 <<
514 help 2703 help
515 This is the default minimal number o !! 2704 Enabled scanning of DMI to identify machine quirks. Say Y
516 Kernel/module parameter 'simdisk_cou !! 2705 here unless you have verified that your setup is not
517 value at runtime. More file names (b !! 2706 affected by entries in the DMI blacklist. Required by PNP
518 specified as parameters, simdisk_cou !! 2707 BIOS code.
519 !! 2708
520 config SIMDISK0_FILENAME !! 2709 config SMP
521 string "Host filename for the first si !! 2710 bool "Multi-Processing support"
522 depends on BLK_DEV_SIMDISK = y !! 2711 depends on SYS_SUPPORTS_SMP
523 default "" <<
524 help <<
525 Attach a first simdisk to a host fil <<
526 contains a root file system. <<
527 <<
528 config SIMDISK1_FILENAME <<
529 string "Host filename for the second s <<
530 depends on BLK_DEV_SIMDISK = y && BLK_ <<
531 default "" <<
532 help <<
533 Another simulated disk in a host fil <<
534 storage. <<
535 <<
536 config XTFPGA_LCD <<
537 bool "Enable XTFPGA LCD driver" <<
538 depends on XTENSA_PLATFORM_XTFPGA <<
539 default n <<
540 help 2712 help
541 There's a 2x16 LCD on most of XTFPGA !! 2713 This enables support for systems with more than one CPU. If you have
542 progress messages there during bootu !! 2714 a system with only one CPU, say N. If you have a system with more
543 during board bringup. !! 2715 than one CPU, say Y.
>> 2716
>> 2717 If you say N here, the kernel will run on uni- and multiprocessor
>> 2718 machines, but will use only one CPU of a multiprocessor machine. If
>> 2719 you say Y here, the kernel will run on many, but not all,
>> 2720 uniprocessor machines. On a uniprocessor machine, the kernel
>> 2721 will run faster if you say N here.
544 2722
545 If unsure, say N. !! 2723 People using multiprocessor machines who say Y here should also say
>> 2724 Y to "Enhanced Real Time Clock Support", below.
546 2725
547 config XTFPGA_LCD_BASE_ADDR !! 2726 See also the SMP-HOWTO available at
548 hex "XTFPGA LCD base address" !! 2727 <https://www.tldp.org/docs.html#howto>.
549 depends on XTFPGA_LCD !! 2728
550 default "0x0d0c0000" !! 2729 If you don't know what to do here, say N.
551 help !! 2730
552 Base address of the LCD controller i !! 2731 config HOTPLUG_CPU
553 Different boards from XTFPGA family !! 2732 bool "Support for hot-pluggable CPUs"
554 addresses. Please consult prototypin !! 2733 depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
555 the correct address. Wrong address h <<
556 <<
557 config XTFPGA_LCD_8BIT_ACCESS <<
558 bool "Use 8-bit access to XTFPGA LCD" <<
559 depends on XTFPGA_LCD <<
560 default n <<
561 help 2734 help
562 LCD may be connected with 4- or 8-bi !! 2735 Say Y here to allow turning CPUs off and on. CPUs can be
563 only be used with 8-bit interface. P !! 2736 controlled through /sys/devices/system/cpu.
564 guide for your board for the correct !! 2737 (Note: power management support will enable this option
565 !! 2738 automatically on SMP systems. )
566 comment "Kernel memory layout" !! 2739 Say N if you want to disable CPU hotplug.
567 <<
568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX <<
569 bool "Initialize Xtensa MMU inside the <<
570 depends on !XTENSA_VARIANT_FSF && !XTE <<
571 default y if XTENSA_VARIANT_DC233C || <<
572 help <<
573 Earlier version initialized the MMU <<
574 before jumping to _startup in head.S <<
575 it was possible to place a software <<
576 then enter your normal kernel breakp <<
577 to the kernel mappings (0XC0000000). <<
578 <<
579 This unfortunately won't work for U- <<
580 work for using KEXEC to have a hot k <<
581 KDUMP. <<
582 <<
583 So now the MMU is initialized in hea <<
584 use hardware breakpoints (gdb 'hbrea <<
585 xt-gdb can't place a Software Breakp <<
586 to mapping the MMU and after mapping <<
587 was mapped gdb wouldn't remove the b <<
588 PC wouldn't match. Since Hardware Br <<
589 Linux configurations it seems reason <<
590 and leave this older mechanism for u <<
591 not to follow Tensilica's recommenda <<
592 <<
593 Selecting this will cause U-Boot to <<
594 address at 0x00003000 instead of the <<
595 <<
596 If in doubt, say Y. <<
597 <<
598 config XIP_KERNEL <<
599 bool "Kernel Execute-In-Place from ROM <<
600 depends on PLATFORM_HAVE_XIP <<
601 help <<
602 Execute-In-Place allows the kernel t <<
603 directly addressable by the CPU, suc <<
604 space since the text section of the <<
605 to RAM. Read-write sections, such as <<
606 are still copied to RAM. The XIP ker <<
607 it has to run directly from flash, s <<
608 store it. The flash address used to <<
609 and for storing it, is configuration <<
610 say Y here, you must know the proper <<
611 store the kernel image depending on <<
612 <<
613 Also note that the make target becom <<
614 "make Image" or "make uImage". The f <<
615 ROM memory will be arch/xtensa/boot/ <<
616 2740
617 If unsure, say N. !! 2741 config SMP_UP
>> 2742 bool
>> 2743
>> 2744 config SYS_SUPPORTS_MIPS_CPS
>> 2745 bool
>> 2746
>> 2747 config SYS_SUPPORTS_SMP
>> 2748 bool
>> 2749
>> 2750 config NR_CPUS_DEFAULT_4
>> 2751 bool
>> 2752
>> 2753 config NR_CPUS_DEFAULT_8
>> 2754 bool
>> 2755
>> 2756 config NR_CPUS_DEFAULT_16
>> 2757 bool
>> 2758
>> 2759 config NR_CPUS_DEFAULT_32
>> 2760 bool
>> 2761
>> 2762 config NR_CPUS_DEFAULT_64
>> 2763 bool
>> 2764
>> 2765 config NR_CPUS
>> 2766 int "Maximum number of CPUs (2-256)"
>> 2767 range 2 256
>> 2768 depends on SMP
>> 2769 default "4" if NR_CPUS_DEFAULT_4
>> 2770 default "8" if NR_CPUS_DEFAULT_8
>> 2771 default "16" if NR_CPUS_DEFAULT_16
>> 2772 default "32" if NR_CPUS_DEFAULT_32
>> 2773 default "64" if NR_CPUS_DEFAULT_64
>> 2774 help
>> 2775 This allows you to specify the maximum number of CPUs which this
>> 2776 kernel will support. The maximum supported value is 32 for 32-bit
>> 2777 kernel and 64 for 64-bit kernels; the minimum value which makes
>> 2778 sense is 1 for Qemu (useful only for kernel debugging purposes)
>> 2779 and 2 for all others.
>> 2780
>> 2781 This is purely to save memory - each supported CPU adds
>> 2782 approximately eight kilobytes to the kernel image. For best
>> 2783 performance should round up your number of processors to the next
>> 2784 power of two.
>> 2785
>> 2786 config MIPS_PERF_SHARED_TC_COUNTERS
>> 2787 bool
>> 2788
>> 2789 config MIPS_NR_CPU_NR_MAP_1024
>> 2790 bool
618 2791
619 config MEMMAP_CACHEATTR !! 2792 config MIPS_NR_CPU_NR_MAP
620 hex "Cache attributes for the memory a !! 2793 int
621 depends on !MMU !! 2794 depends on SMP
622 default 0x22222222 !! 2795 default 1024 if MIPS_NR_CPU_NR_MAP_1024
623 help !! 2796 default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
624 These cache attributes are set up fo <<
625 specifies cache attributes for the c <<
626 region: bits 0..3 -- for addresses 0 <<
627 bits 4..7 -- for addresses 0x2000000 <<
628 <<
629 Cache attribute values are specific <<
630 For region protection MMUs: <<
631 1: WT cached, <<
632 2: cache bypass, <<
633 4: WB cached, <<
634 f: illegal. <<
635 For full MMU: <<
636 bit 0: executable, <<
637 bit 1: writable, <<
638 bits 2..3: <<
639 0: cache bypass, <<
640 1: WB cache, <<
641 2: WT cache, <<
642 3: special (c and e are illegal, <<
643 For MPU: <<
644 0: illegal, <<
645 1: WB cache, <<
646 2: WB, no-write-allocate cache, <<
647 3: WT cache, <<
648 4: cache bypass. <<
649 <<
650 config KSEG_PADDR <<
651 hex "Physical address of the KSEG mapp <<
652 depends on INITIALIZE_XTENSA_MMU_INSID <<
653 default 0x00000000 <<
654 help <<
655 This is the physical address where K <<
656 the chosen KSEG layout help for the <<
657 Unpacked kernel image (including vec <<
658 within KSEG. <<
659 Physical memory below this address i <<
660 <<
661 If unsure, leave the default value h <<
662 <<
663 config KERNEL_VIRTUAL_ADDRESS <<
664 hex "Kernel virtual address" <<
665 depends on MMU && XIP_KERNEL <<
666 default 0xd0003000 <<
667 help <<
668 This is the virtual address where th <<
669 XIP kernel may be mapped into KSEG o <<
670 provided here must match kernel load <<
671 KERNEL_LOAD_ADDRESS. <<
672 <<
673 config KERNEL_LOAD_ADDRESS <<
674 hex "Kernel load address" <<
675 default 0x60003000 if !MMU <<
676 default 0x00003000 if MMU && INITIALIZ <<
677 default 0xd0003000 if MMU && !INITIALI <<
678 help <<
679 This is the address where the kernel <<
680 It is virtual address for MMUv2 conf <<
681 for all other configurations. <<
682 2797
683 If unsure, leave the default value h !! 2798 #
>> 2799 # Timer Interrupt Frequency Configuration
>> 2800 #
684 2801
685 choice 2802 choice
686 prompt "Relocatable vectors location" !! 2803 prompt "Timer frequency"
687 default XTENSA_VECTORS_IN_TEXT !! 2804 default HZ_250
688 help 2805 help
689 Choose whether relocatable vectors a !! 2806 Allows the configuration of the timer frequency.
690 or placed separately at runtime. Thi !! 2807
691 configurations without VECBASE regis !! 2808 config HZ_24
692 placed at their hardware-defined loc !! 2809 bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ
693 !! 2810
694 config XTENSA_VECTORS_IN_TEXT !! 2811 config HZ_48
695 bool "Merge relocatable vectors into k !! 2812 bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ
696 depends on !MTD_XIP !! 2813
697 help !! 2814 config HZ_100
698 This option puts relocatable vectors !! 2815 bool "100 HZ" if SYS_SUPPORTS_100HZ || SYS_SUPPORTS_ARBIT_HZ
699 with proper alignment. !! 2816
700 This is a safe choice for most confi !! 2817 config HZ_128
701 !! 2818 bool "128 HZ" if SYS_SUPPORTS_128HZ || SYS_SUPPORTS_ARBIT_HZ
702 config XTENSA_VECTORS_SEPARATE !! 2819
703 bool "Put relocatable vectors at fixed !! 2820 config HZ_250
704 help !! 2821 bool "250 HZ" if SYS_SUPPORTS_250HZ || SYS_SUPPORTS_ARBIT_HZ
705 This option puts relocatable vectors !! 2822
706 Vectors are merged with the .init da !! 2823 config HZ_256
707 are copied into their designated loc !! 2824 bool "256 HZ" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ
708 Use it to put vectors into IRAM or o !! 2825
709 XIP-aware MTD support. !! 2826 config HZ_1000
>> 2827 bool "1000 HZ" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ
>> 2828
>> 2829 config HZ_1024
>> 2830 bool "1024 HZ" if SYS_SUPPORTS_1024HZ || SYS_SUPPORTS_ARBIT_HZ
710 2831
711 endchoice 2832 endchoice
712 2833
713 config VECTORS_ADDR !! 2834 config SYS_SUPPORTS_24HZ
714 hex "Kernel vectors virtual address" !! 2835 bool
715 default 0x00000000 <<
716 depends on XTENSA_VECTORS_SEPARATE <<
717 help <<
718 This is the virtual address of the ( <<
719 It must be within KSEG if MMU is use <<
720 <<
721 config XIP_DATA_ADDR <<
722 hex "XIP kernel data virtual address" <<
723 depends on XIP_KERNEL <<
724 default 0x00000000 <<
725 help <<
726 This is the virtual address where XI <<
727 It must be within KSEG if MMU is use <<
728 2836
729 config PLATFORM_WANT_DEFAULT_MEM !! 2837 config SYS_SUPPORTS_48HZ
730 def_bool n !! 2838 bool
731 2839
732 config DEFAULT_MEM_START !! 2840 config SYS_SUPPORTS_100HZ
733 hex !! 2841 bool
734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !M !! 2842
735 default 0x60000000 if PLATFORM_WANT_DE !! 2843 config SYS_SUPPORTS_128HZ
736 default 0x00000000 !! 2844 bool
737 help !! 2845
738 This is the base address used for bo !! 2846 config SYS_SUPPORTS_250HZ
739 in noMMU configurations. !! 2847 bool
740 2848
741 If unsure, leave the default value h !! 2849 config SYS_SUPPORTS_256HZ
>> 2850 bool
>> 2851
>> 2852 config SYS_SUPPORTS_1000HZ
>> 2853 bool
>> 2854
>> 2855 config SYS_SUPPORTS_1024HZ
>> 2856 bool
>> 2857
>> 2858 config SYS_SUPPORTS_ARBIT_HZ
>> 2859 bool
>> 2860 default y if !SYS_SUPPORTS_24HZ && \
>> 2861 !SYS_SUPPORTS_48HZ && \
>> 2862 !SYS_SUPPORTS_100HZ && \
>> 2863 !SYS_SUPPORTS_128HZ && \
>> 2864 !SYS_SUPPORTS_250HZ && \
>> 2865 !SYS_SUPPORTS_256HZ && \
>> 2866 !SYS_SUPPORTS_1000HZ && \
>> 2867 !SYS_SUPPORTS_1024HZ
>> 2868
>> 2869 config HZ
>> 2870 int
>> 2871 default 24 if HZ_24
>> 2872 default 48 if HZ_48
>> 2873 default 100 if HZ_100
>> 2874 default 128 if HZ_128
>> 2875 default 250 if HZ_250
>> 2876 default 256 if HZ_256
>> 2877 default 1000 if HZ_1000
>> 2878 default 1024 if HZ_1024
>> 2879
>> 2880 config SCHED_HRTICK
>> 2881 def_bool HIGH_RES_TIMERS
>> 2882
>> 2883 config ARCH_SUPPORTS_KEXEC
>> 2884 def_bool y
>> 2885
>> 2886 config ARCH_SUPPORTS_CRASH_DUMP
>> 2887 def_bool y
>> 2888
>> 2889 config PHYSICAL_START
>> 2890 hex "Physical address where the kernel is loaded"
>> 2891 default "0xffffffff84000000"
>> 2892 depends on CRASH_DUMP
>> 2893 help
>> 2894 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
>> 2895 If you plan to use kernel for capturing the crash dump change
>> 2896 this value to start of the reserved region (the "X" value as
>> 2897 specified in the "crashkernel=YM@XM" command line boot parameter
>> 2898 passed to the panic-ed kernel).
>> 2899
>> 2900 config MIPS_O32_FP64_SUPPORT
>> 2901 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
>> 2902 depends on 32BIT || MIPS32_O32
>> 2903 help
>> 2904 When this is enabled, the kernel will support use of 64-bit floating
>> 2905 point registers with binaries using the O32 ABI along with the
>> 2906 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
>> 2907 32-bit MIPS systems this support is at the cost of increasing the
>> 2908 size and complexity of the compiled FPU emulator. Thus if you are
>> 2909 running a MIPS32 system and know that none of your userland binaries
>> 2910 will require 64-bit floating point, you may wish to reduce the size
>> 2911 of your kernel & potentially improve FP emulation performance by
>> 2912 saying N here.
>> 2913
>> 2914 Although binutils currently supports use of this flag the details
>> 2915 concerning its effect upon the O32 ABI in userland are still being
>> 2916 worked on. In order to avoid userland becoming dependent upon current
>> 2917 behaviour before the details have been finalised, this option should
>> 2918 be considered experimental and only enabled by those working upon
>> 2919 said details.
>> 2920
>> 2921 If unsure, say N.
>> 2922
>> 2923 config USE_OF
>> 2924 bool
>> 2925 select OF
>> 2926 select OF_EARLY_FLATTREE
>> 2927 select IRQ_DOMAIN
>> 2928
>> 2929 config UHI_BOOT
>> 2930 bool
>> 2931
>> 2932 config BUILTIN_DTB
>> 2933 bool
742 2934
743 choice 2935 choice
744 prompt "KSEG layout" !! 2936 prompt "Kernel appended dtb support" if USE_OF
745 depends on MMU !! 2937 default MIPS_NO_APPENDED_DTB
746 default XTENSA_KSEG_MMU_V2 <<
747 <<
748 config XTENSA_KSEG_MMU_V2 <<
749 bool "MMUv2: 128MB cached + 128MB unca <<
750 help <<
751 MMUv2 compatible kernel memory map: <<
752 at KSEG_PADDR to 0xd0000000 with cac <<
753 without cache. <<
754 KSEG_PADDR must be aligned to 128MB. <<
755 <<
756 config XTENSA_KSEG_256M <<
757 bool "256MB cached + 256MB uncached" <<
758 depends on INITIALIZE_XTENSA_MMU_INSID <<
759 help <<
760 TLB way 6 maps 256MB starting at KSE <<
761 with cache and to 0xc0000000 without <<
762 KSEG_PADDR must be aligned to 256MB. <<
763 <<
764 config XTENSA_KSEG_512M <<
765 bool "512MB cached + 512MB uncached" <<
766 depends on INITIALIZE_XTENSA_MMU_INSID <<
767 help <<
768 TLB way 6 maps 512MB starting at KSE <<
769 with cache and to 0xc0000000 without <<
770 KSEG_PADDR must be aligned to 256MB. <<
771 2938
>> 2939 config MIPS_NO_APPENDED_DTB
>> 2940 bool "None"
>> 2941 help
>> 2942 Do not enable appended dtb support.
>> 2943
>> 2944 config MIPS_ELF_APPENDED_DTB
>> 2945 bool "vmlinux"
>> 2946 help
>> 2947 With this option, the boot code will look for a device tree binary
>> 2948 DTB) included in the vmlinux ELF section .appended_dtb. By default
>> 2949 it is empty and the DTB can be appended using binutils command
>> 2950 objcopy:
>> 2951
>> 2952 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
>> 2953
>> 2954 This is meant as a backward compatibility convenience for those
>> 2955 systems with a bootloader that can't be upgraded to accommodate
>> 2956 the documented boot protocol using a device tree.
>> 2957
>> 2958 config MIPS_RAW_APPENDED_DTB
>> 2959 bool "vmlinux.bin or vmlinuz.bin"
>> 2960 help
>> 2961 With this option, the boot code will look for a device tree binary
>> 2962 DTB) appended to raw vmlinux.bin or vmlinuz.bin.
>> 2963 (e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
>> 2964
>> 2965 This is meant as a backward compatibility convenience for those
>> 2966 systems with a bootloader that can't be upgraded to accommodate
>> 2967 the documented boot protocol using a device tree.
>> 2968
>> 2969 Beware that there is very little in terms of protection against
>> 2970 this option being confused by leftover garbage in memory that might
>> 2971 look like a DTB header after a reboot if no actual DTB is appended
>> 2972 to vmlinux.bin. Do not leave this option active in a production kernel
>> 2973 if you don't intend to always append a DTB.
772 endchoice 2974 endchoice
773 2975
774 config HIGHMEM !! 2976 choice
775 bool "High Memory Support" !! 2977 prompt "Kernel command line type" if !CMDLINE_OVERRIDE
776 depends on MMU !! 2978 default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
777 select KMAP_LOCAL !! 2979 !MACH_LOONGSON64 && !MIPS_MALTA && \
778 help !! 2980 !CAVIUM_OCTEON_SOC
779 Linux can use the full amount of RAM !! 2981 default MIPS_CMDLINE_FROM_BOOTLOADER
780 default. However, the default MMUv2 !! 2982
781 lowermost 128 MB of memory linearly !! 2983 config MIPS_CMDLINE_FROM_DTB
782 at 0xd0000000 (cached) and 0xd800000 !! 2984 depends on USE_OF
783 When there are more than 128 MB memo !! 2985 bool "Dtb kernel arguments if available"
784 all of it can be "permanently mapped !! 2986
785 The physical memory that's not perma !! 2987 config MIPS_CMDLINE_DTB_EXTEND
786 "high memory". !! 2988 depends on USE_OF
787 !! 2989 bool "Extend dtb kernel arguments with bootloader arguments"
788 If you are compiling a kernel which !! 2990
789 machine with more than 128 MB total !! 2991 config MIPS_CMDLINE_FROM_BOOTLOADER
790 N here. !! 2992 bool "Bootloader kernel arguments if available"
>> 2993
>> 2994 config MIPS_CMDLINE_BUILTIN_EXTEND
>> 2995 depends on CMDLINE_BOOL
>> 2996 bool "Extend builtin kernel arguments with bootloader arguments"
>> 2997 endchoice
791 2998
792 If unsure, say Y. !! 2999 endmenu
793 3000
794 config ARCH_FORCE_MAX_ORDER !! 3001 config LOCKDEP_SUPPORT
795 int "Order of maximal physically conti !! 3002 bool
796 default "10" !! 3003 default y
797 help <<
798 The kernel page allocator limits the <<
799 contiguous allocations. The limit is <<
800 defines the maximal power of two of <<
801 allocated as a single contiguous blo <<
802 overriding the default setting when <<
803 large blocks of physically contiguou <<
804 3004
805 Don't change if unsure. !! 3005 config STACKTRACE_SUPPORT
>> 3006 bool
>> 3007 default y
>> 3008
>> 3009 config PGTABLE_LEVELS
>> 3010 int
>> 3011 default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
>> 3012 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
>> 3013 default 2
>> 3014
>> 3015 config MIPS_AUTO_PFN_OFFSET
>> 3016 bool
>> 3017
>> 3018 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
>> 3019
>> 3020 config PCI_DRIVERS_GENERIC
>> 3021 select PCI_DOMAINS_GENERIC if PCI
>> 3022 bool
806 3023
>> 3024 config PCI_DRIVERS_LEGACY
>> 3025 def_bool !PCI_DRIVERS_GENERIC
>> 3026 select NO_GENERIC_PCI_IOPORT_MAP
>> 3027 select PCI_DOMAINS if PCI
>> 3028
>> 3029 #
>> 3030 # ISA support is now enabled via select. Too many systems still have the one
>> 3031 # or other ISA chip on the board that users don't know about so don't expect
>> 3032 # users to choose the right thing ...
>> 3033 #
>> 3034 config ISA
>> 3035 bool
>> 3036
>> 3037 config TC
>> 3038 bool "TURBOchannel support"
>> 3039 depends on MACH_DECSTATION
>> 3040 help
>> 3041 TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS
>> 3042 processors. TURBOchannel programming specifications are available
>> 3043 at:
>> 3044 <ftp://ftp.hp.com/pub/alphaserver/archive/triadd/>
>> 3045 and:
>> 3046 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
>> 3047 Linux driver support status is documented at:
>> 3048 <http://www.linux-mips.org/wiki/DECstation>
>> 3049
>> 3050 config MMU
>> 3051 bool
>> 3052 default y
>> 3053
>> 3054 config ARCH_MMAP_RND_BITS_MIN
>> 3055 default 12 if 64BIT
>> 3056 default 8
>> 3057
>> 3058 config ARCH_MMAP_RND_BITS_MAX
>> 3059 default 18 if 64BIT
>> 3060 default 15
>> 3061
>> 3062 config ARCH_MMAP_RND_COMPAT_BITS_MIN
>> 3063 default 8
>> 3064
>> 3065 config ARCH_MMAP_RND_COMPAT_BITS_MAX
>> 3066 default 15
>> 3067
>> 3068 config I8253
>> 3069 bool
>> 3070 select CLKSRC_I8253
>> 3071 select CLKEVT_I8253
>> 3072 select MIPS_EXTERNAL_TIMER
807 endmenu 3073 endmenu
808 3074
>> 3075 config TRAD_SIGNALS
>> 3076 bool
>> 3077
>> 3078 config MIPS32_COMPAT
>> 3079 bool
>> 3080
>> 3081 config COMPAT
>> 3082 bool
>> 3083
>> 3084 config MIPS32_O32
>> 3085 bool "Kernel support for o32 binaries"
>> 3086 depends on 64BIT
>> 3087 select ARCH_WANT_OLD_COMPAT_IPC
>> 3088 select COMPAT
>> 3089 select MIPS32_COMPAT
>> 3090 help
>> 3091 Select this option if you want to run o32 binaries. These are pure
>> 3092 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
>> 3093 existing binaries are in this format.
>> 3094
>> 3095 If unsure, say Y.
>> 3096
>> 3097 config MIPS32_N32
>> 3098 bool "Kernel support for n32 binaries"
>> 3099 depends on 64BIT
>> 3100 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
>> 3101 select COMPAT
>> 3102 select MIPS32_COMPAT
>> 3103 help
>> 3104 Select this option if you want to run n32 binaries. These are
>> 3105 64-bit binaries using 32-bit quantities for addressing and certain
>> 3106 data that would normally be 64-bit. They are used in special
>> 3107 cases.
>> 3108
>> 3109 If unsure, say N.
>> 3110
>> 3111 config CC_HAS_MNO_BRANCH_LIKELY
>> 3112 def_bool y
>> 3113 depends on $(cc-option,-mno-branch-likely)
>> 3114
>> 3115 # https://github.com/llvm/llvm-project/issues/61045
>> 3116 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH
>> 3117 def_bool y if CC_IS_CLANG
>> 3118
809 menu "Power management options" 3119 menu "Power management options"
810 3120
811 config ARCH_HIBERNATION_POSSIBLE 3121 config ARCH_HIBERNATION_POSSIBLE
812 def_bool y 3122 def_bool y
>> 3123 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
>> 3124
>> 3125 config ARCH_SUSPEND_POSSIBLE
>> 3126 def_bool y
>> 3127 depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP
813 3128
814 source "kernel/power/Kconfig" 3129 source "kernel/power/Kconfig"
815 3130
816 endmenu 3131 endmenu
>> 3132
>> 3133 config MIPS_EXTERNAL_TIMER
>> 3134 bool
>> 3135
>> 3136 menu "CPU Power Management"
>> 3137
>> 3138 if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3139 source "drivers/cpufreq/Kconfig"
>> 3140 endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
>> 3141
>> 3142 source "drivers/cpuidle/Kconfig"
>> 3143
>> 3144 endmenu
>> 3145
>> 3146 source "arch/mips/kvm/Kconfig"
>> 3147
>> 3148 source "arch/mips/vdso/Kconfig"
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