1 # SPDX-License-Identifier: GPL-2.0 !! 1 # SPDX-License-Identifier: GPL-2.0-only
2 config XTENSA !! 2 config 64BIT
3 def_bool y !! 3 bool "64-bit kernel" if "$(ARCH)" = "sparc"
4 select ARCH_32BIT_OFF_T !! 4 default "$(ARCH)" = "sparc64"
5 select ARCH_HAS_CPU_CACHE_ALIASING !! 5 help
6 select ARCH_HAS_BINFMT_FLAT if !MMU !! 6 SPARC is a family of RISC microprocessors designed and marketed by
7 select ARCH_HAS_CURRENT_STACK_POINTER !! 7 Sun Microsystems, incorporated. They are very widely found in Sun
8 select ARCH_HAS_DEBUG_VM_PGTABLE !! 8 workstations and clones.
9 select ARCH_HAS_DMA_PREP_COHERENT if M !! 9
10 select ARCH_HAS_GCOV_PROFILE_ALL !! 10 Say yes to build a 64-bit kernel - formerly known as sparc64
11 select ARCH_HAS_KCOV !! 11 Say no to build a 32-bit kernel - formerly known as sparc
12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MM !! 12
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if !! 13 config SPARC
14 select ARCH_HAS_DMA_SET_UNCACHED if MM !! 14 bool
15 select ARCH_HAS_STRNCPY_FROM_USER if ! !! 15 default y
16 select ARCH_HAS_STRNLEN_USER !! 16 select ARCH_MIGHT_HAVE_PC_PARPORT if SPARC64 && PCI
17 select ARCH_NEED_CMPXCHG_1_EMU !! 17 select ARCH_MIGHT_HAVE_PC_SERIO
18 select ARCH_USE_MEMTEST !! 18 select DMA_OPS
19 select ARCH_USE_QUEUED_RWLOCKS !! 19 select OF
20 select ARCH_USE_QUEUED_SPINLOCKS !! 20 select OF_PROMTREE
21 select ARCH_WANT_IPC_PARSE_VERSION !! 21 select HAVE_ASM_MODVERSIONS
22 select BUILDTIME_TABLE_SORT !! 22 select HAVE_ARCH_KGDB if !SMP || SPARC64
23 select CLONE_BACKWARDS !! 23 select HAVE_ARCH_TRACEHOOK
24 select COMMON_CLK !! 24 select HAVE_ARCH_SECCOMP if SPARC64
25 select DMA_NONCOHERENT_MMAP if MMU !! 25 select HAVE_EXIT_THREAD
26 select GENERIC_ATOMIC64 !! 26 select HAVE_PCI
>> 27 select SYSCTL_EXCEPTION_TRACE
>> 28 select RTC_CLASS
>> 29 select RTC_DRV_M48T59
>> 30 select RTC_SYSTOHC
>> 31 select HAVE_ARCH_JUMP_LABEL if SPARC64
27 select GENERIC_IRQ_SHOW 32 select GENERIC_IRQ_SHOW
28 select GENERIC_LIB_CMPDI2 !! 33 select ARCH_WANT_IPC_PARSE_VERSION
29 select GENERIC_LIB_MULDI3 <<
30 select GENERIC_LIB_UCMPDI2 <<
31 select GENERIC_PCI_IOMAP 34 select GENERIC_PCI_IOMAP
32 select GENERIC_SCHED_CLOCK !! 35 select HAVE_NMI_WATCHDOG if SPARC64
33 select GENERIC_IOREMAP if MMU !! 36 select HAVE_CBPF_JIT if SPARC32
34 select HAVE_ARCH_AUDITSYSCALL !! 37 select HAVE_EBPF_JIT if SPARC64
35 select HAVE_ARCH_JUMP_LABEL if !XIP_KE !! 38 select HAVE_DEBUG_BUGVERBOSE
36 select HAVE_ARCH_KASAN if MMU && !XIP_ !! 39 select GENERIC_SMP_IDLE_THREAD
37 select HAVE_ARCH_KCSAN !! 40 select MODULES_USE_ELF_RELA
38 select HAVE_ARCH_SECCOMP_FILTER !! 41 select PCI_SYSCALL if PCI
39 select HAVE_ARCH_TRACEHOOK !! 42 select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
40 select HAVE_ASM_MODVERSIONS !! 43 select ODD_RT_SIGACTION
>> 44 select OLD_SIGSUSPEND
>> 45 select CPU_NO_EFFICIENT_FFS
>> 46 select LOCKDEP_SMALL if LOCKDEP
>> 47 select NEED_DMA_MAP_STATE
>> 48 select NEED_SG_DMA_LENGTH
>> 49 select TRACE_IRQFLAGS_SUPPORT
>> 50
>> 51 config SPARC32
>> 52 def_bool !64BIT
>> 53 select ARCH_32BIT_OFF_T
>> 54 select ARCH_HAS_SYNC_DMA_FOR_CPU
>> 55 select CLZ_TAB
>> 56 select DMA_DIRECT_REMAP
>> 57 select GENERIC_ATOMIC64
>> 58 select HAVE_UID16
>> 59 select OLD_SIGACTION
>> 60 select ZONE_DMA
>> 61
>> 62 config SPARC64
>> 63 def_bool 64BIT
>> 64 select ALTERNATE_USER_ADDRESS_SPACE
>> 65 select HAVE_FUNCTION_TRACER
>> 66 select HAVE_FUNCTION_GRAPH_TRACER
>> 67 select HAVE_KRETPROBES
>> 68 select HAVE_KPROBES
>> 69 select MMU_GATHER_RCU_TABLE_FREE if SMP
>> 70 select MMU_GATHER_MERGE_VMAS
>> 71 select MMU_GATHER_NO_FLUSH_CACHE
>> 72 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
>> 73 select HAVE_DYNAMIC_FTRACE
>> 74 select HAVE_FTRACE_MCOUNT_RECORD
>> 75 select HAVE_SYSCALL_TRACEPOINTS
41 select HAVE_CONTEXT_TRACKING_USER 76 select HAVE_CONTEXT_TRACKING_USER
>> 77 select HAVE_TIF_NOHZ
42 select HAVE_DEBUG_KMEMLEAK 78 select HAVE_DEBUG_KMEMLEAK
43 select HAVE_DMA_CONTIGUOUS !! 79 select IOMMU_HELPER
44 select HAVE_EXIT_THREAD !! 80 select SPARSE_IRQ
45 select HAVE_FUNCTION_TRACER !! 81 select RTC_DRV_CMOS
46 select HAVE_GCC_PLUGINS if GCC_VERSION !! 82 select RTC_DRV_BQ4802
47 select HAVE_HW_BREAKPOINT if PERF_EVEN !! 83 select RTC_DRV_SUN4V
48 select HAVE_IRQ_TIME_ACCOUNTING !! 84 select RTC_DRV_STARFIRE
49 select HAVE_PAGE_SIZE_4KB <<
50 select HAVE_PCI <<
51 select HAVE_PERF_EVENTS 85 select HAVE_PERF_EVENTS
52 select HAVE_STACKPROTECTOR <<
53 select HAVE_SYSCALL_TRACEPOINTS <<
54 select HAVE_VIRT_CPU_ACCOUNTING_GEN <<
55 select IRQ_DOMAIN <<
56 select LOCK_MM_AND_FIND_VMA <<
57 select MODULES_USE_ELF_RELA <<
58 select PERF_USE_VMALLOC 86 select PERF_USE_VMALLOC
59 select TRACE_IRQFLAGS_SUPPORT !! 87 select ARCH_HAVE_NMI_SAFE_CMPXCHG
60 help !! 88 select HAVE_C_RECORDMCOUNT
61 Xtensa processors are 32-bit RISC ma !! 89 select HAVE_ARCH_AUDITSYSCALL
62 primarily for embedded systems. The !! 90 select ARCH_SUPPORTS_ATOMIC_RMW
63 configurable and extensible. The Li !! 91 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
64 architecture supports all processor !! 92 select HAVE_NMI
65 with reasonable minimum requirements !! 93 select HAVE_REGS_AND_STACK_ACCESS_API
66 a home page at <http://www.linux-xte !! 94 select ARCH_USE_QUEUED_RWLOCKS
>> 95 select ARCH_USE_QUEUED_SPINLOCKS
>> 96 select GENERIC_TIME_VSYSCALL
>> 97 select ARCH_CLOCKSOURCE_DATA
>> 98 select ARCH_HAS_PTE_SPECIAL
>> 99 select PCI_DOMAINS if PCI
>> 100 select ARCH_HAS_GIGANTIC_PAGE
>> 101 select HAVE_SOFTIRQ_ON_OWN_STACK
>> 102 select HAVE_SETUP_PER_CPU_AREA
>> 103 select NEED_PER_CPU_EMBED_FIRST_CHUNK
>> 104 select NEED_PER_CPU_PAGE_FIRST_CHUNK
67 105
68 config GENERIC_HWEIGHT !! 106 config ARCH_PROC_KCORE_TEXT
69 def_bool y 107 def_bool y
70 108
71 config ARCH_HAS_ILOG2_U32 !! 109 config CPU_BIG_ENDIAN
72 def_bool n <<
73 <<
74 config ARCH_HAS_ILOG2_U64 <<
75 def_bool n <<
76 <<
77 config ARCH_MTD_XIP <<
78 def_bool y 110 def_bool y
79 111
80 config NO_IOPORT_MAP !! 112 config ARCH_ATU
81 def_bool n !! 113 bool
82 !! 114 default y if SPARC64
83 config HZ <<
84 int <<
85 default 100 <<
86 <<
87 config LOCKDEP_SUPPORT <<
88 def_bool y <<
89 115
90 config STACKTRACE_SUPPORT 116 config STACKTRACE_SUPPORT
91 def_bool y !! 117 bool
92 !! 118 default y if SPARC64
93 config MMU <<
94 def_bool n <<
95 select PFAULT <<
96 <<
97 config HAVE_XTENSA_GPIO32 <<
98 def_bool n <<
99 <<
100 config KASAN_SHADOW_OFFSET <<
101 hex <<
102 default 0x6e400000 <<
103 <<
104 config CPU_BIG_ENDIAN <<
105 def_bool $(success,test "$(shell,echo <<
106 <<
107 config CPU_LITTLE_ENDIAN <<
108 def_bool !CPU_BIG_ENDIAN <<
109 <<
110 config CC_HAVE_CALL0_ABI <<
111 def_bool $(success,test "$(shell,echo <<
112 <<
113 menu "Processor type and features" <<
114 <<
115 choice <<
116 prompt "Xtensa Processor Configuration <<
117 default XTENSA_VARIANT_FSF <<
118 <<
119 config XTENSA_VARIANT_FSF <<
120 bool "fsf - default (not generic) conf <<
121 select MMU <<
122 <<
123 config XTENSA_VARIANT_DC232B <<
124 bool "dc232b - Diamond 232L Standard C <<
125 select MMU <<
126 select HAVE_XTENSA_GPIO32 <<
127 help <<
128 This variant refers to Tensilica's D <<
129 <<
130 config XTENSA_VARIANT_DC233C <<
131 bool "dc233c - Diamond 233L Standard C <<
132 select MMU <<
133 select HAVE_XTENSA_GPIO32 <<
134 help <<
135 This variant refers to Tensilica's D <<
136 <<
137 config XTENSA_VARIANT_CUSTOM <<
138 bool "Custom Xtensa processor configur <<
139 select HAVE_XTENSA_GPIO32 <<
140 help <<
141 Select this variant to use a custom <<
142 You will be prompted for a processor <<
143 endchoice <<
144 <<
145 config XTENSA_VARIANT_CUSTOM_NAME <<
146 string "Xtensa Processor Custom Core V <<
147 depends on XTENSA_VARIANT_CUSTOM <<
148 help <<
149 Provide the name of a custom Xtensa <<
150 This CORENAME selects arch/xtensa/va <<
151 Don't forget you have to select MMU <<
152 <<
153 config XTENSA_VARIANT_NAME <<
154 string <<
155 default "dc232b" <<
156 default "dc233c" <<
157 default "fsf" <<
158 default XTENSA_VARIANT_CUSTOM_NAME <<
159 <<
160 config XTENSA_VARIANT_MMU <<
161 bool "Core variant has a Full MMU (TLB <<
162 depends on XTENSA_VARIANT_CUSTOM <<
163 default y <<
164 select MMU <<
165 help <<
166 Build a Conventional Kernel with ful <<
167 ie: it supports a TLB with auto-load <<
168 <<
169 config XTENSA_VARIANT_HAVE_PERF_EVENTS <<
170 bool "Core variant has Performance Mon <<
171 depends on XTENSA_VARIANT_CUSTOM <<
172 default n <<
173 help <<
174 Enable if core variant has Performan <<
175 External Registers Interface. <<
176 119
177 If unsure, say N. !! 120 config LOCKDEP_SUPPORT
>> 121 bool
>> 122 default y if SPARC64
178 123
179 config XTENSA_FAKE_NMI !! 124 config ARCH_HIBERNATION_POSSIBLE
180 bool "Treat PMM IRQ as NMI" !! 125 def_bool y if SPARC64
181 depends on XTENSA_VARIANT_HAVE_PERF_EV <<
182 default n <<
183 help <<
184 If PMM IRQ is the only IRQ at EXCM l <<
185 treat it as NMI, which improves accu <<
186 <<
187 If there are other interrupts at or <<
188 but not above the EXCM level, PMM IR <<
189 but only if these IRQs are not used. <<
190 saying that this is not safe, and a <<
191 actually fire. <<
192 126
193 If unsure, say N. !! 127 config AUDIT_ARCH
>> 128 bool
>> 129 default y
194 130
195 config PFAULT !! 131 config MMU
196 bool "Handle protection faults" if EXP !! 132 bool
197 default y 133 default y
198 help <<
199 Handle protection faults. MMU config <<
200 noMMU configurations may disable it <<
201 generates protection faults or fault <<
202 134
203 If unsure, say Y. !! 135 config HIGHMEM
>> 136 bool
>> 137 default y if SPARC32
>> 138 select KMAP_LOCAL
204 139
205 config XTENSA_UNALIGNED_USER !! 140 config GENERIC_ISA_DMA
206 bool "Unaligned memory access in user !! 141 bool
207 help !! 142 default y if SPARC32
208 The Xtensa architecture currently do <<
209 memory accesses in hardware but thro <<
210 Per default, unaligned memory access <<
211 143
212 Say Y here to enable unaligned memor !! 144 config PGTABLE_LEVELS
>> 145 default 4 if 64BIT
>> 146 default 3
213 147
214 config XTENSA_LOAD_STORE !! 148 config ARCH_SUPPORTS_UPROBES
215 bool "Load/store exception handler for !! 149 def_bool y if SPARC64
216 help <<
217 The Xtensa architecture only allows <<
218 instruction bus with l32r and l32i i <<
219 instructions raise an exception with <<
220 This makes it hard to use some confi <<
221 literals in FLASH memory attached to <<
222 150
223 Say Y here to enable exception handl !! 151 menu "Processor type and features"
224 byte and 2-byte access to memory att <<
225 152
226 config HAVE_SMP !! 153 config SMP
227 bool "System Supports SMP (MX)" !! 154 bool "Symmetric multi-processing support"
228 depends on XTENSA_VARIANT_CUSTOM <<
229 select XTENSA_MX <<
230 help 155 help
231 This option is used to indicate that !! 156 This enables support for systems with more than one CPU. If you have
232 supports Multiprocessing. Multiproce !! 157 a system with only one CPU, say N. If you have a system with more
233 the CPU core definition and currentl !! 158 than one CPU, say Y.
234 !! 159
235 Multiprocessor support is implemente !! 160 If you say N here, the kernel will run on uni- and multiprocessor
236 interrupt controllers. !! 161 machines, but will use only one CPU of a multiprocessor machine. If
>> 162 you say Y here, the kernel will run on many, but not all,
>> 163 uniprocessor machines. On a uniprocessor machine, the kernel
>> 164 will run faster if you say N here.
>> 165
>> 166 People using multiprocessor machines who say Y here should also say
>> 167 Y to "Enhanced Real Time Clock Support", below. The "Advanced Power
>> 168 Management" code will be disabled if you say Y here.
237 169
238 The MX interrupt distributer adds In !! 170 See also <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO
239 and causes the IRQ numbers to be inc !! 171 available at <https://www.tldp.org/docs.html#howto>.
240 like the open cores ethernet driver <<
241 172
242 You still have to select "Enable SMP !! 173 If you don't know what to do here, say N.
243 <<
244 config SMP <<
245 bool "Enable Symmetric multi-processin <<
246 depends on HAVE_SMP <<
247 select GENERIC_SMP_IDLE_THREAD <<
248 help <<
249 Enabled SMP Software; allows more th <<
250 to be activated during startup. <<
251 174
252 config NR_CPUS 175 config NR_CPUS
>> 176 int "Maximum number of CPUs"
253 depends on SMP 177 depends on SMP
254 int "Maximum number of CPUs (2-32)" !! 178 range 2 32 if SPARC32
255 range 2 32 !! 179 range 2 4096 if SPARC64
256 default "4" !! 180 default 32 if SPARC32
257 !! 181 default 4096 if SPARC64
258 config HOTPLUG_CPU <<
259 bool "Enable CPU hotplug support" <<
260 depends on SMP <<
261 help <<
262 Say Y here to allow turning CPUs off <<
263 controlled through /sys/devices/syst <<
264 182
265 Say N if you want to disable CPU hot !! 183 source "kernel/Kconfig.hz"
266 184
267 config SECONDARY_RESET_VECTOR !! 185 config GENERIC_HWEIGHT
268 bool "Secondary cores use alternative !! 186 bool
269 default y 187 default y
270 depends on HAVE_SMP <<
271 help <<
272 Secondary cores may be configured to <<
273 or all cores may use primary reset v <<
274 Say Y here to supply handler for the <<
275 <<
276 config FAST_SYSCALL_XTENSA <<
277 bool "Enable fast atomic syscalls" <<
278 default n <<
279 help <<
280 fast_syscall_xtensa is a syscall tha <<
281 on UP kernel when processor has no s <<
282 188
283 This syscall is deprecated. It may h !! 189 config GENERIC_CALIBRATE_DELAY
284 invalid arguments. It is provided on !! 190 bool
285 Only enable it if your userspace sof !! 191 default y
286 <<
287 If unsure, say N. <<
288 <<
289 config FAST_SYSCALL_SPILL_REGISTERS <<
290 bool "Enable spill registers syscall" <<
291 default n <<
292 help <<
293 fast_syscall_spill_registers is a sy <<
294 register windows of a calling usersp <<
295 <<
296 This syscall is deprecated. It may h <<
297 invalid arguments. It is provided on <<
298 Only enable it if your userspace sof <<
299 <<
300 If unsure, say N. <<
301 <<
302 choice <<
303 prompt "Kernel ABI" <<
304 default KERNEL_ABI_DEFAULT <<
305 help <<
306 Select ABI for the kernel code. This <<
307 supported userspace ABI and any comb <<
308 kernel/userspace ABI is possible and <<
309 <<
310 In case both kernel and userspace su <<
311 all register windows support code wi <<
312 build. <<
313 <<
314 If unsure, choose the default ABI. <<
315 <<
316 config KERNEL_ABI_DEFAULT <<
317 bool "Default ABI" <<
318 help <<
319 Select this option to compile kernel <<
320 selected for the toolchain. <<
321 Normally cores with windowed registe <<
322 cores without it use call0 ABI. <<
323 <<
324 config KERNEL_ABI_CALL0 <<
325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI <<
326 help <<
327 Select this option to compile kernel <<
328 toolchain that defaults to windowed <<
329 When this option is not selected the <<
330 be used for the kernel code. <<
331 <<
332 endchoice <<
333 192
334 config USER_ABI_CALL0 !! 193 config ARCH_MAY_HAVE_PC_FDC
335 bool 194 bool
>> 195 default y
336 196
337 choice !! 197 config EMULATED_CMPXCHG
338 prompt "Userspace ABI" !! 198 bool
339 default USER_ABI_DEFAULT !! 199 default y if SPARC32
340 help 200 help
341 Select supported userspace ABI. !! 201 Sparc32 does not have a CAS instruction like sparc64. cmpxchg()
>> 202 is emulated, and therefore it is not completely atomic.
342 203
343 If unsure, choose the default ABI. !! 204 # Makefile helpers
>> 205 config SPARC32_SMP
>> 206 bool
>> 207 default y
>> 208 depends on SPARC32 && SMP
344 209
345 config USER_ABI_DEFAULT !! 210 config SPARC64_SMP
346 bool "Default ABI only" !! 211 bool
347 help !! 212 default y
348 Assume default userspace ABI. For XE !! 213 depends on SPARC64 && SMP
349 call0 ABI binaries may be run on suc <<
350 will not work correctly for them. <<
351 214
352 config USER_ABI_CALL0_ONLY !! 215 config EARLYFB
353 bool "Call0 ABI only" !! 216 bool "Support for early boot text console"
354 select USER_ABI_CALL0 !! 217 default y
>> 218 depends on SPARC64
355 help 219 help
356 Select this option to support only c !! 220 Say Y here to enable a faster early framebuffer boot console.
357 Windowed ABI binaries will crash wit <<
358 an illegal instruction exception on <<
359 <<
360 Choose this option if you're plannin <<
361 built with call0 ABI. <<
362 221
363 config USER_ABI_CALL0_PROBE !! 222 config HOTPLUG_CPU
364 bool "Support both windowed and call0 !! 223 bool "Support for hot-pluggable CPUs"
365 select USER_ABI_CALL0 !! 224 depends on SPARC64 && SMP
366 help 225 help
367 Select this option to support both w !! 226 Say Y here to experiment with turning CPUs off and on. CPUs
368 ABIs. When enabled all processes are !! 227 can be controlled through /sys/devices/system/cpu/cpu#.
369 and a fast user exception handler fo !! 228 Say N if you want to disable CPU hotplug.
370 used to turn on PS.WOE bit on the fi <<
371 the userspace. <<
372 <<
373 This option should be enabled for th <<
374 both call0 and windowed ABIs in user <<
375 <<
376 Note that Xtensa ISA does not guaran <<
377 raise an illegal instruction excepti <<
378 PS.WOE is disabled, check whether th <<
379 <<
380 endchoice <<
381 <<
382 endmenu <<
383 229
384 config XTENSA_CALIBRATE_CCOUNT !! 230 if SPARC64
385 def_bool n !! 231 source "drivers/cpufreq/Kconfig"
>> 232 endif
>> 233
>> 234 config US3_MC
>> 235 tristate "UltraSPARC-III Memory Controller driver"
>> 236 depends on SPARC64
>> 237 default y
386 help 238 help
387 On some platforms (XT2000, for examp !! 239 This adds a driver for the UltraSPARC-III memory controller.
388 vary. The frequency can be determin !! 240 Loading this driver allows exact mnemonic strings to be
389 against a well known, fixed frequenc !! 241 printed in the event of a memory error, so that the faulty DIMM
390 !! 242 on the motherboard can be matched to the error.
391 config SERIAL_CONSOLE <<
392 def_bool n <<
393 243
394 config PLATFORM_HAVE_XIP !! 244 If in doubt, say Y, as this information can be very useful.
395 def_bool n <<
396 245
397 menu "Platform options" !! 246 # Global things across all Sun machines.
>> 247 config GENERIC_LOCKBREAK
>> 248 bool
>> 249 default y
>> 250 depends on SPARC64 && SMP && PREEMPTION
398 251
399 choice !! 252 config NUMA
400 prompt "Xtensa System Type" !! 253 bool "NUMA support"
401 default XTENSA_PLATFORM_ISS !! 254 depends on SPARC64 && SMP
>> 255
>> 256 config NODES_SHIFT
>> 257 int "Maximum NUMA Nodes (as a power of 2)"
>> 258 range 4 5 if SPARC64
>> 259 default "5"
>> 260 depends on NUMA
>> 261 help
>> 262 Specify the maximum number of NUMA Nodes available on the target
>> 263 system. Increases memory reserved to accommodate various tables.
>> 264
>> 265 config ARCH_SPARSEMEM_ENABLE
>> 266 def_bool y if SPARC64
>> 267 select SPARSEMEM_VMEMMAP_ENABLE
>> 268
>> 269 config ARCH_SPARSEMEM_DEFAULT
>> 270 def_bool y if SPARC64
>> 271
>> 272 config FORCE_MAX_ZONEORDER
>> 273 int "Maximum zone order"
>> 274 default "13"
>> 275 help
>> 276 The kernel memory allocator divides physically contiguous memory
>> 277 blocks into "zones", where each zone is a power of two number of
>> 278 pages. This option selects the largest power of two that the kernel
>> 279 keeps in the memory allocator. If you need to allocate very large
>> 280 blocks of physically contiguous memory, then you may need to
>> 281 increase this value.
402 282
403 config XTENSA_PLATFORM_ISS !! 283 This config option is actually maximum order plus one. For example,
404 bool "ISS" !! 284 a value of 13 means that the largest free memory block is 2^12 pages.
405 select XTENSA_CALIBRATE_CCOUNT <<
406 select SERIAL_CONSOLE <<
407 help <<
408 ISS is an acronym for Tensilica's In <<
409 285
410 config XTENSA_PLATFORM_XT2000 !! 286 if SPARC64
411 bool "XT2000" !! 287 source "kernel/power/Kconfig"
412 help !! 288 endif
413 XT2000 is the name of Tensilica's fe <<
414 This hardware is capable of running <<
415 289
416 config XTENSA_PLATFORM_XTFPGA !! 290 config SCHED_SMT
417 bool "XTFPGA" !! 291 bool "SMT (Hyperthreading) scheduler support"
418 select ETHOC if ETHERNET !! 292 depends on SPARC64 && SMP
419 select PLATFORM_WANT_DEFAULT_MEM if !M !! 293 default y
420 select SERIAL_CONSOLE <<
421 select XTENSA_CALIBRATE_CCOUNT <<
422 select PLATFORM_HAVE_XIP <<
423 help 294 help
424 XTFPGA is the name of Tensilica boar !! 295 SMT scheduler support improves the CPU scheduler's decision making
425 This hardware is capable of running !! 296 when dealing with SPARC cpus at a cost of slightly increased overhead
426 !! 297 in some places. If unsure say N here.
427 endchoice !! 298
428 !! 299 config SCHED_MC
429 config PLATFORM_NR_IRQS !! 300 bool "Multi-core scheduler support"
430 int !! 301 depends on SPARC64 && SMP
431 default 3 if XTENSA_PLATFORM_XT2000 !! 302 default y
432 default 0 <<
433 <<
434 config XTENSA_CPU_CLOCK <<
435 int "CPU clock rate [MHz]" <<
436 depends on !XTENSA_CALIBRATE_CCOUNT <<
437 default 16 <<
438 <<
439 config GENERIC_CALIBRATE_DELAY <<
440 bool "Auto calibration of the BogoMIPS <<
441 help 303 help
442 The BogoMIPS value can easily be der !! 304 Multi-core scheduler support improves the CPU scheduler's decision
>> 305 making when dealing with multi-core CPU chips at a cost of slightly
>> 306 increased overhead in some places. If unsure say N here.
443 307
444 config CMDLINE_BOOL 308 config CMDLINE_BOOL
445 bool "Default bootloader kernel argume 309 bool "Default bootloader kernel arguments"
>> 310 depends on SPARC64
446 311
447 config CMDLINE 312 config CMDLINE
448 string "Initial kernel command string" 313 string "Initial kernel command string"
449 depends on CMDLINE_BOOL 314 depends on CMDLINE_BOOL
450 default "console=ttyS0,38400 root=/dev !! 315 default "console=ttyS0,9600 root=/dev/sda1"
451 help 316 help
452 On some architectures (EBSA110 and C !! 317 Say Y here if you want to be able to pass default arguments to
453 for the boot loader to pass argument !! 318 the kernel. This will be overridden by the bootloader, if you
454 architectures, you should supply som !! 319 use one (such as SILO). This is most useful if you want to boot
455 time by entering them here. As a min !! 320 a kernel from TFTP, and want default options to be available
456 memory size and the root device (e.g !! 321 with having them passed on the command line.
457 322
458 config USE_OF !! 323 NOTE: This option WILL override the PROM bootargs setting!
459 bool "Flattened Device Tree support" !! 324
460 select OF !! 325 config SUN_PM
461 select OF_EARLY_FLATTREE !! 326 bool
>> 327 default y if SPARC32
462 help 328 help
463 Include support for flattened device !! 329 Enable power management and CPU standby features on supported
>> 330 SPARC platforms.
464 331
465 config BUILTIN_DTB_SOURCE !! 332 config SPARC_LED
466 string "DTB to build into the kernel i !! 333 tristate "Sun4m LED driver"
467 depends on OF !! 334 depends on SPARC32
>> 335 help
>> 336 This driver toggles the front-panel LED on sun4m systems
>> 337 in a user-specifiable manner. Its state can be probed
>> 338 by reading /proc/led and its blinking mode can be changed
>> 339 via writes to /proc/led
468 340
469 config PARSE_BOOTPARAM !! 341 config SERIAL_CONSOLE
470 bool "Parse bootparam block" !! 342 bool
>> 343 depends on SPARC32
471 default y 344 default y
472 help 345 help
473 Parse parameters passed to the kerne !! 346 If you say Y here, it will be possible to use a serial port as the
474 be disabled if the kernel is known t !! 347 system console (the system console is the device which receives all
>> 348 kernel messages and warnings and which allows logins in single user
>> 349 mode). This could be useful if some terminal or printer is connected
>> 350 to that serial port.
>> 351
>> 352 Even if you say Y here, the currently visible virtual console
>> 353 (/dev/tty0) will still be used as the system console by default, but
>> 354 you can alter that using a kernel command line option such as
>> 355 "console=ttyS1". (Try "man bootparam" or see the documentation of
>> 356 your boot loader (silo) about how to pass options to the kernel at
>> 357 boot time.)
>> 358
>> 359 If you don't have a graphics card installed and you say Y here, the
>> 360 kernel will automatically use the first serial line, /dev/ttyS0, as
>> 361 system console.
475 362
476 If unsure, say Y. !! 363 If unsure, say N.
477 <<
478 choice <<
479 prompt "Semihosting interface" <<
480 default XTENSA_SIMCALL_ISS <<
481 depends on XTENSA_PLATFORM_ISS <<
482 help <<
483 Choose semihosting interface that wi <<
484 block device and networking. <<
485 364
486 config XTENSA_SIMCALL_ISS !! 365 config SPARC_LEON
487 bool "simcall" !! 366 bool "Sparc Leon processor family"
>> 367 depends on SPARC32
>> 368 select USB_EHCI_BIG_ENDIAN_MMIO
>> 369 select USB_EHCI_BIG_ENDIAN_DESC
>> 370 select USB_UHCI_BIG_ENDIAN_MMIO
>> 371 select USB_UHCI_BIG_ENDIAN_DESC
>> 372 help
>> 373 If you say Y here if you are running on a SPARC-LEON processor.
>> 374 The LEON processor is a synthesizable VHDL model of the
>> 375 SPARC-v8 standard. LEON is part of the GRLIB collection of
>> 376 IP cores that are distributed under GPL. GRLIB can be downloaded
>> 377 from www.gaisler.com. You can download a sparc-linux cross-compilation
>> 378 toolchain at www.gaisler.com.
>> 379
>> 380 if SPARC_LEON
>> 381 menu "U-Boot options"
>> 382
>> 383 config UBOOT_LOAD_ADDR
>> 384 hex "uImage Load Address"
>> 385 default 0x40004000
>> 386 help
>> 387 U-Boot kernel load address, the address in physical address space
>> 388 where u-boot will place the Linux kernel before booting it.
>> 389 This address is normally the base address of main memory + 0x4000.
>> 390
>> 391 config UBOOT_FLASH_ADDR
>> 392 hex "uImage.o Load Address"
>> 393 default 0x00080000
>> 394 help
>> 395 Optional setting only affecting the uImage.o ELF-image used to
>> 396 download the uImage file to the target using a ELF-loader other than
>> 397 U-Boot. It may for example be used to download an uImage to FLASH with
>> 398 the GRMON utility before even starting u-boot.
>> 399
>> 400 config UBOOT_ENTRY_ADDR
>> 401 hex "uImage Entry Address"
>> 402 default 0xf0004000
488 help 403 help
489 Use simcall instruction. simcall is !! 404 Do not change this unless you know what you're doing. This is
490 it does nothing on hardware. !! 405 hardcoded by the SPARC32 and LEON port.
491 406
492 config XTENSA_SIMCALL_GDBIO !! 407 This is the virtual address u-boot jumps to when booting the Linux
493 bool "GDBIO" !! 408 Kernel.
494 help <<
495 Use break instruction. It is availab <<
496 is attached to it via JTAG. <<
497 409
498 endchoice !! 410 endmenu
>> 411 endif
499 412
500 config BLK_DEV_SIMDISK !! 413 endmenu
501 tristate "Host file-based simulated bl <<
502 default n <<
503 depends on XTENSA_PLATFORM_ISS && BLOC <<
504 help <<
505 Create block devices that map to fil <<
506 Device binding to host file may be c <<
507 interface provided the device is not <<
508 414
509 config BLK_DEV_SIMDISK_COUNT !! 415 menu "Bus options (PCI etc.)"
510 int "Number of host file-based simulat !! 416 config SBUS
511 range 1 10 !! 417 bool
512 depends on BLK_DEV_SIMDISK !! 418 default y
513 default 2 <<
514 help <<
515 This is the default minimal number o <<
516 Kernel/module parameter 'simdisk_cou <<
517 value at runtime. More file names (b <<
518 specified as parameters, simdisk_cou <<
519 419
520 config SIMDISK0_FILENAME !! 420 config SBUSCHAR
521 string "Host filename for the first si !! 421 bool
522 depends on BLK_DEV_SIMDISK = y !! 422 default y
523 default "" <<
524 help <<
525 Attach a first simdisk to a host fil <<
526 contains a root file system. <<
527 423
528 config SIMDISK1_FILENAME !! 424 config SUN_LDOMS
529 string "Host filename for the second s !! 425 bool "Sun Logical Domains support"
530 depends on BLK_DEV_SIMDISK = y && BLK_ !! 426 depends on SPARC64
531 default "" <<
532 help 427 help
533 Another simulated disk in a host fil !! 428 Say Y here is you want to support virtual devices via
534 storage. !! 429 Logical Domains.
535 430
536 config XTFPGA_LCD !! 431 config PCIC_PCI
537 bool "Enable XTFPGA LCD driver" !! 432 bool
538 depends on XTENSA_PLATFORM_XTFPGA !! 433 depends on PCI && SPARC32 && !SPARC_LEON
539 default n !! 434 default y
540 help <<
541 There's a 2x16 LCD on most of XTFPGA <<
542 progress messages there during bootu <<
543 during board bringup. <<
544 435
545 If unsure, say N. !! 436 config LEON_PCI
>> 437 bool
>> 438 depends on PCI && SPARC_LEON
>> 439 default y
546 440
547 config XTFPGA_LCD_BASE_ADDR !! 441 config SPARC_GRPCI1
548 hex "XTFPGA LCD base address" !! 442 bool "GRPCI Host Bridge Support"
549 depends on XTFPGA_LCD !! 443 depends on LEON_PCI
550 default "0x0d0c0000" !! 444 default y
551 help !! 445 help
552 Base address of the LCD controller i !! 446 Say Y here to include the GRPCI Host Bridge Driver. The GRPCI
553 Different boards from XTFPGA family !! 447 PCI host controller is typically found in GRLIB SPARC32/LEON
554 addresses. Please consult prototypin !! 448 systems. The driver has one property (all_pci_errors) controlled
555 the correct address. Wrong address h !! 449 from the bootloader that makes the GRPCI to generate interrupts
556 !! 450 on detected PCI Parity and System errors.
557 config XTFPGA_LCD_8BIT_ACCESS !! 451
558 bool "Use 8-bit access to XTFPGA LCD" !! 452 config SPARC_GRPCI2
559 depends on XTFPGA_LCD !! 453 bool "GRPCI2 Host Bridge Support"
560 default n !! 454 depends on LEON_PCI
561 help !! 455 default y
562 LCD may be connected with 4- or 8-bi !! 456 help
563 only be used with 8-bit interface. P !! 457 Say Y here to include the GRPCI2 Host Bridge Driver.
564 guide for your board for the correct <<
565 <<
566 comment "Kernel memory layout" <<
567 <<
568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX <<
569 bool "Initialize Xtensa MMU inside the <<
570 depends on !XTENSA_VARIANT_FSF && !XTE <<
571 default y if XTENSA_VARIANT_DC233C || <<
572 help <<
573 Earlier version initialized the MMU <<
574 before jumping to _startup in head.S <<
575 it was possible to place a software <<
576 then enter your normal kernel breakp <<
577 to the kernel mappings (0XC0000000). <<
578 <<
579 This unfortunately won't work for U- <<
580 work for using KEXEC to have a hot k <<
581 KDUMP. <<
582 <<
583 So now the MMU is initialized in hea <<
584 use hardware breakpoints (gdb 'hbrea <<
585 xt-gdb can't place a Software Breakp <<
586 to mapping the MMU and after mapping <<
587 was mapped gdb wouldn't remove the b <<
588 PC wouldn't match. Since Hardware Br <<
589 Linux configurations it seems reason <<
590 and leave this older mechanism for u <<
591 not to follow Tensilica's recommenda <<
592 <<
593 Selecting this will cause U-Boot to <<
594 address at 0x00003000 instead of the <<
595 <<
596 If in doubt, say Y. <<
597 <<
598 config XIP_KERNEL <<
599 bool "Kernel Execute-In-Place from ROM <<
600 depends on PLATFORM_HAVE_XIP <<
601 help <<
602 Execute-In-Place allows the kernel t <<
603 directly addressable by the CPU, suc <<
604 space since the text section of the <<
605 to RAM. Read-write sections, such as <<
606 are still copied to RAM. The XIP ker <<
607 it has to run directly from flash, s <<
608 store it. The flash address used to <<
609 and for storing it, is configuration <<
610 say Y here, you must know the proper <<
611 store the kernel image depending on <<
612 <<
613 Also note that the make target becom <<
614 "make Image" or "make uImage". The f <<
615 ROM memory will be arch/xtensa/boot/ <<
616 458
617 If unsure, say N. !! 459 config SUN_OPENPROMFS
>> 460 tristate "Openprom tree appears in /proc/openprom"
>> 461 help
>> 462 If you say Y, the OpenPROM device tree will be available as a
>> 463 virtual file system, which you can mount to /proc/openprom by "mount
>> 464 -t openpromfs none /proc/openprom".
618 465
619 config MEMMAP_CACHEATTR !! 466 To compile the /proc/openprom support as a module, choose M here: the
620 hex "Cache attributes for the memory a !! 467 module will be called openpromfs.
621 depends on !MMU <<
622 default 0x22222222 <<
623 help <<
624 These cache attributes are set up fo <<
625 specifies cache attributes for the c <<
626 region: bits 0..3 -- for addresses 0 <<
627 bits 4..7 -- for addresses 0x2000000 <<
628 <<
629 Cache attribute values are specific <<
630 For region protection MMUs: <<
631 1: WT cached, <<
632 2: cache bypass, <<
633 4: WB cached, <<
634 f: illegal. <<
635 For full MMU: <<
636 bit 0: executable, <<
637 bit 1: writable, <<
638 bits 2..3: <<
639 0: cache bypass, <<
640 1: WB cache, <<
641 2: WT cache, <<
642 3: special (c and e are illegal, <<
643 For MPU: <<
644 0: illegal, <<
645 1: WB cache, <<
646 2: WB, no-write-allocate cache, <<
647 3: WT cache, <<
648 4: cache bypass. <<
649 <<
650 config KSEG_PADDR <<
651 hex "Physical address of the KSEG mapp <<
652 depends on INITIALIZE_XTENSA_MMU_INSID <<
653 default 0x00000000 <<
654 help <<
655 This is the physical address where K <<
656 the chosen KSEG layout help for the <<
657 Unpacked kernel image (including vec <<
658 within KSEG. <<
659 Physical memory below this address i <<
660 <<
661 If unsure, leave the default value h <<
662 <<
663 config KERNEL_VIRTUAL_ADDRESS <<
664 hex "Kernel virtual address" <<
665 depends on MMU && XIP_KERNEL <<
666 default 0xd0003000 <<
667 help <<
668 This is the virtual address where th <<
669 XIP kernel may be mapped into KSEG o <<
670 provided here must match kernel load <<
671 KERNEL_LOAD_ADDRESS. <<
672 <<
673 config KERNEL_LOAD_ADDRESS <<
674 hex "Kernel load address" <<
675 default 0x60003000 if !MMU <<
676 default 0x00003000 if MMU && INITIALIZ <<
677 default 0xd0003000 if MMU && !INITIALI <<
678 help <<
679 This is the address where the kernel <<
680 It is virtual address for MMUv2 conf <<
681 for all other configurations. <<
682 <<
683 If unsure, leave the default value h <<
684 <<
685 choice <<
686 prompt "Relocatable vectors location" <<
687 default XTENSA_VECTORS_IN_TEXT <<
688 help <<
689 Choose whether relocatable vectors a <<
690 or placed separately at runtime. Thi <<
691 configurations without VECBASE regis <<
692 placed at their hardware-defined loc <<
693 <<
694 config XTENSA_VECTORS_IN_TEXT <<
695 bool "Merge relocatable vectors into k <<
696 depends on !MTD_XIP <<
697 help <<
698 This option puts relocatable vectors <<
699 with proper alignment. <<
700 This is a safe choice for most confi <<
701 <<
702 config XTENSA_VECTORS_SEPARATE <<
703 bool "Put relocatable vectors at fixed <<
704 help <<
705 This option puts relocatable vectors <<
706 Vectors are merged with the .init da <<
707 are copied into their designated loc <<
708 Use it to put vectors into IRAM or o <<
709 XIP-aware MTD support. <<
710 <<
711 endchoice <<
712 <<
713 config VECTORS_ADDR <<
714 hex "Kernel vectors virtual address" <<
715 default 0x00000000 <<
716 depends on XTENSA_VECTORS_SEPARATE <<
717 help <<
718 This is the virtual address of the ( <<
719 It must be within KSEG if MMU is use <<
720 <<
721 config XIP_DATA_ADDR <<
722 hex "XIP kernel data virtual address" <<
723 depends on XIP_KERNEL <<
724 default 0x00000000 <<
725 help <<
726 This is the virtual address where XI <<
727 It must be within KSEG if MMU is use <<
728 <<
729 config PLATFORM_WANT_DEFAULT_MEM <<
730 def_bool n <<
731 <<
732 config DEFAULT_MEM_START <<
733 hex <<
734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !M <<
735 default 0x60000000 if PLATFORM_WANT_DE <<
736 default 0x00000000 <<
737 help <<
738 This is the base address used for bo <<
739 in noMMU configurations. <<
740 <<
741 If unsure, leave the default value h <<
742 <<
743 choice <<
744 prompt "KSEG layout" <<
745 depends on MMU <<
746 default XTENSA_KSEG_MMU_V2 <<
747 <<
748 config XTENSA_KSEG_MMU_V2 <<
749 bool "MMUv2: 128MB cached + 128MB unca <<
750 help <<
751 MMUv2 compatible kernel memory map: <<
752 at KSEG_PADDR to 0xd0000000 with cac <<
753 without cache. <<
754 KSEG_PADDR must be aligned to 128MB. <<
755 <<
756 config XTENSA_KSEG_256M <<
757 bool "256MB cached + 256MB uncached" <<
758 depends on INITIALIZE_XTENSA_MMU_INSID <<
759 help <<
760 TLB way 6 maps 256MB starting at KSE <<
761 with cache and to 0xc0000000 without <<
762 KSEG_PADDR must be aligned to 256MB. <<
763 <<
764 config XTENSA_KSEG_512M <<
765 bool "512MB cached + 512MB uncached" <<
766 depends on INITIALIZE_XTENSA_MMU_INSID <<
767 help <<
768 TLB way 6 maps 512MB starting at KSE <<
769 with cache and to 0xc0000000 without <<
770 KSEG_PADDR must be aligned to 256MB. <<
771 468
772 endchoice !! 469 Only choose N if you know in advance that you will not need to modify
>> 470 OpenPROM settings on the running system.
773 471
774 config HIGHMEM !! 472 # Makefile helpers
775 bool "High Memory Support" !! 473 config SPARC64_PCI
776 depends on MMU !! 474 bool
777 select KMAP_LOCAL !! 475 default y
778 help !! 476 depends on SPARC64 && PCI
779 Linux can use the full amount of RAM <<
780 default. However, the default MMUv2 <<
781 lowermost 128 MB of memory linearly <<
782 at 0xd0000000 (cached) and 0xd800000 <<
783 When there are more than 128 MB memo <<
784 all of it can be "permanently mapped <<
785 The physical memory that's not perma <<
786 "high memory". <<
787 <<
788 If you are compiling a kernel which <<
789 machine with more than 128 MB total <<
790 N here. <<
791 <<
792 If unsure, say Y. <<
793 <<
794 config ARCH_FORCE_MAX_ORDER <<
795 int "Order of maximal physically conti <<
796 default "10" <<
797 help <<
798 The kernel page allocator limits the <<
799 contiguous allocations. The limit is <<
800 defines the maximal power of two of <<
801 allocated as a single contiguous blo <<
802 overriding the default setting when <<
803 large blocks of physically contiguou <<
804 477
805 Don't change if unsure. !! 478 config SPARC64_PCI_MSI
>> 479 bool
>> 480 default y
>> 481 depends on SPARC64_PCI && PCI_MSI
806 482
807 endmenu 483 endmenu
808 484
809 menu "Power management options" !! 485 config COMPAT
810 !! 486 bool
811 config ARCH_HIBERNATION_POSSIBLE !! 487 depends on SPARC64
812 def_bool y !! 488 default y
813 !! 489 select HAVE_UID16
814 source "kernel/power/Kconfig" !! 490 select ARCH_WANT_OLD_COMPAT_IPC
>> 491 select COMPAT_OLD_SIGACTION
815 492
816 endmenu !! 493 source "drivers/sbus/char/Kconfig"
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