1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 config XTENSA !! 2 config M68K
3 def_bool y !! 3 bool
>> 4 default y
4 select ARCH_32BIT_OFF_T 5 select ARCH_32BIT_OFF_T
>> 6 select ARCH_HAS_BINFMT_FLAT
5 select ARCH_HAS_CPU_CACHE_ALIASING 7 select ARCH_HAS_CPU_CACHE_ALIASING
6 select ARCH_HAS_BINFMT_FLAT if !MMU !! 8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
7 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_CURRENT_STACK_POINTER
8 select ARCH_HAS_DEBUG_VM_PGTABLE !! 10 select ARCH_HAS_DMA_PREP_COHERENT if M68K_NONCOHERENT_DMA && !COLDFIRE
9 select ARCH_HAS_DMA_PREP_COHERENT if M !! 11 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if M68K_NONCOHERENT_DMA
10 select ARCH_HAS_GCOV_PROFILE_ALL !! 12 select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS
11 select ARCH_HAS_KCOV !! 13 select ARCH_MIGHT_HAVE_PC_PARPORT if ISA
12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MM !! 14 select ARCH_NO_PREEMPT if !COLDFIRE
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if !! 15 select ARCH_USE_MEMTEST if MMU_MOTOROLA
14 select ARCH_HAS_DMA_SET_UNCACHED if MM <<
15 select ARCH_HAS_STRNCPY_FROM_USER if ! <<
16 select ARCH_HAS_STRNLEN_USER <<
17 select ARCH_NEED_CMPXCHG_1_EMU <<
18 select ARCH_USE_MEMTEST <<
19 select ARCH_USE_QUEUED_RWLOCKS <<
20 select ARCH_USE_QUEUED_SPINLOCKS <<
21 select ARCH_WANT_IPC_PARSE_VERSION 16 select ARCH_WANT_IPC_PARSE_VERSION
22 select BUILDTIME_TABLE_SORT !! 17 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
23 select CLONE_BACKWARDS !! 18 select DMA_DIRECT_REMAP if M68K_NONCOHERENT_DMA && !COLDFIRE
24 select COMMON_CLK <<
25 select DMA_NONCOHERENT_MMAP if MMU <<
26 select GENERIC_ATOMIC64 19 select GENERIC_ATOMIC64
>> 20 select GENERIC_CPU_DEVICES
>> 21 select GENERIC_IOMAP if HAS_IOPORT
27 select GENERIC_IRQ_SHOW 22 select GENERIC_IRQ_SHOW
28 select GENERIC_LIB_CMPDI2 !! 23 select GENERIC_LIB_ASHLDI3
29 select GENERIC_LIB_MULDI3 !! 24 select GENERIC_LIB_ASHRDI3
30 select GENERIC_LIB_UCMPDI2 !! 25 select GENERIC_LIB_LSHRDI3
31 select GENERIC_PCI_IOMAP !! 26 select HAS_IOPORT if PCI || ISA || ATARI_ROM_ISA
32 select GENERIC_SCHED_CLOCK !! 27 select HAVE_ARCH_SECCOMP
33 select GENERIC_IOREMAP if MMU <<
34 select HAVE_ARCH_AUDITSYSCALL <<
35 select HAVE_ARCH_JUMP_LABEL if !XIP_KE <<
36 select HAVE_ARCH_KASAN if MMU && !XIP_ <<
37 select HAVE_ARCH_KCSAN <<
38 select HAVE_ARCH_SECCOMP_FILTER 28 select HAVE_ARCH_SECCOMP_FILTER
39 select HAVE_ARCH_TRACEHOOK <<
40 select HAVE_ASM_MODVERSIONS 29 select HAVE_ASM_MODVERSIONS
41 select HAVE_CONTEXT_TRACKING_USER !! 30 select HAVE_DEBUG_BUGVERBOSE
42 select HAVE_DEBUG_KMEMLEAK !! 31 select HAVE_EFFICIENT_UNALIGNED_ACCESS if !CPU_HAS_NO_UNALIGNED
43 select HAVE_DMA_CONTIGUOUS !! 32 select HAVE_MOD_ARCH_SPECIFIC
44 select HAVE_EXIT_THREAD !! 33 select HAVE_UID16
45 select HAVE_FUNCTION_TRACER !! 34 select MMU_GATHER_NO_RANGE if MMU
46 select HAVE_GCC_PLUGINS if GCC_VERSION !! 35 select MODULES_USE_ELF_REL
47 select HAVE_HW_BREAKPOINT if PERF_EVEN <<
48 select HAVE_IRQ_TIME_ACCOUNTING <<
49 select HAVE_PAGE_SIZE_4KB <<
50 select HAVE_PCI <<
51 select HAVE_PERF_EVENTS <<
52 select HAVE_STACKPROTECTOR <<
53 select HAVE_SYSCALL_TRACEPOINTS <<
54 select HAVE_VIRT_CPU_ACCOUNTING_GEN <<
55 select IRQ_DOMAIN <<
56 select LOCK_MM_AND_FIND_VMA <<
57 select MODULES_USE_ELF_RELA 36 select MODULES_USE_ELF_RELA
58 select PERF_USE_VMALLOC !! 37 select NO_DMA if !MMU && !COLDFIRE
59 select TRACE_IRQFLAGS_SUPPORT !! 38 select OLD_SIGACTION
60 help !! 39 select OLD_SIGSUSPEND3
61 Xtensa processors are 32-bit RISC ma !! 40 select UACCESS_MEMCPY if !MMU
62 primarily for embedded systems. The !! 41 select ZONE_DMA
63 configurable and extensible. The Li <<
64 architecture supports all processor <<
65 with reasonable minimum requirements <<
66 a home page at <http://www.linux-xte <<
67 42
68 config GENERIC_HWEIGHT !! 43 config CPU_BIG_ENDIAN
69 def_bool y 44 def_bool y
70 45
71 config ARCH_HAS_ILOG2_U32 46 config ARCH_HAS_ILOG2_U32
72 def_bool n !! 47 bool
73 48
74 config ARCH_HAS_ILOG2_U64 49 config ARCH_HAS_ILOG2_U64
75 def_bool n !! 50 bool
76 <<
77 config ARCH_MTD_XIP <<
78 def_bool y <<
79 <<
80 config NO_IOPORT_MAP <<
81 def_bool n <<
82 <<
83 config HZ <<
84 int <<
85 default 100 <<
86 <<
87 config LOCKDEP_SUPPORT <<
88 def_bool y <<
89 <<
90 config STACKTRACE_SUPPORT <<
91 def_bool y <<
92 <<
93 config MMU <<
94 def_bool n <<
95 select PFAULT <<
96 <<
97 config HAVE_XTENSA_GPIO32 <<
98 def_bool n <<
99 <<
100 config KASAN_SHADOW_OFFSET <<
101 hex <<
102 default 0x6e400000 <<
103 <<
104 config CPU_BIG_ENDIAN <<
105 def_bool $(success,test "$(shell,echo <<
106 <<
107 config CPU_LITTLE_ENDIAN <<
108 def_bool !CPU_BIG_ENDIAN <<
109 <<
110 config CC_HAVE_CALL0_ABI <<
111 def_bool $(success,test "$(shell,echo <<
112 <<
113 menu "Processor type and features" <<
114 <<
115 choice <<
116 prompt "Xtensa Processor Configuration <<
117 default XTENSA_VARIANT_FSF <<
118 <<
119 config XTENSA_VARIANT_FSF <<
120 bool "fsf - default (not generic) conf <<
121 select MMU <<
122 <<
123 config XTENSA_VARIANT_DC232B <<
124 bool "dc232b - Diamond 232L Standard C <<
125 select MMU <<
126 select HAVE_XTENSA_GPIO32 <<
127 help <<
128 This variant refers to Tensilica's D <<
129 <<
130 config XTENSA_VARIANT_DC233C <<
131 bool "dc233c - Diamond 233L Standard C <<
132 select MMU <<
133 select HAVE_XTENSA_GPIO32 <<
134 help <<
135 This variant refers to Tensilica's D <<
136 <<
137 config XTENSA_VARIANT_CUSTOM <<
138 bool "Custom Xtensa processor configur <<
139 select HAVE_XTENSA_GPIO32 <<
140 help <<
141 Select this variant to use a custom <<
142 You will be prompted for a processor <<
143 endchoice <<
144 <<
145 config XTENSA_VARIANT_CUSTOM_NAME <<
146 string "Xtensa Processor Custom Core V <<
147 depends on XTENSA_VARIANT_CUSTOM <<
148 help <<
149 Provide the name of a custom Xtensa <<
150 This CORENAME selects arch/xtensa/va <<
151 Don't forget you have to select MMU <<
152 <<
153 config XTENSA_VARIANT_NAME <<
154 string <<
155 default "dc232b" <<
156 default "dc233c" <<
157 default "fsf" <<
158 default XTENSA_VARIANT_CUSTOM_NAME <<
159 <<
160 config XTENSA_VARIANT_MMU <<
161 bool "Core variant has a Full MMU (TLB <<
162 depends on XTENSA_VARIANT_CUSTOM <<
163 default y <<
164 select MMU <<
165 help <<
166 Build a Conventional Kernel with ful <<
167 ie: it supports a TLB with auto-load <<
168 <<
169 config XTENSA_VARIANT_HAVE_PERF_EVENTS <<
170 bool "Core variant has Performance Mon <<
171 depends on XTENSA_VARIANT_CUSTOM <<
172 default n <<
173 help <<
174 Enable if core variant has Performan <<
175 External Registers Interface. <<
176 <<
177 If unsure, say N. <<
178 <<
179 config XTENSA_FAKE_NMI <<
180 bool "Treat PMM IRQ as NMI" <<
181 depends on XTENSA_VARIANT_HAVE_PERF_EV <<
182 default n <<
183 help <<
184 If PMM IRQ is the only IRQ at EXCM l <<
185 treat it as NMI, which improves accu <<
186 <<
187 If there are other interrupts at or <<
188 but not above the EXCM level, PMM IR <<
189 but only if these IRQs are not used. <<
190 saying that this is not safe, and a <<
191 actually fire. <<
192 <<
193 If unsure, say N. <<
194 51
195 config PFAULT !! 52 config GENERIC_HWEIGHT
196 bool "Handle protection faults" if EXP !! 53 bool
197 default y 54 default y
198 help <<
199 Handle protection faults. MMU config <<
200 noMMU configurations may disable it <<
201 generates protection faults or fault <<
202 <<
203 If unsure, say Y. <<
204 55
205 config XTENSA_UNALIGNED_USER !! 56 config GENERIC_CALIBRATE_DELAY
206 bool "Unaligned memory access in user !! 57 bool
207 help <<
208 The Xtensa architecture currently do <<
209 memory accesses in hardware but thro <<
210 Per default, unaligned memory access <<
211 <<
212 Say Y here to enable unaligned memor <<
213 <<
214 config XTENSA_LOAD_STORE <<
215 bool "Load/store exception handler for <<
216 help <<
217 The Xtensa architecture only allows <<
218 instruction bus with l32r and l32i i <<
219 instructions raise an exception with <<
220 This makes it hard to use some confi <<
221 literals in FLASH memory attached to <<
222 <<
223 Say Y here to enable exception handl <<
224 byte and 2-byte access to memory att <<
225 <<
226 config HAVE_SMP <<
227 bool "System Supports SMP (MX)" <<
228 depends on XTENSA_VARIANT_CUSTOM <<
229 select XTENSA_MX <<
230 help <<
231 This option is used to indicate that <<
232 supports Multiprocessing. Multiproce <<
233 the CPU core definition and currentl <<
234 <<
235 Multiprocessor support is implemente <<
236 interrupt controllers. <<
237 <<
238 The MX interrupt distributer adds In <<
239 and causes the IRQ numbers to be inc <<
240 like the open cores ethernet driver <<
241 <<
242 You still have to select "Enable SMP <<
243 <<
244 config SMP <<
245 bool "Enable Symmetric multi-processin <<
246 depends on HAVE_SMP <<
247 select GENERIC_SMP_IDLE_THREAD <<
248 help <<
249 Enabled SMP Software; allows more th <<
250 to be activated during startup. <<
251 <<
252 config NR_CPUS <<
253 depends on SMP <<
254 int "Maximum number of CPUs (2-32)" <<
255 range 2 32 <<
256 default "4" <<
257 <<
258 config HOTPLUG_CPU <<
259 bool "Enable CPU hotplug support" <<
260 depends on SMP <<
261 help <<
262 Say Y here to allow turning CPUs off <<
263 controlled through /sys/devices/syst <<
264 <<
265 Say N if you want to disable CPU hot <<
266 <<
267 config SECONDARY_RESET_VECTOR <<
268 bool "Secondary cores use alternative <<
269 default y 58 default y
270 depends on HAVE_SMP <<
271 help <<
272 Secondary cores may be configured to <<
273 or all cores may use primary reset v <<
274 Say Y here to supply handler for the <<
275 <<
276 config FAST_SYSCALL_XTENSA <<
277 bool "Enable fast atomic syscalls" <<
278 default n <<
279 help <<
280 fast_syscall_xtensa is a syscall tha <<
281 on UP kernel when processor has no s <<
282 <<
283 This syscall is deprecated. It may h <<
284 invalid arguments. It is provided on <<
285 Only enable it if your userspace sof <<
286 <<
287 If unsure, say N. <<
288 <<
289 config FAST_SYSCALL_SPILL_REGISTERS <<
290 bool "Enable spill registers syscall" <<
291 default n <<
292 help <<
293 fast_syscall_spill_registers is a sy <<
294 register windows of a calling usersp <<
295 <<
296 This syscall is deprecated. It may h <<
297 invalid arguments. It is provided on <<
298 Only enable it if your userspace sof <<
299 <<
300 If unsure, say N. <<
301 <<
302 choice <<
303 prompt "Kernel ABI" <<
304 default KERNEL_ABI_DEFAULT <<
305 help <<
306 Select ABI for the kernel code. This <<
307 supported userspace ABI and any comb <<
308 kernel/userspace ABI is possible and <<
309 <<
310 In case both kernel and userspace su <<
311 all register windows support code wi <<
312 build. <<
313 59
314 If unsure, choose the default ABI. !! 60 config GENERIC_CSUM
315 <<
316 config KERNEL_ABI_DEFAULT <<
317 bool "Default ABI" <<
318 help <<
319 Select this option to compile kernel <<
320 selected for the toolchain. <<
321 Normally cores with windowed registe <<
322 cores without it use call0 ABI. <<
323 <<
324 config KERNEL_ABI_CALL0 <<
325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI <<
326 help <<
327 Select this option to compile kernel <<
328 toolchain that defaults to windowed <<
329 When this option is not selected the <<
330 be used for the kernel code. <<
331 <<
332 endchoice <<
333 <<
334 config USER_ABI_CALL0 <<
335 bool 61 bool
336 62
337 choice !! 63 config TIME_LOW_RES
338 prompt "Userspace ABI" !! 64 bool
339 default USER_ABI_DEFAULT !! 65 default y
340 help <<
341 Select supported userspace ABI. <<
342 <<
343 If unsure, choose the default ABI. <<
344 <<
345 config USER_ABI_DEFAULT <<
346 bool "Default ABI only" <<
347 help <<
348 Assume default userspace ABI. For XE <<
349 call0 ABI binaries may be run on suc <<
350 will not work correctly for them. <<
351 <<
352 config USER_ABI_CALL0_ONLY <<
353 bool "Call0 ABI only" <<
354 select USER_ABI_CALL0 <<
355 help <<
356 Select this option to support only c <<
357 Windowed ABI binaries will crash wit <<
358 an illegal instruction exception on <<
359 <<
360 Choose this option if you're plannin <<
361 built with call0 ABI. <<
362 <<
363 config USER_ABI_CALL0_PROBE <<
364 bool "Support both windowed and call0 <<
365 select USER_ABI_CALL0 <<
366 help <<
367 Select this option to support both w <<
368 ABIs. When enabled all processes are <<
369 and a fast user exception handler fo <<
370 used to turn on PS.WOE bit on the fi <<
371 the userspace. <<
372 <<
373 This option should be enabled for th <<
374 both call0 and windowed ABIs in user <<
375 <<
376 Note that Xtensa ISA does not guaran <<
377 raise an illegal instruction excepti <<
378 PS.WOE is disabled, check whether th <<
379 <<
380 endchoice <<
381 <<
382 endmenu <<
383 <<
384 config XTENSA_CALIBRATE_CCOUNT <<
385 def_bool n <<
386 help <<
387 On some platforms (XT2000, for examp <<
388 vary. The frequency can be determin <<
389 against a well known, fixed frequenc <<
390 <<
391 config SERIAL_CONSOLE <<
392 def_bool n <<
393 <<
394 config PLATFORM_HAVE_XIP <<
395 def_bool n <<
396 <<
397 menu "Platform options" <<
398 <<
399 choice <<
400 prompt "Xtensa System Type" <<
401 default XTENSA_PLATFORM_ISS <<
402 <<
403 config XTENSA_PLATFORM_ISS <<
404 bool "ISS" <<
405 select XTENSA_CALIBRATE_CCOUNT <<
406 select SERIAL_CONSOLE <<
407 help <<
408 ISS is an acronym for Tensilica's In <<
409 <<
410 config XTENSA_PLATFORM_XT2000 <<
411 bool "XT2000" <<
412 help <<
413 XT2000 is the name of Tensilica's fe <<
414 This hardware is capable of running <<
415 <<
416 config XTENSA_PLATFORM_XTFPGA <<
417 bool "XTFPGA" <<
418 select ETHOC if ETHERNET <<
419 select PLATFORM_WANT_DEFAULT_MEM if !M <<
420 select SERIAL_CONSOLE <<
421 select XTENSA_CALIBRATE_CCOUNT <<
422 select PLATFORM_HAVE_XIP <<
423 help <<
424 XTFPGA is the name of Tensilica boar <<
425 This hardware is capable of running <<
426 66
427 endchoice !! 67 config NO_IOPORT_MAP
>> 68 def_bool y
428 69
429 config PLATFORM_NR_IRQS !! 70 config HZ
430 int 71 int
431 default 3 if XTENSA_PLATFORM_XT2000 !! 72 default 1000 if CLEOPATRA
432 default 0 !! 73 default 100
433 <<
434 config XTENSA_CPU_CLOCK <<
435 int "CPU clock rate [MHz]" <<
436 depends on !XTENSA_CALIBRATE_CCOUNT <<
437 default 16 <<
438 <<
439 config GENERIC_CALIBRATE_DELAY <<
440 bool "Auto calibration of the BogoMIPS <<
441 help <<
442 The BogoMIPS value can easily be der <<
443 <<
444 config CMDLINE_BOOL <<
445 bool "Default bootloader kernel argume <<
446 <<
447 config CMDLINE <<
448 string "Initial kernel command string" <<
449 depends on CMDLINE_BOOL <<
450 default "console=ttyS0,38400 root=/dev <<
451 help <<
452 On some architectures (EBSA110 and C <<
453 for the boot loader to pass argument <<
454 architectures, you should supply som <<
455 time by entering them here. As a min <<
456 memory size and the root device (e.g <<
457 <<
458 config USE_OF <<
459 bool "Flattened Device Tree support" <<
460 select OF <<
461 select OF_EARLY_FLATTREE <<
462 help <<
463 Include support for flattened device <<
464 74
465 config BUILTIN_DTB_SOURCE !! 75 config PGTABLE_LEVELS
466 string "DTB to build into the kernel i !! 76 default 2 if SUN3 || COLDFIRE
467 depends on OF !! 77 default 3
468 78
469 config PARSE_BOOTPARAM !! 79 config MMU
470 bool "Parse bootparam block" !! 80 bool "MMU-based Paged Memory Management Support"
471 default y 81 default y
472 help 82 help
473 Parse parameters passed to the kerne !! 83 Select if you want MMU-based virtualised addressing space
474 be disabled if the kernel is known t !! 84 support by paged memory management. If unsure, say 'Y'.
475 85
476 If unsure, say Y. !! 86 config MMU_MOTOROLA
477 !! 87 bool
478 choice !! 88 select HAVE_PAGE_SIZE_4KB
479 prompt "Semihosting interface" <<
480 default XTENSA_SIMCALL_ISS <<
481 depends on XTENSA_PLATFORM_ISS <<
482 help <<
483 Choose semihosting interface that wi <<
484 block device and networking. <<
485 <<
486 config XTENSA_SIMCALL_ISS <<
487 bool "simcall" <<
488 help <<
489 Use simcall instruction. simcall is <<
490 it does nothing on hardware. <<
491 <<
492 config XTENSA_SIMCALL_GDBIO <<
493 bool "GDBIO" <<
494 help <<
495 Use break instruction. It is availab <<
496 is attached to it via JTAG. <<
497 <<
498 endchoice <<
499 <<
500 config BLK_DEV_SIMDISK <<
501 tristate "Host file-based simulated bl <<
502 default n <<
503 depends on XTENSA_PLATFORM_ISS && BLOC <<
504 help <<
505 Create block devices that map to fil <<
506 Device binding to host file may be c <<
507 interface provided the device is not <<
508 <<
509 config BLK_DEV_SIMDISK_COUNT <<
510 int "Number of host file-based simulat <<
511 range 1 10 <<
512 depends on BLK_DEV_SIMDISK <<
513 default 2 <<
514 help <<
515 This is the default minimal number o <<
516 Kernel/module parameter 'simdisk_cou <<
517 value at runtime. More file names (b <<
518 specified as parameters, simdisk_cou <<
519 <<
520 config SIMDISK0_FILENAME <<
521 string "Host filename for the first si <<
522 depends on BLK_DEV_SIMDISK = y <<
523 default "" <<
524 help <<
525 Attach a first simdisk to a host fil <<
526 contains a root file system. <<
527 89
528 config SIMDISK1_FILENAME !! 90 config MMU_COLDFIRE
529 string "Host filename for the second s !! 91 select HAVE_PAGE_SIZE_8KB
530 depends on BLK_DEV_SIMDISK = y && BLK_ !! 92 bool
531 default "" <<
532 help <<
533 Another simulated disk in a host fil <<
534 storage. <<
535 93
536 config XTFPGA_LCD !! 94 config MMU_SUN3
537 bool "Enable XTFPGA LCD driver" !! 95 bool
538 depends on XTENSA_PLATFORM_XTFPGA !! 96 select HAVE_PAGE_SIZE_8KB
539 default n !! 97 depends on MMU && !MMU_MOTOROLA && !MMU_COLDFIRE
540 help <<
541 There's a 2x16 LCD on most of XTFPGA <<
542 progress messages there during bootu <<
543 during board bringup. <<
544 <<
545 If unsure, say N. <<
546 <<
547 config XTFPGA_LCD_BASE_ADDR <<
548 hex "XTFPGA LCD base address" <<
549 depends on XTFPGA_LCD <<
550 default "0x0d0c0000" <<
551 help <<
552 Base address of the LCD controller i <<
553 Different boards from XTFPGA family <<
554 addresses. Please consult prototypin <<
555 the correct address. Wrong address h <<
556 <<
557 config XTFPGA_LCD_8BIT_ACCESS <<
558 bool "Use 8-bit access to XTFPGA LCD" <<
559 depends on XTFPGA_LCD <<
560 default n <<
561 help <<
562 LCD may be connected with 4- or 8-bi <<
563 only be used with 8-bit interface. P <<
564 guide for your board for the correct <<
565 <<
566 comment "Kernel memory layout" <<
567 <<
568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX <<
569 bool "Initialize Xtensa MMU inside the <<
570 depends on !XTENSA_VARIANT_FSF && !XTE <<
571 default y if XTENSA_VARIANT_DC233C || <<
572 help <<
573 Earlier version initialized the MMU <<
574 before jumping to _startup in head.S <<
575 it was possible to place a software <<
576 then enter your normal kernel breakp <<
577 to the kernel mappings (0XC0000000). <<
578 <<
579 This unfortunately won't work for U- <<
580 work for using KEXEC to have a hot k <<
581 KDUMP. <<
582 <<
583 So now the MMU is initialized in hea <<
584 use hardware breakpoints (gdb 'hbrea <<
585 xt-gdb can't place a Software Breakp <<
586 to mapping the MMU and after mapping <<
587 was mapped gdb wouldn't remove the b <<
588 PC wouldn't match. Since Hardware Br <<
589 Linux configurations it seems reason <<
590 and leave this older mechanism for u <<
591 not to follow Tensilica's recommenda <<
592 <<
593 Selecting this will cause U-Boot to <<
594 address at 0x00003000 instead of the <<
595 <<
596 If in doubt, say Y. <<
597 <<
598 config XIP_KERNEL <<
599 bool "Kernel Execute-In-Place from ROM <<
600 depends on PLATFORM_HAVE_XIP <<
601 help <<
602 Execute-In-Place allows the kernel t <<
603 directly addressable by the CPU, suc <<
604 space since the text section of the <<
605 to RAM. Read-write sections, such as <<
606 are still copied to RAM. The XIP ker <<
607 it has to run directly from flash, s <<
608 store it. The flash address used to <<
609 and for storing it, is configuration <<
610 say Y here, you must know the proper <<
611 store the kernel image depending on <<
612 <<
613 Also note that the make target becom <<
614 "make Image" or "make uImage". The f <<
615 ROM memory will be arch/xtensa/boot/ <<
616 <<
617 If unsure, say N. <<
618 <<
619 config MEMMAP_CACHEATTR <<
620 hex "Cache attributes for the memory a <<
621 depends on !MMU <<
622 default 0x22222222 <<
623 help <<
624 These cache attributes are set up fo <<
625 specifies cache attributes for the c <<
626 region: bits 0..3 -- for addresses 0 <<
627 bits 4..7 -- for addresses 0x2000000 <<
628 <<
629 Cache attribute values are specific <<
630 For region protection MMUs: <<
631 1: WT cached, <<
632 2: cache bypass, <<
633 4: WB cached, <<
634 f: illegal. <<
635 For full MMU: <<
636 bit 0: executable, <<
637 bit 1: writable, <<
638 bits 2..3: <<
639 0: cache bypass, <<
640 1: WB cache, <<
641 2: WT cache, <<
642 3: special (c and e are illegal, <<
643 For MPU: <<
644 0: illegal, <<
645 1: WB cache, <<
646 2: WB, no-write-allocate cache, <<
647 3: WT cache, <<
648 4: cache bypass. <<
649 <<
650 config KSEG_PADDR <<
651 hex "Physical address of the KSEG mapp <<
652 depends on INITIALIZE_XTENSA_MMU_INSID <<
653 default 0x00000000 <<
654 help <<
655 This is the physical address where K <<
656 the chosen KSEG layout help for the <<
657 Unpacked kernel image (including vec <<
658 within KSEG. <<
659 Physical memory below this address i <<
660 <<
661 If unsure, leave the default value h <<
662 <<
663 config KERNEL_VIRTUAL_ADDRESS <<
664 hex "Kernel virtual address" <<
665 depends on MMU && XIP_KERNEL <<
666 default 0xd0003000 <<
667 help <<
668 This is the virtual address where th <<
669 XIP kernel may be mapped into KSEG o <<
670 provided here must match kernel load <<
671 KERNEL_LOAD_ADDRESS. <<
672 <<
673 config KERNEL_LOAD_ADDRESS <<
674 hex "Kernel load address" <<
675 default 0x60003000 if !MMU <<
676 default 0x00003000 if MMU && INITIALIZ <<
677 default 0xd0003000 if MMU && !INITIALI <<
678 help <<
679 This is the address where the kernel <<
680 It is virtual address for MMUv2 conf <<
681 for all other configurations. <<
682 <<
683 If unsure, leave the default value h <<
684 <<
685 choice <<
686 prompt "Relocatable vectors location" <<
687 default XTENSA_VECTORS_IN_TEXT <<
688 help <<
689 Choose whether relocatable vectors a <<
690 or placed separately at runtime. Thi <<
691 configurations without VECBASE regis <<
692 placed at their hardware-defined loc <<
693 <<
694 config XTENSA_VECTORS_IN_TEXT <<
695 bool "Merge relocatable vectors into k <<
696 depends on !MTD_XIP <<
697 help <<
698 This option puts relocatable vectors <<
699 with proper alignment. <<
700 This is a safe choice for most confi <<
701 98
702 config XTENSA_VECTORS_SEPARATE !! 99 config ARCH_SUPPORTS_KEXEC
703 bool "Put relocatable vectors at fixed !! 100 def_bool M68KCLASSIC && MMU
704 help <<
705 This option puts relocatable vectors <<
706 Vectors are merged with the .init da <<
707 are copied into their designated loc <<
708 Use it to put vectors into IRAM or o <<
709 XIP-aware MTD support. <<
710 <<
711 endchoice <<
712 <<
713 config VECTORS_ADDR <<
714 hex "Kernel vectors virtual address" <<
715 default 0x00000000 <<
716 depends on XTENSA_VECTORS_SEPARATE <<
717 help <<
718 This is the virtual address of the ( <<
719 It must be within KSEG if MMU is use <<
720 101
721 config XIP_DATA_ADDR !! 102 config BOOTINFO_PROC
722 hex "XIP kernel data virtual address" !! 103 bool "Export bootinfo in procfs"
723 depends on XIP_KERNEL !! 104 depends on KEXEC && M68KCLASSIC
724 default 0x00000000 <<
725 help 105 help
726 This is the virtual address where XI !! 106 Say Y to export the bootinfo used to boot the kernel in a
727 It must be within KSEG if MMU is use !! 107 "bootinfo" file in procfs. This is useful with kexec.
728 108
729 config PLATFORM_WANT_DEFAULT_MEM !! 109 menu "Platform setup"
730 def_bool n <<
731 110
732 config DEFAULT_MEM_START !! 111 source "arch/m68k/Kconfig.cpu"
733 hex <<
734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !M <<
735 default 0x60000000 if PLATFORM_WANT_DE <<
736 default 0x00000000 <<
737 help <<
738 This is the base address used for bo <<
739 in noMMU configurations. <<
740 112
741 If unsure, leave the default value h !! 113 source "arch/m68k/Kconfig.machine"
742 114
743 choice !! 115 source "arch/m68k/Kconfig.bus"
744 prompt "KSEG layout" <<
745 depends on MMU <<
746 default XTENSA_KSEG_MMU_V2 <<
747 116
748 config XTENSA_KSEG_MMU_V2 !! 117 endmenu
749 bool "MMUv2: 128MB cached + 128MB unca <<
750 help <<
751 MMUv2 compatible kernel memory map: <<
752 at KSEG_PADDR to 0xd0000000 with cac <<
753 without cache. <<
754 KSEG_PADDR must be aligned to 128MB. <<
755 <<
756 config XTENSA_KSEG_256M <<
757 bool "256MB cached + 256MB uncached" <<
758 depends on INITIALIZE_XTENSA_MMU_INSID <<
759 help <<
760 TLB way 6 maps 256MB starting at KSE <<
761 with cache and to 0xc0000000 without <<
762 KSEG_PADDR must be aligned to 256MB. <<
763 <<
764 config XTENSA_KSEG_512M <<
765 bool "512MB cached + 512MB uncached" <<
766 depends on INITIALIZE_XTENSA_MMU_INSID <<
767 help <<
768 TLB way 6 maps 512MB starting at KSE <<
769 with cache and to 0xc0000000 without <<
770 KSEG_PADDR must be aligned to 256MB. <<
771 <<
772 endchoice <<
773 <<
774 config HIGHMEM <<
775 bool "High Memory Support" <<
776 depends on MMU <<
777 select KMAP_LOCAL <<
778 help <<
779 Linux can use the full amount of RAM <<
780 default. However, the default MMUv2 <<
781 lowermost 128 MB of memory linearly <<
782 at 0xd0000000 (cached) and 0xd800000 <<
783 When there are more than 128 MB memo <<
784 all of it can be "permanently mapped <<
785 The physical memory that's not perma <<
786 "high memory". <<
787 <<
788 If you are compiling a kernel which <<
789 machine with more than 128 MB total <<
790 N here. <<
791 <<
792 If unsure, say Y. <<
793 <<
794 config ARCH_FORCE_MAX_ORDER <<
795 int "Order of maximal physically conti <<
796 default "10" <<
797 help <<
798 The kernel page allocator limits the <<
799 contiguous allocations. The limit is <<
800 defines the maximal power of two of <<
801 allocated as a single contiguous blo <<
802 overriding the default setting when <<
803 large blocks of physically contiguou <<
804 118
805 Don't change if unsure. !! 119 menu "Kernel Features"
806 120
807 endmenu 121 endmenu
808 122
>> 123 if !MMU
809 menu "Power management options" 124 menu "Power management options"
810 125
811 config ARCH_HIBERNATION_POSSIBLE !! 126 config PM
812 def_bool y !! 127 bool "Power Management support"
813 !! 128 help
814 source "kernel/power/Kconfig" !! 129 Support processor power management modes
815 130
816 endmenu 131 endmenu
>> 132 endif
>> 133
>> 134 source "arch/m68k/Kconfig.devices"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.