Linux/arch/xtensa/kernel/head.S

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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1 /* 1 /* 2 * arch/xtensa/kernel/head.S << 3 * << 4 * Xtensa Processor startup code. << 5 * << 6 * This file is subject to the terms and condi 2 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the mai 3 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 4 * for more details. 9 * 5 * 10 * Copyright (C) 2001 - 2008 Tensilica Inc. !! 6 * Copyright (C) 1994, 1995 Waldorf Electronics 11 * !! 7 * Written by Ralf Baechle and Andreas Busse 12 * Chris Zankel <chris@zankel.net> !! 8 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle 13 * Marc Gauthier <marc@tensilica.com, marc@alum !! 9 * Copyright (C) 1996 Paul M. Antoine 14 * Joe Taylor <joe@tensilica.com, joetylr@yahoo !! 10 * Modified for DECStation and hence R3000 support by Paul M. Antoine 15 * Kevin Chea !! 11 * Further modifications by David S. Miller and Harald Koerfgen >> 12 * Copyright (C) 1999 Silicon Graphics, Inc. >> 13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com >> 14 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 16 */ 15 */ 17 << 18 #include <asm/asmmacro.h> << 19 #include <asm/processor.h> << 20 #include <asm/page.h> << 21 #include <asm/cacheasm.h> << 22 #include <asm/initialize_mmu.h> << 23 #include <asm/mxregs.h> << 24 << 25 #include <linux/init.h> 16 #include <linux/init.h> 26 #include <linux/linkage.h> !! 17 #include <linux/threads.h> 27 << 28 /* << 29 * This module contains the entry code for ker << 30 * minimal setup needed to call the generic C << 31 * << 32 * Prerequisites: << 33 * << 34 * - The kernel image has been loaded to the a << 35 * compiled to. << 36 * - a2 contains either 0 or a pointer to a li << 37 * (see setup.c for more details) << 38 * << 39 */ << 40 << 41 /* << 42 * _start << 43 * << 44 * The bootloader passes a pointer to a list << 45 */ << 46 18 47 /* The first bytes of the kernel image !! 19 #include <asm/addrspace.h> 48 * manually allocate and define the li !! 20 #include <asm/asm.h> 49 * instruction. !! 21 #include <asm/asmmacro.h> 50 */ !! 22 #include <asm/irqflags.h> 51 !! 23 #include <asm/regdef.h> 52 __HEAD !! 24 #include <asm/mipsregs.h> 53 .begin no-absolute-literals !! 25 #include <asm/stackframe.h> 54 26 55 ENTRY(_start) !! 27 #include <kernel-entry-init.h> 56 28 57 /* Preserve the pointer to the boot pa << 58 wsr a2, excsave1 << 59 _j _SetupOCD << 60 << 61 .align 4 << 62 .literal_position << 63 _SetupOCD: << 64 /* 29 /* 65 * Initialize WB, WS, and clear PS.EXC !! 30 * For the moment disable interrupts, mark the kernel mode and 66 * Set Interrupt Level just below XCHA !! 31 * set ST0_KX so that the CPU does not spit fire when using 67 * xt-gdb to single step via DEBUG exc !! 32 * 64-bit addresses. A full initialization of the CPU's status 68 * by ocd. !! 33 * register is done later in per_cpu_trap_init(). 69 */ !! 34 */ 70 #if XCHAL_HAVE_WINDOWED !! 35 .macro setup_c0_status set clr 71 movi a1, 1 !! 36 .set push 72 movi a0, 0 !! 37 mfc0 t0, CP0_STATUS 73 wsr a1, windowstart !! 38 or t0, ST0_KERNEL_CUMASK|\set|0x1f|\clr 74 wsr a0, windowbase !! 39 xor t0, 0x1f|\clr 75 rsync !! 40 mtc0 t0, CP0_STATUS 76 #endif !! 41 .set noreorder 77 !! 42 sll zero,3 # ehb 78 movi a1, LOCKLEVEL !! 43 .set pop 79 wsr a1, ps !! 44 .endm 80 rsync !! 45 81 !! 46 .macro setup_c0_status_pri 82 .global _SetupMMU !! 47 #ifdef CONFIG_64BIT 83 _SetupMMU: !! 48 setup_c0_status ST0_KX 0 84 Offset = _SetupMMU - _start !! 49 #else 85 !! 50 setup_c0_status 0 0 86 #ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VML << 87 initialize_mmu << 88 #if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU << 89 rsr a2, excsave1 << 90 movi a3, XCHAL_KSEG_PADDR << 91 bltu a2, a3, 1f << 92 sub a2, a2, a3 << 93 movi a3, XCHAL_KSEG_SIZE << 94 bgeu a2, a3, 1f << 95 movi a3, XCHAL_KSEG_CACHED_VADDR << 96 add a2, a2, a3 << 97 wsr a2, excsave1 << 98 1: << 99 #endif << 100 #endif << 101 << 102 movi a0, _startup << 103 jx a0 << 104 << 105 ENDPROC(_start) << 106 .end no-absolute-literals << 107 << 108 __REF << 109 .literal_position << 110 << 111 ENTRY(_startup) << 112 << 113 /* Set a0 to 0 for the remaining initi << 114 << 115 movi a0, 0 << 116 << 117 #if XCHAL_HAVE_VECBASE << 118 movi a2, VECBASE_VADDR << 119 wsr a2, vecbase << 120 #endif << 121 << 122 /* Clear debugging registers. */ << 123 << 124 #if XCHAL_HAVE_DEBUG << 125 #if XCHAL_NUM_IBREAK > 0 << 126 wsr a0, ibreakenable << 127 #endif << 128 wsr a0, icount << 129 movi a1, 15 << 130 wsr a0, icountlevel << 131 << 132 .set _index, 0 << 133 .rept XCHAL_NUM_DBREAK << 134 wsr a0, SREG_DBREAKC + _index << 135 .set _index, _index + 1 << 136 .endr << 137 #endif << 138 << 139 /* Clear CCOUNT (not really necessary, << 140 << 141 wsr a0, ccount # not really n << 142 << 143 /* Disable zero-loops. */ << 144 << 145 #if XCHAL_HAVE_LOOPS << 146 wsr a0, lcount << 147 #endif << 148 << 149 /* Disable all timers. */ << 150 << 151 .set _index, 0 << 152 .rept XCHAL_NUM_TIMERS << 153 wsr a0, SREG_CCOMPARE + _index << 154 .set _index, _index + 1 << 155 .endr << 156 << 157 /* Interrupt initialization. */ << 158 << 159 movi a2, XCHAL_INTTYPE_MASK_SOFTWAR << 160 wsr a0, intenable << 161 wsr a2, intclear << 162 << 163 /* Disable coprocessors. */ << 164 << 165 #if XCHAL_HAVE_CP << 166 wsr a0, cpenable << 167 #endif << 168 << 169 /* Initialize the caches. << 170 * a2, a3 are just working registers << 171 */ << 172 << 173 #if XCHAL_DCACHE_LINE_LOCKABLE << 174 ___unlock_dcache_all a2 a3 << 175 #endif << 176 << 177 #if XCHAL_ICACHE_LINE_LOCKABLE << 178 ___unlock_icache_all a2 a3 << 179 #endif 51 #endif >> 52 .endm 180 53 181 ___invalidate_dcache_all a2 a3 !! 54 .macro setup_c0_status_sec 182 ___invalidate_icache_all a2 a3 !! 55 #ifdef CONFIG_64BIT 183 !! 56 setup_c0_status ST0_KX ST0_BEV 184 isync !! 57 #else 185 !! 58 setup_c0_status 0 ST0_BEV 186 initialize_cacheattr << 187 << 188 #ifdef CONFIG_HAVE_SMP << 189 movi a2, CCON # MX External << 190 movi a3, 1 << 191 wer a3, a2 << 192 #endif 59 #endif >> 60 .endm 193 61 194 /* Setup stack and enable window excep !! 62 #ifndef CONFIG_NO_EXCEPT_FILL 195 << 196 movi a1, start_info << 197 l32i a1, a1, 0 << 198 << 199 /* Disable interrupts. */ << 200 /* Enable window exceptions if kernel << 201 movi a2, KERNEL_PS_WOE_MASK | LOCKL << 202 wsr a2, ps << 203 rsync << 204 << 205 #ifdef CONFIG_SMP << 206 /* 63 /* 207 * Notice that we assume with SMP that !! 64 * Reserved space for exception handlers. 208 * supported by the cores. !! 65 * Necessary for machines which link their kernels at KSEG0. 209 */ << 210 rsr a2, prid << 211 bnez a2, .Lboot_secondary << 212 << 213 #endif /* CONFIG_SMP */ << 214 << 215 /* Unpack data sections << 216 * << 217 * The linker script used to build the << 218 * creates a table located at __boot_r << 219 * that contains the information what << 220 * << 221 * Uses a2-a7. << 222 */ 66 */ 223 !! 67 .fill 0x400 224 movi a2, __boot_reloc_table_start << 225 movi a3, __boot_reloc_table_end << 226 << 227 1: beq a2, a3, 3f # no more entr << 228 l32i a4, a2, 0 # start destin << 229 l32i a5, a2, 4 # end destinat << 230 l32i a6, a2, 8 # start source << 231 addi a2, a2, 12 # next entry << 232 beq a4, a5, 1b # skip, empty << 233 beq a4, a6, 1b # skip, source << 234 << 235 2: l32i a7, a6, 0 # load word << 236 addi a6, a6, 4 << 237 s32i a7, a4, 0 # store word << 238 addi a4, a4, 4 << 239 bltu a4, a5, 2b << 240 j 1b << 241 << 242 3: << 243 /* All code and initialized data segme << 244 * Now clear the BSS segment. << 245 */ << 246 << 247 movi a2, __bss_start # start of BSS << 248 movi a3, __bss_stop # end of BSS << 249 << 250 __loopt a2, a3, a4, 2 << 251 s32i a0, a2, 0 << 252 __endla a2, a3, 4 << 253 << 254 #if XCHAL_DCACHE_IS_WRITEBACK << 255 << 256 /* After unpacking, flush the writebac << 257 * instructions/data are available. << 258 */ << 259 << 260 ___flush_dcache_all a2 a3 << 261 #endif 68 #endif 262 memw << 263 isync << 264 ___invalidate_icache_all a2 a3 << 265 isync << 266 << 267 #ifdef CONFIG_XIP_KERNEL << 268 /* Setup bootstrap CPU stack in XIP ke << 269 69 270 movi a1, start_info !! 70 EXPORT(_stext) 271 l32i a1, a1, 0 << 272 #endif << 273 71 274 movi abi_arg0, 0 !! 72 #ifdef CONFIG_BOOT_RAW 275 xsr abi_arg0, excsave1 !! 73 /* 276 !! 74 * Give us a fighting chance of running if execution beings at the 277 /* init_arch kick-starts the linux ker !! 75 * kernel load address. This is needed because this platform does 278 !! 76 * not have a ELF loader yet. 279 abi_call init_arch !! 77 */ 280 abi_call start_kernel !! 78 FEXPORT(__kernel_entry) 281 !! 79 j kernel_entry 282 should_never_return: !! 80 #endif /* CONFIG_BOOT_RAW */ 283 j should_never_return << 284 << 285 #ifdef CONFIG_SMP << 286 .Lboot_secondary: << 287 << 288 movi a2, cpu_start_ccount << 289 1: << 290 memw << 291 l32i a3, a2, 0 << 292 beqi a3, 0, 1b << 293 movi a3, 0 << 294 s32i a3, a2, 0 << 295 1: << 296 memw << 297 l32i a3, a2, 0 << 298 beqi a3, 0, 1b << 299 wsr a3, ccount << 300 movi a3, 0 << 301 s32i a3, a2, 0 << 302 memw << 303 << 304 movi abi_arg0, 0 << 305 wsr abi_arg0, excsave1 << 306 81 307 abi_call secondary_start_kernel !! 82 __REF 308 j should_never_return << 309 83 310 #endif /* CONFIG_SMP */ !! 84 NESTED(kernel_entry, 16, sp) # kernel entry point 311 85 312 ENDPROC(_startup) !! 86 kernel_entry_setup # cpu specific setup 313 87 314 #ifdef CONFIG_HOTPLUG_CPU !! 88 setup_c0_status_pri 315 89 316 ENTRY(cpu_restart) !! 90 /* We might not get launched at the address the kernel is linked to, >> 91 so we jump there. */ >> 92 PTR_LA t0, 0f >> 93 jr t0 >> 94 0: 317 95 318 #if XCHAL_DCACHE_IS_WRITEBACK !! 96 PTR_LA t0, __bss_start # clear .bss 319 ___flush_invalidate_dcache_all a2 a3 !! 97 LONG_S zero, (t0) 320 #else !! 98 PTR_LA t1, __bss_stop - LONGSIZE 321 ___invalidate_dcache_all a2 a3 << 322 #endif << 323 memw << 324 movi a2, CCON # MX External << 325 movi a3, 0 << 326 wer a3, a2 << 327 extw << 328 << 329 rsr a0, prid << 330 neg a2, a0 << 331 movi a3, cpu_start_id << 332 memw << 333 s32i a2, a3, 0 << 334 #if XCHAL_DCACHE_IS_WRITEBACK << 335 dhwbi a3, 0 << 336 #endif << 337 1: 99 1: 338 memw !! 100 PTR_ADDIU t0, LONGSIZE 339 l32i a2, a3, 0 !! 101 LONG_S zero, (t0) 340 dhi a3, 0 !! 102 bne t0, t1, 1b 341 bne a2, a0, 1b !! 103 >> 104 LONG_S a0, fw_arg0 # firmware arguments >> 105 LONG_S a1, fw_arg1 >> 106 LONG_S a2, fw_arg2 >> 107 LONG_S a3, fw_arg3 >> 108 >> 109 MTC0 zero, CP0_CONTEXT # clear context register >> 110 #ifdef CONFIG_64BIT >> 111 MTC0 zero, CP0_XCONTEXT >> 112 #endif >> 113 PTR_LA $28, init_thread_union >> 114 /* Set the SP after an empty pt_regs. */ >> 115 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE >> 116 PTR_ADDU sp, $28 >> 117 back_to_back_c0_hazard >> 118 set_saved_sp sp, t0, t1 >> 119 PTR_SUBU sp, 4 * SZREG # init stack pointer >> 120 >> 121 #ifdef CONFIG_RELOCATABLE >> 122 /* Copy kernel and apply the relocations */ >> 123 jal relocate_kernel >> 124 >> 125 /* Repoint the sp into the new kernel image */ >> 126 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE >> 127 PTR_ADDU sp, $28 >> 128 set_saved_sp sp, t0, t1 >> 129 PTR_SUBU sp, 4 * SZREG # init stack pointer 342 130 343 /* 131 /* 344 * Initialize WB, WS, and clear PS.EXC !! 132 * relocate_kernel returns the entry point either 345 * Set Interrupt Level just below XCHA !! 133 * in the relocated kernel or the original if for 346 * xt-gdb to single step via DEBUG exc !! 134 * some reason relocation failed - jump there now 347 * by ocd. !! 135 * with instruction hazard barrier because of the 348 */ !! 136 * newly sync'd icache. 349 movi a1, 1 !! 137 */ 350 movi a0, 0 !! 138 jr.hb v0 351 wsr a1, windowstart !! 139 #else /* !CONFIG_RELOCATABLE */ 352 wsr a0, windowbase !! 140 j start_kernel 353 rsync !! 141 #endif /* !CONFIG_RELOCATABLE */ 354 !! 142 END(kernel_entry) 355 movi a1, LOCKLEVEL << 356 wsr a1, ps << 357 rsync << 358 << 359 j _startup << 360 << 361 ENDPROC(cpu_restart) << 362 << 363 #endif /* CONFIG_HOTPLUG_CPU */ << 364 << 365 /* << 366 * DATA section << 367 */ << 368 << 369 __REFDATA << 370 .align 4 << 371 ENTRY(start_info) << 372 .long init_thread_union + KERNEL_STA << 373 143 >> 144 #ifdef CONFIG_SMP 374 /* 145 /* 375 * BSS section !! 146 * SMP slave cpus entry point. Board specific code for bootstrap calls this >> 147 * function after setting up the stack and gp registers. 376 */ 148 */ 377 !! 149 NESTED(smp_bootstrap, 16, sp) 378 __PAGE_ALIGNED_BSS !! 150 smp_slave_setup 379 #ifdef CONFIG_MMU !! 151 setup_c0_status_sec 380 ENTRY(swapper_pg_dir) !! 152 j start_secondary 381 .fill PAGE_SIZE, 1, 0 !! 153 END(smp_bootstrap) 382 END(swapper_pg_dir) !! 154 #endif /* CONFIG_SMP */ 383 #endif << 384 ENTRY(empty_zero_page) << 385 .fill PAGE_SIZE, 1, 0 << 386 END(empty_zero_page) <<

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TOMOYO Linux Cross Reference
Linux/arch/xtensa/kernel/head.S

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Differences between /arch/xtensa/kernel/head.S (Version linux-6.12-rc7) and /arch/mips/kernel/head.S (Version linux-5.18.19)

TOMOYO Linux Cross Reference Linux/arch/xtensa/kernel/head.S

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Differences between /arch/xtensa/kernel/head.S (Version linux-6.12-rc7) and /arch/mips/kernel/head.S (Version linux-5.18.19)

TOMOYO Linux Cross Reference
Linux/arch/xtensa/kernel/head.S