1 /* !! 1 /* SPDX-License-Identifier: GPL-2.0 */
2 * arch/xtensa/kernel/vmlinux.lds.S !! 2 #include <asm/asm-offsets.h>
3 * <<
4 * Xtensa linker script <<
5 * <<
6 * This file is subject to the terms and condi <<
7 * License. See the file "COPYING" in the mai <<
8 * for more details. <<
9 * <<
10 * Copyright (C) 2001 - 2008 Tensilica Inc. <<
11 * <<
12 * Chris Zankel <chris@zankel.net> <<
13 * Marc Gauthier <marc@tensilica.com, marc@alum <<
14 * Joe Taylor <joe@tensilica.com, joetylr@yahoo <<
15 */ <<
16 <<
17 #define RO_EXCEPTION_TABLE_ALIGN 16 <<
18 <<
19 #include <asm-generic/vmlinux.lds.h> <<
20 #include <asm/page.h> <<
21 #include <asm/thread_info.h> 3 #include <asm/thread_info.h>
22 4
23 #include <asm/core.h> !! 5 #define PAGE_SIZE _PAGE_SIZE
24 #include <asm/vectors.h> <<
25 <<
26 OUTPUT_ARCH(xtensa) <<
27 ENTRY(_start) <<
28 <<
29 #ifdef __XTENSA_EB__ <<
30 jiffies = jiffies_64 + 4; <<
31 #else <<
32 jiffies = jiffies_64; <<
33 #endif <<
34 <<
35 /* Note: In the following macros, it would be <<
36 vector name and section kind and construct <<
37 CPP concatenation, but that does not work r <<
38 string with "." produces an invalid token. <<
39 warning because it thinks this is an assemb <<
40 them as multiple tokens and there may or ma <<
41 between them. */ <<
42 <<
43 /* Macro for a relocation entry */ <<
44 <<
45 #define RELOCATE_ENTRY(sym, section) <<
46 LONG(sym ## _start); <<
47 LONG(sym ## _end); <<
48 LONG(LOADADDR(section)) <<
49 <<
50 #if !defined(CONFIG_VECTORS_ADDR) && XCHAL_HAV <<
51 #define MERGED_VECTORS 1 <<
52 #else <<
53 #define MERGED_VECTORS 0 <<
54 #endif <<
55 6
56 /* 7 /*
57 * Macro to define a section for a vector. Whe !! 8 * Put .bss..swapper_pg_dir as the first thing in .bss. This will
58 * code for every vector is located with other !! 9 * ensure that it has .bss alignment (64K).
59 * time head.S copies code for every vector to <<
60 * to description recorded in the correspondin <<
61 */ 10 */
>> 11 #define BSS_FIRST_SECTIONS *(.bss..swapper_pg_dir)
62 12
63 #define SECTION_VECTOR4(sym, section, addr, pr !! 13 /* Cavium Octeon should not have a separate PT_NOTE Program Header. */
64 section addr : AT(((LOADADDR(prevsec) + SIZE !! 14 #ifndef CONFIG_CAVIUM_OCTEON_SOC
65 { !! 15 #define EMITS_PT_NOTE
66 . = ALIGN(4); <<
67 sym ## _start = ABSOLUTE(.); <<
68 *(section) <<
69 sym ## _end = ABSOLUTE(.); <<
70 } <<
71 <<
72 #define SECTION_VECTOR2(section, addr) <<
73 . = addr; <<
74 *(section) <<
75 <<
76 /* <<
77 * Mapping of input sections to output sectio <<
78 */ <<
79 <<
80 SECTIONS <<
81 { <<
82 . = KERNELOFFSET; <<
83 /* .text section */ <<
84 <<
85 _text = .; <<
86 _stext = .; <<
87 <<
88 .text : <<
89 { <<
90 /* The HEAD_TEXT section must be the first <<
91 HEAD_TEXT <<
92 <<
93 #if MERGED_VECTORS <<
94 . = ALIGN(PAGE_SIZE); <<
95 _vecbase = .; <<
96 <<
97 #ifdef SUPPORT_WINDOWED <<
98 SECTION_VECTOR2 (.WindowVectors.text, WIND <<
99 #endif <<
100 #if XCHAL_EXCM_LEVEL >= 2 <<
101 SECTION_VECTOR2 (.Level2InterruptVector.te <<
102 #endif <<
103 #if XCHAL_EXCM_LEVEL >= 3 <<
104 SECTION_VECTOR2 (.Level3InterruptVector.te <<
105 #endif <<
106 #if XCHAL_EXCM_LEVEL >= 4 <<
107 SECTION_VECTOR2 (.Level4InterruptVector.te <<
108 #endif <<
109 #if XCHAL_EXCM_LEVEL >= 5 <<
110 SECTION_VECTOR2 (.Level5InterruptVector.te <<
111 #endif <<
112 #if XCHAL_EXCM_LEVEL >= 6 <<
113 SECTION_VECTOR2 (.Level6InterruptVector.te <<
114 #endif <<
115 SECTION_VECTOR2 (.DebugInterruptVector.tex <<
116 SECTION_VECTOR2 (.KernelExceptionVector.te <<
117 SECTION_VECTOR2 (.UserExceptionVector.text <<
118 SECTION_VECTOR2 (.DoubleExceptionVector.te <<
119 <<
120 *(.exception.text) <<
121 *(.xiptext) <<
122 #endif 16 #endif
123 17
124 IRQENTRY_TEXT !! 18 #define RUNTIME_DISCARD_EXIT
125 SOFTIRQENTRY_TEXT <<
126 ENTRY_TEXT <<
127 TEXT_TEXT <<
128 SCHED_TEXT <<
129 LOCK_TEXT <<
130 *(.fixup) <<
131 } <<
132 _etext = .; <<
133 PROVIDE (etext = .); <<
134 19
135 . = ALIGN(16); !! 20 #include <asm-generic/vmlinux.lds.h>
136 <<
137 RO_DATA(4096) <<
138 <<
139 /* Data section */ <<
140 21
141 #ifdef CONFIG_XIP_KERNEL !! 22 #undef mips
142 INIT_TEXT_SECTION(PAGE_SIZE) !! 23 #define mips mips
>> 24 OUTPUT_ARCH(mips)
>> 25 ENTRY(kernel_entry)
>> 26 PHDRS {
>> 27 text PT_LOAD FLAGS(7); /* RWX */
>> 28 #ifndef CONFIG_CAVIUM_OCTEON_SOC
>> 29 note PT_NOTE FLAGS(4); /* R__ */
>> 30 #endif /* CAVIUM_OCTEON_SOC */
>> 31 }
>> 32
>> 33 #ifdef CONFIG_32BIT
>> 34 #ifdef CONFIG_CPU_LITTLE_ENDIAN
>> 35 jiffies = jiffies_64;
>> 36 #else
>> 37 jiffies = jiffies_64 + 4;
>> 38 #endif
143 #else 39 #else
144 _sdata = .; !! 40 jiffies = jiffies_64;
145 RW_DATA(XCHAL_ICACHE_LINESIZE, PAGE_SIZE, TH <<
146 _edata = .; <<
147 <<
148 /* Initialization code and data: */ <<
149 <<
150 . = ALIGN(PAGE_SIZE); <<
151 __init_begin = .; <<
152 INIT_TEXT_SECTION(PAGE_SIZE) <<
153 <<
154 .init.data : <<
155 { <<
156 INIT_DATA <<
157 } <<
158 #endif <<
159 <<
160 .init.rodata : <<
161 { <<
162 . = ALIGN(0x4); <<
163 __tagtable_begin = .; <<
164 *(.taglist) <<
165 __tagtable_end = .; <<
166 <<
167 . = ALIGN(16); <<
168 __boot_reloc_table_start = ABSOLUTE(.); <<
169 <<
170 #if !MERGED_VECTORS <<
171 #ifdef SUPPORT_WINDOWED <<
172 RELOCATE_ENTRY(_WindowVectors_text, <<
173 .WindowVectors.text); <<
174 #endif <<
175 #if XCHAL_EXCM_LEVEL >= 2 <<
176 RELOCATE_ENTRY(_Level2InterruptVector_text <<
177 .Level2InterruptVector.text <<
178 #endif <<
179 #if XCHAL_EXCM_LEVEL >= 3 <<
180 RELOCATE_ENTRY(_Level3InterruptVector_text <<
181 .Level3InterruptVector.text <<
182 #endif <<
183 #if XCHAL_EXCM_LEVEL >= 4 <<
184 RELOCATE_ENTRY(_Level4InterruptVector_text <<
185 .Level4InterruptVector.text <<
186 #endif <<
187 #if XCHAL_EXCM_LEVEL >= 5 <<
188 RELOCATE_ENTRY(_Level5InterruptVector_text <<
189 .Level5InterruptVector.text <<
190 #endif 41 #endif
191 #if XCHAL_EXCM_LEVEL >= 6 <<
192 RELOCATE_ENTRY(_Level6InterruptVector_text <<
193 .Level6InterruptVector.text <<
194 #endif <<
195 RELOCATE_ENTRY(_KernelExceptionVector_text <<
196 .KernelExceptionVector.text <<
197 RELOCATE_ENTRY(_UserExceptionVector_text, <<
198 .UserExceptionVector.text); <<
199 RELOCATE_ENTRY(_DoubleExceptionVector_text <<
200 .DoubleExceptionVector.text <<
201 RELOCATE_ENTRY(_DebugInterruptVector_text, <<
202 .DebugInterruptVector.text) <<
203 RELOCATE_ENTRY(_exception_text, <<
204 .exception.text); <<
205 #ifdef CONFIG_XIP_KERNEL <<
206 RELOCATE_ENTRY(_xip_text, .xiptext); <<
207 #endif <<
208 #endif <<
209 #ifdef CONFIG_XIP_KERNEL <<
210 RELOCATE_ENTRY(_xip_data, .data); <<
211 RELOCATE_ENTRY(_xip_init_data, .init.data) <<
212 #endif <<
213 #if defined(CONFIG_SECONDARY_RESET_VECTOR) <<
214 RELOCATE_ENTRY(_SecondaryResetVector_text, <<
215 .SecondaryResetVector.text) <<
216 #endif <<
217 <<
218 __boot_reloc_table_end = ABSOLUTE(.) ; <<
219 <<
220 INIT_SETUP(XCHAL_ICACHE_LINESIZE) <<
221 INIT_CALLS <<
222 CON_INITCALL <<
223 INIT_RAM_FS <<
224 } <<
225 <<
226 PERCPU_SECTION(XCHAL_ICACHE_LINESIZE) <<
227 <<
228 /* We need this dummy segment here */ <<
229 <<
230 . = ALIGN(4); <<
231 .dummy : { LONG(0) } <<
232 <<
233 #undef LAST <<
234 #define LAST .dummy <<
235 <<
236 #if !MERGED_VECTORS <<
237 /* The vectors are relocated to the real pos <<
238 <<
239 #ifdef SUPPORT_WINDOWED <<
240 SECTION_VECTOR4 (_WindowVectors_text, <<
241 .WindowVectors.text, <<
242 WINDOW_VECTORS_VADDR, <<
243 LAST) <<
244 #undef LAST <<
245 #define LAST .WindowVectors.text <<
246 #endif <<
247 SECTION_VECTOR4 (_DebugInterruptVector_text, <<
248 .DebugInterruptVector.text, <<
249 DEBUG_VECTOR_VADDR, <<
250 LAST) <<
251 #undef LAST <<
252 #define LAST .DebugInterruptVector.text <<
253 #if XCHAL_EXCM_LEVEL >= 2 <<
254 SECTION_VECTOR4 (_Level2InterruptVector_text <<
255 .Level2InterruptVector.text, <<
256 INTLEVEL2_VECTOR_VADDR, <<
257 LAST) <<
258 # undef LAST <<
259 # define LAST .Level2InterruptVector.text <<
260 #endif <<
261 #if XCHAL_EXCM_LEVEL >= 3 <<
262 SECTION_VECTOR4 (_Level3InterruptVector_text <<
263 .Level3InterruptVector.text, <<
264 INTLEVEL3_VECTOR_VADDR, <<
265 LAST) <<
266 # undef LAST <<
267 # define LAST .Level3InterruptVector.text <<
268 #endif <<
269 #if XCHAL_EXCM_LEVEL >= 4 <<
270 SECTION_VECTOR4 (_Level4InterruptVector_text <<
271 .Level4InterruptVector.text, <<
272 INTLEVEL4_VECTOR_VADDR, <<
273 LAST) <<
274 # undef LAST <<
275 # define LAST .Level4InterruptVector.text <<
276 #endif <<
277 #if XCHAL_EXCM_LEVEL >= 5 <<
278 SECTION_VECTOR4 (_Level5InterruptVector_text <<
279 .Level5InterruptVector.text, <<
280 INTLEVEL5_VECTOR_VADDR, <<
281 LAST) <<
282 # undef LAST <<
283 # define LAST .Level5InterruptVector.text <<
284 #endif <<
285 #if XCHAL_EXCM_LEVEL >= 6 <<
286 SECTION_VECTOR4 (_Level6InterruptVector_text <<
287 .Level6InterruptVector.text, <<
288 INTLEVEL6_VECTOR_VADDR, <<
289 LAST) <<
290 # undef LAST <<
291 # define LAST .Level6InterruptVector.text <<
292 #endif <<
293 SECTION_VECTOR4 (_KernelExceptionVector_text <<
294 .KernelExceptionVector.text, <<
295 KERNEL_VECTOR_VADDR, <<
296 LAST) <<
297 #undef LAST <<
298 SECTION_VECTOR4 (_UserExceptionVector_text, <<
299 .UserExceptionVector.text, <<
300 USER_VECTOR_VADDR, <<
301 .KernelExceptionVector.text) <<
302 SECTION_VECTOR4 (_DoubleExceptionVector_text <<
303 .DoubleExceptionVector.text, <<
304 DOUBLEEXC_VECTOR_VADDR, <<
305 .UserExceptionVector.text) <<
306 #define LAST .DoubleExceptionVector.text <<
307 <<
308 #endif <<
309 #if defined(CONFIG_SECONDARY_RESET_VECTOR) <<
310 <<
311 SECTION_VECTOR4 (_SecondaryResetVector_text, <<
312 .SecondaryResetVector.text, <<
313 RESET_VECTOR1_VADDR, <<
314 LAST) <<
315 #undef LAST <<
316 #define LAST .SecondaryResetVector.text <<
317 <<
318 #endif <<
319 #if !MERGED_VECTORS <<
320 SECTION_VECTOR4 (_exception_text, <<
321 .exception.text, <<
322 , <<
323 LAST) <<
324 #undef LAST <<
325 #define LAST .exception.text <<
326 SECTION_VECTOR4 (_xip_text, <<
327 .xiptext, <<
328 , <<
329 LAST) <<
330 #undef LAST <<
331 #define LAST .xiptext <<
332 #endif <<
333 . = (LOADADDR(LAST) + SIZEOF(LAST) + 3) & ~ <<
334 42
335 .dummy1 : AT(ADDR(.dummy1)) { LONG(0) } !! 43 SECTIONS
336 . = ALIGN(PAGE_SIZE); !! 44 {
337 !! 45 #ifdef CONFIG_BOOT_ELF64
338 #ifndef CONFIG_XIP_KERNEL !! 46 /* Read-only sections, merged into text segment: */
339 __init_end = .; !! 47 /* . = 0xc000000000000000; */
340 !! 48
341 BSS_SECTION(0, 8192, 0) !! 49 /* This is the value for an Origin kernel, taken from an IRIX kernel. */
342 #endif !! 50 /* . = 0xc00000000001c000; */
343 !! 51
344 _end = .; !! 52 /* Set the vaddr for the text segment to a value
345 !! 53 * >= 0xa800 0000 0001 9000 if no symmon is going to configured
346 #ifdef CONFIG_XIP_KERNEL !! 54 * >= 0xa800 0000 0030 0000 otherwise
347 . = CONFIG_XIP_DATA_ADDR; !! 55 */
348 !! 56
349 _xip_start = .; !! 57 /* . = 0xa800000000300000; */
350 !! 58 . = 0xffffffff80300000;
351 #undef LOAD_OFFSET !! 59 #endif
352 #define LOAD_OFFSET \ !! 60 . = LINKER_LOAD_ADDRESS;
353 (CONFIG_XIP_DATA_ADDR - (LOADADDR(.dummy1) + !! 61 /* read-only */
354 !! 62 _text = .; /* Text and read-only data */
355 _xip_data_start = .; !! 63 .text : {
356 _sdata = .; !! 64 TEXT_TEXT
357 RW_DATA(XCHAL_ICACHE_LINESIZE, PAGE_SIZE, TH !! 65 SCHED_TEXT
358 _edata = .; !! 66 LOCK_TEXT
359 _xip_data_end = .; !! 67 KPROBES_TEXT
360 !! 68 IRQENTRY_TEXT
361 /* Initialization data: */ !! 69 SOFTIRQENTRY_TEXT
362 !! 70 *(.fixup)
363 STRUCT_ALIGN(); !! 71 *(.gnu.warning)
364 !! 72 . = ALIGN(16);
365 _xip_init_data_start = .; !! 73 *(.got) /* Global offset table */
366 __init_begin = .; !! 74 } :text = 0
367 .init.data : !! 75 _etext = .; /* End of text section */
368 { !! 76
369 INIT_DATA !! 77 EXCEPTION_TABLE(16)
370 } !! 78
371 _xip_init_data_end = .; !! 79 /* Exception table for data bus errors */
372 __init_end = .; !! 80 __dbe_table : {
373 BSS_SECTION(0, 8192, 0) !! 81 __start___dbe_table = .;
374 !! 82 KEEP(*(__dbe_table))
375 _xip_end = .; !! 83 __stop___dbe_table = .;
376 !! 84 }
377 #undef LOAD_OFFSET !! 85
378 #endif !! 86 _sdata = .; /* Start of data section */
379 !! 87 RO_DATA(4096)
380 DWARF_DEBUG !! 88
381 !! 89 /* writeable */
382 .xt.prop 0 : { KEEP(*(.xt.prop .xt.prop.* .g !! 90 .data : { /* Data */
383 .xt.insn 0 : { KEEP(*(.xt.insn .xt.insn.* .g !! 91 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
384 .xt.lit 0 : { KEEP(*(.xt.lit .xt.lit.* .g !! 92
385 !! 93 INIT_TASK_DATA(THREAD_SIZE)
386 /* Sections to be discarded */ !! 94 NOSAVE_DATA
387 DISCARDS !! 95 PAGE_ALIGNED_DATA(PAGE_SIZE)
>> 96 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 97 READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 98 DATA_DATA
>> 99 CONSTRUCTORS
>> 100 }
>> 101 BUG_TABLE
>> 102 _gp = . + 0x8000;
>> 103 .lit8 : {
>> 104 *(.lit8)
>> 105 }
>> 106 .lit4 : {
>> 107 *(.lit4)
>> 108 }
>> 109 /* We want the small data sections together, so single-instruction offsets
>> 110 can access them all, and initialized data all before uninitialized, so
>> 111 we can shorten the on-disk segment size. */
>> 112 .sdata : {
>> 113 *(.sdata)
>> 114 }
>> 115 _edata = .; /* End of data section */
>> 116
>> 117 /* will be freed after init */
>> 118 . = ALIGN(PAGE_SIZE); /* Init code and data */
>> 119 __init_begin = .;
>> 120 INIT_TEXT_SECTION(PAGE_SIZE)
>> 121 INIT_DATA_SECTION(16)
>> 122
>> 123 . = ALIGN(4);
>> 124 .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) {
>> 125 __mips_machines_start = .;
>> 126 KEEP(*(.mips.machines.init))
>> 127 __mips_machines_end = .;
>> 128 }
>> 129
>> 130 /* .exit.text is discarded at runtime, not link time, to deal with
>> 131 * references from .rodata
>> 132 */
>> 133 .exit.text : {
>> 134 EXIT_TEXT
>> 135 }
>> 136 .exit.data : {
>> 137 EXIT_DATA
>> 138 }
>> 139 #ifdef CONFIG_SMP
>> 140 PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
>> 141 #endif
>> 142
>> 143 .rel.dyn : ALIGN(8) {
>> 144 *(.rel)
>> 145 *(.rel*)
>> 146 }
>> 147
>> 148 #ifdef CONFIG_MIPS_ELF_APPENDED_DTB
>> 149 STRUCT_ALIGN();
>> 150 .appended_dtb : AT(ADDR(.appended_dtb) - LOAD_OFFSET) {
>> 151 *(.appended_dtb)
>> 152 KEEP(*(.appended_dtb))
>> 153 }
>> 154 #endif
>> 155
>> 156 #ifdef CONFIG_RELOCATABLE
>> 157 . = ALIGN(4);
>> 158
>> 159 .data.reloc : {
>> 160 _relocation_start = .;
>> 161 /*
>> 162 * Space for relocation table
>> 163 * This needs to be filled so that the
>> 164 * relocs tool can overwrite the content.
>> 165 * An invalid value is left at the start of the
>> 166 * section to abort relocation if the table
>> 167 * has not been filled in.
>> 168 */
>> 169 LONG(0xFFFFFFFF);
>> 170 FILL(0);
>> 171 . += CONFIG_RELOCATION_TABLE_SIZE - 4;
>> 172 _relocation_end = .;
>> 173 }
>> 174 #endif
>> 175
>> 176 #ifdef CONFIG_MIPS_RAW_APPENDED_DTB
>> 177 .fill : {
>> 178 FILL(0);
>> 179 BYTE(0);
>> 180 STRUCT_ALIGN();
>> 181 }
>> 182 __appended_dtb = .;
>> 183 /* leave space for appended DTB */
>> 184 . += 0x100000;
>> 185 #endif
>> 186 /*
>> 187 * Align to 64K in attempt to eliminate holes before the
>> 188 * .bss..swapper_pg_dir section at the start of .bss. This
>> 189 * also satisfies PAGE_SIZE alignment as the largest page size
>> 190 * allowed is 64K.
>> 191 */
>> 192 . = ALIGN(0x10000);
>> 193 __init_end = .;
>> 194 /* freed after init ends here */
>> 195
>> 196 /*
>> 197 * Force .bss to 64K alignment so that .bss..swapper_pg_dir
>> 198 * gets that alignment. .sbss should be empty, so there will be
>> 199 * no holes after __init_end. */
>> 200 BSS_SECTION(0, 0x10000, 8)
>> 201
>> 202 _end = . ;
>> 203
>> 204 /* These mark the ABI of the kernel for debuggers. */
>> 205 .mdebug.abi32 : {
>> 206 KEEP(*(.mdebug.abi32))
>> 207 }
>> 208 .mdebug.abi64 : {
>> 209 KEEP(*(.mdebug.abi64))
>> 210 }
>> 211
>> 212 /* This is the MIPS specific mdebug section. */
>> 213 .mdebug : {
>> 214 *(.mdebug)
>> 215 }
>> 216
>> 217 STABS_DEBUG
>> 218 DWARF_DEBUG
>> 219 ELF_DETAILS
>> 220
>> 221 /* These must appear regardless of . */
>> 222 .gptab.sdata : {
>> 223 *(.gptab.data)
>> 224 *(.gptab.sdata)
>> 225 }
>> 226 .gptab.sbss : {
>> 227 *(.gptab.bss)
>> 228 *(.gptab.sbss)
>> 229 }
>> 230
>> 231 /* Sections to be discarded */
>> 232 DISCARDS
>> 233 /DISCARD/ : {
>> 234 /* ABI crap starts here */
>> 235 *(.MIPS.abiflags)
>> 236 *(.MIPS.options)
>> 237 *(.gnu.attributes)
>> 238 *(.options)
>> 239 *(.pdr)
>> 240 *(.reginfo)
>> 241 }
388 } 242 }
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.