1 /* SPDX-License-Identifier: GPL-2.0 */ !! 1 /* $Id: irq.h,v 1.21 2002/01/23 11:27:36 davem Exp $
2 #ifndef __ASM_GENERIC_IRQ_H !! 2 * irq.h: IRQ registers on the 64-bit Sparc.
3 #define __ASM_GENERIC_IRQ_H !! 3 *
4 !! 4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 /* !! 5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
6 * NR_IRQS is the upper bound of how many inte <<
7 * in the platform. It is used to size the sta <<
8 * so don't make it too big. <<
9 */ 6 */
10 #ifndef NR_IRQS !! 7
11 #define NR_IRQS 64 !! 8 #ifndef _SPARC64_IRQ_H
>> 9 #define _SPARC64_IRQ_H
>> 10
>> 11 #include <linux/config.h>
>> 12 #include <linux/linkage.h>
>> 13 #include <linux/kernel.h>
>> 14 #include <linux/errno.h>
>> 15 #include <linux/interrupt.h>
>> 16 #include <asm/pil.h>
>> 17 #include <asm/ptrace.h>
>> 18
>> 19 /* You should not mess with this directly. That's the job of irq.c.
>> 20 *
>> 21 * If you make changes here, please update hand coded assembler of
>> 22 * SBUS/floppy interrupt handler in entry.S -DaveM
>> 23 *
>> 24 * This is currently one DCACHE line, two buckets per L2 cache
>> 25 * line. Keep this in mind please.
>> 26 */
>> 27 struct ino_bucket {
>> 28 /* Next handler in per-CPU PIL worklist. We know that
>> 29 * bucket pointers have the high 32-bits clear, so to
>> 30 * save space we only store the bits we need.
>> 31 */
>> 32 /*0x00*/unsigned int irq_chain;
>> 33
>> 34 /* PIL to schedule this IVEC at. */
>> 35 /*0x04*/unsigned char pil;
>> 36
>> 37 /* If an IVEC arrives while irq_info is NULL, we
>> 38 * set this to notify request_irq() about the event.
>> 39 */
>> 40 /*0x05*/unsigned char pending;
>> 41
>> 42 /* Miscellaneous flags. */
>> 43 /*0x06*/unsigned char flags;
>> 44
>> 45 /* This is used to deal with IBF_DMA_SYNC on
>> 46 * Sabre systems.
>> 47 */
>> 48 /*0x07*/unsigned char synctab_ent;
>> 49
>> 50 /* Reference to handler for this IRQ. If this is
>> 51 * non-NULL this means it is active and should be
>> 52 * serviced. Else the pending member is set to one
>> 53 * and later registry of the interrupt checks for
>> 54 * this condition.
>> 55 *
>> 56 * Normally this is just an irq_action structure.
>> 57 * But, on PCI, if multiple interrupt sources behind
>> 58 * a bridge have multiple interrupt sources that share
>> 59 * the same INO bucket, this points to an array of
>> 60 * pointers to four IRQ action structures.
>> 61 */
>> 62 /*0x08*/void *irq_info;
>> 63
>> 64 /* Sun5 Interrupt Clear Register. */
>> 65 /*0x10*/unsigned long iclr;
>> 66
>> 67 /* Sun5 Interrupt Mapping Register. */
>> 68 /*0x18*/unsigned long imap;
>> 69
>> 70 };
>> 71
>> 72 #ifdef CONFIG_PCI
>> 73 extern unsigned long pci_dma_wsync;
>> 74 extern unsigned long dma_sync_reg_table[256];
>> 75 extern unsigned char dma_sync_reg_table_entry;
12 #endif 76 #endif
13 77
14 static inline int irq_canonicalize(int irq) !! 78 /* IMAP/ICLR register defines */
>> 79 #define IMAP_VALID 0x80000000 /* IRQ Enabled */
>> 80 #define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
>> 81 #define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */
>> 82 #define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */
>> 83 #define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */
>> 84 #define IMAP_IGN 0x000007c0 /* IRQ Group Number */
>> 85 #define IMAP_INO 0x0000003f /* IRQ Number */
>> 86 #define IMAP_INR 0x000007ff /* Full interrupt number*/
>> 87
>> 88 #define ICLR_IDLE 0x00000000 /* Idle state */
>> 89 #define ICLR_TRANSMIT 0x00000001 /* Transmit state */
>> 90 #define ICLR_PENDING 0x00000003 /* Pending state */
>> 91
>> 92 /* Only 8-bits are available, be careful. -DaveM */
>> 93 #define IBF_DMA_SYNC 0x01 /* DMA synchronization behind PCI bridge needed. */
>> 94 #define IBF_PCI 0x02 /* Indicates PSYCHO/SABRE/SCHIZO PCI interrupt. */
>> 95 #define IBF_ACTIVE 0x04 /* This interrupt is active and has a handler. */
>> 96 #define IBF_MULTI 0x08 /* On PCI, indicates shared bucket. */
>> 97 #define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */
>> 98
>> 99 #define NUM_IVECS (IMAP_INR + 1)
>> 100 extern struct ino_bucket ivector_table[NUM_IVECS];
>> 101
>> 102 #define __irq_ino(irq) \
>> 103 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
>> 104 #define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
>> 105 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
>> 106 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
>> 107
>> 108 static __inline__ char *__irq_itoa(unsigned int irq)
>> 109 {
>> 110 static char buff[16];
>> 111
>> 112 sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
>> 113 return buff;
>> 114 }
>> 115
>> 116 #define NR_IRQS 16
>> 117
>> 118 #define irq_canonicalize(irq) (irq)
>> 119 extern void disable_irq(unsigned int);
>> 120 #define disable_irq_nosync disable_irq
>> 121 extern void enable_irq(unsigned int);
>> 122 extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
>> 123 extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
>> 124
>> 125 extern int request_fast_irq(unsigned int irq,
>> 126 irqreturn_t (*handler)(int, void *, struct pt_regs *),
>> 127 unsigned long flags, __const__ char *devname,
>> 128 void *dev_id);
>> 129
>> 130 static __inline__ void set_softint(unsigned long bits)
15 { 131 {
16 return irq; !! 132 __asm__ __volatile__("wr %0, 0x0, %%set_softint"
>> 133 : /* No outputs */
>> 134 : "r" (bits));
17 } 135 }
18 136
19 #endif /* __ASM_GENERIC_IRQ_H */ !! 137 static __inline__ void clear_softint(unsigned long bits)
>> 138 {
>> 139 __asm__ __volatile__("wr %0, 0x0, %%clear_softint"
>> 140 : /* No outputs */
>> 141 : "r" (bits));
>> 142 }
>> 143
>> 144 static __inline__ unsigned long get_softint(void)
>> 145 {
>> 146 unsigned long retval;
>> 147
>> 148 __asm__ __volatile__("rd %%softint, %0"
>> 149 : "=r" (retval));
>> 150 return retval;
>> 151 }
>> 152
>> 153 #endif
20 154
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