1 /* SPDX-License-Identifier: GPL-2.0 */ !! 1 /*
2 #ifndef __ASM_GENERIC_TIMEX_H !! 2 * This file is subject to the terms and conditions of the GNU General Public
3 #define __ASM_GENERIC_TIMEX_H !! 3 * License. See the file "COPYING" in the main directory of this archive
>> 4 * for more details.
>> 5 *
>> 6 * Copyright (C) 1998, 1999, 2003 by Ralf Baechle
>> 7 */
>> 8 #ifndef _ASM_TIMEX_H
>> 9 #define _ASM_TIMEX_H
>> 10
>> 11 #include <linux/config.h>
>> 12 #include <asm/mipsregs.h>
4 13
5 /* 14 /*
6 * If you have a cycle counter, return the val !! 15 * This is the frequency of the timer used for Linux's timer interrupt.
>> 16 * The value should be defined as accurate as possible or under certain
>> 17 * circumstances Linux timekeeping might become inaccurate or fail.
>> 18 *
>> 19 * For IP22 we cheat and pretend to have a 1MHz timer whic isn't strictly
>> 20 * true - we only use the 8259 timer to calibrate the actual interrupt
>> 21 * timer, so after all it's the master clock source of the system.
>> 22 *
>> 23 * The obscure number 1193182 is the same as used by the original i8254
>> 24 * time in legacy PC hardware; the chip unfortunately also found in a
>> 25 * bunch of MIPS systems.
7 */ 26 */
8 typedef unsigned long cycles_t; !! 27 #ifdef CONFIG_ACER_PICA_61
9 #ifndef get_cycles !! 28 #define CLOCK_TICK_RATE 1193182
10 static inline cycles_t get_cycles(void) !! 29 #elif defined(CONFIG_MIPS_MAGNUM_4000)
11 { !! 30 #define CLOCK_TICK_RATE 1193182
12 return 0; !! 31 #elif defined(CONFIG_OLIVETTI_M700)
13 } !! 32 #define CLOCK_TICK_RATE 1193182
>> 33 #elif defined(CONFIG_SGI_IP22)
>> 34 #define CLOCK_TICK_RATE 1000000
>> 35 #elif defined(CONFIG_SNI_RM200_PCI)
>> 36 #define CLOCK_TICK_RATE 1193182
14 #endif 37 #endif
15 38
16 /* 39 /*
17 * Architectures are encouraged to implement r !! 40 * Standard way to access the cycle counter.
18 * and define this in order to avoid the expen !! 41 * Currently only used on SMP for scheduling.
19 * calibration during boot. !! 42 *
>> 43 * Only the low 32 bits are available as a continuously counting entity.
>> 44 * But this only means we'll force a reschedule every 8 seconds or so,
>> 45 * which isn't an evil thing.
>> 46 *
>> 47 * We know that all SMP capable CPUs have cycle counters.
20 */ 48 */
21 #undef ARCH_HAS_READ_CURRENT_TIMER <<
22 49
23 #endif /* __ASM_GENERIC_TIMEX_H */ !! 50 typedef unsigned int cycles_t;
>> 51 extern cycles_t cacheflush_time;
>> 52
>> 53 static inline cycles_t get_cycles (void)
>> 54 {
>> 55 return read_c0_count();
>> 56 }
>> 57
>> 58 #endif /* _ASM_TIMEX_H */
24 59
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