1 /* 1
2 * Copyright © 2007-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charg
6 * copy of this software and associated docume
7 * to deal in the Software without restriction
8 * the rights to use, copy, modify, merge, pub
9 * and/or sell copies of the Software, and to
10 * Software is furnished to do so, subject to
11 *
12 * The above copyright notice and this permiss
13 * all copies or substantial portions of the S
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT W
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE W
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINF
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIA
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CO
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #ifndef __DRM_EDID_H__
24 #define __DRM_EDID_H__
25
26 #include <linux/types.h>
27
28 enum hdmi_quantization_range;
29 struct drm_connector;
30 struct drm_device;
31 struct drm_display_mode;
32 struct drm_edid;
33 struct drm_printer;
34 struct hdmi_avi_infoframe;
35 struct hdmi_vendor_infoframe;
36 struct i2c_adapter;
37
38 #define EDID_LENGTH 128
39 #define DDC_ADDR 0x50
40 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where Di
41
42 #define CEA_EXT 0x02
43 #define VTB_EXT 0x10
44 #define DI_EXT 0x40
45 #define LS_EXT 0x50
46 #define MI_EXT 0x60
47 #define DISPLAYID_EXT 0x70
48
49 struct est_timings {
50 u8 t1;
51 u8 t2;
52 u8 mfg_rsvd;
53 } __packed;
54
55 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
56 #define EDID_TIMING_ASPECT_SHIFT 6
57 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_
58
59 /* need to add 60 */
60 #define EDID_TIMING_VFREQ_SHIFT 0
61 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID
62
63 struct std_timing {
64 u8 hsize; /* need to multiply by 8 the
65 u8 vfreq_aspect;
66 } __packed;
67
68 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
69 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
70 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
71 #define DRM_EDID_PT_STEREO (1 << 5)
72 #define DRM_EDID_PT_INTERLACED (1 << 7)
73
74 /* If detailed data is pixel timing */
75 struct detailed_pixel_timing {
76 u8 hactive_lo;
77 u8 hblank_lo;
78 u8 hactive_hblank_hi;
79 u8 vactive_lo;
80 u8 vblank_lo;
81 u8 vactive_vblank_hi;
82 u8 hsync_offset_lo;
83 u8 hsync_pulse_width_lo;
84 u8 vsync_offset_pulse_width_lo;
85 u8 hsync_vsync_offset_pulse_width_hi;
86 u8 width_mm_lo;
87 u8 height_mm_lo;
88 u8 width_height_mm_hi;
89 u8 hborder;
90 u8 vborder;
91 u8 misc;
92 } __packed;
93
94 /* If it's not pixel timing, it'll be one of t
95 struct detailed_data_string {
96 u8 str[13];
97 } __packed;
98
99 #define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 <<
100 #define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 <<
101 #define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 <<
102 #define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 <<
103
104 #define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x
105 #define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x
106 #define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x
107 #define DRM_EDID_CVT_SUPPORT_FLAG 0x
108
109 #define DRM_EDID_CVT_FLAGS_STANDARD_BLANKING (
110 #define DRM_EDID_CVT_FLAGS_REDUCED_BLANKING (
111
112 struct detailed_data_monitor_range {
113 u8 min_vfreq;
114 u8 max_vfreq;
115 u8 min_hfreq_khz;
116 u8 max_hfreq_khz;
117 u8 pixel_clock_mhz; /* need to multipl
118 u8 flags;
119 union {
120 struct {
121 u8 reserved;
122 u8 hfreq_start_khz; /*
123 u8 c; /* need to divid
124 __le16 m;
125 u8 k;
126 u8 j; /* need to divid
127 } __packed gtf2;
128 struct {
129 u8 version;
130 u8 data1; /* high 6 bi
131 u8 data2; /* plus low
132 u8 supported_aspects;
133 u8 flags; /* preferred
134 u8 supported_scalings;
135 u8 preferred_refresh;
136 } __packed cvt;
137 } __packed formula;
138 } __packed;
139
140 struct detailed_data_wpindex {
141 u8 white_yx_lo; /* Lower 2 bits each *
142 u8 white_x_hi;
143 u8 white_y_hi;
144 u8 gamma; /* need to divide by 100 the
145 } __packed;
146
147 struct detailed_data_color_point {
148 u8 windex1;
149 u8 wpindex1[3];
150 u8 windex2;
151 u8 wpindex2[3];
152 } __packed;
153
154 struct cvt_timing {
155 u8 code[3];
156 } __packed;
157
158 struct detailed_non_pixel {
159 u8 pad1;
160 u8 type; /* ff=serial, fe=string, fd=m
161 fb=color point data, fa=st
162 f9=undefined, f8=mfg. rese
163 u8 pad2;
164 union {
165 struct detailed_data_string st
166 struct detailed_data_monitor_r
167 struct detailed_data_wpindex c
168 struct std_timing timings[6];
169 struct cvt_timing cvt[4];
170 } __packed data;
171 } __packed;
172
173 #define EDID_DETAIL_EST_TIMINGS 0xf7
174 #define EDID_DETAIL_CVT_3BYTE 0xf8
175 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
176 #define EDID_DETAIL_STD_MODES 0xfa
177 #define EDID_DETAIL_MONITOR_CPDATA 0xfb
178 #define EDID_DETAIL_MONITOR_NAME 0xfc
179 #define EDID_DETAIL_MONITOR_RANGE 0xfd
180 #define EDID_DETAIL_MONITOR_STRING 0xfe
181 #define EDID_DETAIL_MONITOR_SERIAL 0xff
182
183 struct detailed_timing {
184 __le16 pixel_clock; /* need to multipl
185 union {
186 struct detailed_pixel_timing p
187 struct detailed_non_pixel othe
188 } __packed data;
189 } __packed;
190
191 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0
192 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1
193 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2
194 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3
195 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4
196 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5
197 #define DRM_EDID_INPUT_DIGITAL (1 << 7
198 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4
199 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4
200 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4
201 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4
202 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4
203 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4
204 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4
205 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4
206 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4
207 #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0
208 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0
209 #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0
210 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0
211 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0
212 #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0
213 #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0
214 #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0
215
216 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 <
217 #define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 <
218 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 <
219 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 <
220 /* If analog */
221 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 <
222 /* If digital */
223 #define DRM_EDID_FEATURE_COLOR_MASK (3 <
224 #define DRM_EDID_FEATURE_RGB (0 <
225 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 <
226 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 <
227 #define DRM_EDID_FEATURE_RGB_YCRCB (3 <
228
229 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 <
230 #define DRM_EDID_FEATURE_PM_SUSPEND (1 <
231 #define DRM_EDID_FEATURE_PM_STANDBY (1 <
232
233 #define DRM_EDID_HDMI_DC_48 (1 <
234 #define DRM_EDID_HDMI_DC_36 (1 <
235 #define DRM_EDID_HDMI_DC_30 (1 <
236 #define DRM_EDID_HDMI_DC_Y444 (1 <
237
238 /* YCBCR 420 deep color modes */
239 #define DRM_EDID_YCBCR420_DC_48 (1 <
240 #define DRM_EDID_YCBCR420_DC_36 (1 <
241 #define DRM_EDID_YCBCR420_DC_30 (1 <
242 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YC
243 DRM_EDID_Y
244 DRM_EDID_Y
245
246 /* HDMI 2.1 additional fields */
247 #define DRM_EDID_MAX_FRL_RATE_MASK
248 #define DRM_EDID_FAPA_START_LOCATION
249 #define DRM_EDID_ALLM
250 #define DRM_EDID_FVA
251
252 /* Deep Color specific */
253 #define DRM_EDID_DC_30BIT_420
254 #define DRM_EDID_DC_36BIT_420
255 #define DRM_EDID_DC_48BIT_420
256
257 /* VRR specific */
258 #define DRM_EDID_CNMVRR
259 #define DRM_EDID_CINEMA_VRR
260 #define DRM_EDID_MDELTA
261 #define DRM_EDID_VRR_MAX_UPPER_MASK
262 #define DRM_EDID_VRR_MAX_LOWER_MASK
263 #define DRM_EDID_VRR_MIN_MASK
264
265 /* DSC specific */
266 #define DRM_EDID_DSC_10BPC
267 #define DRM_EDID_DSC_12BPC
268 #define DRM_EDID_DSC_16BPC
269 #define DRM_EDID_DSC_ALL_BPP
270 #define DRM_EDID_DSC_NATIVE_420
271 #define DRM_EDID_DSC_1P2
272 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK
273 #define DRM_EDID_DSC_MAX_SLICES
274 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES
275
276 struct drm_edid_product_id {
277 __be16 manufacturer_name;
278 __le16 product_code;
279 __le32 serial_number;
280 u8 week_of_manufacture;
281 u8 year_of_manufacture;
282 } __packed;
283
284 struct edid {
285 u8 header[8];
286 /* Vendor & product info */
287 union {
288 struct drm_edid_product_id pro
289 struct {
290 u8 mfg_id[2];
291 u8 prod_code[2];
292 u32 serial; /* FIXME:
293 u8 mfg_week;
294 u8 mfg_year;
295 } __packed;
296 } __packed;
297 /* EDID version */
298 u8 version;
299 u8 revision;
300 /* Display info: */
301 u8 input;
302 u8 width_cm;
303 u8 height_cm;
304 u8 gamma;
305 u8 features;
306 /* Color characteristics */
307 u8 red_green_lo;
308 u8 blue_white_lo;
309 u8 red_x;
310 u8 red_y;
311 u8 green_x;
312 u8 green_y;
313 u8 blue_x;
314 u8 blue_y;
315 u8 white_x;
316 u8 white_y;
317 /* Est. timings and mfg rsvd timings*/
318 struct est_timings established_timings
319 /* Standard timings 1-8*/
320 struct std_timing standard_timings[8];
321 /* Detailing timings 1-4 */
322 struct detailed_timing detailed_timing
323 /* Number of 128 byte ext. blocks */
324 u8 extensions;
325 /* Checksum */
326 u8 checksum;
327 } __packed;
328
329 /* EDID matching */
330 struct drm_edid_ident {
331 /* ID encoded by drm_edid_encode_panel
332 u32 panel_id;
333 const char *name;
334 };
335
336 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0]
337
338 /* Short Audio Descriptor */
339 struct cea_sad {
340 u8 format;
341 u8 channels; /* max number of channels
342 u8 freq;
343 u8 byte2; /* meaning depends on format
344 };
345
346 int drm_edid_to_sad(const struct edid *edid, s
347 int drm_edid_to_speaker_allocation(const struc
348 int drm_av_sync_delay(struct drm_connector *co
349 const struct drm_display
350
351 int
352 drm_hdmi_avi_infoframe_from_display_mode(struc
353 const
354 const
355 int
356 drm_hdmi_vendor_infoframe_from_display_mode(st
357 co
358 co
359
360 void
361 drm_hdmi_avi_infoframe_quant_range(struct hdmi
362 const struc
363 const struc
364 enum hdmi_q
365
366 /**
367 * drm_edid_decode_mfg_id - Decode the manufac
368 * @mfg_id: The manufacturer ID
369 * @vend: A 4-byte buffer to store the 3-lette
370 * termination
371 */
372 static inline const char *drm_edid_decode_mfg_
373 {
374 vend[0] = '@' + ((mfg_id >> 10) & 0x1f
375 vend[1] = '@' + ((mfg_id >> 5) & 0x1f)
376 vend[2] = '@' + ((mfg_id >> 0) & 0x1f)
377 vend[3] = '\0';
378
379 return vend;
380 }
381
382 /**
383 * drm_edid_encode_panel_id - Encode an ID for
384 * @vend_chr_0: First character of the vendor
385 * @vend_chr_1: Second character of the vendor
386 * @vend_chr_2: Third character of the vendor
387 * @product_id: The 16-bit product ID.
388 *
389 * This is a macro so that it can be calculate
390 * as an initializer.
391 *
392 * For instance:
393 * drm_edid_encode_panel_id('B', 'O', 'E', 0
394 *
395 * Return: a 32-bit ID per panel.
396 */
397 #define drm_edid_encode_panel_id(vend_chr_0, v
398 ((((u32)(vend_chr_0) - '@') & 0x1f) <<
399 (((u32)(vend_chr_1) - '@') & 0x1f) <<
400 (((u32)(vend_chr_2) - '@') & 0x1f) <<
401 ((product_id) & 0xffff))
402
403 /**
404 * drm_edid_decode_panel_id - Decode a panel I
405 * @panel_id: The panel ID to decode.
406 * @vend: A 4-byte buffer to store the 3-lette
407 * termination
408 * @product_id: The product ID will be returne
409 *
410 * For instance, after:
411 * drm_edid_decode_panel_id(0x09e52d08, vend
412 * These will be true:
413 * vend[0] = 'B'
414 * vend[1] = 'O'
415 * vend[2] = 'E'
416 * vend[3] = '\0'
417 * product_id = 0x2d08
418 */
419 static inline void drm_edid_decode_panel_id(u3
420 {
421 *product_id = (u16)(panel_id & 0xffff)
422 drm_edid_decode_mfg_id(panel_id >> 16,
423 }
424
425 bool drm_probe_ddc(struct i2c_adapter *adapter
426 struct edid *drm_get_edid(struct drm_connector
427 struct i2c_adapter *
428 struct edid *drm_get_edid_switcheroo(struct dr
429 struct i2
430 struct edid *drm_edid_duplicate(const struct e
431 int drm_add_edid_modes(struct drm_connector *c
432 int drm_edid_override_connector_update(struct
433
434 u8 drm_match_cea_mode(const struct drm_display
435 bool drm_detect_hdmi_monitor(const struct edid
436 bool drm_detect_monitor_audio(const struct edi
437 enum hdmi_quantization_range
438 drm_default_rgb_quant_range(const struct drm_d
439 int drm_add_modes_noedid(struct drm_connector
440 int hdisplay, int vdi
441
442 int drm_edid_header_is_valid(const void *edid)
443 bool drm_edid_is_valid(struct edid *edid);
444 void drm_edid_get_monitor_name(const struct ed
445 int buflen);
446 struct drm_display_mode *drm_mode_find_dmt(str
447 int
448 boo
449 struct drm_display_mode *
450 drm_display_mode_from_cea_vic(struct drm_devic
451 u8 video_code);
452
453 /* Interface based on struct drm_edid */
454 const struct drm_edid *drm_edid_alloc(const vo
455 const struct drm_edid *drm_edid_dup(const stru
456 void drm_edid_free(const struct drm_edid *drm_
457 bool drm_edid_valid(const struct drm_edid *drm
458 const struct edid *drm_edid_raw(const struct d
459 const struct drm_edid *drm_edid_read(struct dr
460 const struct drm_edid *drm_edid_read_ddc(struc
461 struc
462 const struct drm_edid *drm_edid_read_custom(st
463 in
464 vo
465 const struct drm_edid *drm_edid_read_base_bloc
466 const struct drm_edid *drm_edid_read_switchero
467
468 int drm_edid_connector_update(struct drm_conne
469 const struct drm
470 int drm_edid_connector_add_modes(struct drm_co
471 bool drm_edid_is_digital(const struct drm_edid
472 void drm_edid_get_product_id(const struct drm_
473 struct drm_edid_p
474 void drm_edid_print_product_id(struct drm_prin
475 const struct dr
476 u32 drm_edid_get_panel_id(const struct drm_edi
477 bool drm_edid_match(const struct drm_edid *drm
478 const struct drm_edid_iden
479
480 #endif /* __DRM_EDID_H__ */
481
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.