1 /* 1 /*
2 * Copyright © 2007-2008 Intel Corporation 2 * Copyright © 2007-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com> 3 * Jesse Barnes <jesse.barnes@intel.com>
4 * 4 *
5 * Permission is hereby granted, free of charg 5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated docume 6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction 7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, pub 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to 9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to 10 * Software is furnished to do so, subject to the following conditions:
11 * 11 *
12 * The above copyright notice and this permiss 12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the S 13 * all copies or substantial portions of the Software.
14 * 14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT W 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE W 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINF 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIA 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CO 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE. 21 * OTHER DEALINGS IN THE SOFTWARE.
22 */ 22 */
23 #ifndef __DRM_EDID_H__ 23 #ifndef __DRM_EDID_H__
24 #define __DRM_EDID_H__ 24 #define __DRM_EDID_H__
25 25
26 #include <linux/types.h> 26 #include <linux/types.h>
27 27
28 enum hdmi_quantization_range; <<
29 struct drm_connector; <<
30 struct drm_device; <<
31 struct drm_display_mode; <<
32 struct drm_edid; <<
33 struct drm_printer; <<
34 struct hdmi_avi_infoframe; <<
35 struct hdmi_vendor_infoframe; <<
36 struct i2c_adapter; <<
37 <<
38 #define EDID_LENGTH 128 28 #define EDID_LENGTH 128
39 #define DDC_ADDR 0x50 29 #define DDC_ADDR 0x50
40 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where Di 30 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
41 31
42 #define CEA_EXT 0x02 32 #define CEA_EXT 0x02
43 #define VTB_EXT 0x10 33 #define VTB_EXT 0x10
44 #define DI_EXT 0x40 34 #define DI_EXT 0x40
45 #define LS_EXT 0x50 35 #define LS_EXT 0x50
46 #define MI_EXT 0x60 36 #define MI_EXT 0x60
47 #define DISPLAYID_EXT 0x70 37 #define DISPLAYID_EXT 0x70
48 38
49 struct est_timings { 39 struct est_timings {
50 u8 t1; 40 u8 t1;
51 u8 t2; 41 u8 t2;
52 u8 mfg_rsvd; 42 u8 mfg_rsvd;
53 } __packed; !! 43 } __attribute__((packed));
54 44
55 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 45 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
56 #define EDID_TIMING_ASPECT_SHIFT 6 46 #define EDID_TIMING_ASPECT_SHIFT 6
57 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_ 47 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
58 48
59 /* need to add 60 */ 49 /* need to add 60 */
60 #define EDID_TIMING_VFREQ_SHIFT 0 50 #define EDID_TIMING_VFREQ_SHIFT 0
61 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID 51 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
62 52
63 struct std_timing { 53 struct std_timing {
64 u8 hsize; /* need to multiply by 8 the 54 u8 hsize; /* need to multiply by 8 then add 248 */
65 u8 vfreq_aspect; 55 u8 vfreq_aspect;
66 } __packed; !! 56 } __attribute__((packed));
67 57
68 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 58 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
69 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 59 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
70 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 60 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
71 #define DRM_EDID_PT_STEREO (1 << 5) 61 #define DRM_EDID_PT_STEREO (1 << 5)
72 #define DRM_EDID_PT_INTERLACED (1 << 7) 62 #define DRM_EDID_PT_INTERLACED (1 << 7)
73 63
74 /* If detailed data is pixel timing */ 64 /* If detailed data is pixel timing */
75 struct detailed_pixel_timing { 65 struct detailed_pixel_timing {
76 u8 hactive_lo; 66 u8 hactive_lo;
77 u8 hblank_lo; 67 u8 hblank_lo;
78 u8 hactive_hblank_hi; 68 u8 hactive_hblank_hi;
79 u8 vactive_lo; 69 u8 vactive_lo;
80 u8 vblank_lo; 70 u8 vblank_lo;
81 u8 vactive_vblank_hi; 71 u8 vactive_vblank_hi;
82 u8 hsync_offset_lo; 72 u8 hsync_offset_lo;
83 u8 hsync_pulse_width_lo; 73 u8 hsync_pulse_width_lo;
84 u8 vsync_offset_pulse_width_lo; 74 u8 vsync_offset_pulse_width_lo;
85 u8 hsync_vsync_offset_pulse_width_hi; 75 u8 hsync_vsync_offset_pulse_width_hi;
86 u8 width_mm_lo; 76 u8 width_mm_lo;
87 u8 height_mm_lo; 77 u8 height_mm_lo;
88 u8 width_height_mm_hi; 78 u8 width_height_mm_hi;
89 u8 hborder; 79 u8 hborder;
90 u8 vborder; 80 u8 vborder;
91 u8 misc; 81 u8 misc;
92 } __packed; !! 82 } __attribute__((packed));
93 83
94 /* If it's not pixel timing, it'll be one of t 84 /* If it's not pixel timing, it'll be one of the below */
95 struct detailed_data_string { 85 struct detailed_data_string {
96 u8 str[13]; 86 u8 str[13];
97 } __packed; !! 87 } __attribute__((packed));
98 <<
99 #define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << <<
100 #define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << <<
101 #define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << <<
102 #define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << <<
103 <<
104 #define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x <<
105 #define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x <<
106 #define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x <<
107 #define DRM_EDID_CVT_SUPPORT_FLAG 0x <<
108 <<
109 #define DRM_EDID_CVT_FLAGS_STANDARD_BLANKING ( <<
110 #define DRM_EDID_CVT_FLAGS_REDUCED_BLANKING ( <<
111 88
112 struct detailed_data_monitor_range { 89 struct detailed_data_monitor_range {
113 u8 min_vfreq; 90 u8 min_vfreq;
114 u8 max_vfreq; 91 u8 max_vfreq;
115 u8 min_hfreq_khz; 92 u8 min_hfreq_khz;
116 u8 max_hfreq_khz; 93 u8 max_hfreq_khz;
117 u8 pixel_clock_mhz; /* need to multipl 94 u8 pixel_clock_mhz; /* need to multiply by 10 */
118 u8 flags; 95 u8 flags;
119 union { 96 union {
120 struct { 97 struct {
121 u8 reserved; 98 u8 reserved;
122 u8 hfreq_start_khz; /* 99 u8 hfreq_start_khz; /* need to multiply by 2 */
123 u8 c; /* need to divid 100 u8 c; /* need to divide by 2 */
124 __le16 m; 101 __le16 m;
125 u8 k; 102 u8 k;
126 u8 j; /* need to divid 103 u8 j; /* need to divide by 2 */
127 } __packed gtf2; !! 104 } __attribute__((packed)) gtf2;
128 struct { 105 struct {
129 u8 version; 106 u8 version;
130 u8 data1; /* high 6 bi 107 u8 data1; /* high 6 bits: extra clock resolution */
131 u8 data2; /* plus low 108 u8 data2; /* plus low 2 of above: max hactive */
132 u8 supported_aspects; 109 u8 supported_aspects;
133 u8 flags; /* preferred 110 u8 flags; /* preferred aspect and blanking support */
134 u8 supported_scalings; 111 u8 supported_scalings;
135 u8 preferred_refresh; 112 u8 preferred_refresh;
136 } __packed cvt; !! 113 } __attribute__((packed)) cvt;
137 } __packed formula; !! 114 } formula;
138 } __packed; !! 115 } __attribute__((packed));
139 116
140 struct detailed_data_wpindex { 117 struct detailed_data_wpindex {
141 u8 white_yx_lo; /* Lower 2 bits each * 118 u8 white_yx_lo; /* Lower 2 bits each */
142 u8 white_x_hi; 119 u8 white_x_hi;
143 u8 white_y_hi; 120 u8 white_y_hi;
144 u8 gamma; /* need to divide by 100 the 121 u8 gamma; /* need to divide by 100 then add 1 */
145 } __packed; !! 122 } __attribute__((packed));
146 123
147 struct detailed_data_color_point { 124 struct detailed_data_color_point {
148 u8 windex1; 125 u8 windex1;
149 u8 wpindex1[3]; 126 u8 wpindex1[3];
150 u8 windex2; 127 u8 windex2;
151 u8 wpindex2[3]; 128 u8 wpindex2[3];
152 } __packed; !! 129 } __attribute__((packed));
153 130
154 struct cvt_timing { 131 struct cvt_timing {
155 u8 code[3]; 132 u8 code[3];
156 } __packed; !! 133 } __attribute__((packed));
157 134
158 struct detailed_non_pixel { 135 struct detailed_non_pixel {
159 u8 pad1; 136 u8 pad1;
160 u8 type; /* ff=serial, fe=string, fd=m 137 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
161 fb=color point data, fa=st 138 fb=color point data, fa=standard timing data,
162 f9=undefined, f8=mfg. rese 139 f9=undefined, f8=mfg. reserved */
163 u8 pad2; 140 u8 pad2;
164 union { 141 union {
165 struct detailed_data_string st 142 struct detailed_data_string str;
166 struct detailed_data_monitor_r 143 struct detailed_data_monitor_range range;
167 struct detailed_data_wpindex c 144 struct detailed_data_wpindex color;
168 struct std_timing timings[6]; 145 struct std_timing timings[6];
169 struct cvt_timing cvt[4]; 146 struct cvt_timing cvt[4];
170 } __packed data; !! 147 } data;
171 } __packed; !! 148 } __attribute__((packed));
172 149
173 #define EDID_DETAIL_EST_TIMINGS 0xf7 150 #define EDID_DETAIL_EST_TIMINGS 0xf7
174 #define EDID_DETAIL_CVT_3BYTE 0xf8 151 #define EDID_DETAIL_CVT_3BYTE 0xf8
175 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 152 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
176 #define EDID_DETAIL_STD_MODES 0xfa 153 #define EDID_DETAIL_STD_MODES 0xfa
177 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 154 #define EDID_DETAIL_MONITOR_CPDATA 0xfb
178 #define EDID_DETAIL_MONITOR_NAME 0xfc 155 #define EDID_DETAIL_MONITOR_NAME 0xfc
179 #define EDID_DETAIL_MONITOR_RANGE 0xfd 156 #define EDID_DETAIL_MONITOR_RANGE 0xfd
180 #define EDID_DETAIL_MONITOR_STRING 0xfe 157 #define EDID_DETAIL_MONITOR_STRING 0xfe
181 #define EDID_DETAIL_MONITOR_SERIAL 0xff 158 #define EDID_DETAIL_MONITOR_SERIAL 0xff
182 159
183 struct detailed_timing { 160 struct detailed_timing {
184 __le16 pixel_clock; /* need to multipl 161 __le16 pixel_clock; /* need to multiply by 10 KHz */
185 union { 162 union {
186 struct detailed_pixel_timing p 163 struct detailed_pixel_timing pixel_data;
187 struct detailed_non_pixel othe 164 struct detailed_non_pixel other_data;
188 } __packed data; !! 165 } data;
189 } __packed; !! 166 } __attribute__((packed));
190 167
191 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0 168 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
192 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1 169 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
193 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2 170 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
194 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3 171 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
195 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4 172 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
196 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5 173 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
197 #define DRM_EDID_INPUT_DIGITAL (1 << 7 174 #define DRM_EDID_INPUT_DIGITAL (1 << 7)
198 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4 !! 175 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4)
199 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4 !! 176 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4)
200 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4 !! 177 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4)
201 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4 !! 178 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4)
202 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4 !! 179 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4)
203 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4 !! 180 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4)
204 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4 !! 181 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4)
205 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4 !! 182 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4)
206 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4 !! 183 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4)
207 #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0 !! 184 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0)
208 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0 !! 185 #define DRM_EDID_DIGITAL_TYPE_DVI (1)
209 #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0 !! 186 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2)
210 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0 !! 187 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3)
211 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0 !! 188 #define DRM_EDID_DIGITAL_TYPE_MDDI (4)
212 #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0 !! 189 #define DRM_EDID_DIGITAL_TYPE_DP (5)
213 #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0 <<
214 #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0 <<
215 190
216 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 < !! 191 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
217 #define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 < <<
218 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 < 192 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
219 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 < 193 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
220 /* If analog */ 194 /* If analog */
221 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 < 195 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
222 /* If digital */ 196 /* If digital */
223 #define DRM_EDID_FEATURE_COLOR_MASK (3 < 197 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
224 #define DRM_EDID_FEATURE_RGB (0 < 198 #define DRM_EDID_FEATURE_RGB (0 << 3)
225 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 < 199 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
226 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 < 200 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
227 #define DRM_EDID_FEATURE_RGB_YCRCB (3 < 201 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
228 202
229 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 < 203 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
230 #define DRM_EDID_FEATURE_PM_SUSPEND (1 < 204 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
231 #define DRM_EDID_FEATURE_PM_STANDBY (1 < 205 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
232 206
233 #define DRM_EDID_HDMI_DC_48 (1 < 207 #define DRM_EDID_HDMI_DC_48 (1 << 6)
234 #define DRM_EDID_HDMI_DC_36 (1 < 208 #define DRM_EDID_HDMI_DC_36 (1 << 5)
235 #define DRM_EDID_HDMI_DC_30 (1 < 209 #define DRM_EDID_HDMI_DC_30 (1 << 4)
236 #define DRM_EDID_HDMI_DC_Y444 (1 < 210 #define DRM_EDID_HDMI_DC_Y444 (1 << 3)
237 211
238 /* YCBCR 420 deep color modes */ !! 212 /* ELD Header Block */
239 #define DRM_EDID_YCBCR420_DC_48 (1 < !! 213 #define DRM_ELD_HEADER_BLOCK_SIZE 4
240 #define DRM_EDID_YCBCR420_DC_36 (1 < !! 214
241 #define DRM_EDID_YCBCR420_DC_30 (1 < !! 215 #define DRM_ELD_VER 0
242 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YC !! 216 # define DRM_ELD_VER_SHIFT 3
243 DRM_EDID_Y !! 217 # define DRM_ELD_VER_MASK (0x1f << 3)
244 DRM_EDID_Y !! 218 # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */
245 !! 219 # define DRM_ELD_VER_CANNED (0x1f << 3)
246 /* HDMI 2.1 additional fields */ !! 220
247 #define DRM_EDID_MAX_FRL_RATE_MASK !! 221 #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */
248 #define DRM_EDID_FAPA_START_LOCATION !! 222
249 #define DRM_EDID_ALLM !! 223 /* ELD Baseline Block for ELD_Ver == 2 */
250 #define DRM_EDID_FVA !! 224 #define DRM_ELD_CEA_EDID_VER_MNL 4
251 !! 225 # define DRM_ELD_CEA_EDID_VER_SHIFT 5
252 /* Deep Color specific */ !! 226 # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5)
253 #define DRM_EDID_DC_30BIT_420 !! 227 # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5)
254 #define DRM_EDID_DC_36BIT_420 !! 228 # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5)
255 #define DRM_EDID_DC_48BIT_420 !! 229 # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5)
256 !! 230 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5)
257 /* VRR specific */ !! 231 # define DRM_ELD_MNL_SHIFT 0
258 #define DRM_EDID_CNMVRR !! 232 # define DRM_ELD_MNL_MASK (0x1f << 0)
259 #define DRM_EDID_CINEMA_VRR !! 233
260 #define DRM_EDID_MDELTA !! 234 #define DRM_ELD_SAD_COUNT_CONN_TYPE 5
261 #define DRM_EDID_VRR_MAX_UPPER_MASK !! 235 # define DRM_ELD_SAD_COUNT_SHIFT 4
262 #define DRM_EDID_VRR_MAX_LOWER_MASK !! 236 # define DRM_ELD_SAD_COUNT_MASK (0xf << 4)
263 #define DRM_EDID_VRR_MIN_MASK !! 237 # define DRM_ELD_CONN_TYPE_SHIFT 2
264 !! 238 # define DRM_ELD_CONN_TYPE_MASK (3 << 2)
265 /* DSC specific */ !! 239 # define DRM_ELD_CONN_TYPE_HDMI (0 << 2)
266 #define DRM_EDID_DSC_10BPC !! 240 # define DRM_ELD_CONN_TYPE_DP (1 << 2)
267 #define DRM_EDID_DSC_12BPC !! 241 # define DRM_ELD_SUPPORTS_AI (1 << 1)
268 #define DRM_EDID_DSC_16BPC !! 242 # define DRM_ELD_SUPPORTS_HDCP (1 << 0)
269 #define DRM_EDID_DSC_ALL_BPP !! 243
270 #define DRM_EDID_DSC_NATIVE_420 !! 244 #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */
271 #define DRM_EDID_DSC_1P2 !! 245 # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */
272 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK !! 246
273 #define DRM_EDID_DSC_MAX_SLICES !! 247 #define DRM_ELD_SPEAKER 7
274 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES !! 248 # define DRM_ELD_SPEAKER_RLRC (1 << 6)
275 !! 249 # define DRM_ELD_SPEAKER_FLRC (1 << 5)
276 struct drm_edid_product_id { !! 250 # define DRM_ELD_SPEAKER_RC (1 << 4)
277 __be16 manufacturer_name; !! 251 # define DRM_ELD_SPEAKER_RLR (1 << 3)
278 __le16 product_code; !! 252 # define DRM_ELD_SPEAKER_FC (1 << 2)
279 __le32 serial_number; !! 253 # define DRM_ELD_SPEAKER_LFE (1 << 1)
280 u8 week_of_manufacture; !! 254 # define DRM_ELD_SPEAKER_FLR (1 << 0)
281 u8 year_of_manufacture; !! 255
282 } __packed; !! 256 #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */
>> 257 # define DRM_ELD_PORT_ID_LEN 8
>> 258
>> 259 #define DRM_ELD_MANUFACTURER_NAME0 16
>> 260 #define DRM_ELD_MANUFACTURER_NAME1 17
>> 261
>> 262 #define DRM_ELD_PRODUCT_CODE0 18
>> 263 #define DRM_ELD_PRODUCT_CODE1 19
>> 264
>> 265 #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */
>> 266
>> 267 #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad))
283 268
284 struct edid { 269 struct edid {
285 u8 header[8]; 270 u8 header[8];
286 /* Vendor & product info */ 271 /* Vendor & product info */
287 union { !! 272 u8 mfg_id[2];
288 struct drm_edid_product_id pro !! 273 u8 prod_code[2];
289 struct { !! 274 u32 serial; /* FIXME: byte order */
290 u8 mfg_id[2]; !! 275 u8 mfg_week;
291 u8 prod_code[2]; !! 276 u8 mfg_year;
292 u32 serial; /* FIXME: <<
293 u8 mfg_week; <<
294 u8 mfg_year; <<
295 } __packed; <<
296 } __packed; <<
297 /* EDID version */ 277 /* EDID version */
298 u8 version; 278 u8 version;
299 u8 revision; 279 u8 revision;
300 /* Display info: */ 280 /* Display info: */
301 u8 input; 281 u8 input;
302 u8 width_cm; 282 u8 width_cm;
303 u8 height_cm; 283 u8 height_cm;
304 u8 gamma; 284 u8 gamma;
305 u8 features; 285 u8 features;
306 /* Color characteristics */ 286 /* Color characteristics */
307 u8 red_green_lo; 287 u8 red_green_lo;
308 u8 blue_white_lo; !! 288 u8 black_white_lo;
309 u8 red_x; 289 u8 red_x;
310 u8 red_y; 290 u8 red_y;
311 u8 green_x; 291 u8 green_x;
312 u8 green_y; 292 u8 green_y;
313 u8 blue_x; 293 u8 blue_x;
314 u8 blue_y; 294 u8 blue_y;
315 u8 white_x; 295 u8 white_x;
316 u8 white_y; 296 u8 white_y;
317 /* Est. timings and mfg rsvd timings*/ 297 /* Est. timings and mfg rsvd timings*/
318 struct est_timings established_timings 298 struct est_timings established_timings;
319 /* Standard timings 1-8*/ 299 /* Standard timings 1-8*/
320 struct std_timing standard_timings[8]; 300 struct std_timing standard_timings[8];
321 /* Detailing timings 1-4 */ 301 /* Detailing timings 1-4 */
322 struct detailed_timing detailed_timing 302 struct detailed_timing detailed_timings[4];
323 /* Number of 128 byte ext. blocks */ 303 /* Number of 128 byte ext. blocks */
324 u8 extensions; 304 u8 extensions;
325 /* Checksum */ 305 /* Checksum */
326 u8 checksum; 306 u8 checksum;
327 } __packed; !! 307 } __attribute__((packed));
328 <<
329 /* EDID matching */ <<
330 struct drm_edid_ident { <<
331 /* ID encoded by drm_edid_encode_panel <<
332 u32 panel_id; <<
333 const char *name; <<
334 }; <<
335 308
336 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] 309 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
337 310
338 /* Short Audio Descriptor */ 311 /* Short Audio Descriptor */
339 struct cea_sad { 312 struct cea_sad {
340 u8 format; 313 u8 format;
341 u8 channels; /* max number of channels 314 u8 channels; /* max number of channels - 1 */
342 u8 freq; 315 u8 freq;
343 u8 byte2; /* meaning depends on format 316 u8 byte2; /* meaning depends on format */
344 }; 317 };
345 318
346 int drm_edid_to_sad(const struct edid *edid, s !! 319 struct drm_encoder;
347 int drm_edid_to_speaker_allocation(const struc !! 320 struct drm_connector;
>> 321 struct drm_display_mode;
>> 322 struct hdmi_avi_infoframe;
>> 323 struct hdmi_vendor_infoframe;
>> 324
>> 325 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
>> 326 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
>> 327 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
348 int drm_av_sync_delay(struct drm_connector *co 328 int drm_av_sync_delay(struct drm_connector *connector,
349 const struct drm_display 329 const struct drm_display_mode *mode);
>> 330 struct drm_connector *drm_select_eld(struct drm_encoder *encoder);
>> 331 int drm_load_edid_firmware(struct drm_connector *connector);
350 332
351 int 333 int
352 drm_hdmi_avi_infoframe_from_display_mode(struc 334 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
353 const <<
354 const 335 const struct drm_display_mode *mode);
355 int 336 int
356 drm_hdmi_vendor_infoframe_from_display_mode(st 337 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
357 co <<
358 co 338 const struct drm_display_mode *mode);
359 339
360 void !! 340 /**
361 drm_hdmi_avi_infoframe_quant_range(struct hdmi !! 341 * drm_eld_mnl - Get ELD monitor name length in bytes.
362 const struc !! 342 * @eld: pointer to an eld memory structure with mnl set
363 const struc !! 343 */
364 enum hdmi_q !! 344 static inline int drm_eld_mnl(const uint8_t *eld)
>> 345 {
>> 346 return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
>> 347 }
365 348
366 /** 349 /**
367 * drm_edid_decode_mfg_id - Decode the manufac !! 350 * drm_eld_sad - Get ELD SAD structures.
368 * @mfg_id: The manufacturer ID !! 351 * @eld: pointer to an eld memory structure with sad_count set
369 * @vend: A 4-byte buffer to store the 3-lette <<
370 * termination <<
371 */ 352 */
372 static inline const char *drm_edid_decode_mfg_ !! 353 static inline const uint8_t *drm_eld_sad(const uint8_t *eld)
373 { 354 {
374 vend[0] = '@' + ((mfg_id >> 10) & 0x1f !! 355 unsigned int ver, mnl;
375 vend[1] = '@' + ((mfg_id >> 5) & 0x1f) !! 356
376 vend[2] = '@' + ((mfg_id >> 0) & 0x1f) !! 357 ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT;
377 vend[3] = '\0'; !! 358 if (ver != 2 && ver != 31)
>> 359 return NULL;
378 360
379 return vend; !! 361 mnl = drm_eld_mnl(eld);
>> 362 if (mnl > 16)
>> 363 return NULL;
>> 364
>> 365 return eld + DRM_ELD_CEA_SAD(mnl, 0);
380 } 366 }
381 367
382 /** 368 /**
383 * drm_edid_encode_panel_id - Encode an ID for !! 369 * drm_eld_sad_count - Get ELD SAD count.
384 * @vend_chr_0: First character of the vendor !! 370 * @eld: pointer to an eld memory structure with sad_count set
385 * @vend_chr_1: Second character of the vendor !! 371 */
386 * @vend_chr_2: Third character of the vendor !! 372 static inline int drm_eld_sad_count(const uint8_t *eld)
387 * @product_id: The 16-bit product ID. !! 373 {
388 * !! 374 return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
389 * This is a macro so that it can be calculate !! 375 DRM_ELD_SAD_COUNT_SHIFT;
390 * as an initializer. !! 376 }
391 * !! 377
392 * For instance: !! 378 /**
393 * drm_edid_encode_panel_id('B', 'O', 'E', 0 !! 379 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
>> 380 * @eld: pointer to an eld memory structure with mnl and sad_count set
394 * 381 *
395 * Return: a 32-bit ID per panel. !! 382 * This is a helper for determining the payload size of the baseline block, in
>> 383 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
396 */ 384 */
397 #define drm_edid_encode_panel_id(vend_chr_0, v !! 385 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
398 ((((u32)(vend_chr_0) - '@') & 0x1f) << !! 386 {
399 (((u32)(vend_chr_1) - '@') & 0x1f) << !! 387 return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
400 (((u32)(vend_chr_2) - '@') & 0x1f) << !! 388 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
401 ((product_id) & 0xffff)) !! 389 }
402 390
403 /** 391 /**
404 * drm_edid_decode_panel_id - Decode a panel I !! 392 * drm_eld_size - Get ELD size in bytes
405 * @panel_id: The panel ID to decode. !! 393 * @eld: pointer to a complete eld memory structure
406 * @vend: A 4-byte buffer to store the 3-lette !! 394 *
407 * termination !! 395 * The returned value does not include the vendor block. It's vendor specific,
408 * @product_id: The product ID will be returne !! 396 * and comprises of the remaining bytes in the ELD memory buffer after
>> 397 * drm_eld_size() bytes of header and baseline block.
409 * 398 *
410 * For instance, after: !! 399 * The returned value is guaranteed to be a multiple of 4.
411 * drm_edid_decode_panel_id(0x09e52d08, vend <<
412 * These will be true: <<
413 * vend[0] = 'B' <<
414 * vend[1] = 'O' <<
415 * vend[2] = 'E' <<
416 * vend[3] = '\0' <<
417 * product_id = 0x2d08 <<
418 */ 400 */
419 static inline void drm_edid_decode_panel_id(u3 !! 401 static inline int drm_eld_size(const uint8_t *eld)
420 { 402 {
421 *product_id = (u16)(panel_id & 0xffff) !! 403 return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
422 drm_edid_decode_mfg_id(panel_id >> 16, <<
423 } 404 }
424 405
425 bool drm_probe_ddc(struct i2c_adapter *adapter !! 406 struct edid *drm_do_get_edid(struct drm_connector *connector,
426 struct edid *drm_get_edid(struct drm_connector !! 407 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
427 struct i2c_adapter * !! 408 size_t len),
428 struct edid *drm_get_edid_switcheroo(struct dr !! 409 void *data);
429 struct i2 <<
430 struct edid *drm_edid_duplicate(const struct e <<
431 int drm_add_edid_modes(struct drm_connector *c <<
432 int drm_edid_override_connector_update(struct <<
433 <<
434 u8 drm_match_cea_mode(const struct drm_display <<
435 bool drm_detect_hdmi_monitor(const struct edid <<
436 bool drm_detect_monitor_audio(const struct edi <<
437 enum hdmi_quantization_range <<
438 drm_default_rgb_quant_range(const struct drm_d <<
439 int drm_add_modes_noedid(struct drm_connector <<
440 int hdisplay, int vdi <<
441 <<
442 int drm_edid_header_is_valid(const void *edid) <<
443 bool drm_edid_is_valid(struct edid *edid); <<
444 void drm_edid_get_monitor_name(const struct ed <<
445 int buflen); <<
446 struct drm_display_mode *drm_mode_find_dmt(str <<
447 int <<
448 boo <<
449 struct drm_display_mode * <<
450 drm_display_mode_from_cea_vic(struct drm_devic <<
451 u8 video_code); <<
452 <<
453 /* Interface based on struct drm_edid */ <<
454 const struct drm_edid *drm_edid_alloc(const vo <<
455 const struct drm_edid *drm_edid_dup(const stru <<
456 void drm_edid_free(const struct drm_edid *drm_ <<
457 bool drm_edid_valid(const struct drm_edid *drm <<
458 const struct edid *drm_edid_raw(const struct d <<
459 const struct drm_edid *drm_edid_read(struct dr <<
460 const struct drm_edid *drm_edid_read_ddc(struc <<
461 struc <<
462 const struct drm_edid *drm_edid_read_custom(st <<
463 in <<
464 vo <<
465 const struct drm_edid *drm_edid_read_base_bloc <<
466 const struct drm_edid *drm_edid_read_switchero <<
467 <<
468 int drm_edid_connector_update(struct drm_conne <<
469 const struct drm <<
470 int drm_edid_connector_add_modes(struct drm_co <<
471 bool drm_edid_is_digital(const struct drm_edid <<
472 void drm_edid_get_product_id(const struct drm_ <<
473 struct drm_edid_p <<
474 void drm_edid_print_product_id(struct drm_prin <<
475 const struct dr <<
476 u32 drm_edid_get_panel_id(const struct drm_edi <<
477 bool drm_edid_match(const struct drm_edid *drm <<
478 const struct drm_edid_iden <<
479 410
480 #endif /* __DRM_EDID_H__ */ 411 #endif /* __DRM_EDID_H__ */
481 412
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