1 /* 1 /*
2 * Copyright © 2007-2008 Intel Corporation 2 * Copyright © 2007-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com> 3 * Jesse Barnes <jesse.barnes@intel.com>
4 * 4 *
5 * Permission is hereby granted, free of charg 5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated docume 6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction 7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, pub 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to 9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to 10 * Software is furnished to do so, subject to the following conditions:
11 * 11 *
12 * The above copyright notice and this permiss 12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the S 13 * all copies or substantial portions of the Software.
14 * 14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT W 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE W 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINF 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIA 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CO 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE. 21 * OTHER DEALINGS IN THE SOFTWARE.
22 */ 22 */
23 #ifndef __DRM_EDID_H__ 23 #ifndef __DRM_EDID_H__
24 #define __DRM_EDID_H__ 24 #define __DRM_EDID_H__
25 25
26 #include <linux/types.h> 26 #include <linux/types.h>
>> 27 #include <linux/hdmi.h>
>> 28 #include <drm/drm_mode.h>
27 29
28 enum hdmi_quantization_range; <<
29 struct drm_connector; <<
30 struct drm_device; 30 struct drm_device;
31 struct drm_display_mode; <<
32 struct drm_edid; <<
33 struct drm_printer; <<
34 struct hdmi_avi_infoframe; <<
35 struct hdmi_vendor_infoframe; <<
36 struct i2c_adapter; 31 struct i2c_adapter;
37 32
38 #define EDID_LENGTH 128 33 #define EDID_LENGTH 128
39 #define DDC_ADDR 0x50 34 #define DDC_ADDR 0x50
40 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where Di 35 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
41 36
42 #define CEA_EXT 0x02 37 #define CEA_EXT 0x02
43 #define VTB_EXT 0x10 38 #define VTB_EXT 0x10
44 #define DI_EXT 0x40 39 #define DI_EXT 0x40
45 #define LS_EXT 0x50 40 #define LS_EXT 0x50
46 #define MI_EXT 0x60 41 #define MI_EXT 0x60
47 #define DISPLAYID_EXT 0x70 42 #define DISPLAYID_EXT 0x70
48 43
49 struct est_timings { 44 struct est_timings {
50 u8 t1; 45 u8 t1;
51 u8 t2; 46 u8 t2;
52 u8 mfg_rsvd; 47 u8 mfg_rsvd;
53 } __packed; !! 48 } __attribute__((packed));
54 49
55 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 50 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
56 #define EDID_TIMING_ASPECT_SHIFT 6 51 #define EDID_TIMING_ASPECT_SHIFT 6
57 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_ 52 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
58 53
59 /* need to add 60 */ 54 /* need to add 60 */
60 #define EDID_TIMING_VFREQ_SHIFT 0 55 #define EDID_TIMING_VFREQ_SHIFT 0
61 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID 56 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
62 57
63 struct std_timing { 58 struct std_timing {
64 u8 hsize; /* need to multiply by 8 the 59 u8 hsize; /* need to multiply by 8 then add 248 */
65 u8 vfreq_aspect; 60 u8 vfreq_aspect;
66 } __packed; !! 61 } __attribute__((packed));
67 62
68 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 63 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
69 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 64 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
70 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 65 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
71 #define DRM_EDID_PT_STEREO (1 << 5) 66 #define DRM_EDID_PT_STEREO (1 << 5)
72 #define DRM_EDID_PT_INTERLACED (1 << 7) 67 #define DRM_EDID_PT_INTERLACED (1 << 7)
73 68
74 /* If detailed data is pixel timing */ 69 /* If detailed data is pixel timing */
75 struct detailed_pixel_timing { 70 struct detailed_pixel_timing {
76 u8 hactive_lo; 71 u8 hactive_lo;
77 u8 hblank_lo; 72 u8 hblank_lo;
78 u8 hactive_hblank_hi; 73 u8 hactive_hblank_hi;
79 u8 vactive_lo; 74 u8 vactive_lo;
80 u8 vblank_lo; 75 u8 vblank_lo;
81 u8 vactive_vblank_hi; 76 u8 vactive_vblank_hi;
82 u8 hsync_offset_lo; 77 u8 hsync_offset_lo;
83 u8 hsync_pulse_width_lo; 78 u8 hsync_pulse_width_lo;
84 u8 vsync_offset_pulse_width_lo; 79 u8 vsync_offset_pulse_width_lo;
85 u8 hsync_vsync_offset_pulse_width_hi; 80 u8 hsync_vsync_offset_pulse_width_hi;
86 u8 width_mm_lo; 81 u8 width_mm_lo;
87 u8 height_mm_lo; 82 u8 height_mm_lo;
88 u8 width_height_mm_hi; 83 u8 width_height_mm_hi;
89 u8 hborder; 84 u8 hborder;
90 u8 vborder; 85 u8 vborder;
91 u8 misc; 86 u8 misc;
92 } __packed; !! 87 } __attribute__((packed));
93 88
94 /* If it's not pixel timing, it'll be one of t 89 /* If it's not pixel timing, it'll be one of the below */
95 struct detailed_data_string { 90 struct detailed_data_string {
96 u8 str[13]; 91 u8 str[13];
97 } __packed; !! 92 } __attribute__((packed));
98 93
99 #define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << !! 94 #define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00
100 #define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << !! 95 #define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01
101 #define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << !! 96 #define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02
102 #define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << !! 97 #define DRM_EDID_CVT_SUPPORT_FLAG 0x04
103 <<
104 #define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x <<
105 #define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x <<
106 #define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x <<
107 #define DRM_EDID_CVT_SUPPORT_FLAG 0x <<
108 <<
109 #define DRM_EDID_CVT_FLAGS_STANDARD_BLANKING ( <<
110 #define DRM_EDID_CVT_FLAGS_REDUCED_BLANKING ( <<
111 98
112 struct detailed_data_monitor_range { 99 struct detailed_data_monitor_range {
113 u8 min_vfreq; 100 u8 min_vfreq;
114 u8 max_vfreq; 101 u8 max_vfreq;
115 u8 min_hfreq_khz; 102 u8 min_hfreq_khz;
116 u8 max_hfreq_khz; 103 u8 max_hfreq_khz;
117 u8 pixel_clock_mhz; /* need to multipl 104 u8 pixel_clock_mhz; /* need to multiply by 10 */
118 u8 flags; 105 u8 flags;
119 union { 106 union {
120 struct { 107 struct {
121 u8 reserved; 108 u8 reserved;
122 u8 hfreq_start_khz; /* 109 u8 hfreq_start_khz; /* need to multiply by 2 */
123 u8 c; /* need to divid 110 u8 c; /* need to divide by 2 */
124 __le16 m; 111 __le16 m;
125 u8 k; 112 u8 k;
126 u8 j; /* need to divid 113 u8 j; /* need to divide by 2 */
127 } __packed gtf2; !! 114 } __attribute__((packed)) gtf2;
128 struct { 115 struct {
129 u8 version; 116 u8 version;
130 u8 data1; /* high 6 bi 117 u8 data1; /* high 6 bits: extra clock resolution */
131 u8 data2; /* plus low 118 u8 data2; /* plus low 2 of above: max hactive */
132 u8 supported_aspects; 119 u8 supported_aspects;
133 u8 flags; /* preferred 120 u8 flags; /* preferred aspect and blanking support */
134 u8 supported_scalings; 121 u8 supported_scalings;
135 u8 preferred_refresh; 122 u8 preferred_refresh;
136 } __packed cvt; !! 123 } __attribute__((packed)) cvt;
137 } __packed formula; !! 124 } formula;
138 } __packed; !! 125 } __attribute__((packed));
139 126
140 struct detailed_data_wpindex { 127 struct detailed_data_wpindex {
141 u8 white_yx_lo; /* Lower 2 bits each * 128 u8 white_yx_lo; /* Lower 2 bits each */
142 u8 white_x_hi; 129 u8 white_x_hi;
143 u8 white_y_hi; 130 u8 white_y_hi;
144 u8 gamma; /* need to divide by 100 the 131 u8 gamma; /* need to divide by 100 then add 1 */
145 } __packed; !! 132 } __attribute__((packed));
146 133
147 struct detailed_data_color_point { 134 struct detailed_data_color_point {
148 u8 windex1; 135 u8 windex1;
149 u8 wpindex1[3]; 136 u8 wpindex1[3];
150 u8 windex2; 137 u8 windex2;
151 u8 wpindex2[3]; 138 u8 wpindex2[3];
152 } __packed; !! 139 } __attribute__((packed));
153 140
154 struct cvt_timing { 141 struct cvt_timing {
155 u8 code[3]; 142 u8 code[3];
156 } __packed; !! 143 } __attribute__((packed));
157 144
158 struct detailed_non_pixel { 145 struct detailed_non_pixel {
159 u8 pad1; 146 u8 pad1;
160 u8 type; /* ff=serial, fe=string, fd=m 147 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
161 fb=color point data, fa=st 148 fb=color point data, fa=standard timing data,
162 f9=undefined, f8=mfg. rese 149 f9=undefined, f8=mfg. reserved */
163 u8 pad2; 150 u8 pad2;
164 union { 151 union {
165 struct detailed_data_string st 152 struct detailed_data_string str;
166 struct detailed_data_monitor_r 153 struct detailed_data_monitor_range range;
167 struct detailed_data_wpindex c 154 struct detailed_data_wpindex color;
168 struct std_timing timings[6]; 155 struct std_timing timings[6];
169 struct cvt_timing cvt[4]; 156 struct cvt_timing cvt[4];
170 } __packed data; !! 157 } data;
171 } __packed; !! 158 } __attribute__((packed));
172 159
173 #define EDID_DETAIL_EST_TIMINGS 0xf7 160 #define EDID_DETAIL_EST_TIMINGS 0xf7
174 #define EDID_DETAIL_CVT_3BYTE 0xf8 161 #define EDID_DETAIL_CVT_3BYTE 0xf8
175 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 162 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
176 #define EDID_DETAIL_STD_MODES 0xfa 163 #define EDID_DETAIL_STD_MODES 0xfa
177 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 164 #define EDID_DETAIL_MONITOR_CPDATA 0xfb
178 #define EDID_DETAIL_MONITOR_NAME 0xfc 165 #define EDID_DETAIL_MONITOR_NAME 0xfc
179 #define EDID_DETAIL_MONITOR_RANGE 0xfd 166 #define EDID_DETAIL_MONITOR_RANGE 0xfd
180 #define EDID_DETAIL_MONITOR_STRING 0xfe 167 #define EDID_DETAIL_MONITOR_STRING 0xfe
181 #define EDID_DETAIL_MONITOR_SERIAL 0xff 168 #define EDID_DETAIL_MONITOR_SERIAL 0xff
182 169
183 struct detailed_timing { 170 struct detailed_timing {
184 __le16 pixel_clock; /* need to multipl 171 __le16 pixel_clock; /* need to multiply by 10 KHz */
185 union { 172 union {
186 struct detailed_pixel_timing p 173 struct detailed_pixel_timing pixel_data;
187 struct detailed_non_pixel othe 174 struct detailed_non_pixel other_data;
188 } __packed data; !! 175 } data;
189 } __packed; !! 176 } __attribute__((packed));
190 177
191 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0 178 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
192 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1 179 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
193 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2 180 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
194 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3 181 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
195 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4 182 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
196 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5 183 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
197 #define DRM_EDID_INPUT_DIGITAL (1 << 7 184 #define DRM_EDID_INPUT_DIGITAL (1 << 7)
198 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4 185 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */
199 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4 186 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */
200 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4 187 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */
201 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4 188 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */
202 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4 189 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */
203 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4 190 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */
204 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4 191 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */
205 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4 192 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */
206 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4 193 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */
207 #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0 194 #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */
208 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0 195 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */
209 #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0 196 #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */
210 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0 197 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */
211 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0 198 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */
212 #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0 199 #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */
213 #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0 200 #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */
214 #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0 201 #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */
215 202
216 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 < !! 203 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
217 #define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 < <<
218 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 < 204 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
219 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 < 205 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
220 /* If analog */ 206 /* If analog */
221 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 < 207 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
222 /* If digital */ 208 /* If digital */
223 #define DRM_EDID_FEATURE_COLOR_MASK (3 < 209 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
224 #define DRM_EDID_FEATURE_RGB (0 < 210 #define DRM_EDID_FEATURE_RGB (0 << 3)
225 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 < 211 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
226 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 < 212 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
227 #define DRM_EDID_FEATURE_RGB_YCRCB (3 < 213 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
228 214
229 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 < 215 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
230 #define DRM_EDID_FEATURE_PM_SUSPEND (1 < 216 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
231 #define DRM_EDID_FEATURE_PM_STANDBY (1 < 217 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
232 218
233 #define DRM_EDID_HDMI_DC_48 (1 < 219 #define DRM_EDID_HDMI_DC_48 (1 << 6)
234 #define DRM_EDID_HDMI_DC_36 (1 < 220 #define DRM_EDID_HDMI_DC_36 (1 << 5)
235 #define DRM_EDID_HDMI_DC_30 (1 < 221 #define DRM_EDID_HDMI_DC_30 (1 << 4)
236 #define DRM_EDID_HDMI_DC_Y444 (1 < 222 #define DRM_EDID_HDMI_DC_Y444 (1 << 3)
237 223
238 /* YCBCR 420 deep color modes */ 224 /* YCBCR 420 deep color modes */
239 #define DRM_EDID_YCBCR420_DC_48 (1 < 225 #define DRM_EDID_YCBCR420_DC_48 (1 << 2)
240 #define DRM_EDID_YCBCR420_DC_36 (1 < 226 #define DRM_EDID_YCBCR420_DC_36 (1 << 1)
241 #define DRM_EDID_YCBCR420_DC_30 (1 < 227 #define DRM_EDID_YCBCR420_DC_30 (1 << 0)
242 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YC 228 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
243 DRM_EDID_Y 229 DRM_EDID_YCBCR420_DC_36 | \
244 DRM_EDID_Y 230 DRM_EDID_YCBCR420_DC_30)
245 231
246 /* HDMI 2.1 additional fields */ 232 /* HDMI 2.1 additional fields */
247 #define DRM_EDID_MAX_FRL_RATE_MASK 233 #define DRM_EDID_MAX_FRL_RATE_MASK 0xf0
248 #define DRM_EDID_FAPA_START_LOCATION 234 #define DRM_EDID_FAPA_START_LOCATION (1 << 0)
249 #define DRM_EDID_ALLM 235 #define DRM_EDID_ALLM (1 << 1)
250 #define DRM_EDID_FVA 236 #define DRM_EDID_FVA (1 << 2)
251 237
252 /* Deep Color specific */ 238 /* Deep Color specific */
253 #define DRM_EDID_DC_30BIT_420 239 #define DRM_EDID_DC_30BIT_420 (1 << 0)
254 #define DRM_EDID_DC_36BIT_420 240 #define DRM_EDID_DC_36BIT_420 (1 << 1)
255 #define DRM_EDID_DC_48BIT_420 241 #define DRM_EDID_DC_48BIT_420 (1 << 2)
256 242
257 /* VRR specific */ 243 /* VRR specific */
258 #define DRM_EDID_CNMVRR 244 #define DRM_EDID_CNMVRR (1 << 3)
259 #define DRM_EDID_CINEMA_VRR 245 #define DRM_EDID_CINEMA_VRR (1 << 4)
260 #define DRM_EDID_MDELTA 246 #define DRM_EDID_MDELTA (1 << 5)
261 #define DRM_EDID_VRR_MAX_UPPER_MASK 247 #define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0
262 #define DRM_EDID_VRR_MAX_LOWER_MASK 248 #define DRM_EDID_VRR_MAX_LOWER_MASK 0xff
263 #define DRM_EDID_VRR_MIN_MASK 249 #define DRM_EDID_VRR_MIN_MASK 0x3f
264 250
265 /* DSC specific */ 251 /* DSC specific */
266 #define DRM_EDID_DSC_10BPC 252 #define DRM_EDID_DSC_10BPC (1 << 0)
267 #define DRM_EDID_DSC_12BPC 253 #define DRM_EDID_DSC_12BPC (1 << 1)
268 #define DRM_EDID_DSC_16BPC 254 #define DRM_EDID_DSC_16BPC (1 << 2)
269 #define DRM_EDID_DSC_ALL_BPP 255 #define DRM_EDID_DSC_ALL_BPP (1 << 3)
270 #define DRM_EDID_DSC_NATIVE_420 256 #define DRM_EDID_DSC_NATIVE_420 (1 << 6)
271 #define DRM_EDID_DSC_1P2 257 #define DRM_EDID_DSC_1P2 (1 << 7)
272 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK 258 #define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0
273 #define DRM_EDID_DSC_MAX_SLICES 259 #define DRM_EDID_DSC_MAX_SLICES 0xf
274 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 260 #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f
275 261
276 struct drm_edid_product_id { !! 262 /* ELD Header Block */
277 __be16 manufacturer_name; !! 263 #define DRM_ELD_HEADER_BLOCK_SIZE 4
278 __le16 product_code; !! 264
279 __le32 serial_number; !! 265 #define DRM_ELD_VER 0
280 u8 week_of_manufacture; !! 266 # define DRM_ELD_VER_SHIFT 3
281 u8 year_of_manufacture; !! 267 # define DRM_ELD_VER_MASK (0x1f << 3)
282 } __packed; !! 268 # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */
>> 269 # define DRM_ELD_VER_CANNED (0x1f << 3)
>> 270
>> 271 #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */
>> 272
>> 273 /* ELD Baseline Block for ELD_Ver == 2 */
>> 274 #define DRM_ELD_CEA_EDID_VER_MNL 4
>> 275 # define DRM_ELD_CEA_EDID_VER_SHIFT 5
>> 276 # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5)
>> 277 # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5)
>> 278 # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5)
>> 279 # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5)
>> 280 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5)
>> 281 # define DRM_ELD_MNL_SHIFT 0
>> 282 # define DRM_ELD_MNL_MASK (0x1f << 0)
>> 283
>> 284 #define DRM_ELD_SAD_COUNT_CONN_TYPE 5
>> 285 # define DRM_ELD_SAD_COUNT_SHIFT 4
>> 286 # define DRM_ELD_SAD_COUNT_MASK (0xf << 4)
>> 287 # define DRM_ELD_CONN_TYPE_SHIFT 2
>> 288 # define DRM_ELD_CONN_TYPE_MASK (3 << 2)
>> 289 # define DRM_ELD_CONN_TYPE_HDMI (0 << 2)
>> 290 # define DRM_ELD_CONN_TYPE_DP (1 << 2)
>> 291 # define DRM_ELD_SUPPORTS_AI (1 << 1)
>> 292 # define DRM_ELD_SUPPORTS_HDCP (1 << 0)
>> 293
>> 294 #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */
>> 295 # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */
>> 296
>> 297 #define DRM_ELD_SPEAKER 7
>> 298 # define DRM_ELD_SPEAKER_MASK 0x7f
>> 299 # define DRM_ELD_SPEAKER_RLRC (1 << 6)
>> 300 # define DRM_ELD_SPEAKER_FLRC (1 << 5)
>> 301 # define DRM_ELD_SPEAKER_RC (1 << 4)
>> 302 # define DRM_ELD_SPEAKER_RLR (1 << 3)
>> 303 # define DRM_ELD_SPEAKER_FC (1 << 2)
>> 304 # define DRM_ELD_SPEAKER_LFE (1 << 1)
>> 305 # define DRM_ELD_SPEAKER_FLR (1 << 0)
>> 306
>> 307 #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */
>> 308 # define DRM_ELD_PORT_ID_LEN 8
>> 309
>> 310 #define DRM_ELD_MANUFACTURER_NAME0 16
>> 311 #define DRM_ELD_MANUFACTURER_NAME1 17
>> 312
>> 313 #define DRM_ELD_PRODUCT_CODE0 18
>> 314 #define DRM_ELD_PRODUCT_CODE1 19
>> 315
>> 316 #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */
>> 317
>> 318 #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad))
283 319
284 struct edid { 320 struct edid {
285 u8 header[8]; 321 u8 header[8];
286 /* Vendor & product info */ 322 /* Vendor & product info */
287 union { !! 323 u8 mfg_id[2];
288 struct drm_edid_product_id pro !! 324 u8 prod_code[2];
289 struct { !! 325 u32 serial; /* FIXME: byte order */
290 u8 mfg_id[2]; !! 326 u8 mfg_week;
291 u8 prod_code[2]; !! 327 u8 mfg_year;
292 u32 serial; /* FIXME: <<
293 u8 mfg_week; <<
294 u8 mfg_year; <<
295 } __packed; <<
296 } __packed; <<
297 /* EDID version */ 328 /* EDID version */
298 u8 version; 329 u8 version;
299 u8 revision; 330 u8 revision;
300 /* Display info: */ 331 /* Display info: */
301 u8 input; 332 u8 input;
302 u8 width_cm; 333 u8 width_cm;
303 u8 height_cm; 334 u8 height_cm;
304 u8 gamma; 335 u8 gamma;
305 u8 features; 336 u8 features;
306 /* Color characteristics */ 337 /* Color characteristics */
307 u8 red_green_lo; 338 u8 red_green_lo;
308 u8 blue_white_lo; !! 339 u8 black_white_lo;
309 u8 red_x; 340 u8 red_x;
310 u8 red_y; 341 u8 red_y;
311 u8 green_x; 342 u8 green_x;
312 u8 green_y; 343 u8 green_y;
313 u8 blue_x; 344 u8 blue_x;
314 u8 blue_y; 345 u8 blue_y;
315 u8 white_x; 346 u8 white_x;
316 u8 white_y; 347 u8 white_y;
317 /* Est. timings and mfg rsvd timings*/ 348 /* Est. timings and mfg rsvd timings*/
318 struct est_timings established_timings 349 struct est_timings established_timings;
319 /* Standard timings 1-8*/ 350 /* Standard timings 1-8*/
320 struct std_timing standard_timings[8]; 351 struct std_timing standard_timings[8];
321 /* Detailing timings 1-4 */ 352 /* Detailing timings 1-4 */
322 struct detailed_timing detailed_timing 353 struct detailed_timing detailed_timings[4];
323 /* Number of 128 byte ext. blocks */ 354 /* Number of 128 byte ext. blocks */
324 u8 extensions; 355 u8 extensions;
325 /* Checksum */ 356 /* Checksum */
326 u8 checksum; 357 u8 checksum;
327 } __packed; !! 358 } __attribute__((packed));
328 <<
329 /* EDID matching */ <<
330 struct drm_edid_ident { <<
331 /* ID encoded by drm_edid_encode_panel <<
332 u32 panel_id; <<
333 const char *name; <<
334 }; <<
335 359
336 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] 360 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
337 361
338 /* Short Audio Descriptor */ 362 /* Short Audio Descriptor */
339 struct cea_sad { 363 struct cea_sad {
340 u8 format; 364 u8 format;
341 u8 channels; /* max number of channels 365 u8 channels; /* max number of channels - 1 */
342 u8 freq; 366 u8 freq;
343 u8 byte2; /* meaning depends on format 367 u8 byte2; /* meaning depends on format */
344 }; 368 };
345 369
346 int drm_edid_to_sad(const struct edid *edid, s !! 370 struct drm_encoder;
347 int drm_edid_to_speaker_allocation(const struc !! 371 struct drm_connector;
>> 372 struct drm_connector_state;
>> 373 struct drm_display_mode;
>> 374
>> 375 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
>> 376 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
348 int drm_av_sync_delay(struct drm_connector *co 377 int drm_av_sync_delay(struct drm_connector *connector,
349 const struct drm_display 378 const struct drm_display_mode *mode);
350 379
>> 380 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
>> 381 struct edid *drm_load_edid_firmware(struct drm_connector *connector);
>> 382 int __drm_set_edid_firmware_path(const char *path);
>> 383 int __drm_get_edid_firmware_path(char *buf, size_t bufsize);
>> 384 #else
>> 385 static inline struct edid *
>> 386 drm_load_edid_firmware(struct drm_connector *connector)
>> 387 {
>> 388 return ERR_PTR(-ENOENT);
>> 389 }
>> 390 #endif
>> 391
>> 392 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2);
>> 393
351 int 394 int
352 drm_hdmi_avi_infoframe_from_display_mode(struc 395 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
353 const 396 const struct drm_connector *connector,
354 const 397 const struct drm_display_mode *mode);
355 int 398 int
356 drm_hdmi_vendor_infoframe_from_display_mode(st 399 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
357 co 400 const struct drm_connector *connector,
358 co 401 const struct drm_display_mode *mode);
359 402
360 void 403 void
>> 404 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
>> 405 const struct drm_connector_state *conn_state);
>> 406
>> 407 void
>> 408 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
>> 409 const struct drm_connector_state *conn_state);
>> 410
>> 411 void
361 drm_hdmi_avi_infoframe_quant_range(struct hdmi 412 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
362 const struc 413 const struct drm_connector *connector,
363 const struc 414 const struct drm_display_mode *mode,
364 enum hdmi_q 415 enum hdmi_quantization_range rgb_quant_range);
365 416
>> 417 int
>> 418 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
>> 419 const struct drm_connector_state *conn_state);
>> 420
366 /** 421 /**
367 * drm_edid_decode_mfg_id - Decode the manufac !! 422 * drm_eld_mnl - Get ELD monitor name length in bytes.
368 * @mfg_id: The manufacturer ID !! 423 * @eld: pointer to an eld memory structure with mnl set
369 * @vend: A 4-byte buffer to store the 3-lette <<
370 * termination <<
371 */ 424 */
372 static inline const char *drm_edid_decode_mfg_ !! 425 static inline int drm_eld_mnl(const uint8_t *eld)
373 { 426 {
374 vend[0] = '@' + ((mfg_id >> 10) & 0x1f !! 427 return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
375 vend[1] = '@' + ((mfg_id >> 5) & 0x1f) !! 428 }
376 vend[2] = '@' + ((mfg_id >> 0) & 0x1f) <<
377 vend[3] = '\0'; <<
378 429
379 return vend; !! 430 /**
>> 431 * drm_eld_sad - Get ELD SAD structures.
>> 432 * @eld: pointer to an eld memory structure with sad_count set
>> 433 */
>> 434 static inline const uint8_t *drm_eld_sad(const uint8_t *eld)
>> 435 {
>> 436 unsigned int ver, mnl;
>> 437
>> 438 ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT;
>> 439 if (ver != 2 && ver != 31)
>> 440 return NULL;
>> 441
>> 442 mnl = drm_eld_mnl(eld);
>> 443 if (mnl > 16)
>> 444 return NULL;
>> 445
>> 446 return eld + DRM_ELD_CEA_SAD(mnl, 0);
>> 447 }
>> 448
>> 449 /**
>> 450 * drm_eld_sad_count - Get ELD SAD count.
>> 451 * @eld: pointer to an eld memory structure with sad_count set
>> 452 */
>> 453 static inline int drm_eld_sad_count(const uint8_t *eld)
>> 454 {
>> 455 return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
>> 456 DRM_ELD_SAD_COUNT_SHIFT;
>> 457 }
>> 458
>> 459 /**
>> 460 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
>> 461 * @eld: pointer to an eld memory structure with mnl and sad_count set
>> 462 *
>> 463 * This is a helper for determining the payload size of the baseline block, in
>> 464 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
>> 465 */
>> 466 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
>> 467 {
>> 468 return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
>> 469 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
380 } 470 }
381 471
382 /** 472 /**
383 * drm_edid_encode_panel_id - Encode an ID for !! 473 * drm_eld_size - Get ELD size in bytes
384 * @vend_chr_0: First character of the vendor !! 474 * @eld: pointer to a complete eld memory structure
385 * @vend_chr_1: Second character of the vendor <<
386 * @vend_chr_2: Third character of the vendor <<
387 * @product_id: The 16-bit product ID. <<
388 * 475 *
389 * This is a macro so that it can be calculate !! 476 * The returned value does not include the vendor block. It's vendor specific,
390 * as an initializer. !! 477 * and comprises of the remaining bytes in the ELD memory buffer after
>> 478 * drm_eld_size() bytes of header and baseline block.
391 * 479 *
392 * For instance: !! 480 * The returned value is guaranteed to be a multiple of 4.
393 * drm_edid_encode_panel_id('B', 'O', 'E', 0 !! 481 */
>> 482 static inline int drm_eld_size(const uint8_t *eld)
>> 483 {
>> 484 return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
>> 485 }
>> 486
>> 487 /**
>> 488 * drm_eld_get_spk_alloc - Get speaker allocation
>> 489 * @eld: pointer to an ELD memory structure
394 * 490 *
395 * Return: a 32-bit ID per panel. !! 491 * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER
>> 492 * field definitions to identify speakers.
396 */ 493 */
397 #define drm_edid_encode_panel_id(vend_chr_0, v !! 494 static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld)
398 ((((u32)(vend_chr_0) - '@') & 0x1f) << !! 495 {
399 (((u32)(vend_chr_1) - '@') & 0x1f) << !! 496 return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK;
400 (((u32)(vend_chr_2) - '@') & 0x1f) << !! 497 }
401 ((product_id) & 0xffff)) <<
402 498
403 /** 499 /**
404 * drm_edid_decode_panel_id - Decode a panel I !! 500 * drm_eld_get_conn_type - Get device type hdmi/dp connected
405 * @panel_id: The panel ID to decode. !! 501 * @eld: pointer to an ELD memory structure
406 * @vend: A 4-byte buffer to store the 3-lette <<
407 * termination <<
408 * @product_id: The product ID will be returne <<
409 * 502 *
410 * For instance, after: !! 503 * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to
411 * drm_edid_decode_panel_id(0x09e52d08, vend !! 504 * identify the display type connected.
412 * These will be true: <<
413 * vend[0] = 'B' <<
414 * vend[1] = 'O' <<
415 * vend[2] = 'E' <<
416 * vend[3] = '\0' <<
417 * product_id = 0x2d08 <<
418 */ 505 */
419 static inline void drm_edid_decode_panel_id(u3 !! 506 static inline u8 drm_eld_get_conn_type(const uint8_t *eld)
420 { 507 {
421 *product_id = (u16)(panel_id & 0xffff) !! 508 return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK;
422 drm_edid_decode_mfg_id(panel_id >> 16, <<
423 } 509 }
424 510
425 bool drm_probe_ddc(struct i2c_adapter *adapter 511 bool drm_probe_ddc(struct i2c_adapter *adapter);
>> 512 struct edid *drm_do_get_edid(struct drm_connector *connector,
>> 513 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
>> 514 size_t len),
>> 515 void *data);
426 struct edid *drm_get_edid(struct drm_connector 516 struct edid *drm_get_edid(struct drm_connector *connector,
427 struct i2c_adapter * 517 struct i2c_adapter *adapter);
428 struct edid *drm_get_edid_switcheroo(struct dr 518 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
429 struct i2 519 struct i2c_adapter *adapter);
430 struct edid *drm_edid_duplicate(const struct e 520 struct edid *drm_edid_duplicate(const struct edid *edid);
431 int drm_add_edid_modes(struct drm_connector *c 521 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
432 int drm_edid_override_connector_update(struct !! 522 int drm_add_override_edid_modes(struct drm_connector *connector);
433 523
434 u8 drm_match_cea_mode(const struct drm_display 524 u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
435 bool drm_detect_hdmi_monitor(const struct edid !! 525 bool drm_detect_hdmi_monitor(struct edid *edid);
436 bool drm_detect_monitor_audio(const struct edi !! 526 bool drm_detect_monitor_audio(struct edid *edid);
437 enum hdmi_quantization_range 527 enum hdmi_quantization_range
438 drm_default_rgb_quant_range(const struct drm_d 528 drm_default_rgb_quant_range(const struct drm_display_mode *mode);
439 int drm_add_modes_noedid(struct drm_connector 529 int drm_add_modes_noedid(struct drm_connector *connector,
440 int hdisplay, int vdi 530 int hdisplay, int vdisplay);
>> 531 void drm_set_preferred_mode(struct drm_connector *connector,
>> 532 int hpref, int vpref);
441 533
442 int drm_edid_header_is_valid(const void *edid) !! 534 int drm_edid_header_is_valid(const u8 *raw_edid);
>> 535 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
>> 536 bool *edid_corrupt);
443 bool drm_edid_is_valid(struct edid *edid); 537 bool drm_edid_is_valid(struct edid *edid);
444 void drm_edid_get_monitor_name(const struct ed !! 538 void drm_edid_get_monitor_name(struct edid *edid, char *name,
445 int buflen); 539 int buflen);
446 struct drm_display_mode *drm_mode_find_dmt(str 540 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
447 int 541 int hsize, int vsize, int fresh,
448 boo 542 bool rb);
449 struct drm_display_mode * 543 struct drm_display_mode *
450 drm_display_mode_from_cea_vic(struct drm_devic 544 drm_display_mode_from_cea_vic(struct drm_device *dev,
451 u8 video_code); 545 u8 video_code);
>> 546 const u8 *drm_find_edid_extension(const struct edid *edid,
>> 547 int ext_id, int *ext_index);
452 548
453 /* Interface based on struct drm_edid */ <<
454 const struct drm_edid *drm_edid_alloc(const vo <<
455 const struct drm_edid *drm_edid_dup(const stru <<
456 void drm_edid_free(const struct drm_edid *drm_ <<
457 bool drm_edid_valid(const struct drm_edid *drm <<
458 const struct edid *drm_edid_raw(const struct d <<
459 const struct drm_edid *drm_edid_read(struct dr <<
460 const struct drm_edid *drm_edid_read_ddc(struc <<
461 struc <<
462 const struct drm_edid *drm_edid_read_custom(st <<
463 in <<
464 vo <<
465 const struct drm_edid *drm_edid_read_base_bloc <<
466 const struct drm_edid *drm_edid_read_switchero <<
467 <<
468 int drm_edid_connector_update(struct drm_conne <<
469 const struct drm <<
470 int drm_edid_connector_add_modes(struct drm_co <<
471 bool drm_edid_is_digital(const struct drm_edid <<
472 void drm_edid_get_product_id(const struct drm_ <<
473 struct drm_edid_p <<
474 void drm_edid_print_product_id(struct drm_prin <<
475 const struct dr <<
476 u32 drm_edid_get_panel_id(const struct drm_edi <<
477 bool drm_edid_match(const struct drm_edid *drm <<
478 const struct drm_edid_iden <<
479 549
480 #endif /* __DRM_EDID_H__ */ 550 #endif /* __DRM_EDID_H__ */
481 551
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