1 /* 1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc. 2 * Copyright 2019 Advanced Micro Devices, Inc.
3 * 3 *
4 * Permission is hereby granted, free of charg 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated docume 5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction 6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, pub 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to 8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to 9 * Software is furnished to do so, subject to the following conditions:
10 * 10 *
11 * The above copyright notice and this permiss 11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the S 12 * all copies or substantial portions of the Software.
13 * 13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT W 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE W 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINF 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIA 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CO 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE. 20 * OTHER DEALINGS IN THE SOFTWARE.
21 * 21 *
22 */ 22 */
23 #include <linux/semaphore.h> 23 #include <linux/semaphore.h>
24 #include <linux/atomic.h> 24 #include <linux/atomic.h>
25 25
26 /* 26 /*
27 * Reusable 2 PHASE task barrier (rendez-vous 27 * Reusable 2 PHASE task barrier (rendez-vous point) implementation for N tasks.
28 * Based on the Little book of semaphores - ht 28 * Based on the Little book of semaphores - https://greenteapress.com/wp/semaphores/
29 */ 29 */
30 30
31 31
32 32
33 #ifndef DRM_TASK_BARRIER_H_ 33 #ifndef DRM_TASK_BARRIER_H_
34 #define DRM_TASK_BARRIER_H_ 34 #define DRM_TASK_BARRIER_H_
35 35
36 /* 36 /*
37 * Represents an instance of a task barrier. 37 * Represents an instance of a task barrier.
38 */ 38 */
39 struct task_barrier { 39 struct task_barrier {
40 unsigned int n; 40 unsigned int n;
41 atomic_t count; 41 atomic_t count;
42 struct semaphore enter_turnstile; 42 struct semaphore enter_turnstile;
43 struct semaphore exit_turnstile; 43 struct semaphore exit_turnstile;
44 }; 44 };
45 45
46 static inline void task_barrier_signal_turnsti 46 static inline void task_barrier_signal_turnstile(struct semaphore *turnstile,
47 47 unsigned int n)
48 { 48 {
49 int i; 49 int i;
50 50
51 for (i = 0 ; i < n; i++) 51 for (i = 0 ; i < n; i++)
52 up(turnstile); 52 up(turnstile);
53 } 53 }
54 54
55 static inline void task_barrier_init(struct ta 55 static inline void task_barrier_init(struct task_barrier *tb)
56 { 56 {
57 tb->n = 0; 57 tb->n = 0;
58 atomic_set(&tb->count, 0); 58 atomic_set(&tb->count, 0);
59 sema_init(&tb->enter_turnstile, 0); 59 sema_init(&tb->enter_turnstile, 0);
60 sema_init(&tb->exit_turnstile, 0); 60 sema_init(&tb->exit_turnstile, 0);
61 } 61 }
62 62
63 static inline void task_barrier_add_task(struc 63 static inline void task_barrier_add_task(struct task_barrier *tb)
64 { 64 {
65 tb->n++; 65 tb->n++;
66 } 66 }
67 67
68 static inline void task_barrier_rem_task(struc 68 static inline void task_barrier_rem_task(struct task_barrier *tb)
69 { 69 {
70 tb->n--; 70 tb->n--;
71 } 71 }
72 72
73 /* 73 /*
74 * Lines up all the threads BEFORE the critica 74 * Lines up all the threads BEFORE the critical point.
75 * 75 *
76 * When all thread passed this code the entry 76 * When all thread passed this code the entry barrier is back to locked state.
77 */ 77 */
78 static inline void task_barrier_enter(struct t 78 static inline void task_barrier_enter(struct task_barrier *tb)
79 { 79 {
80 if (atomic_inc_return(&tb->count) == t 80 if (atomic_inc_return(&tb->count) == tb->n)
81 task_barrier_signal_turnstile( 81 task_barrier_signal_turnstile(&tb->enter_turnstile, tb->n);
82 82
83 down(&tb->enter_turnstile); 83 down(&tb->enter_turnstile);
84 } 84 }
85 85
86 /* 86 /*
87 * Lines up all the threads AFTER the critical 87 * Lines up all the threads AFTER the critical point.
88 * 88 *
89 * This function is used to avoid any one thre 89 * This function is used to avoid any one thread running ahead if the barrier is
90 * used repeatedly . 90 * used repeatedly .
91 */ 91 */
92 static inline void task_barrier_exit(struct ta 92 static inline void task_barrier_exit(struct task_barrier *tb)
93 { 93 {
94 if (atomic_dec_return(&tb->count) == 0 94 if (atomic_dec_return(&tb->count) == 0)
95 task_barrier_signal_turnstile( 95 task_barrier_signal_turnstile(&tb->exit_turnstile, tb->n);
96 96
97 down(&tb->exit_turnstile); 97 down(&tb->exit_turnstile);
98 } 98 }
99 99
100 /* Convinieince function when nothing to be do 100 /* Convinieince function when nothing to be done in between entry and exit */
101 static inline void task_barrier_full(struct ta 101 static inline void task_barrier_full(struct task_barrier *tb)
102 { 102 {
103 task_barrier_enter(tb); 103 task_barrier_enter(tb);
104 task_barrier_exit(tb); 104 task_barrier_exit(tb);
105 } 105 }
106 106
107 #endif 107 #endif
108 108
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