1 /* SPDX-License-Identifier: GPL-2.0 1 /* SPDX-License-Identifier: GPL-2.0 2 * 2 * 3 * Device Tree binding constants for Actions S 3 * Device Tree binding constants for Actions Semi S700 Clock Management Unit 4 * 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 7 * 8 * Author: Pathiban Nallathambi <pn@denx.de> 8 * Author: Pathiban Nallathambi <pn@denx.de> 9 * Author: Saravanan Sekar <sravanhome@gmail.c 9 * Author: Saravanan Sekar <sravanhome@gmail.com> 10 */ 10 */ 11 11 12 #ifndef __DT_BINDINGS_CLOCK_S700_H 12 #ifndef __DT_BINDINGS_CLOCK_S700_H 13 #define __DT_BINDINGS_CLOCK_S700_H 13 #define __DT_BINDINGS_CLOCK_S700_H 14 14 15 #define CLK_NONE 0 15 #define CLK_NONE 0 16 16 17 /* pll clocks */ 17 /* pll clocks */ 18 #define CLK_CORE_PLL 1 18 #define CLK_CORE_PLL 1 19 #define CLK_DEV_PLL 2 19 #define CLK_DEV_PLL 2 20 #define CLK_DDR_PLL 3 20 #define CLK_DDR_PLL 3 21 #define CLK_NAND_PLL 4 21 #define CLK_NAND_PLL 4 22 #define CLK_DISPLAY_PLL 5 22 #define CLK_DISPLAY_PLL 5 23 #define CLK_TVOUT_PLL 6 23 #define CLK_TVOUT_PLL 6 24 #define CLK_CVBS_PLL 7 24 #define CLK_CVBS_PLL 7 25 #define CLK_AUDIO_PLL 8 25 #define CLK_AUDIO_PLL 8 26 #define CLK_ETHERNET_PLL 9 26 #define CLK_ETHERNET_PLL 9 27 27 28 /* system clock */ 28 /* system clock */ 29 #define CLK_CPU 10 29 #define CLK_CPU 10 30 #define CLK_DEV 11 30 #define CLK_DEV 11 31 #define CLK_AHB 12 31 #define CLK_AHB 12 32 #define CLK_APB 13 32 #define CLK_APB 13 33 #define CLK_DMAC 14 33 #define CLK_DMAC 14 34 #define CLK_NOC0_CLK_MUX 15 34 #define CLK_NOC0_CLK_MUX 15 35 #define CLK_NOC1_CLK_MUX 16 35 #define CLK_NOC1_CLK_MUX 16 36 #define CLK_HP_CLK_MUX 17 36 #define CLK_HP_CLK_MUX 17 37 #define CLK_HP_CLK_DIV 18 37 #define CLK_HP_CLK_DIV 18 38 #define CLK_NOC1_CLK_DIV 19 38 #define CLK_NOC1_CLK_DIV 19 39 #define CLK_NOC0 20 39 #define CLK_NOC0 20 40 #define CLK_NOC1 21 40 #define CLK_NOC1 21 41 #define CLK_SENOR_SRC 22 41 #define CLK_SENOR_SRC 22 42 42 43 /* peripheral device clock */ 43 /* peripheral device clock */ 44 #define CLK_GPIO 23 44 #define CLK_GPIO 23 45 #define CLK_TIMER 24 45 #define CLK_TIMER 24 46 #define CLK_DSI 25 46 #define CLK_DSI 25 47 #define CLK_CSI 26 47 #define CLK_CSI 26 48 #define CLK_SI 27 48 #define CLK_SI 27 49 #define CLK_DE 28 49 #define CLK_DE 28 50 #define CLK_HDE 29 50 #define CLK_HDE 29 51 #define CLK_VDE 30 51 #define CLK_VDE 30 52 #define CLK_VCE 31 52 #define CLK_VCE 31 53 #define CLK_NAND 32 53 #define CLK_NAND 32 54 #define CLK_SD0 33 54 #define CLK_SD0 33 55 #define CLK_SD1 34 55 #define CLK_SD1 34 56 #define CLK_SD2 35 56 #define CLK_SD2 35 57 57 58 #define CLK_UART0 36 58 #define CLK_UART0 36 59 #define CLK_UART1 37 59 #define CLK_UART1 37 60 #define CLK_UART2 38 60 #define CLK_UART2 38 61 #define CLK_UART3 39 61 #define CLK_UART3 39 62 #define CLK_UART4 40 62 #define CLK_UART4 40 63 #define CLK_UART5 41 63 #define CLK_UART5 41 64 #define CLK_UART6 42 64 #define CLK_UART6 42 65 65 66 #define CLK_PWM0 43 66 #define CLK_PWM0 43 67 #define CLK_PWM1 44 67 #define CLK_PWM1 44 68 #define CLK_PWM2 45 68 #define CLK_PWM2 45 69 #define CLK_PWM3 46 69 #define CLK_PWM3 46 70 #define CLK_PWM4 47 70 #define CLK_PWM4 47 71 #define CLK_PWM5 48 71 #define CLK_PWM5 48 72 #define CLK_GPU3D 49 72 #define CLK_GPU3D 49 73 73 74 #define CLK_I2C0 50 74 #define CLK_I2C0 50 75 #define CLK_I2C1 51 75 #define CLK_I2C1 51 76 #define CLK_I2C2 52 76 #define CLK_I2C2 52 77 #define CLK_I2C3 53 77 #define CLK_I2C3 53 78 78 79 #define CLK_SPI0 54 79 #define CLK_SPI0 54 80 #define CLK_SPI1 55 80 #define CLK_SPI1 55 81 #define CLK_SPI2 56 81 #define CLK_SPI2 56 82 #define CLK_SPI3 57 82 #define CLK_SPI3 57 83 83 84 #define CLK_USB3_480MPLL0 58 84 #define CLK_USB3_480MPLL0 58 85 #define CLK_USB3_480MPHY0 59 85 #define CLK_USB3_480MPHY0 59 86 #define CLK_USB3_5GPHY 60 86 #define CLK_USB3_5GPHY 60 87 #define CLK_USB3_CCE 61 87 #define CLK_USB3_CCE 61 88 #define CLK_USB3_MAC 62 88 #define CLK_USB3_MAC 62 89 89 90 #define CLK_LCD 63 90 #define CLK_LCD 63 91 #define CLK_HDMI_AUDIO 64 91 #define CLK_HDMI_AUDIO 64 92 #define CLK_I2SRX 65 92 #define CLK_I2SRX 65 93 #define CLK_I2STX 66 93 #define CLK_I2STX 66 94 94 95 #define CLK_SENSOR0 67 95 #define CLK_SENSOR0 67 96 #define CLK_SENSOR1 68 96 #define CLK_SENSOR1 68 97 97 98 #define CLK_HDMI_DEV 69 98 #define CLK_HDMI_DEV 69 99 99 100 #define CLK_ETHERNET 70 100 #define CLK_ETHERNET 70 101 #define CLK_RMII_REF 71 101 #define CLK_RMII_REF 71 102 102 103 #define CLK_USB2H0_PLLEN 72 103 #define CLK_USB2H0_PLLEN 72 104 #define CLK_USB2H0_PHY 73 104 #define CLK_USB2H0_PHY 73 105 #define CLK_USB2H0_CCE 74 105 #define CLK_USB2H0_CCE 74 106 #define CLK_USB2H1_PLLEN 75 106 #define CLK_USB2H1_PLLEN 75 107 #define CLK_USB2H1_PHY 76 107 #define CLK_USB2H1_PHY 76 108 #define CLK_USB2H1_CCE 77 108 #define CLK_USB2H1_CCE 77 109 109 110 #define CLK_TVOUT 78 110 #define CLK_TVOUT 78 111 111 112 #define CLK_THERMAL_SENSOR 79 112 #define CLK_THERMAL_SENSOR 79 113 113 114 #define CLK_IRC_SWITCH 80 114 #define CLK_IRC_SWITCH 80 115 #define CLK_PCM1 81 115 #define CLK_PCM1 81 116 #define CLK_NR_CLKS (CLK_P 116 #define CLK_NR_CLKS (CLK_PCM1 + 1) 117 117 118 #endif /* __DT_BINDINGS_CLOCK_S700_H */ 118 #endif /* __DT_BINDINGS_CLOCK_S700_H */ 119 119
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