1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 2 /* 3 * Copyright (C) 2019, Intel Corporation 3 * Copyright (C) 2019, Intel Corporation 4 */ 4 */ 5 5 6 #ifndef __AGILEX_CLOCK_H 6 #ifndef __AGILEX_CLOCK_H 7 #define __AGILEX_CLOCK_H 7 #define __AGILEX_CLOCK_H 8 8 9 /* fixed rate clocks */ 9 /* fixed rate clocks */ 10 #define AGILEX_OSC1 0 10 #define AGILEX_OSC1 0 11 #define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 11 #define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 12 #define AGILEX_CB_INTOSC_LS_CLK 2 12 #define AGILEX_CB_INTOSC_LS_CLK 2 13 #define AGILEX_L4_SYS_FREE_CLK 3 13 #define AGILEX_L4_SYS_FREE_CLK 3 14 #define AGILEX_F2S_FREE_CLK 4 14 #define AGILEX_F2S_FREE_CLK 4 15 15 16 /* PLL clocks */ 16 /* PLL clocks */ 17 #define AGILEX_MAIN_PLL_CLK 5 17 #define AGILEX_MAIN_PLL_CLK 5 18 #define AGILEX_MAIN_PLL_C0_CLK 6 18 #define AGILEX_MAIN_PLL_C0_CLK 6 19 #define AGILEX_MAIN_PLL_C1_CLK 7 19 #define AGILEX_MAIN_PLL_C1_CLK 7 20 #define AGILEX_MAIN_PLL_C2_CLK 8 20 #define AGILEX_MAIN_PLL_C2_CLK 8 21 #define AGILEX_MAIN_PLL_C3_CLK 9 21 #define AGILEX_MAIN_PLL_C3_CLK 9 22 #define AGILEX_PERIPH_PLL_CLK 10 22 #define AGILEX_PERIPH_PLL_CLK 10 23 #define AGILEX_PERIPH_PLL_C0_CLK 11 23 #define AGILEX_PERIPH_PLL_C0_CLK 11 24 #define AGILEX_PERIPH_PLL_C1_CLK 12 24 #define AGILEX_PERIPH_PLL_C1_CLK 12 25 #define AGILEX_PERIPH_PLL_C2_CLK 13 25 #define AGILEX_PERIPH_PLL_C2_CLK 13 26 #define AGILEX_PERIPH_PLL_C3_CLK 14 26 #define AGILEX_PERIPH_PLL_C3_CLK 14 27 #define AGILEX_MPU_FREE_CLK 15 27 #define AGILEX_MPU_FREE_CLK 15 28 #define AGILEX_MPU_CCU_CLK 16 28 #define AGILEX_MPU_CCU_CLK 16 29 #define AGILEX_BOOT_CLK 17 29 #define AGILEX_BOOT_CLK 17 30 30 31 /* fixed factor clocks */ 31 /* fixed factor clocks */ 32 #define AGILEX_L3_MAIN_FREE_CLK 18 32 #define AGILEX_L3_MAIN_FREE_CLK 18 33 #define AGILEX_NOC_FREE_CLK 19 33 #define AGILEX_NOC_FREE_CLK 19 34 #define AGILEX_S2F_USR0_CLK 20 34 #define AGILEX_S2F_USR0_CLK 20 35 #define AGILEX_NOC_CLK 21 35 #define AGILEX_NOC_CLK 21 36 #define AGILEX_EMAC_A_FREE_CLK 22 36 #define AGILEX_EMAC_A_FREE_CLK 22 37 #define AGILEX_EMAC_B_FREE_CLK 23 37 #define AGILEX_EMAC_B_FREE_CLK 23 38 #define AGILEX_EMAC_PTP_FREE_CLK 24 38 #define AGILEX_EMAC_PTP_FREE_CLK 24 39 #define AGILEX_GPIO_DB_FREE_CLK 25 39 #define AGILEX_GPIO_DB_FREE_CLK 25 40 #define AGILEX_SDMMC_FREE_CLK 26 40 #define AGILEX_SDMMC_FREE_CLK 26 41 #define AGILEX_S2F_USER0_FREE_CLK 27 41 #define AGILEX_S2F_USER0_FREE_CLK 27 42 #define AGILEX_S2F_USER1_FREE_CLK 28 42 #define AGILEX_S2F_USER1_FREE_CLK 28 43 #define AGILEX_PSI_REF_FREE_CLK 29 43 #define AGILEX_PSI_REF_FREE_CLK 29 44 44 45 /* Gate clocks */ 45 /* Gate clocks */ 46 #define AGILEX_MPU_CLK 30 46 #define AGILEX_MPU_CLK 30 47 #define AGILEX_MPU_L2RAM_CLK 31 47 #define AGILEX_MPU_L2RAM_CLK 31 48 #define AGILEX_MPU_PERIPH_CLK 32 48 #define AGILEX_MPU_PERIPH_CLK 32 49 #define AGILEX_L4_MAIN_CLK 33 49 #define AGILEX_L4_MAIN_CLK 33 50 #define AGILEX_L4_MP_CLK 34 50 #define AGILEX_L4_MP_CLK 34 51 #define AGILEX_L4_SP_CLK 35 51 #define AGILEX_L4_SP_CLK 35 52 #define AGILEX_CS_AT_CLK 36 52 #define AGILEX_CS_AT_CLK 36 53 #define AGILEX_CS_TRACE_CLK 37 53 #define AGILEX_CS_TRACE_CLK 37 54 #define AGILEX_CS_PDBG_CLK 38 54 #define AGILEX_CS_PDBG_CLK 38 55 #define AGILEX_CS_TIMER_CLK 39 55 #define AGILEX_CS_TIMER_CLK 39 56 #define AGILEX_S2F_USER0_CLK 40 56 #define AGILEX_S2F_USER0_CLK 40 57 #define AGILEX_EMAC0_CLK 41 57 #define AGILEX_EMAC0_CLK 41 58 #define AGILEX_EMAC1_CLK 43 58 #define AGILEX_EMAC1_CLK 43 59 #define AGILEX_EMAC2_CLK 44 59 #define AGILEX_EMAC2_CLK 44 60 #define AGILEX_EMAC_PTP_CLK 45 60 #define AGILEX_EMAC_PTP_CLK 45 61 #define AGILEX_GPIO_DB_CLK 46 61 #define AGILEX_GPIO_DB_CLK 46 62 #define AGILEX_NAND_CLK 47 62 #define AGILEX_NAND_CLK 47 63 #define AGILEX_PSI_REF_CLK 48 63 #define AGILEX_PSI_REF_CLK 48 64 #define AGILEX_S2F_USER1_CLK 49 64 #define AGILEX_S2F_USER1_CLK 49 65 #define AGILEX_SDMMC_CLK 50 65 #define AGILEX_SDMMC_CLK 50 66 #define AGILEX_SPI_M_CLK 51 66 #define AGILEX_SPI_M_CLK 51 67 #define AGILEX_USB_CLK 52 67 #define AGILEX_USB_CLK 52 68 #define AGILEX_NAND_X_CLK 53 68 #define AGILEX_NAND_X_CLK 53 69 #define AGILEX_NAND_ECC_CLK 54 69 #define AGILEX_NAND_ECC_CLK 54 70 #define AGILEX_NUM_CLKS 55 70 #define AGILEX_NUM_CLKS 55 71 71 72 #endif /* __AGILEX_CLOCK_H */ 72 #endif /* __AGILEX_CLOCK_H */ 73 73
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