1 /* SPDX-License-Identifier: (GPL-2.0-only OR M 1 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 /* 2 /* 3 * Copyright (c) 2023 Amlogic, Inc. All rights 3 * Copyright (c) 2023 Amlogic, Inc. All rights reserved. 4 * Author: Chuan Liu <chuan.liu@amlogic.com> 4 * Author: Chuan Liu <chuan.liu@amlogic.com> 5 */ 5 */ 6 6 7 #ifndef __AMLOGIC_C3_SCMI_CLKC_H 7 #ifndef __AMLOGIC_C3_SCMI_CLKC_H 8 #define __AMLOGIC_C3_SCMI_CLKC_H 8 #define __AMLOGIC_C3_SCMI_CLKC_H 9 9 10 #define CLKID_DDR_PLL_OSC 10 #define CLKID_DDR_PLL_OSC 0 11 #define CLKID_DDR_PHY 11 #define CLKID_DDR_PHY 1 12 #define CLKID_TOP_PLL_OSC 12 #define CLKID_TOP_PLL_OSC 2 13 #define CLKID_USB_PLL_OSC 13 #define CLKID_USB_PLL_OSC 3 14 #define CLKID_MIPIISP_VOUT 14 #define CLKID_MIPIISP_VOUT 4 15 #define CLKID_MCLK_PLL_OSC 15 #define CLKID_MCLK_PLL_OSC 5 16 #define CLKID_USB_CTRL 16 #define CLKID_USB_CTRL 6 17 #define CLKID_ETH_PLL_OSC 17 #define CLKID_ETH_PLL_OSC 7 18 #define CLKID_OSC 18 #define CLKID_OSC 8 19 #define CLKID_SYS_CLK 19 #define CLKID_SYS_CLK 9 20 #define CLKID_AXI_CLK 20 #define CLKID_AXI_CLK 10 21 #define CLKID_CPU_CLK 21 #define CLKID_CPU_CLK 11 22 #define CLKID_FIXED_PLL_OSC 22 #define CLKID_FIXED_PLL_OSC 12 23 #define CLKID_GP1_PLL_OSC 23 #define CLKID_GP1_PLL_OSC 13 24 #define CLKID_SYS_PLL_DIV16 24 #define CLKID_SYS_PLL_DIV16 14 25 #define CLKID_CPU_CLK_DIV16 25 #define CLKID_CPU_CLK_DIV16 15 26 26 27 #endif /* __AMLOGIC_C3_SCMI_CLKC_H */ 27 #endif /* __AMLOGIC_C3_SCMI_CLKC_H */ 28 28
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