1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * Copyright (c) 2013 Samsung Electronics Co., 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4 * Author: Andrzej Hajda <a.hajda@samsung.com> 4 * Author: Andrzej Hajda <a.hajda@samsung.com>
5 * 5 *
6 * Device Tree binding constants for Exynos525 6 * Device Tree binding constants for Exynos5250 clock controller.
7 */ 7 */
8 8
9 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H 9 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
10 #define _DT_BINDINGS_CLOCK_EXYNOS_5250_H 10 #define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
11 11
12 /* core clocks */ 12 /* core clocks */
13 #define CLK_FIN_PLL 1 13 #define CLK_FIN_PLL 1
14 #define CLK_FOUT_APLL 2 14 #define CLK_FOUT_APLL 2
15 #define CLK_FOUT_MPLL 3 15 #define CLK_FOUT_MPLL 3
16 #define CLK_FOUT_BPLL 4 16 #define CLK_FOUT_BPLL 4
17 #define CLK_FOUT_GPLL 5 17 #define CLK_FOUT_GPLL 5
18 #define CLK_FOUT_CPLL 6 18 #define CLK_FOUT_CPLL 6
19 #define CLK_FOUT_EPLL 7 19 #define CLK_FOUT_EPLL 7
20 #define CLK_FOUT_VPLL 8 20 #define CLK_FOUT_VPLL 8
21 #define CLK_ARM_CLK 9 21 #define CLK_ARM_CLK 9
22 #define CLK_DIV_ARM2 10 <<
23 22
24 /* gate for special clocks (sclk) */ 23 /* gate for special clocks (sclk) */
25 #define CLK_SCLK_CAM_BAYER 128 24 #define CLK_SCLK_CAM_BAYER 128
26 #define CLK_SCLK_CAM0 129 25 #define CLK_SCLK_CAM0 129
27 #define CLK_SCLK_CAM1 130 26 #define CLK_SCLK_CAM1 130
28 #define CLK_SCLK_GSCL_WA 131 27 #define CLK_SCLK_GSCL_WA 131
29 #define CLK_SCLK_GSCL_WB 132 28 #define CLK_SCLK_GSCL_WB 132
30 #define CLK_SCLK_FIMD1 133 29 #define CLK_SCLK_FIMD1 133
31 #define CLK_SCLK_MIPI1 134 30 #define CLK_SCLK_MIPI1 134
32 #define CLK_SCLK_DP 135 31 #define CLK_SCLK_DP 135
33 #define CLK_SCLK_HDMI 136 32 #define CLK_SCLK_HDMI 136
34 #define CLK_SCLK_PIXEL 137 33 #define CLK_SCLK_PIXEL 137
35 #define CLK_SCLK_AUDIO0 138 34 #define CLK_SCLK_AUDIO0 138
36 #define CLK_SCLK_MMC0 139 35 #define CLK_SCLK_MMC0 139
37 #define CLK_SCLK_MMC1 140 36 #define CLK_SCLK_MMC1 140
38 #define CLK_SCLK_MMC2 141 37 #define CLK_SCLK_MMC2 141
39 #define CLK_SCLK_MMC3 142 38 #define CLK_SCLK_MMC3 142
40 #define CLK_SCLK_SATA 143 39 #define CLK_SCLK_SATA 143
41 #define CLK_SCLK_USB3 144 40 #define CLK_SCLK_USB3 144
42 #define CLK_SCLK_JPEG 145 41 #define CLK_SCLK_JPEG 145
43 #define CLK_SCLK_UART0 146 42 #define CLK_SCLK_UART0 146
44 #define CLK_SCLK_UART1 147 43 #define CLK_SCLK_UART1 147
45 #define CLK_SCLK_UART2 148 44 #define CLK_SCLK_UART2 148
46 #define CLK_SCLK_UART3 149 45 #define CLK_SCLK_UART3 149
47 #define CLK_SCLK_PWM 150 46 #define CLK_SCLK_PWM 150
48 #define CLK_SCLK_AUDIO1 151 47 #define CLK_SCLK_AUDIO1 151
49 #define CLK_SCLK_AUDIO2 152 48 #define CLK_SCLK_AUDIO2 152
50 #define CLK_SCLK_SPDIF 153 49 #define CLK_SCLK_SPDIF 153
51 #define CLK_SCLK_SPI0 154 50 #define CLK_SCLK_SPI0 154
52 #define CLK_SCLK_SPI1 155 51 #define CLK_SCLK_SPI1 155
53 #define CLK_SCLK_SPI2 156 52 #define CLK_SCLK_SPI2 156
54 #define CLK_DIV_I2S1 157 53 #define CLK_DIV_I2S1 157
55 #define CLK_DIV_I2S2 158 54 #define CLK_DIV_I2S2 158
56 #define CLK_SCLK_HDMIPHY 159 55 #define CLK_SCLK_HDMIPHY 159
57 #define CLK_DIV_PCM0 160 56 #define CLK_DIV_PCM0 160
58 57
59 /* gate clocks */ 58 /* gate clocks */
60 #define CLK_GSCL0 256 59 #define CLK_GSCL0 256
61 #define CLK_GSCL1 257 60 #define CLK_GSCL1 257
62 #define CLK_GSCL2 258 61 #define CLK_GSCL2 258
63 #define CLK_GSCL3 259 62 #define CLK_GSCL3 259
64 #define CLK_GSCL_WA 260 63 #define CLK_GSCL_WA 260
65 #define CLK_GSCL_WB 261 64 #define CLK_GSCL_WB 261
66 #define CLK_SMMU_GSCL0 262 65 #define CLK_SMMU_GSCL0 262
67 #define CLK_SMMU_GSCL1 263 66 #define CLK_SMMU_GSCL1 263
68 #define CLK_SMMU_GSCL2 264 67 #define CLK_SMMU_GSCL2 264
69 #define CLK_SMMU_GSCL3 265 68 #define CLK_SMMU_GSCL3 265
70 #define CLK_MFC 266 69 #define CLK_MFC 266
71 #define CLK_SMMU_MFCL 267 70 #define CLK_SMMU_MFCL 267
72 #define CLK_SMMU_MFCR 268 71 #define CLK_SMMU_MFCR 268
73 #define CLK_ROTATOR 269 72 #define CLK_ROTATOR 269
74 #define CLK_JPEG 270 73 #define CLK_JPEG 270
75 #define CLK_MDMA1 271 74 #define CLK_MDMA1 271
76 #define CLK_SMMU_ROTATOR 272 75 #define CLK_SMMU_ROTATOR 272
77 #define CLK_SMMU_JPEG 273 76 #define CLK_SMMU_JPEG 273
78 #define CLK_SMMU_MDMA1 274 77 #define CLK_SMMU_MDMA1 274
79 #define CLK_PDMA0 275 78 #define CLK_PDMA0 275
80 #define CLK_PDMA1 276 79 #define CLK_PDMA1 276
81 #define CLK_SATA 277 80 #define CLK_SATA 277
82 #define CLK_USBOTG 278 81 #define CLK_USBOTG 278
83 #define CLK_MIPI_HSI 279 82 #define CLK_MIPI_HSI 279
84 #define CLK_SDMMC0 280 83 #define CLK_SDMMC0 280
85 #define CLK_SDMMC1 281 84 #define CLK_SDMMC1 281
86 #define CLK_SDMMC2 282 85 #define CLK_SDMMC2 282
87 #define CLK_SDMMC3 283 86 #define CLK_SDMMC3 283
88 #define CLK_SROMC 284 87 #define CLK_SROMC 284
89 #define CLK_USB2 285 88 #define CLK_USB2 285
90 #define CLK_USB3 286 89 #define CLK_USB3 286
91 #define CLK_SATA_PHYCTRL 287 90 #define CLK_SATA_PHYCTRL 287
92 #define CLK_SATA_PHYI2C 288 91 #define CLK_SATA_PHYI2C 288
93 #define CLK_UART0 289 92 #define CLK_UART0 289
94 #define CLK_UART1 290 93 #define CLK_UART1 290
95 #define CLK_UART2 291 94 #define CLK_UART2 291
96 #define CLK_UART3 292 95 #define CLK_UART3 292
97 #define CLK_UART4 293 96 #define CLK_UART4 293
98 #define CLK_I2C0 294 97 #define CLK_I2C0 294
99 #define CLK_I2C1 295 98 #define CLK_I2C1 295
100 #define CLK_I2C2 296 99 #define CLK_I2C2 296
101 #define CLK_I2C3 297 100 #define CLK_I2C3 297
102 #define CLK_I2C4 298 101 #define CLK_I2C4 298
103 #define CLK_I2C5 299 102 #define CLK_I2C5 299
104 #define CLK_I2C6 300 103 #define CLK_I2C6 300
105 #define CLK_I2C7 301 104 #define CLK_I2C7 301
106 #define CLK_I2C_HDMI 302 105 #define CLK_I2C_HDMI 302
107 #define CLK_ADC 303 106 #define CLK_ADC 303
108 #define CLK_SPI0 304 107 #define CLK_SPI0 304
109 #define CLK_SPI1 305 108 #define CLK_SPI1 305
110 #define CLK_SPI2 306 109 #define CLK_SPI2 306
111 #define CLK_I2S1 307 110 #define CLK_I2S1 307
112 #define CLK_I2S2 308 111 #define CLK_I2S2 308
113 #define CLK_PCM1 309 112 #define CLK_PCM1 309
114 #define CLK_PCM2 310 113 #define CLK_PCM2 310
115 #define CLK_PWM 311 114 #define CLK_PWM 311
116 #define CLK_SPDIF 312 115 #define CLK_SPDIF 312
117 #define CLK_AC97 313 116 #define CLK_AC97 313
118 #define CLK_HSI2C0 314 117 #define CLK_HSI2C0 314
119 #define CLK_HSI2C1 315 118 #define CLK_HSI2C1 315
120 #define CLK_HSI2C2 316 119 #define CLK_HSI2C2 316
121 #define CLK_HSI2C3 317 120 #define CLK_HSI2C3 317
122 #define CLK_CHIPID 318 121 #define CLK_CHIPID 318
123 #define CLK_SYSREG 319 122 #define CLK_SYSREG 319
124 #define CLK_PMU 320 123 #define CLK_PMU 320
125 #define CLK_CMU_TOP 321 124 #define CLK_CMU_TOP 321
126 #define CLK_CMU_CORE 322 125 #define CLK_CMU_CORE 322
127 #define CLK_CMU_MEM 323 126 #define CLK_CMU_MEM 323
128 #define CLK_TZPC0 324 127 #define CLK_TZPC0 324
129 #define CLK_TZPC1 325 128 #define CLK_TZPC1 325
130 #define CLK_TZPC2 326 129 #define CLK_TZPC2 326
131 #define CLK_TZPC3 327 130 #define CLK_TZPC3 327
132 #define CLK_TZPC4 328 131 #define CLK_TZPC4 328
133 #define CLK_TZPC5 329 132 #define CLK_TZPC5 329
134 #define CLK_TZPC6 330 133 #define CLK_TZPC6 330
135 #define CLK_TZPC7 331 134 #define CLK_TZPC7 331
136 #define CLK_TZPC8 332 135 #define CLK_TZPC8 332
137 #define CLK_TZPC9 333 136 #define CLK_TZPC9 333
138 #define CLK_HDMI_CEC 334 137 #define CLK_HDMI_CEC 334
139 #define CLK_MCT 335 138 #define CLK_MCT 335
140 #define CLK_WDT 336 139 #define CLK_WDT 336
141 #define CLK_RTC 337 140 #define CLK_RTC 337
142 #define CLK_TMU 338 141 #define CLK_TMU 338
143 #define CLK_FIMD1 339 142 #define CLK_FIMD1 339
144 #define CLK_MIE1 340 143 #define CLK_MIE1 340
145 #define CLK_DSIM0 341 144 #define CLK_DSIM0 341
146 #define CLK_DP 342 145 #define CLK_DP 342
147 #define CLK_MIXER 343 146 #define CLK_MIXER 343
148 #define CLK_HDMI 344 147 #define CLK_HDMI 344
149 #define CLK_G2D 345 148 #define CLK_G2D 345
150 #define CLK_MDMA0 346 149 #define CLK_MDMA0 346
151 #define CLK_SMMU_MDMA0 347 150 #define CLK_SMMU_MDMA0 347
152 #define CLK_SSS 348 151 #define CLK_SSS 348
153 #define CLK_G3D 349 152 #define CLK_G3D 349
154 #define CLK_SMMU_TV 350 153 #define CLK_SMMU_TV 350
155 #define CLK_SMMU_FIMD1 351 154 #define CLK_SMMU_FIMD1 351
156 #define CLK_SMMU_2D 352 155 #define CLK_SMMU_2D 352
157 #define CLK_SMMU_FIMC_ISP 353 156 #define CLK_SMMU_FIMC_ISP 353
158 #define CLK_SMMU_FIMC_DRC 354 157 #define CLK_SMMU_FIMC_DRC 354
159 #define CLK_SMMU_FIMC_SCC 355 158 #define CLK_SMMU_FIMC_SCC 355
160 #define CLK_SMMU_FIMC_SCP 356 159 #define CLK_SMMU_FIMC_SCP 356
161 #define CLK_SMMU_FIMC_FD 357 160 #define CLK_SMMU_FIMC_FD 357
162 #define CLK_SMMU_FIMC_MCU 358 161 #define CLK_SMMU_FIMC_MCU 358
163 #define CLK_SMMU_FIMC_ODC 359 162 #define CLK_SMMU_FIMC_ODC 359
164 #define CLK_SMMU_FIMC_DIS0 360 163 #define CLK_SMMU_FIMC_DIS0 360
165 #define CLK_SMMU_FIMC_DIS1 361 164 #define CLK_SMMU_FIMC_DIS1 361
166 #define CLK_SMMU_FIMC_3DNR 362 165 #define CLK_SMMU_FIMC_3DNR 362
167 #define CLK_SMMU_FIMC_LITE0 363 166 #define CLK_SMMU_FIMC_LITE0 363
168 #define CLK_SMMU_FIMC_LITE1 364 167 #define CLK_SMMU_FIMC_LITE1 364
169 #define CLK_CAMIF_TOP 365 168 #define CLK_CAMIF_TOP 365
170 169
171 /* mux clocks */ 170 /* mux clocks */
172 #define CLK_MOUT_HDMI 1024 171 #define CLK_MOUT_HDMI 1024
173 #define CLK_MOUT_GPLL 1025 172 #define CLK_MOUT_GPLL 1025
174 #define CLK_MOUT_ACLK200_DISP1_SUB 1026 173 #define CLK_MOUT_ACLK200_DISP1_SUB 1026
175 #define CLK_MOUT_ACLK300_DISP1_SUB 1027 174 #define CLK_MOUT_ACLK300_DISP1_SUB 1027
176 #define CLK_MOUT_APLL 1028 175 #define CLK_MOUT_APLL 1028
177 #define CLK_MOUT_MPLL 1029 176 #define CLK_MOUT_MPLL 1029
178 #define CLK_MOUT_VPLLSRC 1030 !! 177
>> 178 /* must be greater than maximal clock id */
>> 179 #define CLK_NR_CLKS 1030
179 180
180 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ 181 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
181 182
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