1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * Copyright (c) 2013 Samsung Electronics Co., 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4 * Author: Andrzej Hajda <a.hajda@samsung.com> 4 * Author: Andrzej Hajda <a.hajda@samsung.com>
5 * 5 *
6 * Device Tree binding constants for Exynos525 6 * Device Tree binding constants for Exynos5250 clock controller.
7 */ 7 */
8 8
9 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H 9 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
10 #define _DT_BINDINGS_CLOCK_EXYNOS_5250_H 10 #define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
11 11
12 /* core clocks */ 12 /* core clocks */
13 #define CLK_FIN_PLL 1 13 #define CLK_FIN_PLL 1
14 #define CLK_FOUT_APLL 2 14 #define CLK_FOUT_APLL 2
15 #define CLK_FOUT_MPLL 3 15 #define CLK_FOUT_MPLL 3
16 #define CLK_FOUT_BPLL 4 16 #define CLK_FOUT_BPLL 4
17 #define CLK_FOUT_GPLL 5 17 #define CLK_FOUT_GPLL 5
18 #define CLK_FOUT_CPLL 6 18 #define CLK_FOUT_CPLL 6
19 #define CLK_FOUT_EPLL 7 19 #define CLK_FOUT_EPLL 7
20 #define CLK_FOUT_VPLL 8 20 #define CLK_FOUT_VPLL 8
21 #define CLK_ARM_CLK 9 21 #define CLK_ARM_CLK 9
22 #define CLK_DIV_ARM2 10 22 #define CLK_DIV_ARM2 10
23 23
24 /* gate for special clocks (sclk) */ 24 /* gate for special clocks (sclk) */
25 #define CLK_SCLK_CAM_BAYER 128 25 #define CLK_SCLK_CAM_BAYER 128
26 #define CLK_SCLK_CAM0 129 26 #define CLK_SCLK_CAM0 129
27 #define CLK_SCLK_CAM1 130 27 #define CLK_SCLK_CAM1 130
28 #define CLK_SCLK_GSCL_WA 131 28 #define CLK_SCLK_GSCL_WA 131
29 #define CLK_SCLK_GSCL_WB 132 29 #define CLK_SCLK_GSCL_WB 132
30 #define CLK_SCLK_FIMD1 133 30 #define CLK_SCLK_FIMD1 133
31 #define CLK_SCLK_MIPI1 134 31 #define CLK_SCLK_MIPI1 134
32 #define CLK_SCLK_DP 135 32 #define CLK_SCLK_DP 135
33 #define CLK_SCLK_HDMI 136 33 #define CLK_SCLK_HDMI 136
34 #define CLK_SCLK_PIXEL 137 34 #define CLK_SCLK_PIXEL 137
35 #define CLK_SCLK_AUDIO0 138 35 #define CLK_SCLK_AUDIO0 138
36 #define CLK_SCLK_MMC0 139 36 #define CLK_SCLK_MMC0 139
37 #define CLK_SCLK_MMC1 140 37 #define CLK_SCLK_MMC1 140
38 #define CLK_SCLK_MMC2 141 38 #define CLK_SCLK_MMC2 141
39 #define CLK_SCLK_MMC3 142 39 #define CLK_SCLK_MMC3 142
40 #define CLK_SCLK_SATA 143 40 #define CLK_SCLK_SATA 143
41 #define CLK_SCLK_USB3 144 41 #define CLK_SCLK_USB3 144
42 #define CLK_SCLK_JPEG 145 42 #define CLK_SCLK_JPEG 145
43 #define CLK_SCLK_UART0 146 43 #define CLK_SCLK_UART0 146
44 #define CLK_SCLK_UART1 147 44 #define CLK_SCLK_UART1 147
45 #define CLK_SCLK_UART2 148 45 #define CLK_SCLK_UART2 148
46 #define CLK_SCLK_UART3 149 46 #define CLK_SCLK_UART3 149
47 #define CLK_SCLK_PWM 150 47 #define CLK_SCLK_PWM 150
48 #define CLK_SCLK_AUDIO1 151 48 #define CLK_SCLK_AUDIO1 151
49 #define CLK_SCLK_AUDIO2 152 49 #define CLK_SCLK_AUDIO2 152
50 #define CLK_SCLK_SPDIF 153 50 #define CLK_SCLK_SPDIF 153
51 #define CLK_SCLK_SPI0 154 51 #define CLK_SCLK_SPI0 154
52 #define CLK_SCLK_SPI1 155 52 #define CLK_SCLK_SPI1 155
53 #define CLK_SCLK_SPI2 156 53 #define CLK_SCLK_SPI2 156
54 #define CLK_DIV_I2S1 157 54 #define CLK_DIV_I2S1 157
55 #define CLK_DIV_I2S2 158 55 #define CLK_DIV_I2S2 158
56 #define CLK_SCLK_HDMIPHY 159 56 #define CLK_SCLK_HDMIPHY 159
57 #define CLK_DIV_PCM0 160 57 #define CLK_DIV_PCM0 160
58 58
59 /* gate clocks */ 59 /* gate clocks */
60 #define CLK_GSCL0 256 60 #define CLK_GSCL0 256
61 #define CLK_GSCL1 257 61 #define CLK_GSCL1 257
62 #define CLK_GSCL2 258 62 #define CLK_GSCL2 258
63 #define CLK_GSCL3 259 63 #define CLK_GSCL3 259
64 #define CLK_GSCL_WA 260 64 #define CLK_GSCL_WA 260
65 #define CLK_GSCL_WB 261 65 #define CLK_GSCL_WB 261
66 #define CLK_SMMU_GSCL0 262 66 #define CLK_SMMU_GSCL0 262
67 #define CLK_SMMU_GSCL1 263 67 #define CLK_SMMU_GSCL1 263
68 #define CLK_SMMU_GSCL2 264 68 #define CLK_SMMU_GSCL2 264
69 #define CLK_SMMU_GSCL3 265 69 #define CLK_SMMU_GSCL3 265
70 #define CLK_MFC 266 70 #define CLK_MFC 266
71 #define CLK_SMMU_MFCL 267 71 #define CLK_SMMU_MFCL 267
72 #define CLK_SMMU_MFCR 268 72 #define CLK_SMMU_MFCR 268
73 #define CLK_ROTATOR 269 73 #define CLK_ROTATOR 269
74 #define CLK_JPEG 270 74 #define CLK_JPEG 270
75 #define CLK_MDMA1 271 75 #define CLK_MDMA1 271
76 #define CLK_SMMU_ROTATOR 272 76 #define CLK_SMMU_ROTATOR 272
77 #define CLK_SMMU_JPEG 273 77 #define CLK_SMMU_JPEG 273
78 #define CLK_SMMU_MDMA1 274 78 #define CLK_SMMU_MDMA1 274
79 #define CLK_PDMA0 275 79 #define CLK_PDMA0 275
80 #define CLK_PDMA1 276 80 #define CLK_PDMA1 276
81 #define CLK_SATA 277 81 #define CLK_SATA 277
82 #define CLK_USBOTG 278 82 #define CLK_USBOTG 278
83 #define CLK_MIPI_HSI 279 83 #define CLK_MIPI_HSI 279
84 #define CLK_SDMMC0 280 84 #define CLK_SDMMC0 280
85 #define CLK_SDMMC1 281 85 #define CLK_SDMMC1 281
86 #define CLK_SDMMC2 282 86 #define CLK_SDMMC2 282
87 #define CLK_SDMMC3 283 87 #define CLK_SDMMC3 283
88 #define CLK_SROMC 284 88 #define CLK_SROMC 284
89 #define CLK_USB2 285 89 #define CLK_USB2 285
90 #define CLK_USB3 286 90 #define CLK_USB3 286
91 #define CLK_SATA_PHYCTRL 287 91 #define CLK_SATA_PHYCTRL 287
92 #define CLK_SATA_PHYI2C 288 92 #define CLK_SATA_PHYI2C 288
93 #define CLK_UART0 289 93 #define CLK_UART0 289
94 #define CLK_UART1 290 94 #define CLK_UART1 290
95 #define CLK_UART2 291 95 #define CLK_UART2 291
96 #define CLK_UART3 292 96 #define CLK_UART3 292
97 #define CLK_UART4 293 97 #define CLK_UART4 293
98 #define CLK_I2C0 294 98 #define CLK_I2C0 294
99 #define CLK_I2C1 295 99 #define CLK_I2C1 295
100 #define CLK_I2C2 296 100 #define CLK_I2C2 296
101 #define CLK_I2C3 297 101 #define CLK_I2C3 297
102 #define CLK_I2C4 298 102 #define CLK_I2C4 298
103 #define CLK_I2C5 299 103 #define CLK_I2C5 299
104 #define CLK_I2C6 300 104 #define CLK_I2C6 300
105 #define CLK_I2C7 301 105 #define CLK_I2C7 301
106 #define CLK_I2C_HDMI 302 106 #define CLK_I2C_HDMI 302
107 #define CLK_ADC 303 107 #define CLK_ADC 303
108 #define CLK_SPI0 304 108 #define CLK_SPI0 304
109 #define CLK_SPI1 305 109 #define CLK_SPI1 305
110 #define CLK_SPI2 306 110 #define CLK_SPI2 306
111 #define CLK_I2S1 307 111 #define CLK_I2S1 307
112 #define CLK_I2S2 308 112 #define CLK_I2S2 308
113 #define CLK_PCM1 309 113 #define CLK_PCM1 309
114 #define CLK_PCM2 310 114 #define CLK_PCM2 310
115 #define CLK_PWM 311 115 #define CLK_PWM 311
116 #define CLK_SPDIF 312 116 #define CLK_SPDIF 312
117 #define CLK_AC97 313 117 #define CLK_AC97 313
118 #define CLK_HSI2C0 314 118 #define CLK_HSI2C0 314
119 #define CLK_HSI2C1 315 119 #define CLK_HSI2C1 315
120 #define CLK_HSI2C2 316 120 #define CLK_HSI2C2 316
121 #define CLK_HSI2C3 317 121 #define CLK_HSI2C3 317
122 #define CLK_CHIPID 318 122 #define CLK_CHIPID 318
123 #define CLK_SYSREG 319 123 #define CLK_SYSREG 319
124 #define CLK_PMU 320 124 #define CLK_PMU 320
125 #define CLK_CMU_TOP 321 125 #define CLK_CMU_TOP 321
126 #define CLK_CMU_CORE 322 126 #define CLK_CMU_CORE 322
127 #define CLK_CMU_MEM 323 127 #define CLK_CMU_MEM 323
128 #define CLK_TZPC0 324 128 #define CLK_TZPC0 324
129 #define CLK_TZPC1 325 129 #define CLK_TZPC1 325
130 #define CLK_TZPC2 326 130 #define CLK_TZPC2 326
131 #define CLK_TZPC3 327 131 #define CLK_TZPC3 327
132 #define CLK_TZPC4 328 132 #define CLK_TZPC4 328
133 #define CLK_TZPC5 329 133 #define CLK_TZPC5 329
134 #define CLK_TZPC6 330 134 #define CLK_TZPC6 330
135 #define CLK_TZPC7 331 135 #define CLK_TZPC7 331
136 #define CLK_TZPC8 332 136 #define CLK_TZPC8 332
137 #define CLK_TZPC9 333 137 #define CLK_TZPC9 333
138 #define CLK_HDMI_CEC 334 138 #define CLK_HDMI_CEC 334
139 #define CLK_MCT 335 139 #define CLK_MCT 335
140 #define CLK_WDT 336 140 #define CLK_WDT 336
141 #define CLK_RTC 337 141 #define CLK_RTC 337
142 #define CLK_TMU 338 142 #define CLK_TMU 338
143 #define CLK_FIMD1 339 143 #define CLK_FIMD1 339
144 #define CLK_MIE1 340 144 #define CLK_MIE1 340
145 #define CLK_DSIM0 341 145 #define CLK_DSIM0 341
146 #define CLK_DP 342 146 #define CLK_DP 342
147 #define CLK_MIXER 343 147 #define CLK_MIXER 343
148 #define CLK_HDMI 344 148 #define CLK_HDMI 344
149 #define CLK_G2D 345 149 #define CLK_G2D 345
150 #define CLK_MDMA0 346 150 #define CLK_MDMA0 346
151 #define CLK_SMMU_MDMA0 347 151 #define CLK_SMMU_MDMA0 347
152 #define CLK_SSS 348 152 #define CLK_SSS 348
153 #define CLK_G3D 349 153 #define CLK_G3D 349
154 #define CLK_SMMU_TV 350 154 #define CLK_SMMU_TV 350
155 #define CLK_SMMU_FIMD1 351 155 #define CLK_SMMU_FIMD1 351
156 #define CLK_SMMU_2D 352 156 #define CLK_SMMU_2D 352
157 #define CLK_SMMU_FIMC_ISP 353 157 #define CLK_SMMU_FIMC_ISP 353
158 #define CLK_SMMU_FIMC_DRC 354 158 #define CLK_SMMU_FIMC_DRC 354
159 #define CLK_SMMU_FIMC_SCC 355 159 #define CLK_SMMU_FIMC_SCC 355
160 #define CLK_SMMU_FIMC_SCP 356 160 #define CLK_SMMU_FIMC_SCP 356
161 #define CLK_SMMU_FIMC_FD 357 161 #define CLK_SMMU_FIMC_FD 357
162 #define CLK_SMMU_FIMC_MCU 358 162 #define CLK_SMMU_FIMC_MCU 358
163 #define CLK_SMMU_FIMC_ODC 359 163 #define CLK_SMMU_FIMC_ODC 359
164 #define CLK_SMMU_FIMC_DIS0 360 164 #define CLK_SMMU_FIMC_DIS0 360
165 #define CLK_SMMU_FIMC_DIS1 361 165 #define CLK_SMMU_FIMC_DIS1 361
166 #define CLK_SMMU_FIMC_3DNR 362 166 #define CLK_SMMU_FIMC_3DNR 362
167 #define CLK_SMMU_FIMC_LITE0 363 167 #define CLK_SMMU_FIMC_LITE0 363
168 #define CLK_SMMU_FIMC_LITE1 364 168 #define CLK_SMMU_FIMC_LITE1 364
169 #define CLK_CAMIF_TOP 365 169 #define CLK_CAMIF_TOP 365
170 170
171 /* mux clocks */ 171 /* mux clocks */
172 #define CLK_MOUT_HDMI 1024 172 #define CLK_MOUT_HDMI 1024
173 #define CLK_MOUT_GPLL 1025 173 #define CLK_MOUT_GPLL 1025
174 #define CLK_MOUT_ACLK200_DISP1_SUB 1026 174 #define CLK_MOUT_ACLK200_DISP1_SUB 1026
175 #define CLK_MOUT_ACLK300_DISP1_SUB 1027 175 #define CLK_MOUT_ACLK300_DISP1_SUB 1027
176 #define CLK_MOUT_APLL 1028 176 #define CLK_MOUT_APLL 1028
177 #define CLK_MOUT_MPLL 1029 177 #define CLK_MOUT_MPLL 1029
178 #define CLK_MOUT_VPLLSRC 1030 178 #define CLK_MOUT_VPLLSRC 1030
179 179
>> 180 /* must be greater than maximal clock id */
>> 181 #define CLK_NR_CLKS 1031
>> 182
180 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ 183 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
181 184
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