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TOMOYO Linux Cross Reference
Linux/include/dt-bindings/clock/exynos7885.h

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

Diff markup

Differences between /include/dt-bindings/clock/exynos7885.h (Architecture alpha) and /include/dt-bindings/clock/exynos7885.h (Architecture i386)


  1 /* SPDX-License-Identifier: (GPL-2.0-only OR B      1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2 /*                                                  2 /*
  3  * Copyright (c) 2021 Dávid Virág                 3  * Copyright (c) 2021 Dávid Virág
  4  *                                                  4  *
  5  * Device Tree binding constants for Exynos788      5  * Device Tree binding constants for Exynos7885 clock controller.
  6  */                                                 6  */
  7                                                     7 
  8 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H            8 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H
  9 #define _DT_BINDINGS_CLOCK_EXYNOS_7885_H            9 #define _DT_BINDINGS_CLOCK_EXYNOS_7885_H
 10                                                    10 
 11 /* CMU_TOP */                                      11 /* CMU_TOP */
 12 #define CLK_FOUT_SHARED0_PLL            1          12 #define CLK_FOUT_SHARED0_PLL            1
 13 #define CLK_FOUT_SHARED1_PLL            2          13 #define CLK_FOUT_SHARED1_PLL            2
 14 #define CLK_DOUT_SHARED0_DIV2           3          14 #define CLK_DOUT_SHARED0_DIV2           3
 15 #define CLK_DOUT_SHARED0_DIV3           4          15 #define CLK_DOUT_SHARED0_DIV3           4
 16 #define CLK_DOUT_SHARED0_DIV4           5          16 #define CLK_DOUT_SHARED0_DIV4           5
 17 #define CLK_DOUT_SHARED0_DIV5           6          17 #define CLK_DOUT_SHARED0_DIV5           6
 18 #define CLK_DOUT_SHARED1_DIV2           7          18 #define CLK_DOUT_SHARED1_DIV2           7
 19 #define CLK_DOUT_SHARED1_DIV3           8          19 #define CLK_DOUT_SHARED1_DIV3           8
 20 #define CLK_DOUT_SHARED1_DIV4           9          20 #define CLK_DOUT_SHARED1_DIV4           9
 21 #define CLK_MOUT_CORE_BUS               10         21 #define CLK_MOUT_CORE_BUS               10
 22 #define CLK_MOUT_CORE_CCI               11         22 #define CLK_MOUT_CORE_CCI               11
 23 #define CLK_MOUT_CORE_G3D               12         23 #define CLK_MOUT_CORE_G3D               12
 24 #define CLK_DOUT_CORE_BUS               13         24 #define CLK_DOUT_CORE_BUS               13
 25 #define CLK_DOUT_CORE_CCI               14         25 #define CLK_DOUT_CORE_CCI               14
 26 #define CLK_DOUT_CORE_G3D               15         26 #define CLK_DOUT_CORE_G3D               15
 27 #define CLK_GOUT_CORE_BUS               16         27 #define CLK_GOUT_CORE_BUS               16
 28 #define CLK_GOUT_CORE_CCI               17         28 #define CLK_GOUT_CORE_CCI               17
 29 #define CLK_GOUT_CORE_G3D               18         29 #define CLK_GOUT_CORE_G3D               18
 30 #define CLK_MOUT_PERI_BUS               19         30 #define CLK_MOUT_PERI_BUS               19
 31 #define CLK_MOUT_PERI_SPI0              20         31 #define CLK_MOUT_PERI_SPI0              20
 32 #define CLK_MOUT_PERI_SPI1              21         32 #define CLK_MOUT_PERI_SPI1              21
 33 #define CLK_MOUT_PERI_UART0             22         33 #define CLK_MOUT_PERI_UART0             22
 34 #define CLK_MOUT_PERI_UART1             23         34 #define CLK_MOUT_PERI_UART1             23
 35 #define CLK_MOUT_PERI_UART2             24         35 #define CLK_MOUT_PERI_UART2             24
 36 #define CLK_MOUT_PERI_USI0              25         36 #define CLK_MOUT_PERI_USI0              25
 37 #define CLK_MOUT_PERI_USI1              26         37 #define CLK_MOUT_PERI_USI1              26
 38 #define CLK_MOUT_PERI_USI2              27         38 #define CLK_MOUT_PERI_USI2              27
 39 #define CLK_DOUT_PERI_BUS               28         39 #define CLK_DOUT_PERI_BUS               28
 40 #define CLK_DOUT_PERI_SPI0              29         40 #define CLK_DOUT_PERI_SPI0              29
 41 #define CLK_DOUT_PERI_SPI1              30         41 #define CLK_DOUT_PERI_SPI1              30
 42 #define CLK_DOUT_PERI_UART0             31         42 #define CLK_DOUT_PERI_UART0             31
 43 #define CLK_DOUT_PERI_UART1             32         43 #define CLK_DOUT_PERI_UART1             32
 44 #define CLK_DOUT_PERI_UART2             33         44 #define CLK_DOUT_PERI_UART2             33
 45 #define CLK_DOUT_PERI_USI0              34         45 #define CLK_DOUT_PERI_USI0              34
 46 #define CLK_DOUT_PERI_USI1              35         46 #define CLK_DOUT_PERI_USI1              35
 47 #define CLK_DOUT_PERI_USI2              36         47 #define CLK_DOUT_PERI_USI2              36
 48 #define CLK_GOUT_PERI_BUS               37         48 #define CLK_GOUT_PERI_BUS               37
 49 #define CLK_GOUT_PERI_SPI0              38         49 #define CLK_GOUT_PERI_SPI0              38
 50 #define CLK_GOUT_PERI_SPI1              39         50 #define CLK_GOUT_PERI_SPI1              39
 51 #define CLK_GOUT_PERI_UART0             40         51 #define CLK_GOUT_PERI_UART0             40
 52 #define CLK_GOUT_PERI_UART1             41         52 #define CLK_GOUT_PERI_UART1             41
 53 #define CLK_GOUT_PERI_UART2             42         53 #define CLK_GOUT_PERI_UART2             42
 54 #define CLK_GOUT_PERI_USI0              43         54 #define CLK_GOUT_PERI_USI0              43
 55 #define CLK_GOUT_PERI_USI1              44         55 #define CLK_GOUT_PERI_USI1              44
 56 #define CLK_GOUT_PERI_USI2              45         56 #define CLK_GOUT_PERI_USI2              45
 57 #define CLK_MOUT_FSYS_BUS               46         57 #define CLK_MOUT_FSYS_BUS               46
 58 #define CLK_MOUT_FSYS_MMC_CARD          47         58 #define CLK_MOUT_FSYS_MMC_CARD          47
 59 #define CLK_MOUT_FSYS_MMC_EMBD          48         59 #define CLK_MOUT_FSYS_MMC_EMBD          48
 60 #define CLK_MOUT_FSYS_MMC_SDIO          49         60 #define CLK_MOUT_FSYS_MMC_SDIO          49
 61 #define CLK_MOUT_FSYS_USB30DRD          50         61 #define CLK_MOUT_FSYS_USB30DRD          50
 62 #define CLK_DOUT_FSYS_BUS               51         62 #define CLK_DOUT_FSYS_BUS               51
 63 #define CLK_DOUT_FSYS_MMC_CARD          52         63 #define CLK_DOUT_FSYS_MMC_CARD          52
 64 #define CLK_DOUT_FSYS_MMC_EMBD          53         64 #define CLK_DOUT_FSYS_MMC_EMBD          53
 65 #define CLK_DOUT_FSYS_MMC_SDIO          54         65 #define CLK_DOUT_FSYS_MMC_SDIO          54
 66 #define CLK_DOUT_FSYS_USB30DRD          55         66 #define CLK_DOUT_FSYS_USB30DRD          55
 67 #define CLK_GOUT_FSYS_BUS               56         67 #define CLK_GOUT_FSYS_BUS               56
 68 #define CLK_GOUT_FSYS_MMC_CARD          57         68 #define CLK_GOUT_FSYS_MMC_CARD          57
 69 #define CLK_GOUT_FSYS_MMC_EMBD          58         69 #define CLK_GOUT_FSYS_MMC_EMBD          58
 70 #define CLK_GOUT_FSYS_MMC_SDIO          59         70 #define CLK_GOUT_FSYS_MMC_SDIO          59
 71 #define CLK_GOUT_FSYS_USB30DRD          60         71 #define CLK_GOUT_FSYS_USB30DRD          60
 72                                                    72 
 73 /* CMU_CORE */                                     73 /* CMU_CORE */
 74 #define CLK_MOUT_CORE_BUS_USER                     74 #define CLK_MOUT_CORE_BUS_USER                  1
 75 #define CLK_MOUT_CORE_CCI_USER                     75 #define CLK_MOUT_CORE_CCI_USER                  2
 76 #define CLK_MOUT_CORE_G3D_USER                     76 #define CLK_MOUT_CORE_G3D_USER                  3
 77 #define CLK_MOUT_CORE_GIC                          77 #define CLK_MOUT_CORE_GIC                       4
 78 #define CLK_DOUT_CORE_BUSP                         78 #define CLK_DOUT_CORE_BUSP                      5
 79 #define CLK_GOUT_CCI_ACLK                          79 #define CLK_GOUT_CCI_ACLK                       6
 80 #define CLK_GOUT_GIC400_CLK                        80 #define CLK_GOUT_GIC400_CLK                     7
 81 #define CLK_GOUT_TREX_D_CORE_ACLK                  81 #define CLK_GOUT_TREX_D_CORE_ACLK               8
 82 #define CLK_GOUT_TREX_D_CORE_GCLK                  82 #define CLK_GOUT_TREX_D_CORE_GCLK               9
 83 #define CLK_GOUT_TREX_D_CORE_PCLK                  83 #define CLK_GOUT_TREX_D_CORE_PCLK               10
 84 #define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE           84 #define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE        11
 85 #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE           85 #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE        12
 86 #define CLK_GOUT_TREX_P_CORE_PCLK                  86 #define CLK_GOUT_TREX_P_CORE_PCLK               13
 87 #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE           87 #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE        14
 88                                                    88 
 89 /* CMU_PERI */                                     89 /* CMU_PERI */
 90 #define CLK_MOUT_PERI_BUS_USER          1          90 #define CLK_MOUT_PERI_BUS_USER          1
 91 #define CLK_MOUT_PERI_SPI0_USER         2          91 #define CLK_MOUT_PERI_SPI0_USER         2
 92 #define CLK_MOUT_PERI_SPI1_USER         3          92 #define CLK_MOUT_PERI_SPI1_USER         3
 93 #define CLK_MOUT_PERI_UART0_USER        4          93 #define CLK_MOUT_PERI_UART0_USER        4
 94 #define CLK_MOUT_PERI_UART1_USER        5          94 #define CLK_MOUT_PERI_UART1_USER        5
 95 #define CLK_MOUT_PERI_UART2_USER        6          95 #define CLK_MOUT_PERI_UART2_USER        6
 96 #define CLK_MOUT_PERI_USI0_USER         7          96 #define CLK_MOUT_PERI_USI0_USER         7
 97 #define CLK_MOUT_PERI_USI1_USER         8          97 #define CLK_MOUT_PERI_USI1_USER         8
 98 #define CLK_MOUT_PERI_USI2_USER         9          98 #define CLK_MOUT_PERI_USI2_USER         9
 99 #define CLK_GOUT_GPIO_TOP_PCLK          10         99 #define CLK_GOUT_GPIO_TOP_PCLK          10
100 #define CLK_GOUT_HSI2C0_PCLK            11        100 #define CLK_GOUT_HSI2C0_PCLK            11
101 #define CLK_GOUT_HSI2C1_PCLK            12        101 #define CLK_GOUT_HSI2C1_PCLK            12
102 #define CLK_GOUT_HSI2C2_PCLK            13        102 #define CLK_GOUT_HSI2C2_PCLK            13
103 #define CLK_GOUT_HSI2C3_PCLK            14        103 #define CLK_GOUT_HSI2C3_PCLK            14
104 #define CLK_GOUT_I2C0_PCLK              15        104 #define CLK_GOUT_I2C0_PCLK              15
105 #define CLK_GOUT_I2C1_PCLK              16        105 #define CLK_GOUT_I2C1_PCLK              16
106 #define CLK_GOUT_I2C2_PCLK              17        106 #define CLK_GOUT_I2C2_PCLK              17
107 #define CLK_GOUT_I2C3_PCLK              18        107 #define CLK_GOUT_I2C3_PCLK              18
108 #define CLK_GOUT_I2C4_PCLK              19        108 #define CLK_GOUT_I2C4_PCLK              19
109 #define CLK_GOUT_I2C5_PCLK              20        109 #define CLK_GOUT_I2C5_PCLK              20
110 #define CLK_GOUT_I2C6_PCLK              21        110 #define CLK_GOUT_I2C6_PCLK              21
111 #define CLK_GOUT_I2C7_PCLK              22        111 #define CLK_GOUT_I2C7_PCLK              22
112 #define CLK_GOUT_PWM_MOTOR_PCLK         23        112 #define CLK_GOUT_PWM_MOTOR_PCLK         23
113 #define CLK_GOUT_SPI0_PCLK              24        113 #define CLK_GOUT_SPI0_PCLK              24
114 #define CLK_GOUT_SPI0_EXT_CLK           25        114 #define CLK_GOUT_SPI0_EXT_CLK           25
115 #define CLK_GOUT_SPI1_PCLK              26        115 #define CLK_GOUT_SPI1_PCLK              26
116 #define CLK_GOUT_SPI1_EXT_CLK           27        116 #define CLK_GOUT_SPI1_EXT_CLK           27
117 #define CLK_GOUT_UART0_EXT_UCLK         28        117 #define CLK_GOUT_UART0_EXT_UCLK         28
118 #define CLK_GOUT_UART0_PCLK             29        118 #define CLK_GOUT_UART0_PCLK             29
119 #define CLK_GOUT_UART1_EXT_UCLK         30        119 #define CLK_GOUT_UART1_EXT_UCLK         30
120 #define CLK_GOUT_UART1_PCLK             31        120 #define CLK_GOUT_UART1_PCLK             31
121 #define CLK_GOUT_UART2_EXT_UCLK         32        121 #define CLK_GOUT_UART2_EXT_UCLK         32
122 #define CLK_GOUT_UART2_PCLK             33        122 #define CLK_GOUT_UART2_PCLK             33
123 #define CLK_GOUT_USI0_PCLK              34        123 #define CLK_GOUT_USI0_PCLK              34
124 #define CLK_GOUT_USI0_SCLK              35        124 #define CLK_GOUT_USI0_SCLK              35
125 #define CLK_GOUT_USI1_PCLK              36        125 #define CLK_GOUT_USI1_PCLK              36
126 #define CLK_GOUT_USI1_SCLK              37        126 #define CLK_GOUT_USI1_SCLK              37
127 #define CLK_GOUT_USI2_PCLK              38        127 #define CLK_GOUT_USI2_PCLK              38
128 #define CLK_GOUT_USI2_SCLK              39        128 #define CLK_GOUT_USI2_SCLK              39
129 #define CLK_GOUT_MCT_PCLK               40        129 #define CLK_GOUT_MCT_PCLK               40
130 #define CLK_GOUT_SYSREG_PERI_PCLK       41        130 #define CLK_GOUT_SYSREG_PERI_PCLK       41
131 #define CLK_GOUT_WDT0_PCLK              42        131 #define CLK_GOUT_WDT0_PCLK              42
132 #define CLK_GOUT_WDT1_PCLK              43        132 #define CLK_GOUT_WDT1_PCLK              43
133                                                   133 
134 /* CMU_FSYS */                                    134 /* CMU_FSYS */
135 #define CLK_MOUT_FSYS_BUS_USER          1         135 #define CLK_MOUT_FSYS_BUS_USER          1
136 #define CLK_MOUT_FSYS_MMC_CARD_USER     2         136 #define CLK_MOUT_FSYS_MMC_CARD_USER     2
137 #define CLK_MOUT_FSYS_MMC_EMBD_USER     3         137 #define CLK_MOUT_FSYS_MMC_EMBD_USER     3
138 #define CLK_MOUT_FSYS_MMC_SDIO_USER     4         138 #define CLK_MOUT_FSYS_MMC_SDIO_USER     4
139 #define CLK_GOUT_MMC_CARD_ACLK          5         139 #define CLK_GOUT_MMC_CARD_ACLK          5
140 #define CLK_GOUT_MMC_CARD_SDCLKIN       6         140 #define CLK_GOUT_MMC_CARD_SDCLKIN       6
141 #define CLK_GOUT_MMC_EMBD_ACLK          7         141 #define CLK_GOUT_MMC_EMBD_ACLK          7
142 #define CLK_GOUT_MMC_EMBD_SDCLKIN       8         142 #define CLK_GOUT_MMC_EMBD_SDCLKIN       8
143 #define CLK_GOUT_MMC_SDIO_ACLK          9         143 #define CLK_GOUT_MMC_SDIO_ACLK          9
144 #define CLK_GOUT_MMC_SDIO_SDCLKIN       10        144 #define CLK_GOUT_MMC_SDIO_SDCLKIN       10
145 #define CLK_MOUT_FSYS_USB30DRD_USER     11        145 #define CLK_MOUT_FSYS_USB30DRD_USER     11
146                                                   146 
147 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */     147 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
148                                                   148 

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