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TOMOYO Linux Cross Reference
Linux/include/dt-bindings/clock/exynos7885.h

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

Diff markup

Differences between /include/dt-bindings/clock/exynos7885.h (Version linux-6.12-rc7) and /include/dt-bindings/clock/exynos7885.h (Version linux-6.1.116)


  1 /* SPDX-License-Identifier: (GPL-2.0-only OR B      1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2 /*                                                  2 /*
  3  * Copyright (c) 2021 Dávid Virág                 3  * Copyright (c) 2021 Dávid Virág
  4  *                                                  4  *
  5  * Device Tree binding constants for Exynos788      5  * Device Tree binding constants for Exynos7885 clock controller.
  6  */                                                 6  */
  7                                                     7 
  8 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H            8 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H
  9 #define _DT_BINDINGS_CLOCK_EXYNOS_7885_H            9 #define _DT_BINDINGS_CLOCK_EXYNOS_7885_H
 10                                                    10 
 11 /* CMU_TOP */                                      11 /* CMU_TOP */
 12 #define CLK_FOUT_SHARED0_PLL            1          12 #define CLK_FOUT_SHARED0_PLL            1
 13 #define CLK_FOUT_SHARED1_PLL            2          13 #define CLK_FOUT_SHARED1_PLL            2
 14 #define CLK_DOUT_SHARED0_DIV2           3          14 #define CLK_DOUT_SHARED0_DIV2           3
 15 #define CLK_DOUT_SHARED0_DIV3           4          15 #define CLK_DOUT_SHARED0_DIV3           4
 16 #define CLK_DOUT_SHARED0_DIV4           5          16 #define CLK_DOUT_SHARED0_DIV4           5
 17 #define CLK_DOUT_SHARED0_DIV5           6          17 #define CLK_DOUT_SHARED0_DIV5           6
 18 #define CLK_DOUT_SHARED1_DIV2           7          18 #define CLK_DOUT_SHARED1_DIV2           7
 19 #define CLK_DOUT_SHARED1_DIV3           8          19 #define CLK_DOUT_SHARED1_DIV3           8
 20 #define CLK_DOUT_SHARED1_DIV4           9          20 #define CLK_DOUT_SHARED1_DIV4           9
 21 #define CLK_MOUT_CORE_BUS               10         21 #define CLK_MOUT_CORE_BUS               10
 22 #define CLK_MOUT_CORE_CCI               11         22 #define CLK_MOUT_CORE_CCI               11
 23 #define CLK_MOUT_CORE_G3D               12         23 #define CLK_MOUT_CORE_G3D               12
 24 #define CLK_DOUT_CORE_BUS               13         24 #define CLK_DOUT_CORE_BUS               13
 25 #define CLK_DOUT_CORE_CCI               14         25 #define CLK_DOUT_CORE_CCI               14
 26 #define CLK_DOUT_CORE_G3D               15         26 #define CLK_DOUT_CORE_G3D               15
 27 #define CLK_GOUT_CORE_BUS               16         27 #define CLK_GOUT_CORE_BUS               16
 28 #define CLK_GOUT_CORE_CCI               17         28 #define CLK_GOUT_CORE_CCI               17
 29 #define CLK_GOUT_CORE_G3D               18         29 #define CLK_GOUT_CORE_G3D               18
 30 #define CLK_MOUT_PERI_BUS               19         30 #define CLK_MOUT_PERI_BUS               19
 31 #define CLK_MOUT_PERI_SPI0              20         31 #define CLK_MOUT_PERI_SPI0              20
 32 #define CLK_MOUT_PERI_SPI1              21         32 #define CLK_MOUT_PERI_SPI1              21
 33 #define CLK_MOUT_PERI_UART0             22         33 #define CLK_MOUT_PERI_UART0             22
 34 #define CLK_MOUT_PERI_UART1             23         34 #define CLK_MOUT_PERI_UART1             23
 35 #define CLK_MOUT_PERI_UART2             24         35 #define CLK_MOUT_PERI_UART2             24
 36 #define CLK_MOUT_PERI_USI0              25         36 #define CLK_MOUT_PERI_USI0              25
 37 #define CLK_MOUT_PERI_USI1              26         37 #define CLK_MOUT_PERI_USI1              26
 38 #define CLK_MOUT_PERI_USI2              27         38 #define CLK_MOUT_PERI_USI2              27
 39 #define CLK_DOUT_PERI_BUS               28         39 #define CLK_DOUT_PERI_BUS               28
 40 #define CLK_DOUT_PERI_SPI0              29         40 #define CLK_DOUT_PERI_SPI0              29
 41 #define CLK_DOUT_PERI_SPI1              30         41 #define CLK_DOUT_PERI_SPI1              30
 42 #define CLK_DOUT_PERI_UART0             31         42 #define CLK_DOUT_PERI_UART0             31
 43 #define CLK_DOUT_PERI_UART1             32         43 #define CLK_DOUT_PERI_UART1             32
 44 #define CLK_DOUT_PERI_UART2             33         44 #define CLK_DOUT_PERI_UART2             33
 45 #define CLK_DOUT_PERI_USI0              34         45 #define CLK_DOUT_PERI_USI0              34
 46 #define CLK_DOUT_PERI_USI1              35         46 #define CLK_DOUT_PERI_USI1              35
 47 #define CLK_DOUT_PERI_USI2              36         47 #define CLK_DOUT_PERI_USI2              36
 48 #define CLK_GOUT_PERI_BUS               37         48 #define CLK_GOUT_PERI_BUS               37
 49 #define CLK_GOUT_PERI_SPI0              38         49 #define CLK_GOUT_PERI_SPI0              38
 50 #define CLK_GOUT_PERI_SPI1              39         50 #define CLK_GOUT_PERI_SPI1              39
 51 #define CLK_GOUT_PERI_UART0             40         51 #define CLK_GOUT_PERI_UART0             40
 52 #define CLK_GOUT_PERI_UART1             41         52 #define CLK_GOUT_PERI_UART1             41
 53 #define CLK_GOUT_PERI_UART2             42         53 #define CLK_GOUT_PERI_UART2             42
 54 #define CLK_GOUT_PERI_USI0              43         54 #define CLK_GOUT_PERI_USI0              43
 55 #define CLK_GOUT_PERI_USI1              44         55 #define CLK_GOUT_PERI_USI1              44
 56 #define CLK_GOUT_PERI_USI2              45         56 #define CLK_GOUT_PERI_USI2              45
 57 #define CLK_MOUT_FSYS_BUS               46         57 #define CLK_MOUT_FSYS_BUS               46
 58 #define CLK_MOUT_FSYS_MMC_CARD          47         58 #define CLK_MOUT_FSYS_MMC_CARD          47
 59 #define CLK_MOUT_FSYS_MMC_EMBD          48         59 #define CLK_MOUT_FSYS_MMC_EMBD          48
 60 #define CLK_MOUT_FSYS_MMC_SDIO          49         60 #define CLK_MOUT_FSYS_MMC_SDIO          49
 61 #define CLK_MOUT_FSYS_USB30DRD          50         61 #define CLK_MOUT_FSYS_USB30DRD          50
 62 #define CLK_DOUT_FSYS_BUS               51         62 #define CLK_DOUT_FSYS_BUS               51
 63 #define CLK_DOUT_FSYS_MMC_CARD          52         63 #define CLK_DOUT_FSYS_MMC_CARD          52
 64 #define CLK_DOUT_FSYS_MMC_EMBD          53         64 #define CLK_DOUT_FSYS_MMC_EMBD          53
 65 #define CLK_DOUT_FSYS_MMC_SDIO          54         65 #define CLK_DOUT_FSYS_MMC_SDIO          54
 66 #define CLK_DOUT_FSYS_USB30DRD          55         66 #define CLK_DOUT_FSYS_USB30DRD          55
 67 #define CLK_GOUT_FSYS_BUS               56         67 #define CLK_GOUT_FSYS_BUS               56
 68 #define CLK_GOUT_FSYS_MMC_CARD          57         68 #define CLK_GOUT_FSYS_MMC_CARD          57
 69 #define CLK_GOUT_FSYS_MMC_EMBD          58         69 #define CLK_GOUT_FSYS_MMC_EMBD          58
 70 #define CLK_GOUT_FSYS_MMC_SDIO          59         70 #define CLK_GOUT_FSYS_MMC_SDIO          59
 71 #define CLK_GOUT_FSYS_USB30DRD          60         71 #define CLK_GOUT_FSYS_USB30DRD          60
 72 #define CLK_MOUT_SHARED0_PLL            61     !!  72 #define TOP_NR_CLK                      61
 73 #define CLK_MOUT_SHARED1_PLL            62     << 
 74                                                    73 
 75 /* CMU_CORE */                                     74 /* CMU_CORE */
 76 #define CLK_MOUT_CORE_BUS_USER                     75 #define CLK_MOUT_CORE_BUS_USER                  1
 77 #define CLK_MOUT_CORE_CCI_USER                     76 #define CLK_MOUT_CORE_CCI_USER                  2
 78 #define CLK_MOUT_CORE_G3D_USER                     77 #define CLK_MOUT_CORE_G3D_USER                  3
 79 #define CLK_MOUT_CORE_GIC                          78 #define CLK_MOUT_CORE_GIC                       4
 80 #define CLK_DOUT_CORE_BUSP                         79 #define CLK_DOUT_CORE_BUSP                      5
 81 #define CLK_GOUT_CCI_ACLK                          80 #define CLK_GOUT_CCI_ACLK                       6
 82 #define CLK_GOUT_GIC400_CLK                        81 #define CLK_GOUT_GIC400_CLK                     7
 83 #define CLK_GOUT_TREX_D_CORE_ACLK                  82 #define CLK_GOUT_TREX_D_CORE_ACLK               8
 84 #define CLK_GOUT_TREX_D_CORE_GCLK                  83 #define CLK_GOUT_TREX_D_CORE_GCLK               9
 85 #define CLK_GOUT_TREX_D_CORE_PCLK                  84 #define CLK_GOUT_TREX_D_CORE_PCLK               10
 86 #define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE           85 #define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE        11
 87 #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE           86 #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE        12
 88 #define CLK_GOUT_TREX_P_CORE_PCLK                  87 #define CLK_GOUT_TREX_P_CORE_PCLK               13
 89 #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE           88 #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE        14
                                                   >>  89 #define CORE_NR_CLK                             15
 90                                                    90 
 91 /* CMU_PERI */                                     91 /* CMU_PERI */
 92 #define CLK_MOUT_PERI_BUS_USER          1          92 #define CLK_MOUT_PERI_BUS_USER          1
 93 #define CLK_MOUT_PERI_SPI0_USER         2          93 #define CLK_MOUT_PERI_SPI0_USER         2
 94 #define CLK_MOUT_PERI_SPI1_USER         3          94 #define CLK_MOUT_PERI_SPI1_USER         3
 95 #define CLK_MOUT_PERI_UART0_USER        4          95 #define CLK_MOUT_PERI_UART0_USER        4
 96 #define CLK_MOUT_PERI_UART1_USER        5          96 #define CLK_MOUT_PERI_UART1_USER        5
 97 #define CLK_MOUT_PERI_UART2_USER        6          97 #define CLK_MOUT_PERI_UART2_USER        6
 98 #define CLK_MOUT_PERI_USI0_USER         7          98 #define CLK_MOUT_PERI_USI0_USER         7
 99 #define CLK_MOUT_PERI_USI1_USER         8          99 #define CLK_MOUT_PERI_USI1_USER         8
100 #define CLK_MOUT_PERI_USI2_USER         9         100 #define CLK_MOUT_PERI_USI2_USER         9
101 #define CLK_GOUT_GPIO_TOP_PCLK          10        101 #define CLK_GOUT_GPIO_TOP_PCLK          10
102 #define CLK_GOUT_HSI2C0_PCLK            11        102 #define CLK_GOUT_HSI2C0_PCLK            11
103 #define CLK_GOUT_HSI2C1_PCLK            12        103 #define CLK_GOUT_HSI2C1_PCLK            12
104 #define CLK_GOUT_HSI2C2_PCLK            13        104 #define CLK_GOUT_HSI2C2_PCLK            13
105 #define CLK_GOUT_HSI2C3_PCLK            14        105 #define CLK_GOUT_HSI2C3_PCLK            14
106 #define CLK_GOUT_I2C0_PCLK              15        106 #define CLK_GOUT_I2C0_PCLK              15
107 #define CLK_GOUT_I2C1_PCLK              16        107 #define CLK_GOUT_I2C1_PCLK              16
108 #define CLK_GOUT_I2C2_PCLK              17        108 #define CLK_GOUT_I2C2_PCLK              17
109 #define CLK_GOUT_I2C3_PCLK              18        109 #define CLK_GOUT_I2C3_PCLK              18
110 #define CLK_GOUT_I2C4_PCLK              19        110 #define CLK_GOUT_I2C4_PCLK              19
111 #define CLK_GOUT_I2C5_PCLK              20        111 #define CLK_GOUT_I2C5_PCLK              20
112 #define CLK_GOUT_I2C6_PCLK              21        112 #define CLK_GOUT_I2C6_PCLK              21
113 #define CLK_GOUT_I2C7_PCLK              22        113 #define CLK_GOUT_I2C7_PCLK              22
114 #define CLK_GOUT_PWM_MOTOR_PCLK         23        114 #define CLK_GOUT_PWM_MOTOR_PCLK         23
115 #define CLK_GOUT_SPI0_PCLK              24        115 #define CLK_GOUT_SPI0_PCLK              24
116 #define CLK_GOUT_SPI0_EXT_CLK           25        116 #define CLK_GOUT_SPI0_EXT_CLK           25
117 #define CLK_GOUT_SPI1_PCLK              26        117 #define CLK_GOUT_SPI1_PCLK              26
118 #define CLK_GOUT_SPI1_EXT_CLK           27        118 #define CLK_GOUT_SPI1_EXT_CLK           27
119 #define CLK_GOUT_UART0_EXT_UCLK         28        119 #define CLK_GOUT_UART0_EXT_UCLK         28
120 #define CLK_GOUT_UART0_PCLK             29        120 #define CLK_GOUT_UART0_PCLK             29
121 #define CLK_GOUT_UART1_EXT_UCLK         30        121 #define CLK_GOUT_UART1_EXT_UCLK         30
122 #define CLK_GOUT_UART1_PCLK             31        122 #define CLK_GOUT_UART1_PCLK             31
123 #define CLK_GOUT_UART2_EXT_UCLK         32        123 #define CLK_GOUT_UART2_EXT_UCLK         32
124 #define CLK_GOUT_UART2_PCLK             33        124 #define CLK_GOUT_UART2_PCLK             33
125 #define CLK_GOUT_USI0_PCLK              34        125 #define CLK_GOUT_USI0_PCLK              34
126 #define CLK_GOUT_USI0_SCLK              35        126 #define CLK_GOUT_USI0_SCLK              35
127 #define CLK_GOUT_USI1_PCLK              36        127 #define CLK_GOUT_USI1_PCLK              36
128 #define CLK_GOUT_USI1_SCLK              37        128 #define CLK_GOUT_USI1_SCLK              37
129 #define CLK_GOUT_USI2_PCLK              38        129 #define CLK_GOUT_USI2_PCLK              38
130 #define CLK_GOUT_USI2_SCLK              39        130 #define CLK_GOUT_USI2_SCLK              39
131 #define CLK_GOUT_MCT_PCLK               40        131 #define CLK_GOUT_MCT_PCLK               40
132 #define CLK_GOUT_SYSREG_PERI_PCLK       41        132 #define CLK_GOUT_SYSREG_PERI_PCLK       41
133 #define CLK_GOUT_WDT0_PCLK              42        133 #define CLK_GOUT_WDT0_PCLK              42
134 #define CLK_GOUT_WDT1_PCLK              43        134 #define CLK_GOUT_WDT1_PCLK              43
                                                   >> 135 #define PERI_NR_CLK                     44
135                                                   136 
136 /* CMU_FSYS */                                    137 /* CMU_FSYS */
137 #define CLK_MOUT_FSYS_BUS_USER                 !! 138 #define CLK_MOUT_FSYS_BUS_USER          1
138 #define CLK_MOUT_FSYS_MMC_CARD_USER            !! 139 #define CLK_MOUT_FSYS_MMC_CARD_USER     2
139 #define CLK_MOUT_FSYS_MMC_EMBD_USER            !! 140 #define CLK_MOUT_FSYS_MMC_EMBD_USER     3
140 #define CLK_MOUT_FSYS_MMC_SDIO_USER            !! 141 #define CLK_MOUT_FSYS_MMC_SDIO_USER     4
141 #define CLK_GOUT_MMC_CARD_ACLK                 !! 142 #define CLK_GOUT_MMC_CARD_ACLK          5
142 #define CLK_GOUT_MMC_CARD_SDCLKIN              !! 143 #define CLK_GOUT_MMC_CARD_SDCLKIN       6
143 #define CLK_GOUT_MMC_EMBD_ACLK                 !! 144 #define CLK_GOUT_MMC_EMBD_ACLK          7
144 #define CLK_GOUT_MMC_EMBD_SDCLKIN              !! 145 #define CLK_GOUT_MMC_EMBD_SDCLKIN       8
145 #define CLK_GOUT_MMC_SDIO_ACLK                 !! 146 #define CLK_GOUT_MMC_SDIO_ACLK          9
146 #define CLK_GOUT_MMC_SDIO_SDCLKIN              !! 147 #define CLK_GOUT_MMC_SDIO_SDCLKIN       10
147 #define CLK_MOUT_FSYS_USB30DRD_USER            !! 148 #define CLK_MOUT_FSYS_USB30DRD_USER     11
148 #define CLK_MOUT_USB_PLL                       !! 149 #define FSYS_NR_CLK                     12
149 #define CLK_FOUT_USB_PLL                       << 
150 #define CLK_FSYS_USB20PHY_CLKCORE              << 
151 #define CLK_FSYS_USB30DRD_ACLK_20PHYCTRL       << 
152 #define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0     << 
153 #define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1     << 
154 #define CLK_FSYS_USB30DRD_BUS_CLK_EARLY        << 
155 #define CLK_FSYS_USB30DRD_REF_CLK              << 
156                                                   150 
157 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */     151 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
158                                                   152 

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