Linux/include/dt-bindings/clock/exynos850.h

Version: ~ [ linux-6.11.5 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.58 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.114 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.169 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.228 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.284 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.322 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.9 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 2 /* 3 * Copyright (C) 2021 Linaro Ltd. 3 * Copyright (C) 2021 Linaro Ltd. 4 * Author: Sam Protsenko <semen.protsenko@lina 4 * Author: Sam Protsenko <semen.protsenko@linaro.org> 5 * 5 * 6 * Device Tree binding constants for Exynos850 6 * Device Tree binding constants for Exynos850 clock controller. 7 */ 7 */ 8 8 9 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H 9 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H 10 #define _DT_BINDINGS_CLOCK_EXYNOS_850_H 10 #define _DT_BINDINGS_CLOCK_EXYNOS_850_H 11 11 12 /* CMU_TOP */ 12 /* CMU_TOP */ 13 #define CLK_FOUT_SHARED0_PLL 1 13 #define CLK_FOUT_SHARED0_PLL 1 14 #define CLK_FOUT_SHARED1_PLL 2 14 #define CLK_FOUT_SHARED1_PLL 2 15 #define CLK_FOUT_MMC_PLL 3 15 #define CLK_FOUT_MMC_PLL 3 16 #define CLK_MOUT_SHARED0_PLL 4 16 #define CLK_MOUT_SHARED0_PLL 4 17 #define CLK_MOUT_SHARED1_PLL 5 17 #define CLK_MOUT_SHARED1_PLL 5 18 #define CLK_MOUT_MMC_PLL 6 18 #define CLK_MOUT_MMC_PLL 6 19 #define CLK_MOUT_CORE_BUS 7 19 #define CLK_MOUT_CORE_BUS 7 20 #define CLK_MOUT_CORE_CCI 8 20 #define CLK_MOUT_CORE_CCI 8 21 #define CLK_MOUT_CORE_MMC_EMBD 9 21 #define CLK_MOUT_CORE_MMC_EMBD 9 22 #define CLK_MOUT_CORE_SSS 10 22 #define CLK_MOUT_CORE_SSS 10 23 #define CLK_MOUT_DPU 11 23 #define CLK_MOUT_DPU 11 24 #define CLK_MOUT_HSI_BUS 12 24 #define CLK_MOUT_HSI_BUS 12 25 #define CLK_MOUT_HSI_MMC_CARD 13 25 #define CLK_MOUT_HSI_MMC_CARD 13 26 #define CLK_MOUT_HSI_USB20DRD 14 26 #define CLK_MOUT_HSI_USB20DRD 14 27 #define CLK_MOUT_PERI_BUS 15 27 #define CLK_MOUT_PERI_BUS 15 28 #define CLK_MOUT_PERI_UART 16 28 #define CLK_MOUT_PERI_UART 16 29 #define CLK_MOUT_PERI_IP 17 29 #define CLK_MOUT_PERI_IP 17 30 #define CLK_DOUT_SHARED0_DIV3 18 30 #define CLK_DOUT_SHARED0_DIV3 18 31 #define CLK_DOUT_SHARED0_DIV2 19 31 #define CLK_DOUT_SHARED0_DIV2 19 32 #define CLK_DOUT_SHARED1_DIV3 20 32 #define CLK_DOUT_SHARED1_DIV3 20 33 #define CLK_DOUT_SHARED1_DIV2 21 33 #define CLK_DOUT_SHARED1_DIV2 21 34 #define CLK_DOUT_SHARED0_DIV4 22 34 #define CLK_DOUT_SHARED0_DIV4 22 35 #define CLK_DOUT_SHARED1_DIV4 23 35 #define CLK_DOUT_SHARED1_DIV4 23 36 #define CLK_DOUT_CORE_BUS 24 36 #define CLK_DOUT_CORE_BUS 24 37 #define CLK_DOUT_CORE_CCI 25 37 #define CLK_DOUT_CORE_CCI 25 38 #define CLK_DOUT_CORE_MMC_EMBD 26 38 #define CLK_DOUT_CORE_MMC_EMBD 26 39 #define CLK_DOUT_CORE_SSS 27 39 #define CLK_DOUT_CORE_SSS 27 40 #define CLK_DOUT_DPU 28 40 #define CLK_DOUT_DPU 28 41 #define CLK_DOUT_HSI_BUS 29 41 #define CLK_DOUT_HSI_BUS 29 42 #define CLK_DOUT_HSI_MMC_CARD 30 42 #define CLK_DOUT_HSI_MMC_CARD 30 43 #define CLK_DOUT_HSI_USB20DRD 31 43 #define CLK_DOUT_HSI_USB20DRD 31 44 #define CLK_DOUT_PERI_BUS 32 44 #define CLK_DOUT_PERI_BUS 32 45 #define CLK_DOUT_PERI_UART 33 45 #define CLK_DOUT_PERI_UART 33 46 #define CLK_DOUT_PERI_IP 34 46 #define CLK_DOUT_PERI_IP 34 47 #define CLK_GOUT_CORE_BUS 35 47 #define CLK_GOUT_CORE_BUS 35 48 #define CLK_GOUT_CORE_CCI 36 48 #define CLK_GOUT_CORE_CCI 36 49 #define CLK_GOUT_CORE_MMC_EMBD 37 49 #define CLK_GOUT_CORE_MMC_EMBD 37 50 #define CLK_GOUT_CORE_SSS 38 50 #define CLK_GOUT_CORE_SSS 38 51 #define CLK_GOUT_DPU 39 51 #define CLK_GOUT_DPU 39 52 #define CLK_GOUT_HSI_BUS 40 52 #define CLK_GOUT_HSI_BUS 40 53 #define CLK_GOUT_HSI_MMC_CARD 41 53 #define CLK_GOUT_HSI_MMC_CARD 41 54 #define CLK_GOUT_HSI_USB20DRD 42 54 #define CLK_GOUT_HSI_USB20DRD 42 55 #define CLK_GOUT_PERI_BUS 43 55 #define CLK_GOUT_PERI_BUS 43 56 #define CLK_GOUT_PERI_UART 44 56 #define CLK_GOUT_PERI_UART 44 57 #define CLK_GOUT_PERI_IP 45 57 #define CLK_GOUT_PERI_IP 45 58 #define CLK_MOUT_CLKCMU_APM_BUS 46 58 #define CLK_MOUT_CLKCMU_APM_BUS 46 59 #define CLK_DOUT_CLKCMU_APM_BUS 47 59 #define CLK_DOUT_CLKCMU_APM_BUS 47 60 #define CLK_GOUT_CLKCMU_APM_BUS 48 60 #define CLK_GOUT_CLKCMU_APM_BUS 48 61 #define CLK_MOUT_AUD 49 !! 61 #define TOP_NR_CLK 49 62 #define CLK_GOUT_AUD 50 << 63 #define CLK_DOUT_AUD 51 << 64 #define CLK_MOUT_IS_BUS 52 << 65 #define CLK_MOUT_IS_ITP 53 << 66 #define CLK_MOUT_IS_VRA 54 << 67 #define CLK_MOUT_IS_GDC 55 << 68 #define CLK_GOUT_IS_BUS 56 << 69 #define CLK_GOUT_IS_ITP 57 << 70 #define CLK_GOUT_IS_VRA 58 << 71 #define CLK_GOUT_IS_GDC 59 << 72 #define CLK_DOUT_IS_BUS 60 << 73 #define CLK_DOUT_IS_ITP 61 << 74 #define CLK_DOUT_IS_VRA 62 << 75 #define CLK_DOUT_IS_GDC 63 << 76 #define CLK_MOUT_MFCMSCL_MFC 64 << 77 #define CLK_MOUT_MFCMSCL_M2M 65 << 78 #define CLK_MOUT_MFCMSCL_MCSC 66 << 79 #define CLK_MOUT_MFCMSCL_JPEG 67 << 80 #define CLK_GOUT_MFCMSCL_MFC 68 << 81 #define CLK_GOUT_MFCMSCL_M2M 69 << 82 #define CLK_GOUT_MFCMSCL_MCSC 70 << 83 #define CLK_GOUT_MFCMSCL_JPEG 71 << 84 #define CLK_DOUT_MFCMSCL_MFC 72 << 85 #define CLK_DOUT_MFCMSCL_M2M 73 << 86 #define CLK_DOUT_MFCMSCL_MCSC 74 << 87 #define CLK_DOUT_MFCMSCL_JPEG 75 << 88 #define CLK_MOUT_G3D_SWITCH 76 << 89 #define CLK_GOUT_G3D_SWITCH 77 << 90 #define CLK_DOUT_G3D_SWITCH 78 << 91 #define CLK_MOUT_CPUCL0_DBG 79 << 92 #define CLK_MOUT_CPUCL0_SWITCH 80 << 93 #define CLK_GOUT_CPUCL0_DBG 81 << 94 #define CLK_GOUT_CPUCL0_SWITCH 82 << 95 #define CLK_DOUT_CPUCL0_DBG 83 << 96 #define CLK_DOUT_CPUCL0_SWITCH 84 << 97 #define CLK_MOUT_CPUCL1_DBG 85 << 98 #define CLK_MOUT_CPUCL1_SWITCH 86 << 99 #define CLK_GOUT_CPUCL1_DBG 87 << 100 #define CLK_GOUT_CPUCL1_SWITCH 88 << 101 #define CLK_DOUT_CPUCL1_DBG 89 << 102 #define CLK_DOUT_CPUCL1_SWITCH 90 << 103 62 104 /* CMU_APM */ 63 /* CMU_APM */ 105 #define CLK_RCO_I3C_PMIC 1 64 #define CLK_RCO_I3C_PMIC 1 106 #define OSCCLK_RCO_APM 2 65 #define OSCCLK_RCO_APM 2 107 #define CLK_RCO_APM__ALV 3 66 #define CLK_RCO_APM__ALV 3 108 #define CLK_DLL_DCO 4 67 #define CLK_DLL_DCO 4 109 #define CLK_MOUT_APM_BUS_USER 5 68 #define CLK_MOUT_APM_BUS_USER 5 110 #define CLK_MOUT_RCO_APM_I3C_USER 6 69 #define CLK_MOUT_RCO_APM_I3C_USER 6 111 #define CLK_MOUT_RCO_APM_USER 7 70 #define CLK_MOUT_RCO_APM_USER 7 112 #define CLK_MOUT_DLL_USER 8 71 #define CLK_MOUT_DLL_USER 8 113 #define CLK_MOUT_CLKCMU_CHUB_BUS 9 72 #define CLK_MOUT_CLKCMU_CHUB_BUS 9 114 #define CLK_MOUT_APM_BUS 10 73 #define CLK_MOUT_APM_BUS 10 115 #define CLK_MOUT_APM_I3C 11 74 #define CLK_MOUT_APM_I3C 11 116 #define CLK_DOUT_CLKCMU_CHUB_BUS 12 75 #define CLK_DOUT_CLKCMU_CHUB_BUS 12 117 #define CLK_DOUT_APM_BUS 13 76 #define CLK_DOUT_APM_BUS 13 118 #define CLK_DOUT_APM_I3C 14 77 #define CLK_DOUT_APM_I3C 14 119 #define CLK_GOUT_CLKCMU_CMGP_BUS 15 78 #define CLK_GOUT_CLKCMU_CMGP_BUS 15 120 #define CLK_GOUT_CLKCMU_CHUB_BUS 16 79 #define CLK_GOUT_CLKCMU_CHUB_BUS 16 121 #define CLK_GOUT_RTC_PCLK 17 80 #define CLK_GOUT_RTC_PCLK 17 122 #define CLK_GOUT_TOP_RTC_PCLK 18 81 #define CLK_GOUT_TOP_RTC_PCLK 18 123 #define CLK_GOUT_I3C_PCLK 19 82 #define CLK_GOUT_I3C_PCLK 19 124 #define CLK_GOUT_I3C_SCLK 20 83 #define CLK_GOUT_I3C_SCLK 20 125 #define CLK_GOUT_SPEEDY_PCLK 21 84 #define CLK_GOUT_SPEEDY_PCLK 21 126 #define CLK_GOUT_GPIO_ALIVE_PCLK 22 85 #define CLK_GOUT_GPIO_ALIVE_PCLK 22 127 #define CLK_GOUT_PMU_ALIVE_PCLK 23 86 #define CLK_GOUT_PMU_ALIVE_PCLK 23 128 #define CLK_GOUT_SYSREG_APM_PCLK 24 87 #define CLK_GOUT_SYSREG_APM_PCLK 24 129 !! 88 #define APM_NR_CLK 25 130 /* CMU_AUD */ << 131 #define CLK_DOUT_AUD_AUDIF 1 << 132 #define CLK_DOUT_AUD_BUSD 2 << 133 #define CLK_DOUT_AUD_BUSP 3 << 134 #define CLK_DOUT_AUD_CNT 4 << 135 #define CLK_DOUT_AUD_CPU 5 << 136 #define CLK_DOUT_AUD_CPU_ACLK 6 << 137 #define CLK_DOUT_AUD_CPU_PCLKDBG 7 << 138 #define CLK_DOUT_AUD_FM 8 << 139 #define CLK_DOUT_AUD_FM_SPDY 9 << 140 #define CLK_DOUT_AUD_MCLK 10 << 141 #define CLK_DOUT_AUD_UAIF0 11 << 142 #define CLK_DOUT_AUD_UAIF1 12 << 143 #define CLK_DOUT_AUD_UAIF2 13 << 144 #define CLK_DOUT_AUD_UAIF3 14 << 145 #define CLK_DOUT_AUD_UAIF4 15 << 146 #define CLK_DOUT_AUD_UAIF5 16 << 147 #define CLK_DOUT_AUD_UAIF6 17 << 148 #define CLK_FOUT_AUD_PLL 18 << 149 #define CLK_GOUT_AUD_ABOX_ACLK 19 << 150 #define CLK_GOUT_AUD_ASB_CCLK 20 << 151 #define CLK_GOUT_AUD_CA32_CCLK 21 << 152 #define CLK_GOUT_AUD_CNT_BCLK 22 << 153 #define CLK_GOUT_AUD_CODEC_MCLK 23 << 154 #define CLK_GOUT_AUD_DAP_CCLK 24 << 155 #define CLK_GOUT_AUD_GPIO_PCLK 25 << 156 #define CLK_GOUT_AUD_PPMU_ACLK 26 << 157 #define CLK_GOUT_AUD_PPMU_PCLK 27 << 158 #define CLK_GOUT_AUD_SPDY_BCLK 28 << 159 #define CLK_GOUT_AUD_SYSMMU_CLK 29 << 160 #define CLK_GOUT_AUD_SYSREG_PCLK 30 << 161 #define CLK_GOUT_AUD_TZPC_PCLK 31 << 162 #define CLK_GOUT_AUD_UAIF0_BCLK 32 << 163 #define CLK_GOUT_AUD_UAIF1_BCLK 33 << 164 #define CLK_GOUT_AUD_UAIF2_BCLK 34 << 165 #define CLK_GOUT_AUD_UAIF3_BCLK 35 << 166 #define CLK_GOUT_AUD_UAIF4_BCLK 36 << 167 #define CLK_GOUT_AUD_UAIF5_BCLK 37 << 168 #define CLK_GOUT_AUD_UAIF6_BCLK 38 << 169 #define CLK_GOUT_AUD_WDT_PCLK 39 << 170 #define CLK_MOUT_AUD_CPU 40 << 171 #define CLK_MOUT_AUD_CPU_HCH 41 << 172 #define CLK_MOUT_AUD_CPU_USER 42 << 173 #define CLK_MOUT_AUD_FM 43 << 174 #define CLK_MOUT_AUD_PLL 44 << 175 #define CLK_MOUT_AUD_TICK_USB_USER 45 << 176 #define CLK_MOUT_AUD_UAIF0 46 << 177 #define CLK_MOUT_AUD_UAIF1 47 << 178 #define CLK_MOUT_AUD_UAIF2 48 << 179 #define CLK_MOUT_AUD_UAIF3 49 << 180 #define CLK_MOUT_AUD_UAIF4 50 << 181 #define CLK_MOUT_AUD_UAIF5 51 << 182 #define CLK_MOUT_AUD_UAIF6 52 << 183 #define IOCLK_AUDIOCDCLK0 53 << 184 #define IOCLK_AUDIOCDCLK1 54 << 185 #define IOCLK_AUDIOCDCLK2 55 << 186 #define IOCLK_AUDIOCDCLK3 56 << 187 #define IOCLK_AUDIOCDCLK4 57 << 188 #define IOCLK_AUDIOCDCLK5 58 << 189 #define IOCLK_AUDIOCDCLK6 59 << 190 #define TICK_USB 60 << 191 #define CLK_GOUT_AUD_CMU_AUD_PCLK 61 << 192 89 193 /* CMU_CMGP */ 90 /* CMU_CMGP */ 194 #define CLK_RCO_CMGP 1 91 #define CLK_RCO_CMGP 1 195 #define CLK_MOUT_CMGP_ADC 2 92 #define CLK_MOUT_CMGP_ADC 2 196 #define CLK_MOUT_CMGP_USI0 3 93 #define CLK_MOUT_CMGP_USI0 3 197 #define CLK_MOUT_CMGP_USI1 4 94 #define CLK_MOUT_CMGP_USI1 4 198 #define CLK_DOUT_CMGP_ADC 5 95 #define CLK_DOUT_CMGP_ADC 5 199 #define CLK_DOUT_CMGP_USI0 6 96 #define CLK_DOUT_CMGP_USI0 6 200 #define CLK_DOUT_CMGP_USI1 7 97 #define CLK_DOUT_CMGP_USI1 7 201 #define CLK_GOUT_CMGP_ADC_S0_PCLK 8 98 #define CLK_GOUT_CMGP_ADC_S0_PCLK 8 202 #define CLK_GOUT_CMGP_ADC_S1_PCLK 9 99 #define CLK_GOUT_CMGP_ADC_S1_PCLK 9 203 #define CLK_GOUT_CMGP_GPIO_PCLK 10 100 #define CLK_GOUT_CMGP_GPIO_PCLK 10 204 #define CLK_GOUT_CMGP_USI0_IPCLK 11 101 #define CLK_GOUT_CMGP_USI0_IPCLK 11 205 #define CLK_GOUT_CMGP_USI0_PCLK 12 102 #define CLK_GOUT_CMGP_USI0_PCLK 12 206 #define CLK_GOUT_CMGP_USI1_IPCLK 13 103 #define CLK_GOUT_CMGP_USI1_IPCLK 13 207 #define CLK_GOUT_CMGP_USI1_PCLK 14 104 #define CLK_GOUT_CMGP_USI1_PCLK 14 208 #define CLK_GOUT_SYSREG_CMGP_PCLK 15 105 #define CLK_GOUT_SYSREG_CMGP_PCLK 15 209 !! 106 #define CMGP_NR_CLK 16 210 /* CMU_CPUCL0 */ << 211 #define CLK_FOUT_CPUCL0_PLL 1 << 212 #define CLK_MOUT_PLL_CPUCL0 2 << 213 #define CLK_MOUT_CPUCL0_SWITCH_USER 3 << 214 #define CLK_MOUT_CPUCL0_DBG_USER 4 << 215 #define CLK_MOUT_CPUCL0_PLL 5 << 216 #define CLK_DOUT_CPUCL0_CPU 6 << 217 #define CLK_DOUT_CPUCL0_CMUREF 7 << 218 #define CLK_DOUT_CPUCL0_PCLK 8 << 219 #define CLK_DOUT_CLUSTER0_ACLK 9 << 220 #define CLK_DOUT_CLUSTER0_ATCLK 10 << 221 #define CLK_DOUT_CLUSTER0_PCLKDBG 11 << 222 #define CLK_DOUT_CLUSTER0_PERIPHCLK 12 << 223 #define CLK_GOUT_CLUSTER0_ATCLK 13 << 224 #define CLK_GOUT_CLUSTER0_PCLK 14 << 225 #define CLK_GOUT_CLUSTER0_PERIPHCLK 15 << 226 #define CLK_GOUT_CLUSTER0_SCLK 16 << 227 #define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK 17 << 228 #define CLK_GOUT_CLUSTER0_CPU 18 << 229 #define CLK_CLUSTER0_SCLK 19 << 230 << 231 /* CMU_CPUCL1 */ << 232 #define CLK_FOUT_CPUCL1_PLL 1 << 233 #define CLK_MOUT_PLL_CPUCL1 2 << 234 #define CLK_MOUT_CPUCL1_SWITCH_USER 3 << 235 #define CLK_MOUT_CPUCL1_DBG_USER 4 << 236 #define CLK_MOUT_CPUCL1_PLL 5 << 237 #define CLK_DOUT_CPUCL1_CPU 6 << 238 #define CLK_DOUT_CPUCL1_CMUREF 7 << 239 #define CLK_DOUT_CPUCL1_PCLK 8 << 240 #define CLK_DOUT_CLUSTER1_ACLK 9 << 241 #define CLK_DOUT_CLUSTER1_ATCLK 10 << 242 #define CLK_DOUT_CLUSTER1_PCLKDBG 11 << 243 #define CLK_DOUT_CLUSTER1_PERIPHCLK 12 << 244 #define CLK_GOUT_CLUSTER1_ATCLK 13 << 245 #define CLK_GOUT_CLUSTER1_PCLK 14 << 246 #define CLK_GOUT_CLUSTER1_PERIPHCLK 15 << 247 #define CLK_GOUT_CLUSTER1_SCLK 16 << 248 #define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK 17 << 249 #define CLK_GOUT_CLUSTER1_CPU 18 << 250 #define CLK_CLUSTER1_SCLK 19 << 251 << 252 /* CMU_G3D */ << 253 #define CLK_FOUT_G3D_PLL 1 << 254 #define CLK_MOUT_G3D_PLL 2 << 255 #define CLK_MOUT_G3D_SWITCH_USER 3 << 256 #define CLK_MOUT_G3D_BUSD 4 << 257 #define CLK_DOUT_G3D_BUSP 5 << 258 #define CLK_GOUT_G3D_CMU_G3D_PCLK 6 << 259 #define CLK_GOUT_G3D_GPU_CLK 7 << 260 #define CLK_GOUT_G3D_TZPC_PCLK 8 << 261 #define CLK_GOUT_G3D_GRAY2BIN_CLK 9 << 262 #define CLK_GOUT_G3D_BUSD_CLK 10 << 263 #define CLK_GOUT_G3D_BUSP_CLK 11 << 264 #define CLK_GOUT_G3D_SYSREG_PCLK 12 << 265 107 266 /* CMU_HSI */ 108 /* CMU_HSI */ 267 #define CLK_MOUT_HSI_BUS_USER 1 109 #define CLK_MOUT_HSI_BUS_USER 1 268 #define CLK_MOUT_HSI_MMC_CARD_USER 2 110 #define CLK_MOUT_HSI_MMC_CARD_USER 2 269 #define CLK_MOUT_HSI_USB20DRD_USER 3 111 #define CLK_MOUT_HSI_USB20DRD_USER 3 270 #define CLK_MOUT_HSI_RTC 4 112 #define CLK_MOUT_HSI_RTC 4 271 #define CLK_GOUT_USB_RTC_CLK 5 113 #define CLK_GOUT_USB_RTC_CLK 5 272 #define CLK_GOUT_USB_REF_CLK 6 114 #define CLK_GOUT_USB_REF_CLK 6 273 #define CLK_GOUT_USB_PHY_REF_CLK 7 115 #define CLK_GOUT_USB_PHY_REF_CLK 7 274 #define CLK_GOUT_USB_PHY_ACLK 8 116 #define CLK_GOUT_USB_PHY_ACLK 8 275 #define CLK_GOUT_USB_BUS_EARLY_CLK 9 117 #define CLK_GOUT_USB_BUS_EARLY_CLK 9 276 #define CLK_GOUT_GPIO_HSI_PCLK 10 118 #define CLK_GOUT_GPIO_HSI_PCLK 10 277 #define CLK_GOUT_MMC_CARD_ACLK 11 119 #define CLK_GOUT_MMC_CARD_ACLK 11 278 #define CLK_GOUT_MMC_CARD_SDCLKIN 12 120 #define CLK_GOUT_MMC_CARD_SDCLKIN 12 279 #define CLK_GOUT_SYSREG_HSI_PCLK 13 121 #define CLK_GOUT_SYSREG_HSI_PCLK 13 280 #define CLK_GOUT_HSI_PPMU_ACLK 14 !! 122 #define HSI_NR_CLK 14 281 #define CLK_GOUT_HSI_PPMU_PCLK 15 << 282 #define CLK_GOUT_HSI_CMU_HSI_PCLK 16 << 283 << 284 /* CMU_IS */ << 285 #define CLK_MOUT_IS_BUS_USER 1 << 286 #define CLK_MOUT_IS_ITP_USER 2 << 287 #define CLK_MOUT_IS_VRA_USER 3 << 288 #define CLK_MOUT_IS_GDC_USER 4 << 289 #define CLK_DOUT_IS_BUSP 5 << 290 #define CLK_GOUT_IS_CMU_IS_PCLK 6 << 291 #define CLK_GOUT_IS_CSIS0_ACLK 7 << 292 #define CLK_GOUT_IS_CSIS1_ACLK 8 << 293 #define CLK_GOUT_IS_CSIS2_ACLK 9 << 294 #define CLK_GOUT_IS_TZPC_PCLK 10 << 295 #define CLK_GOUT_IS_CSIS_DMA_CLK 11 << 296 #define CLK_GOUT_IS_GDC_CLK 12 << 297 #define CLK_GOUT_IS_IPP_CLK 13 << 298 #define CLK_GOUT_IS_ITP_CLK 14 << 299 #define CLK_GOUT_IS_MCSC_CLK 15 << 300 #define CLK_GOUT_IS_VRA_CLK 16 << 301 #define CLK_GOUT_IS_PPMU_IS0_ACLK 17 << 302 #define CLK_GOUT_IS_PPMU_IS0_PCLK 18 << 303 #define CLK_GOUT_IS_PPMU_IS1_ACLK 19 << 304 #define CLK_GOUT_IS_PPMU_IS1_PCLK 20 << 305 #define CLK_GOUT_IS_SYSMMU_IS0_CLK 21 << 306 #define CLK_GOUT_IS_SYSMMU_IS1_CLK 22 << 307 #define CLK_GOUT_IS_SYSREG_PCLK 23 << 308 << 309 /* CMU_MFCMSCL */ << 310 #define CLK_MOUT_MFCMSCL_MFC_USER << 311 #define CLK_MOUT_MFCMSCL_M2M_USER << 312 #define CLK_MOUT_MFCMSCL_MCSC_USER << 313 #define CLK_MOUT_MFCMSCL_JPEG_USER << 314 #define CLK_DOUT_MFCMSCL_BUSP << 315 #define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK << 316 #define CLK_GOUT_MFCMSCL_TZPC_PCLK << 317 #define CLK_GOUT_MFCMSCL_JPEG_ACLK << 318 #define CLK_GOUT_MFCMSCL_M2M_ACLK << 319 #define CLK_GOUT_MFCMSCL_MCSC_CLK << 320 #define CLK_GOUT_MFCMSCL_MFC_ACLK << 321 #define CLK_GOUT_MFCMSCL_PPMU_ACLK << 322 #define CLK_GOUT_MFCMSCL_PPMU_PCLK << 323 #define CLK_GOUT_MFCMSCL_SYSMMU_CLK << 324 #define CLK_GOUT_MFCMSCL_SYSREG_PCLK << 325 123 326 /* CMU_PERI */ 124 /* CMU_PERI */ 327 #define CLK_MOUT_PERI_BUS_USER 1 125 #define CLK_MOUT_PERI_BUS_USER 1 328 #define CLK_MOUT_PERI_UART_USER 2 126 #define CLK_MOUT_PERI_UART_USER 2 329 #define CLK_MOUT_PERI_HSI2C_USER 3 127 #define CLK_MOUT_PERI_HSI2C_USER 3 330 #define CLK_MOUT_PERI_SPI_USER 4 128 #define CLK_MOUT_PERI_SPI_USER 4 331 #define CLK_DOUT_PERI_HSI2C0 5 129 #define CLK_DOUT_PERI_HSI2C0 5 332 #define CLK_DOUT_PERI_HSI2C1 6 130 #define CLK_DOUT_PERI_HSI2C1 6 333 #define CLK_DOUT_PERI_HSI2C2 7 131 #define CLK_DOUT_PERI_HSI2C2 7 334 #define CLK_DOUT_PERI_SPI0 8 132 #define CLK_DOUT_PERI_SPI0 8 335 #define CLK_GOUT_PERI_HSI2C0 9 133 #define CLK_GOUT_PERI_HSI2C0 9 336 #define CLK_GOUT_PERI_HSI2C1 10 134 #define CLK_GOUT_PERI_HSI2C1 10 337 #define CLK_GOUT_PERI_HSI2C2 11 135 #define CLK_GOUT_PERI_HSI2C2 11 338 #define CLK_GOUT_GPIO_PERI_PCLK 12 136 #define CLK_GOUT_GPIO_PERI_PCLK 12 339 #define CLK_GOUT_HSI2C0_IPCLK 13 137 #define CLK_GOUT_HSI2C0_IPCLK 13 340 #define CLK_GOUT_HSI2C0_PCLK 14 138 #define CLK_GOUT_HSI2C0_PCLK 14 341 #define CLK_GOUT_HSI2C1_IPCLK 15 139 #define CLK_GOUT_HSI2C1_IPCLK 15 342 #define CLK_GOUT_HSI2C1_PCLK 16 140 #define CLK_GOUT_HSI2C1_PCLK 16 343 #define CLK_GOUT_HSI2C2_IPCLK 17 141 #define CLK_GOUT_HSI2C2_IPCLK 17 344 #define CLK_GOUT_HSI2C2_PCLK 18 142 #define CLK_GOUT_HSI2C2_PCLK 18 345 #define CLK_GOUT_I2C0_PCLK 19 143 #define CLK_GOUT_I2C0_PCLK 19 346 #define CLK_GOUT_I2C1_PCLK 20 144 #define CLK_GOUT_I2C1_PCLK 20 347 #define CLK_GOUT_I2C2_PCLK 21 145 #define CLK_GOUT_I2C2_PCLK 21 348 #define CLK_GOUT_I2C3_PCLK 22 146 #define CLK_GOUT_I2C3_PCLK 22 349 #define CLK_GOUT_I2C4_PCLK 23 147 #define CLK_GOUT_I2C4_PCLK 23 350 #define CLK_GOUT_I2C5_PCLK 24 148 #define CLK_GOUT_I2C5_PCLK 24 351 #define CLK_GOUT_I2C6_PCLK 25 149 #define CLK_GOUT_I2C6_PCLK 25 352 #define CLK_GOUT_MCT_PCLK 26 150 #define CLK_GOUT_MCT_PCLK 26 353 #define CLK_GOUT_PWM_MOTOR_PCLK 27 151 #define CLK_GOUT_PWM_MOTOR_PCLK 27 354 #define CLK_GOUT_SPI0_IPCLK 28 152 #define CLK_GOUT_SPI0_IPCLK 28 355 #define CLK_GOUT_SPI0_PCLK 29 153 #define CLK_GOUT_SPI0_PCLK 29 356 #define CLK_GOUT_SYSREG_PERI_PCLK 30 154 #define CLK_GOUT_SYSREG_PERI_PCLK 30 357 #define CLK_GOUT_UART_IPCLK 31 155 #define CLK_GOUT_UART_IPCLK 31 358 #define CLK_GOUT_UART_PCLK 32 156 #define CLK_GOUT_UART_PCLK 32 359 #define CLK_GOUT_WDT0_PCLK 33 157 #define CLK_GOUT_WDT0_PCLK 33 360 #define CLK_GOUT_WDT1_PCLK 34 158 #define CLK_GOUT_WDT1_PCLK 34 >> 159 #define PERI_NR_CLK 35 361 160 362 /* CMU_CORE */ 161 /* CMU_CORE */ 363 #define CLK_MOUT_CORE_BUS_USER 1 162 #define CLK_MOUT_CORE_BUS_USER 1 364 #define CLK_MOUT_CORE_CCI_USER 2 163 #define CLK_MOUT_CORE_CCI_USER 2 365 #define CLK_MOUT_CORE_MMC_EMBD_USER 3 164 #define CLK_MOUT_CORE_MMC_EMBD_USER 3 366 #define CLK_MOUT_CORE_SSS_USER 4 165 #define CLK_MOUT_CORE_SSS_USER 4 367 #define CLK_MOUT_CORE_GIC 5 166 #define CLK_MOUT_CORE_GIC 5 368 #define CLK_DOUT_CORE_BUSP 6 167 #define CLK_DOUT_CORE_BUSP 6 369 #define CLK_GOUT_CCI_ACLK 7 168 #define CLK_GOUT_CCI_ACLK 7 370 #define CLK_GOUT_GIC_CLK 8 169 #define CLK_GOUT_GIC_CLK 8 371 #define CLK_GOUT_MMC_EMBD_ACLK 9 170 #define CLK_GOUT_MMC_EMBD_ACLK 9 372 #define CLK_GOUT_MMC_EMBD_SDCLKIN 10 171 #define CLK_GOUT_MMC_EMBD_SDCLKIN 10 373 #define CLK_GOUT_SSS_ACLK 11 172 #define CLK_GOUT_SSS_ACLK 11 374 #define CLK_GOUT_SSS_PCLK 12 173 #define CLK_GOUT_SSS_PCLK 12 375 #define CLK_GOUT_GPIO_CORE_PCLK 13 174 #define CLK_GOUT_GPIO_CORE_PCLK 13 376 #define CLK_GOUT_SYSREG_CORE_PCLK 14 175 #define CLK_GOUT_SYSREG_CORE_PCLK 14 377 #define CLK_GOUT_PDMA_CORE_ACLK 15 !! 176 #define CORE_NR_CLK 15 378 #define CLK_GOUT_SPDMA_CORE_ACLK 16 << 379 177 380 /* CMU_DPU */ 178 /* CMU_DPU */ 381 #define CLK_MOUT_DPU_USER 1 179 #define CLK_MOUT_DPU_USER 1 382 #define CLK_DOUT_DPU_BUSP 2 180 #define CLK_DOUT_DPU_BUSP 2 383 #define CLK_GOUT_DPU_CMU_DPU_PCLK 3 181 #define CLK_GOUT_DPU_CMU_DPU_PCLK 3 384 #define CLK_GOUT_DPU_DECON0_ACLK 4 182 #define CLK_GOUT_DPU_DECON0_ACLK 4 385 #define CLK_GOUT_DPU_DMA_ACLK 5 183 #define CLK_GOUT_DPU_DMA_ACLK 5 386 #define CLK_GOUT_DPU_DPP_ACLK 6 184 #define CLK_GOUT_DPU_DPP_ACLK 6 387 #define CLK_GOUT_DPU_PPMU_ACLK 7 185 #define CLK_GOUT_DPU_PPMU_ACLK 7 388 #define CLK_GOUT_DPU_PPMU_PCLK 8 186 #define CLK_GOUT_DPU_PPMU_PCLK 8 389 #define CLK_GOUT_DPU_SMMU_CLK 9 187 #define CLK_GOUT_DPU_SMMU_CLK 9 390 #define CLK_GOUT_DPU_SYSREG_PCLK 10 188 #define CLK_GOUT_DPU_SYSREG_PCLK 10 391 #define DPU_NR_CLK 11 189 #define DPU_NR_CLK 11 392 190 393 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */ 191 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */ 394 192

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TOMOYO Linux Cross Reference
Linux/include/dt-bindings/clock/exynos850.h

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Differences between /include/dt-bindings/clock/exynos850.h (Version linux-6.11.5) and /include/dt-bindings/clock/exynos850.h (Version linux-6.0.19)

TOMOYO Linux Cross Reference Linux/include/dt-bindings/clock/exynos850.h

Diff markup

Differences between /include/dt-bindings/clock/exynos850.h (Version linux-6.11.5) and /include/dt-bindings/clock/exynos850.h (Version linux-6.0.19)

TOMOYO Linux Cross Reference
Linux/include/dt-bindings/clock/exynos850.h