1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * Copyright (c) 2017 - 2022: Samsung Electron 4 * https://www.samsung.com 5 * Copyright (c) 2017-2022 Tesla, Inc. 6 * https://www.tesla.com 7 * 8 * The constants defined in this header are be 9 * and fsd platform driver. 10 */ 11 12 #ifndef _DT_BINDINGS_CLOCK_FSD_H 13 #define _DT_BINDINGS_CLOCK_FSD_H 14 15 /* CMU */ 16 #define DOUT_CMU_PLL_SHARED0_DIV4 17 #define DOUT_CMU_PERIC_SHARED1DIV36 18 #define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 19 #define DOUT_CMU_PERIC_SHARED0DIV20 20 #define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 21 #define DOUT_CMU_PLL_SHARED0_DIV6 22 #define DOUT_CMU_FSYS0_SHARED1DIV4 23 #define DOUT_CMU_FSYS0_SHARED0DIV4 24 #define DOUT_CMU_FSYS1_SHARED0DIV8 25 #define DOUT_CMU_FSYS1_SHARED0DIV4 26 #define CMU_CPUCL_SWITCH_GATE 27 #define DOUT_CMU_IMEM_TCUCLK 28 #define DOUT_CMU_IMEM_ACLK 29 #define DOUT_CMU_IMEM_DMACLK 30 #define GAT_CMU_FSYS0_SHARED0DIV4 31 #define CMU_NR_CLK 32 33 /* PERIC */ 34 #define PERIC_SCLK_UART0 35 #define PERIC_PCLK_UART0 36 #define PERIC_SCLK_UART1 37 #define PERIC_PCLK_UART1 38 #define PERIC_DMA0_IPCLKPORT_ACLK 39 #define PERIC_DMA1_IPCLKPORT_ACLK 40 #define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 41 #define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 42 #define PERIC_PCLK_SPI0 43 #define PERIC_SCLK_SPI0 44 #define PERIC_PCLK_SPI1 45 #define PERIC_SCLK_SPI1 46 #define PERIC_PCLK_SPI2 47 #define PERIC_SCLK_SPI2 48 #define PERIC_PCLK_TDM0 49 #define PERIC_PCLK_HSI2C0 50 #define PERIC_PCLK_HSI2C1 51 #define PERIC_PCLK_HSI2C2 52 #define PERIC_PCLK_HSI2C3 53 #define PERIC_PCLK_HSI2C4 54 #define PERIC_PCLK_HSI2C5 55 #define PERIC_PCLK_HSI2C6 56 #define PERIC_PCLK_HSI2C7 57 #define PERIC_MCAN0_IPCLKPORT_CCLK 58 #define PERIC_MCAN0_IPCLKPORT_PCLK 59 #define PERIC_MCAN1_IPCLKPORT_CCLK 60 #define PERIC_MCAN1_IPCLKPORT_PCLK 61 #define PERIC_MCAN2_IPCLKPORT_CCLK 62 #define PERIC_MCAN2_IPCLKPORT_PCLK 63 #define PERIC_MCAN3_IPCLKPORT_CCLK 64 #define PERIC_MCAN3_IPCLKPORT_PCLK 65 #define PERIC_PCLK_ADCIF 66 #define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 67 #define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 68 #define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 69 #define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 70 #define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 71 #define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 72 #define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 73 #define PERIC_HCLK_TDM0 74 #define PERIC_PCLK_TDM1 75 #define PERIC_HCLK_TDM1 76 #define PERIC_EQOS_PHYRXCLK_MUX 77 #define PERIC_EQOS_PHYRXCLK 78 #define PERIC_DOUT_RGMII_CLK 79 #define PERIC_NR_CLK 80 81 /* FSYS0 */ 82 #define UFS0_MPHY_REFCLK_IXTAL24 83 #define UFS0_MPHY_REFCLK_IXTAL26 84 #define UFS1_MPHY_REFCLK_IXTAL24 85 #define UFS1_MPHY_REFCLK_IXTAL26 86 #define UFS0_TOP0_HCLK_BUS 87 #define UFS0_TOP0_ACLK 88 #define UFS0_TOP0_CLK_UNIPRO 89 #define UFS0_TOP0_FMP_CLK 90 #define UFS1_TOP1_HCLK_BUS 91 #define UFS1_TOP1_ACLK 92 #define UFS1_TOP1_CLK_UNIPRO 93 #define UFS1_TOP1_FMP_CLK 94 #define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 95 #define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 96 #define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 97 #define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 98 #define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_ 99 #define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 100 #define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 101 #define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 102 #define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 103 #define FSYS0_DOUT_FSYS0_PERIBUS_GRP 104 #define FSYS0_NR_CLK 105 106 /* FSYS1 */ 107 #define PCIE_LINK0_IPCLKPORT_DBI_ACLK 108 #define PCIE_LINK0_IPCLKPORT_AUX_ACLK 109 #define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 110 #define PCIE_LINK0_IPCLKPORT_SLV_ACLK 111 #define PCIE_LINK1_IPCLKPORT_DBI_ACLK 112 #define PCIE_LINK1_IPCLKPORT_AUX_ACLK 113 #define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 114 #define PCIE_LINK1_IPCLKPORT_SLV_ACLK 115 #define FSYS1_NR_CLK 116 117 /* IMEM */ 118 #define IMEM_DMA0_IPCLKPORT_ACLK 119 #define IMEM_DMA1_IPCLKPORT_ACLK 120 #define IMEM_WDT0_IPCLKPORT_PCLK 121 #define IMEM_WDT1_IPCLKPORT_PCLK 122 #define IMEM_WDT2_IPCLKPORT_PCLK 123 #define IMEM_MCT_PCLK 124 #define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 125 #define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 126 #define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 127 #define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 128 #define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 129 #define IMEM_NR_CLK 130 131 /* MFC */ 132 #define MFC_MFC_IPCLKPORT_ACLK 133 #define MFC_NR_CLK 134 135 /* CAM_CSI */ 136 #define CAM_CSI0_0_IPCLKPORT_I_ACLK 137 #define CAM_CSI0_1_IPCLKPORT_I_ACLK 138 #define CAM_CSI0_2_IPCLKPORT_I_ACLK 139 #define CAM_CSI0_3_IPCLKPORT_I_ACLK 140 #define CAM_CSI1_0_IPCLKPORT_I_ACLK 141 #define CAM_CSI1_1_IPCLKPORT_I_ACLK 142 #define CAM_CSI1_2_IPCLKPORT_I_ACLK 143 #define CAM_CSI1_3_IPCLKPORT_I_ACLK 144 #define CAM_CSI2_0_IPCLKPORT_I_ACLK 145 #define CAM_CSI2_1_IPCLKPORT_I_ACLK 146 #define CAM_CSI2_2_IPCLKPORT_I_ACLK 147 #define CAM_CSI2_3_IPCLKPORT_I_ACLK 148 #define CAM_CSI_NR_CLK 149 150 #endif /*_DT_BINDINGS_CLOCK_FSD_H */ 151
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