1 /* SPDX-License-Identifier: (GPL-2.0-only OR B 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 2 /* 3 * Copyright (C) 2023 Linaro Ltd. 3 * Copyright (C) 2023 Linaro Ltd. 4 * Author: Peter Griffin <peter.griffin@linaro 4 * Author: Peter Griffin <peter.griffin@linaro.org> 5 * 5 * 6 * Device Tree binding constants for Google gs 6 * Device Tree binding constants for Google gs101 clock controller. 7 */ 7 */ 8 8 9 #ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H 9 #ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H 10 #define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H 10 #define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H 11 11 12 /* CMU_TOP PLL */ 12 /* CMU_TOP PLL */ 13 #define CLK_FOUT_SHARED0_PLL 1 13 #define CLK_FOUT_SHARED0_PLL 1 14 #define CLK_FOUT_SHARED1_PLL 2 14 #define CLK_FOUT_SHARED1_PLL 2 15 #define CLK_FOUT_SHARED2_PLL 3 15 #define CLK_FOUT_SHARED2_PLL 3 16 #define CLK_FOUT_SHARED3_PLL 4 16 #define CLK_FOUT_SHARED3_PLL 4 17 #define CLK_FOUT_SPARE_PLL 5 17 #define CLK_FOUT_SPARE_PLL 5 18 18 19 /* CMU_TOP MUX */ 19 /* CMU_TOP MUX */ 20 #define CLK_MOUT_PLL_SHARED0 6 20 #define CLK_MOUT_PLL_SHARED0 6 21 #define CLK_MOUT_PLL_SHARED1 7 21 #define CLK_MOUT_PLL_SHARED1 7 22 #define CLK_MOUT_PLL_SHARED2 8 22 #define CLK_MOUT_PLL_SHARED2 8 23 #define CLK_MOUT_PLL_SHARED3 9 23 #define CLK_MOUT_PLL_SHARED3 9 24 #define CLK_MOUT_PLL_SPARE 10 24 #define CLK_MOUT_PLL_SPARE 10 25 #define CLK_MOUT_CMU_BO_BUS 11 25 #define CLK_MOUT_CMU_BO_BUS 11 26 #define CLK_MOUT_CMU_BUS0_BUS 12 26 #define CLK_MOUT_CMU_BUS0_BUS 12 27 #define CLK_MOUT_CMU_BUS1_BUS 13 27 #define CLK_MOUT_CMU_BUS1_BUS 13 28 #define CLK_MOUT_CMU_BUS2_BUS 14 28 #define CLK_MOUT_CMU_BUS2_BUS 14 29 #define CLK_MOUT_CMU_CIS_CLK0 15 29 #define CLK_MOUT_CMU_CIS_CLK0 15 30 #define CLK_MOUT_CMU_CIS_CLK1 16 30 #define CLK_MOUT_CMU_CIS_CLK1 16 31 #define CLK_MOUT_CMU_CIS_CLK2 17 31 #define CLK_MOUT_CMU_CIS_CLK2 17 32 #define CLK_MOUT_CMU_CIS_CLK3 18 32 #define CLK_MOUT_CMU_CIS_CLK3 18 33 #define CLK_MOUT_CMU_CIS_CLK4 19 33 #define CLK_MOUT_CMU_CIS_CLK4 19 34 #define CLK_MOUT_CMU_CIS_CLK5 20 34 #define CLK_MOUT_CMU_CIS_CLK5 20 35 #define CLK_MOUT_CMU_CIS_CLK6 21 35 #define CLK_MOUT_CMU_CIS_CLK6 21 36 #define CLK_MOUT_CMU_CIS_CLK7 22 36 #define CLK_MOUT_CMU_CIS_CLK7 22 37 #define CLK_MOUT_CMU_CMU_BOOST 23 37 #define CLK_MOUT_CMU_CMU_BOOST 23 38 #define CLK_MOUT_CMU_BOOST_OPTION1 24 38 #define CLK_MOUT_CMU_BOOST_OPTION1 24 39 #define CLK_MOUT_CMU_CORE_BUS 25 39 #define CLK_MOUT_CMU_CORE_BUS 25 40 #define CLK_MOUT_CMU_CPUCL0_DBG 26 40 #define CLK_MOUT_CMU_CPUCL0_DBG 26 41 #define CLK_MOUT_CMU_CPUCL0_SWITCH 27 41 #define CLK_MOUT_CMU_CPUCL0_SWITCH 27 42 #define CLK_MOUT_CMU_CPUCL1_SWITCH 28 42 #define CLK_MOUT_CMU_CPUCL1_SWITCH 28 43 #define CLK_MOUT_CMU_CPUCL2_SWITCH 29 43 #define CLK_MOUT_CMU_CPUCL2_SWITCH 29 44 #define CLK_MOUT_CMU_CSIS_BUS 30 44 #define CLK_MOUT_CMU_CSIS_BUS 30 45 #define CLK_MOUT_CMU_DISP_BUS 31 45 #define CLK_MOUT_CMU_DISP_BUS 31 46 #define CLK_MOUT_CMU_DNS_BUS 32 46 #define CLK_MOUT_CMU_DNS_BUS 32 47 #define CLK_MOUT_CMU_DPU_BUS 33 47 #define CLK_MOUT_CMU_DPU_BUS 33 48 #define CLK_MOUT_CMU_EH_BUS 34 48 #define CLK_MOUT_CMU_EH_BUS 34 49 #define CLK_MOUT_CMU_G2D_G2D 35 49 #define CLK_MOUT_CMU_G2D_G2D 35 50 #define CLK_MOUT_CMU_G2D_MSCL 36 50 #define CLK_MOUT_CMU_G2D_MSCL 36 51 #define CLK_MOUT_CMU_G3AA_G3AA 37 51 #define CLK_MOUT_CMU_G3AA_G3AA 37 52 #define CLK_MOUT_CMU_G3D_BUSD 38 52 #define CLK_MOUT_CMU_G3D_BUSD 38 53 #define CLK_MOUT_CMU_G3D_GLB 39 53 #define CLK_MOUT_CMU_G3D_GLB 39 54 #define CLK_MOUT_CMU_G3D_SWITCH 40 54 #define CLK_MOUT_CMU_G3D_SWITCH 40 55 #define CLK_MOUT_CMU_GDC_GDC0 41 55 #define CLK_MOUT_CMU_GDC_GDC0 41 56 #define CLK_MOUT_CMU_GDC_GDC1 42 56 #define CLK_MOUT_CMU_GDC_GDC1 42 57 #define CLK_MOUT_CMU_GDC_SCSC 43 57 #define CLK_MOUT_CMU_GDC_SCSC 43 58 #define CLK_MOUT_CMU_HPM 44 58 #define CLK_MOUT_CMU_HPM 44 59 #define CLK_MOUT_CMU_HSI0_BUS 45 59 #define CLK_MOUT_CMU_HSI0_BUS 45 60 #define CLK_MOUT_CMU_HSI0_DPGTC 46 60 #define CLK_MOUT_CMU_HSI0_DPGTC 46 61 #define CLK_MOUT_CMU_HSI0_USB31DRD 47 61 #define CLK_MOUT_CMU_HSI0_USB31DRD 47 62 #define CLK_MOUT_CMU_HSI0_USBDPDBG 48 62 #define CLK_MOUT_CMU_HSI0_USBDPDBG 48 63 #define CLK_MOUT_CMU_HSI1_BUS 49 63 #define CLK_MOUT_CMU_HSI1_BUS 49 64 #define CLK_MOUT_CMU_HSI1_PCIE 50 64 #define CLK_MOUT_CMU_HSI1_PCIE 50 65 #define CLK_MOUT_CMU_HSI2_BUS 51 65 #define CLK_MOUT_CMU_HSI2_BUS 51 66 #define CLK_MOUT_CMU_HSI2_MMC_CARD 52 66 #define CLK_MOUT_CMU_HSI2_MMC_CARD 52 67 #define CLK_MOUT_CMU_HSI2_PCIE 53 67 #define CLK_MOUT_CMU_HSI2_PCIE 53 68 #define CLK_MOUT_CMU_HSI2_UFS_EMBD 54 68 #define CLK_MOUT_CMU_HSI2_UFS_EMBD 54 69 #define CLK_MOUT_CMU_IPP_BUS 55 69 #define CLK_MOUT_CMU_IPP_BUS 55 70 #define CLK_MOUT_CMU_ITP_BUS 56 70 #define CLK_MOUT_CMU_ITP_BUS 56 71 #define CLK_MOUT_CMU_MCSC_ITSC 57 71 #define CLK_MOUT_CMU_MCSC_ITSC 57 72 #define CLK_MOUT_CMU_MCSC_MCSC 58 72 #define CLK_MOUT_CMU_MCSC_MCSC 58 73 #define CLK_MOUT_CMU_MFC_MFC 59 73 #define CLK_MOUT_CMU_MFC_MFC 59 74 #define CLK_MOUT_CMU_MIF_BUSP 60 74 #define CLK_MOUT_CMU_MIF_BUSP 60 75 #define CLK_MOUT_CMU_MIF_SWITCH 61 75 #define CLK_MOUT_CMU_MIF_SWITCH 61 76 #define CLK_MOUT_CMU_MISC_BUS 62 76 #define CLK_MOUT_CMU_MISC_BUS 62 77 #define CLK_MOUT_CMU_MISC_SSS 63 77 #define CLK_MOUT_CMU_MISC_SSS 63 78 #define CLK_MOUT_CMU_PDP_BUS 64 78 #define CLK_MOUT_CMU_PDP_BUS 64 79 #define CLK_MOUT_CMU_PDP_VRA 65 79 #define CLK_MOUT_CMU_PDP_VRA 65 80 #define CLK_MOUT_CMU_PERIC0_BUS 66 80 #define CLK_MOUT_CMU_PERIC0_BUS 66 81 #define CLK_MOUT_CMU_PERIC0_IP 67 81 #define CLK_MOUT_CMU_PERIC0_IP 67 82 #define CLK_MOUT_CMU_PERIC1_BUS 68 82 #define CLK_MOUT_CMU_PERIC1_BUS 68 83 #define CLK_MOUT_CMU_PERIC1_IP 69 83 #define CLK_MOUT_CMU_PERIC1_IP 69 84 #define CLK_MOUT_CMU_TNR_BUS 70 84 #define CLK_MOUT_CMU_TNR_BUS 70 85 #define CLK_MOUT_CMU_TOP_BOOST_OPTION1 71 85 #define CLK_MOUT_CMU_TOP_BOOST_OPTION1 71 86 #define CLK_MOUT_CMU_TOP_CMUREF 72 86 #define CLK_MOUT_CMU_TOP_CMUREF 72 87 #define CLK_MOUT_CMU_TPU_BUS 73 87 #define CLK_MOUT_CMU_TPU_BUS 73 88 #define CLK_MOUT_CMU_TPU_TPU 74 88 #define CLK_MOUT_CMU_TPU_TPU 74 89 #define CLK_MOUT_CMU_TPU_TPUCTL 75 89 #define CLK_MOUT_CMU_TPU_TPUCTL 75 90 #define CLK_MOUT_CMU_TPU_UART 76 90 #define CLK_MOUT_CMU_TPU_UART 76 91 #define CLK_MOUT_CMU_CMUREF 77 91 #define CLK_MOUT_CMU_CMUREF 77 92 92 93 /* CMU_TOP Dividers */ 93 /* CMU_TOP Dividers */ 94 #define CLK_DOUT_CMU_BO_BUS 78 94 #define CLK_DOUT_CMU_BO_BUS 78 95 #define CLK_DOUT_CMU_BUS0_BUS 79 95 #define CLK_DOUT_CMU_BUS0_BUS 79 96 #define CLK_DOUT_CMU_BUS1_BUS 80 96 #define CLK_DOUT_CMU_BUS1_BUS 80 97 #define CLK_DOUT_CMU_BUS2_BUS 81 97 #define CLK_DOUT_CMU_BUS2_BUS 81 98 #define CLK_DOUT_CMU_CIS_CLK0 82 98 #define CLK_DOUT_CMU_CIS_CLK0 82 99 #define CLK_DOUT_CMU_CIS_CLK1 83 99 #define CLK_DOUT_CMU_CIS_CLK1 83 100 #define CLK_DOUT_CMU_CIS_CLK2 84 100 #define CLK_DOUT_CMU_CIS_CLK2 84 101 #define CLK_DOUT_CMU_CIS_CLK3 85 101 #define CLK_DOUT_CMU_CIS_CLK3 85 102 #define CLK_DOUT_CMU_CIS_CLK4 86 102 #define CLK_DOUT_CMU_CIS_CLK4 86 103 #define CLK_DOUT_CMU_CIS_CLK5 87 103 #define CLK_DOUT_CMU_CIS_CLK5 87 104 #define CLK_DOUT_CMU_CIS_CLK6 88 104 #define CLK_DOUT_CMU_CIS_CLK6 88 105 #define CLK_DOUT_CMU_CIS_CLK7 89 105 #define CLK_DOUT_CMU_CIS_CLK7 89 106 #define CLK_DOUT_CMU_CORE_BUS 90 106 #define CLK_DOUT_CMU_CORE_BUS 90 107 #define CLK_DOUT_CMU_CPUCL0_DBG 91 107 #define CLK_DOUT_CMU_CPUCL0_DBG 91 108 #define CLK_DOUT_CMU_CPUCL0_SWITCH 92 108 #define CLK_DOUT_CMU_CPUCL0_SWITCH 92 109 #define CLK_DOUT_CMU_CPUCL1_SWITCH 93 109 #define CLK_DOUT_CMU_CPUCL1_SWITCH 93 110 #define CLK_DOUT_CMU_CPUCL2_SWITCH 94 110 #define CLK_DOUT_CMU_CPUCL2_SWITCH 94 111 #define CLK_DOUT_CMU_CSIS_BUS 95 111 #define CLK_DOUT_CMU_CSIS_BUS 95 112 #define CLK_DOUT_CMU_DISP_BUS 96 112 #define CLK_DOUT_CMU_DISP_BUS 96 113 #define CLK_DOUT_CMU_DNS_BUS 97 113 #define CLK_DOUT_CMU_DNS_BUS 97 114 #define CLK_DOUT_CMU_DPU_BUS 98 114 #define CLK_DOUT_CMU_DPU_BUS 98 115 #define CLK_DOUT_CMU_EH_BUS 99 115 #define CLK_DOUT_CMU_EH_BUS 99 116 #define CLK_DOUT_CMU_G2D_G2D 100 116 #define CLK_DOUT_CMU_G2D_G2D 100 117 #define CLK_DOUT_CMU_G2D_MSCL 101 117 #define CLK_DOUT_CMU_G2D_MSCL 101 118 #define CLK_DOUT_CMU_G3AA_G3AA 102 118 #define CLK_DOUT_CMU_G3AA_G3AA 102 119 #define CLK_DOUT_CMU_G3D_BUSD 103 119 #define CLK_DOUT_CMU_G3D_BUSD 103 120 #define CLK_DOUT_CMU_G3D_GLB 104 120 #define CLK_DOUT_CMU_G3D_GLB 104 121 #define CLK_DOUT_CMU_G3D_SWITCH 105 121 #define CLK_DOUT_CMU_G3D_SWITCH 105 122 #define CLK_DOUT_CMU_GDC_GDC0 106 122 #define CLK_DOUT_CMU_GDC_GDC0 106 123 #define CLK_DOUT_CMU_GDC_GDC1 107 123 #define CLK_DOUT_CMU_GDC_GDC1 107 124 #define CLK_DOUT_CMU_GDC_SCSC 108 124 #define CLK_DOUT_CMU_GDC_SCSC 108 125 #define CLK_DOUT_CMU_CMU_HPM 109 125 #define CLK_DOUT_CMU_CMU_HPM 109 126 #define CLK_DOUT_CMU_HSI0_BUS 110 126 #define CLK_DOUT_CMU_HSI0_BUS 110 127 #define CLK_DOUT_CMU_HSI0_DPGTC 111 127 #define CLK_DOUT_CMU_HSI0_DPGTC 111 128 #define CLK_DOUT_CMU_HSI0_USB31DRD 112 128 #define CLK_DOUT_CMU_HSI0_USB31DRD 112 129 #define CLK_DOUT_CMU_HSI0_USBDPDBG 113 129 #define CLK_DOUT_CMU_HSI0_USBDPDBG 113 130 #define CLK_DOUT_CMU_HSI1_BUS 114 130 #define CLK_DOUT_CMU_HSI1_BUS 114 131 #define CLK_DOUT_CMU_HSI1_PCIE 115 131 #define CLK_DOUT_CMU_HSI1_PCIE 115 132 #define CLK_DOUT_CMU_HSI2_BUS 116 132 #define CLK_DOUT_CMU_HSI2_BUS 116 133 #define CLK_DOUT_CMU_HSI2_MMC_CARD 117 133 #define CLK_DOUT_CMU_HSI2_MMC_CARD 117 134 #define CLK_DOUT_CMU_HSI2_PCIE 118 134 #define CLK_DOUT_CMU_HSI2_PCIE 118 135 #define CLK_DOUT_CMU_HSI2_UFS_EMBD 119 135 #define CLK_DOUT_CMU_HSI2_UFS_EMBD 119 136 #define CLK_DOUT_CMU_IPP_BUS 120 136 #define CLK_DOUT_CMU_IPP_BUS 120 137 #define CLK_DOUT_CMU_ITP_BUS 121 137 #define CLK_DOUT_CMU_ITP_BUS 121 138 #define CLK_DOUT_CMU_MCSC_ITSC 122 138 #define CLK_DOUT_CMU_MCSC_ITSC 122 139 #define CLK_DOUT_CMU_MCSC_MCSC 123 139 #define CLK_DOUT_CMU_MCSC_MCSC 123 140 #define CLK_DOUT_CMU_MFC_MFC 124 140 #define CLK_DOUT_CMU_MFC_MFC 124 141 #define CLK_DOUT_CMU_MIF_BUSP 125 141 #define CLK_DOUT_CMU_MIF_BUSP 125 142 #define CLK_DOUT_CMU_MISC_BUS 126 142 #define CLK_DOUT_CMU_MISC_BUS 126 143 #define CLK_DOUT_CMU_MISC_SSS 127 143 #define CLK_DOUT_CMU_MISC_SSS 127 144 #define CLK_DOUT_CMU_OTP 128 144 #define CLK_DOUT_CMU_OTP 128 145 #define CLK_DOUT_CMU_PDP_BUS 129 145 #define CLK_DOUT_CMU_PDP_BUS 129 146 #define CLK_DOUT_CMU_PDP_VRA 130 146 #define CLK_DOUT_CMU_PDP_VRA 130 147 #define CLK_DOUT_CMU_PERIC0_BUS 131 147 #define CLK_DOUT_CMU_PERIC0_BUS 131 148 #define CLK_DOUT_CMU_PERIC0_IP 132 148 #define CLK_DOUT_CMU_PERIC0_IP 132 149 #define CLK_DOUT_CMU_PERIC1_BUS 133 149 #define CLK_DOUT_CMU_PERIC1_BUS 133 150 #define CLK_DOUT_CMU_PERIC1_IP 134 150 #define CLK_DOUT_CMU_PERIC1_IP 134 151 #define CLK_DOUT_CMU_TNR_BUS 135 151 #define CLK_DOUT_CMU_TNR_BUS 135 152 #define CLK_DOUT_CMU_TPU_BUS 136 152 #define CLK_DOUT_CMU_TPU_BUS 136 153 #define CLK_DOUT_CMU_TPU_TPU 137 153 #define CLK_DOUT_CMU_TPU_TPU 137 154 #define CLK_DOUT_CMU_TPU_TPUCTL 138 154 #define CLK_DOUT_CMU_TPU_TPUCTL 138 155 #define CLK_DOUT_CMU_TPU_UART 139 155 #define CLK_DOUT_CMU_TPU_UART 139 156 #define CLK_DOUT_CMU_CMU_BOOST 140 156 #define CLK_DOUT_CMU_CMU_BOOST 140 157 #define CLK_DOUT_CMU_CMU_CMUREF 141 157 #define CLK_DOUT_CMU_CMU_CMUREF 141 158 #define CLK_DOUT_CMU_SHARED0_DIV2 142 158 #define CLK_DOUT_CMU_SHARED0_DIV2 142 159 #define CLK_DOUT_CMU_SHARED0_DIV3 143 159 #define CLK_DOUT_CMU_SHARED0_DIV3 143 160 #define CLK_DOUT_CMU_SHARED0_DIV4 144 160 #define CLK_DOUT_CMU_SHARED0_DIV4 144 161 #define CLK_DOUT_CMU_SHARED0_DIV5 145 161 #define CLK_DOUT_CMU_SHARED0_DIV5 145 162 #define CLK_DOUT_CMU_SHARED1_DIV2 146 162 #define CLK_DOUT_CMU_SHARED1_DIV2 146 163 #define CLK_DOUT_CMU_SHARED1_DIV3 147 163 #define CLK_DOUT_CMU_SHARED1_DIV3 147 164 #define CLK_DOUT_CMU_SHARED1_DIV4 148 164 #define CLK_DOUT_CMU_SHARED1_DIV4 148 165 #define CLK_DOUT_CMU_SHARED2_DIV2 149 165 #define CLK_DOUT_CMU_SHARED2_DIV2 149 166 #define CLK_DOUT_CMU_SHARED3_DIV2 150 166 #define CLK_DOUT_CMU_SHARED3_DIV2 150 167 167 168 /* CMU_TOP Gates */ 168 /* CMU_TOP Gates */ 169 #define CLK_GOUT_CMU_BUS0_BOOST 151 169 #define CLK_GOUT_CMU_BUS0_BOOST 151 170 #define CLK_GOUT_CMU_BUS1_BOOST 152 170 #define CLK_GOUT_CMU_BUS1_BOOST 152 171 #define CLK_GOUT_CMU_BUS2_BOOST 153 171 #define CLK_GOUT_CMU_BUS2_BOOST 153 172 #define CLK_GOUT_CMU_CORE_BOOST 154 172 #define CLK_GOUT_CMU_CORE_BOOST 154 173 #define CLK_GOUT_CMU_CPUCL0_BOOST 155 173 #define CLK_GOUT_CMU_CPUCL0_BOOST 155 174 #define CLK_GOUT_CMU_CPUCL1_BOOST 156 174 #define CLK_GOUT_CMU_CPUCL1_BOOST 156 175 #define CLK_GOUT_CMU_CPUCL2_BOOST 157 175 #define CLK_GOUT_CMU_CPUCL2_BOOST 157 176 #define CLK_GOUT_CMU_MIF_BOOST 158 176 #define CLK_GOUT_CMU_MIF_BOOST 158 177 #define CLK_GOUT_CMU_MIF_SWITCH 159 177 #define CLK_GOUT_CMU_MIF_SWITCH 159 178 #define CLK_GOUT_CMU_BO_BUS 160 178 #define CLK_GOUT_CMU_BO_BUS 160 179 #define CLK_GOUT_CMU_BUS0_BUS 161 179 #define CLK_GOUT_CMU_BUS0_BUS 161 180 #define CLK_GOUT_CMU_BUS1_BUS 162 180 #define CLK_GOUT_CMU_BUS1_BUS 162 181 #define CLK_GOUT_CMU_BUS2_BUS 163 181 #define CLK_GOUT_CMU_BUS2_BUS 163 182 #define CLK_GOUT_CMU_CIS_CLK0 164 182 #define CLK_GOUT_CMU_CIS_CLK0 164 183 #define CLK_GOUT_CMU_CIS_CLK1 165 183 #define CLK_GOUT_CMU_CIS_CLK1 165 184 #define CLK_GOUT_CMU_CIS_CLK2 166 184 #define CLK_GOUT_CMU_CIS_CLK2 166 185 #define CLK_GOUT_CMU_CIS_CLK3 167 185 #define CLK_GOUT_CMU_CIS_CLK3 167 186 #define CLK_GOUT_CMU_CIS_CLK4 168 186 #define CLK_GOUT_CMU_CIS_CLK4 168 187 #define CLK_GOUT_CMU_CIS_CLK5 169 187 #define CLK_GOUT_CMU_CIS_CLK5 169 188 #define CLK_GOUT_CMU_CIS_CLK6 170 188 #define CLK_GOUT_CMU_CIS_CLK6 170 189 #define CLK_GOUT_CMU_CIS_CLK7 171 189 #define CLK_GOUT_CMU_CIS_CLK7 171 190 #define CLK_GOUT_CMU_CMU_BOOST 172 190 #define CLK_GOUT_CMU_CMU_BOOST 172 191 #define CLK_GOUT_CMU_CORE_BUS 173 191 #define CLK_GOUT_CMU_CORE_BUS 173 192 #define CLK_GOUT_CMU_CPUCL0_DBG 174 192 #define CLK_GOUT_CMU_CPUCL0_DBG 174 193 #define CLK_GOUT_CMU_CPUCL0_SWITCH 175 193 #define CLK_GOUT_CMU_CPUCL0_SWITCH 175 194 #define CLK_GOUT_CMU_CPUCL1_SWITCH 176 194 #define CLK_GOUT_CMU_CPUCL1_SWITCH 176 195 #define CLK_GOUT_CMU_CPUCL2_SWITCH 177 195 #define CLK_GOUT_CMU_CPUCL2_SWITCH 177 196 #define CLK_GOUT_CMU_CSIS_BUS 178 196 #define CLK_GOUT_CMU_CSIS_BUS 178 197 #define CLK_GOUT_CMU_DISP_BUS 179 197 #define CLK_GOUT_CMU_DISP_BUS 179 198 #define CLK_GOUT_CMU_DNS_BUS 180 198 #define CLK_GOUT_CMU_DNS_BUS 180 199 #define CLK_GOUT_CMU_DPU_BUS 181 199 #define CLK_GOUT_CMU_DPU_BUS 181 200 #define CLK_GOUT_CMU_EH_BUS 182 200 #define CLK_GOUT_CMU_EH_BUS 182 201 #define CLK_GOUT_CMU_G2D_G2D 183 201 #define CLK_GOUT_CMU_G2D_G2D 183 202 #define CLK_GOUT_CMU_G2D_MSCL 184 202 #define CLK_GOUT_CMU_G2D_MSCL 184 203 #define CLK_GOUT_CMU_G3AA_G3AA 185 203 #define CLK_GOUT_CMU_G3AA_G3AA 185 204 #define CLK_GOUT_CMU_G3D_BUSD 186 204 #define CLK_GOUT_CMU_G3D_BUSD 186 205 #define CLK_GOUT_CMU_G3D_GLB 187 205 #define CLK_GOUT_CMU_G3D_GLB 187 206 #define CLK_GOUT_CMU_G3D_SWITCH 188 206 #define CLK_GOUT_CMU_G3D_SWITCH 188 207 #define CLK_GOUT_CMU_GDC_GDC0 189 207 #define CLK_GOUT_CMU_GDC_GDC0 189 208 #define CLK_GOUT_CMU_GDC_GDC1 190 208 #define CLK_GOUT_CMU_GDC_GDC1 190 209 #define CLK_GOUT_CMU_GDC_SCSC 191 209 #define CLK_GOUT_CMU_GDC_SCSC 191 210 #define CLK_GOUT_CMU_HPM 192 210 #define CLK_GOUT_CMU_HPM 192 211 #define CLK_GOUT_CMU_HSI0_BUS 193 211 #define CLK_GOUT_CMU_HSI0_BUS 193 212 #define CLK_GOUT_CMU_HSI0_DPGTC 194 212 #define CLK_GOUT_CMU_HSI0_DPGTC 194 213 #define CLK_GOUT_CMU_HSI0_USB31DRD 195 213 #define CLK_GOUT_CMU_HSI0_USB31DRD 195 214 #define CLK_GOUT_CMU_HSI0_USBDPDBG 196 214 #define CLK_GOUT_CMU_HSI0_USBDPDBG 196 215 #define CLK_GOUT_CMU_HSI1_BUS 197 215 #define CLK_GOUT_CMU_HSI1_BUS 197 216 #define CLK_GOUT_CMU_HSI1_PCIE 198 216 #define CLK_GOUT_CMU_HSI1_PCIE 198 217 #define CLK_GOUT_CMU_HSI2_BUS 199 217 #define CLK_GOUT_CMU_HSI2_BUS 199 218 #define CLK_GOUT_CMU_HSI2_MMC_CARD 200 218 #define CLK_GOUT_CMU_HSI2_MMC_CARD 200 219 #define CLK_GOUT_CMU_HSI2_PCIE 201 219 #define CLK_GOUT_CMU_HSI2_PCIE 201 220 #define CLK_GOUT_CMU_HSI2_UFS_EMBD 202 220 #define CLK_GOUT_CMU_HSI2_UFS_EMBD 202 221 #define CLK_GOUT_CMU_IPP_BUS 203 221 #define CLK_GOUT_CMU_IPP_BUS 203 222 #define CLK_GOUT_CMU_ITP_BUS 204 222 #define CLK_GOUT_CMU_ITP_BUS 204 223 #define CLK_GOUT_CMU_MCSC_ITSC 205 223 #define CLK_GOUT_CMU_MCSC_ITSC 205 224 #define CLK_GOUT_CMU_MCSC_MCSC 206 224 #define CLK_GOUT_CMU_MCSC_MCSC 206 225 #define CLK_GOUT_CMU_MFC_MFC 207 225 #define CLK_GOUT_CMU_MFC_MFC 207 226 #define CLK_GOUT_CMU_MIF_BUSP 208 226 #define CLK_GOUT_CMU_MIF_BUSP 208 227 #define CLK_GOUT_CMU_MISC_BUS 209 227 #define CLK_GOUT_CMU_MISC_BUS 209 228 #define CLK_GOUT_CMU_MISC_SSS 210 228 #define CLK_GOUT_CMU_MISC_SSS 210 229 #define CLK_GOUT_CMU_PDP_BUS 211 229 #define CLK_GOUT_CMU_PDP_BUS 211 230 #define CLK_GOUT_CMU_PDP_VRA 212 230 #define CLK_GOUT_CMU_PDP_VRA 212 231 #define CLK_GOUT_CMU_G3AA 213 231 #define CLK_GOUT_CMU_G3AA 213 232 #define CLK_GOUT_CMU_PERIC0_BUS 214 232 #define CLK_GOUT_CMU_PERIC0_BUS 214 233 #define CLK_GOUT_CMU_PERIC0_IP 215 233 #define CLK_GOUT_CMU_PERIC0_IP 215 234 #define CLK_GOUT_CMU_PERIC1_BUS 216 234 #define CLK_GOUT_CMU_PERIC1_BUS 216 235 #define CLK_GOUT_CMU_PERIC1_IP 217 235 #define CLK_GOUT_CMU_PERIC1_IP 217 236 #define CLK_GOUT_CMU_TNR_BUS 218 236 #define CLK_GOUT_CMU_TNR_BUS 218 237 #define CLK_GOUT_CMU_TOP_CMUREF 219 237 #define CLK_GOUT_CMU_TOP_CMUREF 219 238 #define CLK_GOUT_CMU_TPU_BUS 220 238 #define CLK_GOUT_CMU_TPU_BUS 220 239 #define CLK_GOUT_CMU_TPU_TPU 221 239 #define CLK_GOUT_CMU_TPU_TPU 221 240 #define CLK_GOUT_CMU_TPU_TPUCTL 222 240 #define CLK_GOUT_CMU_TPU_TPUCTL 222 241 #define CLK_GOUT_CMU_TPU_UART 223 241 #define CLK_GOUT_CMU_TPU_UART 223 242 242 243 /* CMU_APM */ 243 /* CMU_APM */ 244 #define CLK_MOUT_APM_FUNC 244 #define CLK_MOUT_APM_FUNC 1 245 #define CLK_MOUT_APM_FUNCSRC 245 #define CLK_MOUT_APM_FUNCSRC 2 246 #define CLK_DOUT_APM_BOOST 246 #define CLK_DOUT_APM_BOOST 3 247 #define CLK_DOUT_APM_USI0_UART 247 #define CLK_DOUT_APM_USI0_UART 4 248 #define CLK_DOUT_APM_USI0_USI 248 #define CLK_DOUT_APM_USI0_USI 5 249 #define CLK_DOUT_APM_USI1_UART 249 #define CLK_DOUT_APM_USI1_UART 6 250 #define CLK_GOUT_APM_APM_CMU_APM_PCLK 250 #define CLK_GOUT_APM_APM_CMU_APM_PCLK 7 251 #define CLK_GOUT_BUS0_BOOST_OPTION1 251 #define CLK_GOUT_BUS0_BOOST_OPTION1 8 252 #define CLK_GOUT_CMU_BOOST_OPTION1 252 #define CLK_GOUT_CMU_BOOST_OPTION1 9 253 #define CLK_GOUT_CORE_BOOST_OPTION1 253 #define CLK_GOUT_CORE_BOOST_OPTION1 10 254 #define CLK_GOUT_APM_FUNC 254 #define CLK_GOUT_APM_FUNC 11 255 #define CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 255 #define CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 12 256 #define CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK 256 #define CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK 13 257 #define CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK 257 #define CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK 14 258 #define CLK_GOUT_APM_APBIF_RTC_PCLK 258 #define CLK_GOUT_APM_APBIF_RTC_PCLK 15 259 #define CLK_GOUT_APM_APBIF_TRTC_PCLK 259 #define CLK_GOUT_APM_APBIF_TRTC_PCLK 16 260 #define CLK_GOUT_APM_APM_USI0_UART_IPCLK 260 #define CLK_GOUT_APM_APM_USI0_UART_IPCLK 17 261 #define CLK_GOUT_APM_APM_USI0_UART_PCLK 261 #define CLK_GOUT_APM_APM_USI0_UART_PCLK 18 262 #define CLK_GOUT_APM_APM_USI0_USI_IPCLK 262 #define CLK_GOUT_APM_APM_USI0_USI_IPCLK 19 263 #define CLK_GOUT_APM_APM_USI0_USI_PCLK 263 #define CLK_GOUT_APM_APM_USI0_USI_PCLK 20 264 #define CLK_GOUT_APM_APM_USI1_UART_IPCLK 264 #define CLK_GOUT_APM_APM_USI1_UART_IPCLK 21 265 #define CLK_GOUT_APM_APM_USI1_UART_PCLK 265 #define CLK_GOUT_APM_APM_USI1_UART_PCLK 22 266 #define CLK_GOUT_APM_D_TZPC_APM_PCLK 266 #define CLK_GOUT_APM_D_TZPC_APM_PCLK 23 267 #define CLK_GOUT_APM_GPC_APM_PCLK 267 #define CLK_GOUT_APM_GPC_APM_PCLK 24 268 #define CLK_GOUT_APM_GREBEINTEGRATION_HCLK 268 #define CLK_GOUT_APM_GREBEINTEGRATION_HCLK 25 269 #define CLK_GOUT_APM_INTMEM_ACLK 269 #define CLK_GOUT_APM_INTMEM_ACLK 26 270 #define CLK_GOUT_APM_INTMEM_PCLK 270 #define CLK_GOUT_APM_INTMEM_PCLK 27 271 #define CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK 271 #define CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK 28 272 #define CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK 272 #define CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK 29 273 #define CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK 273 #define CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK 30 274 #define CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK 274 #define CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK 31 275 #define CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK 275 #define CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK 32 276 #define CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK 276 #define CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK 33 277 #define CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK 277 #define CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK 34 278 #define CLK_GOUT_APM_MAILBOX_APM_AP_PCLK 278 #define CLK_GOUT_APM_MAILBOX_APM_AP_PCLK 35 279 #define CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK 279 #define CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK 36 280 #define CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK 280 #define CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK 37 281 #define CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK 281 #define CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK 38 282 #define CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK 282 #define CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK 39 283 #define CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK 283 #define CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK 40 284 #define CLK_GOUT_APM_PMU_INTR_GEN_PCLK 284 #define CLK_GOUT_APM_PMU_INTR_GEN_PCLK 41 285 #define CLK_GOUT_APM_ROM_CRC32_HOST_ACLK 285 #define CLK_GOUT_APM_ROM_CRC32_HOST_ACLK 42 286 #define CLK_GOUT_APM_ROM_CRC32_HOST_PCLK 286 #define CLK_GOUT_APM_ROM_CRC32_HOST_PCLK 43 287 #define CLK_GOUT_APM_CLK_APM_BUS_CLK 287 #define CLK_GOUT_APM_CLK_APM_BUS_CLK 44 288 #define CLK_GOUT_APM_CLK_APM_USI0_UART_CLK 288 #define CLK_GOUT_APM_CLK_APM_USI0_UART_CLK 45 289 #define CLK_GOUT_APM_CLK_APM_USI0_USI_CLK 289 #define CLK_GOUT_APM_CLK_APM_USI0_USI_CLK 46 290 #define CLK_GOUT_APM_CLK_APM_USI1_UART_CLK 290 #define CLK_GOUT_APM_CLK_APM_USI1_UART_CLK 47 291 #define CLK_GOUT_APM_SPEEDY_APM_PCLK 291 #define CLK_GOUT_APM_SPEEDY_APM_PCLK 48 292 #define CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK 292 #define CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK 49 293 #define CLK_GOUT_APM_SSMT_D_APM_ACLK 293 #define CLK_GOUT_APM_SSMT_D_APM_ACLK 50 294 #define CLK_GOUT_APM_SSMT_D_APM_PCLK 294 #define CLK_GOUT_APM_SSMT_D_APM_PCLK 51 295 #define CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK 295 #define CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK 52 296 #define CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK 296 #define CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK 53 297 #define CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCL 297 #define CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK 54 298 #define CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2 298 #define CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2 55 299 #define CLK_GOUT_APM_SYSREG_APM_PCLK 299 #define CLK_GOUT_APM_SYSREG_APM_PCLK 56 300 #define CLK_GOUT_APM_UASC_APM_ACLK 300 #define CLK_GOUT_APM_UASC_APM_ACLK 57 301 #define CLK_GOUT_APM_UASC_APM_PCLK 301 #define CLK_GOUT_APM_UASC_APM_PCLK 58 302 #define CLK_GOUT_APM_UASC_DBGCORE_ACLK 302 #define CLK_GOUT_APM_UASC_DBGCORE_ACLK 59 303 #define CLK_GOUT_APM_UASC_DBGCORE_PCLK 303 #define CLK_GOUT_APM_UASC_DBGCORE_PCLK 60 304 #define CLK_GOUT_APM_UASC_G_SWD_ACLK 304 #define CLK_GOUT_APM_UASC_G_SWD_ACLK 61 305 #define CLK_GOUT_APM_UASC_G_SWD_PCLK 305 #define CLK_GOUT_APM_UASC_G_SWD_PCLK 62 306 #define CLK_GOUT_APM_UASC_P_AOCAPM_ACLK 306 #define CLK_GOUT_APM_UASC_P_AOCAPM_ACLK 63 307 #define CLK_GOUT_APM_UASC_P_AOCAPM_PCLK 307 #define CLK_GOUT_APM_UASC_P_AOCAPM_PCLK 64 308 #define CLK_GOUT_APM_UASC_P_APM_ACLK 308 #define CLK_GOUT_APM_UASC_P_APM_ACLK 65 309 #define CLK_GOUT_APM_UASC_P_APM_PCLK 309 #define CLK_GOUT_APM_UASC_P_APM_PCLK 66 310 #define CLK_GOUT_APM_WDT_APM_PCLK 310 #define CLK_GOUT_APM_WDT_APM_PCLK 67 311 #define CLK_GOUT_APM_XIU_DP_APM_ACLK 311 #define CLK_GOUT_APM_XIU_DP_APM_ACLK 68 312 #define CLK_APM_PLL_DIV2_APM 312 #define CLK_APM_PLL_DIV2_APM 69 313 #define CLK_APM_PLL_DIV4_APM 313 #define CLK_APM_PLL_DIV4_APM 70 314 #define CLK_APM_PLL_DIV16_APM 314 #define CLK_APM_PLL_DIV16_APM 71 315 315 316 /* CMU_HSI0 */ << 317 #define CLK_FOUT_USB_PLL << 318 #define CLK_MOUT_PLL_USB << 319 #define CLK_MOUT_HSI0_ALT_USER << 320 #define CLK_MOUT_HSI0_BUS_USER << 321 #define CLK_MOUT_HSI0_DPGTC_USER << 322 #define CLK_MOUT_HSI0_TCXO_USER << 323 #define CLK_MOUT_HSI0_USB20_USER << 324 #define CLK_MOUT_HSI0_USB31DRD_USER << 325 #define CLK_MOUT_HSI0_USBDPDBG_USER << 326 #define CLK_MOUT_HSI0_BUS << 327 #define CLK_MOUT_HSI0_USB20_REF << 328 #define CLK_MOUT_HSI0_USB31DRD << 329 #define CLK_DOUT_HSI0_USB31DRD << 330 #define CLK_GOUT_HSI0_PCLK << 331 #define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSP << 332 #define CLK_GOUT_HSI0_CLK_HSI0_ALT << 333 #define CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK << 334 #define CLK_GOUT_HSI0_DP_LINK_I_PCLK << 335 #define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK << 336 #define CLK_GOUT_HSI0_ETR_MIU_I_ACLK << 337 #define CLK_GOUT_HSI0_ETR_MIU_I_PCLK << 338 #define CLK_GOUT_HSI0_GPC_HSI0_PCLK << 339 #define CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK << 340 #define CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK << 341 #define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK << 342 #define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK << 343 #define CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK << 344 #define CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK << 345 #define CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK << 346 #define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK << 347 #define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK << 348 #define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK << 349 #define CLK_GOUT_HSI0_SSMT_USB_ACLK << 350 #define CLK_GOUT_HSI0_SSMT_USB_PCLK << 351 #define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 << 352 #define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK << 353 #define CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK << 354 #define CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK << 355 #define CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK << 356 #define CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK << 357 #define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL << 358 #define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY << 359 #define CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REF << 360 #define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_ << 361 #define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_ << 362 #define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_ << 363 #define CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CL << 364 #define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK << 365 #define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I << 366 #define CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK << 367 #define CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK << 368 #define CLK_GOUT_HSI0_XIU_P_HSI0_ACLK << 369 << 370 /* CMU_HSI2 */ << 371 #define CLK_MOUT_HSI2_BUS_USER << 372 #define CLK_MOUT_HSI2_MMC_CARD_USER << 373 #define CLK_MOUT_HSI2_PCIE_USER << 374 #define CLK_MOUT_HSI2_UFS_EMBD_USER << 375 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY << 376 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY << 377 #define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACL << 378 #define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCL << 379 #define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACL << 380 #define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCL << 381 #define CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK << 382 #define CLK_GOUT_HSI2_GPC_HSI2_PCLK << 383 #define CLK_GOUT_HSI2_GPIO_HSI2_PCLK << 384 #define CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK << 385 #define CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK << 386 #define CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK << 387 #define CLK_GOUT_HSI2_MMC_CARD_I_ACLK << 388 #define CLK_GOUT_HSI2_MMC_CARD_SDCLKIN << 389 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI << 390 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MST << 391 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV << 392 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_D << 393 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI << 394 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MST << 395 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV << 396 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_D << 397 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_ << 398 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE << 399 #define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIE << 400 #define CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK << 401 #define CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK << 402 #define CLK_GOUT_HSI2_PPMU_HSI2_ACLK << 403 #define CLK_GOUT_HSI2_PPMU_HSI2_PCLK << 404 #define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK << 405 #define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK << 406 #define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK << 407 #define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK << 408 #define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK << 409 #define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK << 410 #define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK << 411 #define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK << 412 #define CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK << 413 #define CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK << 414 #define CLK_GOUT_HSI2_SSMT_HSI2_ACLK << 415 #define CLK_GOUT_HSI2_SSMT_HSI2_PCLK << 416 #define CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2 << 417 #define CLK_GOUT_HSI2_SYSREG_HSI2_PCLK << 418 #define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_AC << 419 #define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PC << 420 #define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_AC << 421 #define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PC << 422 #define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_AC << 423 #define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PC << 424 #define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_AC << 425 #define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PC << 426 #define CLK_GOUT_HSI2_UFS_EMBD_I_ACLK << 427 #define CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO << 428 #define CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK << 429 #define CLK_GOUT_HSI2_XIU_D_HSI2_ACLK << 430 #define CLK_GOUT_HSI2_XIU_P_HSI2_ACLK << 431 << 432 /* CMU_MISC */ 316 /* CMU_MISC */ 433 #define CLK_MOUT_MISC_BUS_USER 317 #define CLK_MOUT_MISC_BUS_USER 1 434 #define CLK_MOUT_MISC_SSS_USER 318 #define CLK_MOUT_MISC_SSS_USER 2 435 #define CLK_MOUT_MISC_GIC 319 #define CLK_MOUT_MISC_GIC 3 436 #define CLK_DOUT_MISC_BUSP 320 #define CLK_DOUT_MISC_BUSP 4 437 #define CLK_DOUT_MISC_GIC 321 #define CLK_DOUT_MISC_GIC 5 438 #define CLK_GOUT_MISC_MISC_CMU_MISC_PCLK 322 #define CLK_GOUT_MISC_MISC_CMU_MISC_PCLK 6 439 #define CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK 323 #define CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK 7 440 #define CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK 324 #define CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK 8 441 #define CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK 325 #define CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK 9 442 #define CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK 326 #define CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK 10 443 #define CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM 327 #define CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM 11 444 #define CLK_GOUT_MISC_AD_APB_DIT_PCLKM 328 #define CLK_GOUT_MISC_AD_APB_DIT_PCLKM 12 445 #define CLK_GOUT_MISC_AD_APB_PUF_PCLKM 329 #define CLK_GOUT_MISC_AD_APB_PUF_PCLKM 13 446 #define CLK_GOUT_MISC_DIT_ICLKL2A 330 #define CLK_GOUT_MISC_DIT_ICLKL2A 14 447 #define CLK_GOUT_MISC_D_TZPC_MISC_PCLK 331 #define CLK_GOUT_MISC_D_TZPC_MISC_PCLK 15 448 #define CLK_GOUT_MISC_GIC_GICCLK 332 #define CLK_GOUT_MISC_GIC_GICCLK 16 449 #define CLK_GOUT_MISC_GPC_MISC_PCLK 333 #define CLK_GOUT_MISC_GPC_MISC_PCLK 17 450 #define CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK 334 #define CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK 18 451 #define CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK 335 #define CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK 19 452 #define CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK 336 #define CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK 20 453 #define CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK 337 #define CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK 21 454 #define CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK 338 #define CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK 22 455 #define CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK 339 #define CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK 23 456 #define CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK 340 #define CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK 24 457 #define CLK_GOUT_MISC_MCT_PCLK 341 #define CLK_GOUT_MISC_MCT_PCLK 25 458 #define CLK_GOUT_MISC_OTP_CON_BIRA_PCLK 342 #define CLK_GOUT_MISC_OTP_CON_BIRA_PCLK 26 459 #define CLK_GOUT_MISC_OTP_CON_BISR_PCLK 343 #define CLK_GOUT_MISC_OTP_CON_BISR_PCLK 27 460 #define CLK_GOUT_MISC_OTP_CON_TOP_PCLK 344 #define CLK_GOUT_MISC_OTP_CON_TOP_PCLK 28 461 #define CLK_GOUT_MISC_PDMA_ACLK 345 #define CLK_GOUT_MISC_PDMA_ACLK 29 462 #define CLK_GOUT_MISC_PPMU_DMA_ACLK 346 #define CLK_GOUT_MISC_PPMU_DMA_ACLK 30 463 #define CLK_GOUT_MISC_PPMU_MISC_ACLK 347 #define CLK_GOUT_MISC_PPMU_MISC_ACLK 31 464 #define CLK_GOUT_MISC_PPMU_MISC_PCLK 348 #define CLK_GOUT_MISC_PPMU_MISC_PCLK 32 465 #define CLK_GOUT_MISC_PUF_I_CLK 349 #define CLK_GOUT_MISC_PUF_I_CLK 33 466 #define CLK_GOUT_MISC_QE_DIT_ACLK 350 #define CLK_GOUT_MISC_QE_DIT_ACLK 34 467 #define CLK_GOUT_MISC_QE_DIT_PCLK 351 #define CLK_GOUT_MISC_QE_DIT_PCLK 35 468 #define CLK_GOUT_MISC_QE_PDMA_ACLK 352 #define CLK_GOUT_MISC_QE_PDMA_ACLK 36 469 #define CLK_GOUT_MISC_QE_PDMA_PCLK 353 #define CLK_GOUT_MISC_QE_PDMA_PCLK 37 470 #define CLK_GOUT_MISC_QE_PPMU_DMA_ACLK 354 #define CLK_GOUT_MISC_QE_PPMU_DMA_ACLK 38 471 #define CLK_GOUT_MISC_QE_PPMU_DMA_PCLK 355 #define CLK_GOUT_MISC_QE_PPMU_DMA_PCLK 39 472 #define CLK_GOUT_MISC_QE_RTIC_ACLK 356 #define CLK_GOUT_MISC_QE_RTIC_ACLK 40 473 #define CLK_GOUT_MISC_QE_RTIC_PCLK 357 #define CLK_GOUT_MISC_QE_RTIC_PCLK 41 474 #define CLK_GOUT_MISC_QE_SPDMA_ACLK 358 #define CLK_GOUT_MISC_QE_SPDMA_ACLK 42 475 #define CLK_GOUT_MISC_QE_SPDMA_PCLK 359 #define CLK_GOUT_MISC_QE_SPDMA_PCLK 43 476 #define CLK_GOUT_MISC_QE_SSS_ACLK 360 #define CLK_GOUT_MISC_QE_SSS_ACLK 44 477 #define CLK_GOUT_MISC_QE_SSS_PCLK 361 #define CLK_GOUT_MISC_QE_SSS_PCLK 45 478 #define CLK_GOUT_MISC_CLK_MISC_BUSD_CLK 362 #define CLK_GOUT_MISC_CLK_MISC_BUSD_CLK 46 479 #define CLK_GOUT_MISC_CLK_MISC_BUSP_CLK 363 #define CLK_GOUT_MISC_CLK_MISC_BUSP_CLK 47 480 #define CLK_GOUT_MISC_CLK_MISC_GIC_CLK 364 #define CLK_GOUT_MISC_CLK_MISC_GIC_CLK 48 481 #define CLK_GOUT_MISC_CLK_MISC_SSS_CLK 365 #define CLK_GOUT_MISC_CLK_MISC_SSS_CLK 49 482 #define CLK_GOUT_MISC_RTIC_I_ACLK 366 #define CLK_GOUT_MISC_RTIC_I_ACLK 50 483 #define CLK_GOUT_MISC_RTIC_I_PCLK 367 #define CLK_GOUT_MISC_RTIC_I_PCLK 51 484 #define CLK_GOUT_MISC_SPDMA_ACLK 368 #define CLK_GOUT_MISC_SPDMA_ACLK 52 485 #define CLK_GOUT_MISC_SSMT_DIT_ACLK 369 #define CLK_GOUT_MISC_SSMT_DIT_ACLK 53 486 #define CLK_GOUT_MISC_SSMT_DIT_PCLK 370 #define CLK_GOUT_MISC_SSMT_DIT_PCLK 54 487 #define CLK_GOUT_MISC_SSMT_PDMA_ACLK 371 #define CLK_GOUT_MISC_SSMT_PDMA_ACLK 55 488 #define CLK_GOUT_MISC_SSMT_PDMA_PCLK 372 #define CLK_GOUT_MISC_SSMT_PDMA_PCLK 56 489 #define CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK 373 #define CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK 57 490 #define CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK 374 #define CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK 58 491 #define CLK_GOUT_MISC_SSMT_RTIC_ACLK 375 #define CLK_GOUT_MISC_SSMT_RTIC_ACLK 59 492 #define CLK_GOUT_MISC_SSMT_RTIC_PCLK 376 #define CLK_GOUT_MISC_SSMT_RTIC_PCLK 60 493 #define CLK_GOUT_MISC_SSMT_SPDMA_ACLK 377 #define CLK_GOUT_MISC_SSMT_SPDMA_ACLK 61 494 #define CLK_GOUT_MISC_SSMT_SPDMA_PCLK 378 #define CLK_GOUT_MISC_SSMT_SPDMA_PCLK 62 495 #define CLK_GOUT_MISC_SSMT_SSS_ACLK 379 #define CLK_GOUT_MISC_SSMT_SSS_ACLK 63 496 #define CLK_GOUT_MISC_SSMT_SSS_PCLK 380 #define CLK_GOUT_MISC_SSMT_SSS_PCLK 64 497 #define CLK_GOUT_MISC_SSS_I_ACLK 381 #define CLK_GOUT_MISC_SSS_I_ACLK 65 498 #define CLK_GOUT_MISC_SSS_I_PCLK 382 #define CLK_GOUT_MISC_SSS_I_PCLK 66 499 #define CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2 383 #define CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2 67 500 #define CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1 384 #define CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1 68 501 #define CLK_GOUT_MISC_SYSREG_MISC_PCLK 385 #define CLK_GOUT_MISC_SYSREG_MISC_PCLK 69 502 #define CLK_GOUT_MISC_TMU_SUB_PCLK 386 #define CLK_GOUT_MISC_TMU_SUB_PCLK 70 503 #define CLK_GOUT_MISC_TMU_TOP_PCLK 387 #define CLK_GOUT_MISC_TMU_TOP_PCLK 71 504 #define CLK_GOUT_MISC_WDT_CLUSTER0_PCLK 388 #define CLK_GOUT_MISC_WDT_CLUSTER0_PCLK 72 505 #define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 389 #define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73 506 #define CLK_GOUT_MISC_XIU_D_MISC_ACLK 390 #define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74 507 << 508 /* CMU_PERIC0 */ << 509 #define CLK_MOUT_PERIC0_BUS_USER << 510 #define CLK_MOUT_PERIC0_I3C_USER << 511 #define CLK_MOUT_PERIC0_USI0_UART_USER << 512 #define CLK_MOUT_PERIC0_USI14_USI_USER << 513 #define CLK_MOUT_PERIC0_USI1_USI_USER << 514 #define CLK_MOUT_PERIC0_USI2_USI_USER << 515 #define CLK_MOUT_PERIC0_USI3_USI_USER << 516 #define CLK_MOUT_PERIC0_USI4_USI_USER << 517 #define CLK_MOUT_PERIC0_USI5_USI_USER << 518 #define CLK_MOUT_PERIC0_USI6_USI_USER << 519 #define CLK_MOUT_PERIC0_USI7_USI_USER << 520 #define CLK_MOUT_PERIC0_USI8_USI_USER << 521 #define CLK_DOUT_PERIC0_I3C << 522 #define CLK_DOUT_PERIC0_USI0_UART << 523 #define CLK_DOUT_PERIC0_USI14_USI << 524 #define CLK_DOUT_PERIC0_USI1_USI << 525 #define CLK_DOUT_PERIC0_USI2_USI << 526 #define CLK_DOUT_PERIC0_USI3_USI << 527 #define CLK_DOUT_PERIC0_USI4_USI << 528 #define CLK_DOUT_PERIC0_USI5_USI << 529 #define CLK_DOUT_PERIC0_USI6_USI << 530 #define CLK_DOUT_PERIC0_USI7_USI << 531 #define CLK_DOUT_PERIC0_USI8_USI << 532 #define CLK_GOUT_PERIC0_IP << 533 #define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK << 534 #define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK << 535 #define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK << 536 #define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK << 537 #define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK << 538 #define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK << 539 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 << 540 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 << 541 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 << 542 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 << 543 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 << 544 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 << 545 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 << 546 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 << 547 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 << 548 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 << 549 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 << 550 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 << 551 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 << 552 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 << 553 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 << 554 #define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 << 555 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 << 556 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 << 557 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 << 558 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 << 559 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 << 560 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 << 561 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 << 562 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 << 563 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 << 564 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 << 565 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 << 566 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 << 567 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 << 568 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 << 569 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 << 570 #define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 << 571 #define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 << 572 #define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 << 573 #define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 << 574 #define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 << 575 #define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK << 576 #define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK << 577 #define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_C << 578 #define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_C << 579 #define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CL << 580 #define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CL << 581 #define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CL << 582 #define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CL << 583 #define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CL << 584 #define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CL << 585 #define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CL << 586 #define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CL << 587 #define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK << 588 << 589 /* CMU_PERIC1 */ << 590 #define CLK_MOUT_PERIC1_BUS_USER << 591 #define CLK_MOUT_PERIC1_I3C_USER << 592 #define CLK_MOUT_PERIC1_USI0_USI_USER << 593 #define CLK_MOUT_PERIC1_USI10_USI_USER << 594 #define CLK_MOUT_PERIC1_USI11_USI_USER << 595 #define CLK_MOUT_PERIC1_USI12_USI_USER << 596 #define CLK_MOUT_PERIC1_USI13_USI_USER << 597 #define CLK_MOUT_PERIC1_USI9_USI_USER << 598 #define CLK_DOUT_PERIC1_I3C << 599 #define CLK_DOUT_PERIC1_USI0_USI << 600 #define CLK_DOUT_PERIC1_USI10_USI << 601 #define CLK_DOUT_PERIC1_USI11_USI << 602 #define CLK_DOUT_PERIC1_USI12_USI << 603 #define CLK_DOUT_PERIC1_USI13_USI << 604 #define CLK_DOUT_PERIC1_USI9_USI << 605 #define CLK_GOUT_PERIC1_IP << 606 #define CLK_GOUT_PERIC1_PCLK << 607 #define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK << 608 #define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK << 609 #define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK << 610 #define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK << 611 #define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK << 612 #define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK << 613 #define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 << 614 #define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 << 615 #define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 << 616 #define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 << 617 #define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 << 618 #define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 << 619 #define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 << 620 #define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 << 621 #define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 << 622 #define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 << 623 #define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 << 624 #define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 << 625 #define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 << 626 #define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 << 627 #define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 << 628 #define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK << 629 #define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CL << 630 #define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_C << 631 #define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_C << 632 #define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_C << 633 #define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_C << 634 #define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CL << 635 #define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK << 636 391 637 #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ 392 #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ 638 393
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