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TOMOYO Linux Cross Reference
Linux/include/dt-bindings/clock/hix5hd2-clock.h

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Diff markup

Differences between /include/dt-bindings/clock/hix5hd2-clock.h (Version linux-6.12-rc7) and /include/dt-bindings/clock/hix5hd2-clock.h (Version policy-sample)


  1 /* SPDX-License-Identifier: GPL-2.0-only */         1 
  2 /*                                                
  3  * Copyright (c) 2014 Linaro Ltd.                 
  4  * Copyright (c) 2014 Hisilicon Limited.          
  5  */                                               
  6                                                   
  7 #ifndef __DTS_HIX5HD2_CLOCK_H                     
  8 #define __DTS_HIX5HD2_CLOCK_H                     
  9                                                   
 10 /* fixed rate */                                  
 11 #define HIX5HD2_FIXED_1200M             1         
 12 #define HIX5HD2_FIXED_400M              2         
 13 #define HIX5HD2_FIXED_48M               3         
 14 #define HIX5HD2_FIXED_24M               4         
 15 #define HIX5HD2_FIXED_600M              5         
 16 #define HIX5HD2_FIXED_300M              6         
 17 #define HIX5HD2_FIXED_75M               7         
 18 #define HIX5HD2_FIXED_200M              8         
 19 #define HIX5HD2_FIXED_100M              9         
 20 #define HIX5HD2_FIXED_40M               10        
 21 #define HIX5HD2_FIXED_150M              11        
 22 #define HIX5HD2_FIXED_1728M             12        
 23 #define HIX5HD2_FIXED_28P8M             13        
 24 #define HIX5HD2_FIXED_432M              14        
 25 #define HIX5HD2_FIXED_345P6M            15        
 26 #define HIX5HD2_FIXED_288M              16        
 27 #define HIX5HD2_FIXED_60M               17        
 28 #define HIX5HD2_FIXED_750M              18        
 29 #define HIX5HD2_FIXED_500M              19        
 30 #define HIX5HD2_FIXED_54M               20        
 31 #define HIX5HD2_FIXED_27M               21        
 32 #define HIX5HD2_FIXED_1500M             22        
 33 #define HIX5HD2_FIXED_375M              23        
 34 #define HIX5HD2_FIXED_187M              24        
 35 #define HIX5HD2_FIXED_250M              25        
 36 #define HIX5HD2_FIXED_125M              26        
 37 #define HIX5HD2_FIXED_2P02M             27        
 38 #define HIX5HD2_FIXED_50M               28        
 39 #define HIX5HD2_FIXED_25M               29        
 40 #define HIX5HD2_FIXED_83M               30        
 41                                                   
 42 /* mux clocks */                                  
 43 #define HIX5HD2_SFC_MUX                 64        
 44 #define HIX5HD2_MMC_MUX                 65        
 45 #define HIX5HD2_FEPHY_MUX               66        
 46 #define HIX5HD2_SD_MUX                  67        
 47                                                   
 48 /* gate clocks */                                 
 49 #define HIX5HD2_SFC_RST                 128       
 50 #define HIX5HD2_SFC_CLK                 129       
 51 #define HIX5HD2_MMC_CIU_CLK             130       
 52 #define HIX5HD2_MMC_BIU_CLK             131       
 53 #define HIX5HD2_MMC_CIU_RST             132       
 54 #define HIX5HD2_FWD_BUS_CLK             133       
 55 #define HIX5HD2_FWD_SYS_CLK             134       
 56 #define HIX5HD2_MAC0_PHY_CLK            135       
 57 #define HIX5HD2_SD_CIU_CLK              136       
 58 #define HIX5HD2_SD_BIU_CLK              137       
 59 #define HIX5HD2_SD_CIU_RST              138       
 60 #define HIX5HD2_WDG0_CLK                139       
 61 #define HIX5HD2_WDG0_RST                140       
 62 #define HIX5HD2_I2C0_CLK                141       
 63 #define HIX5HD2_I2C0_RST                142       
 64 #define HIX5HD2_I2C1_CLK                143       
 65 #define HIX5HD2_I2C1_RST                144       
 66 #define HIX5HD2_I2C2_CLK                145       
 67 #define HIX5HD2_I2C2_RST                146       
 68 #define HIX5HD2_I2C3_CLK                147       
 69 #define HIX5HD2_I2C3_RST                148       
 70 #define HIX5HD2_I2C4_CLK                149       
 71 #define HIX5HD2_I2C4_RST                150       
 72 #define HIX5HD2_I2C5_CLK                151       
 73 #define HIX5HD2_I2C5_RST                152       
 74                                                   
 75 /* complex */                                     
 76 #define HIX5HD2_MAC0_CLK                192       
 77 #define HIX5HD2_MAC1_CLK                193       
 78 #define HIX5HD2_SATA_CLK                194       
 79 #define HIX5HD2_USB_CLK                 195       
 80                                                   
 81 #define HIX5HD2_NR_CLKS                 256       
 82 #endif  /* __DTS_HIX5HD2_CLOCK_H */               
 83                                                   

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