1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright (C) 2014 Alexander Shiyan <shc_wo 2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
>> 3 *
>> 4 * This program is free software; you can redistribute it and/or modify
>> 5 * it under the terms of the GNU General Public License version 2 as
>> 6 * published by the Free Software Foundation.
>> 7 *
4 */ 8 */
5 9
6 #ifndef __DT_BINDINGS_CLOCK_IMX27_H 10 #ifndef __DT_BINDINGS_CLOCK_IMX27_H
7 #define __DT_BINDINGS_CLOCK_IMX27_H 11 #define __DT_BINDINGS_CLOCK_IMX27_H
8 12
9 #define IMX27_CLK_DUMMY 0 13 #define IMX27_CLK_DUMMY 0
10 #define IMX27_CLK_CKIH 1 14 #define IMX27_CLK_CKIH 1
11 #define IMX27_CLK_CKIL 2 15 #define IMX27_CLK_CKIL 2
12 #define IMX27_CLK_MPLL 3 16 #define IMX27_CLK_MPLL 3
13 #define IMX27_CLK_SPLL 4 17 #define IMX27_CLK_SPLL 4
14 #define IMX27_CLK_MPLL_MAIN2 5 18 #define IMX27_CLK_MPLL_MAIN2 5
15 #define IMX27_CLK_AHB 6 19 #define IMX27_CLK_AHB 6
16 #define IMX27_CLK_IPG 7 20 #define IMX27_CLK_IPG 7
17 #define IMX27_CLK_NFC_DIV 8 21 #define IMX27_CLK_NFC_DIV 8
18 #define IMX27_CLK_PER1_DIV 9 22 #define IMX27_CLK_PER1_DIV 9
19 #define IMX27_CLK_PER2_DIV 10 23 #define IMX27_CLK_PER2_DIV 10
20 #define IMX27_CLK_PER3_DIV 11 24 #define IMX27_CLK_PER3_DIV 11
21 #define IMX27_CLK_PER4_DIV 12 25 #define IMX27_CLK_PER4_DIV 12
22 #define IMX27_CLK_VPU_SEL 13 26 #define IMX27_CLK_VPU_SEL 13
23 #define IMX27_CLK_VPU_DIV 14 27 #define IMX27_CLK_VPU_DIV 14
24 #define IMX27_CLK_USB_DIV 15 28 #define IMX27_CLK_USB_DIV 15
25 #define IMX27_CLK_CPU_SEL 16 29 #define IMX27_CLK_CPU_SEL 16
26 #define IMX27_CLK_CLKO_SEL 17 30 #define IMX27_CLK_CLKO_SEL 17
27 #define IMX27_CLK_CPU_DIV 18 31 #define IMX27_CLK_CPU_DIV 18
28 #define IMX27_CLK_CLKO_DIV 19 32 #define IMX27_CLK_CLKO_DIV 19
29 #define IMX27_CLK_SSI1_SEL 20 33 #define IMX27_CLK_SSI1_SEL 20
30 #define IMX27_CLK_SSI2_SEL 21 34 #define IMX27_CLK_SSI2_SEL 21
31 #define IMX27_CLK_SSI1_DIV 22 35 #define IMX27_CLK_SSI1_DIV 22
32 #define IMX27_CLK_SSI2_DIV 23 36 #define IMX27_CLK_SSI2_DIV 23
33 #define IMX27_CLK_CLKO_EN 24 37 #define IMX27_CLK_CLKO_EN 24
34 #define IMX27_CLK_SSI2_IPG_GATE 25 38 #define IMX27_CLK_SSI2_IPG_GATE 25
35 #define IMX27_CLK_SSI1_IPG_GATE 26 39 #define IMX27_CLK_SSI1_IPG_GATE 26
36 #define IMX27_CLK_SLCDC_IPG_GATE 27 40 #define IMX27_CLK_SLCDC_IPG_GATE 27
37 #define IMX27_CLK_SDHC3_IPG_GATE 28 41 #define IMX27_CLK_SDHC3_IPG_GATE 28
38 #define IMX27_CLK_SDHC2_IPG_GATE 29 42 #define IMX27_CLK_SDHC2_IPG_GATE 29
39 #define IMX27_CLK_SDHC1_IPG_GATE 30 43 #define IMX27_CLK_SDHC1_IPG_GATE 30
40 #define IMX27_CLK_SCC_IPG_GATE 31 44 #define IMX27_CLK_SCC_IPG_GATE 31
41 #define IMX27_CLK_SAHARA_IPG_GATE 32 45 #define IMX27_CLK_SAHARA_IPG_GATE 32
42 #define IMX27_CLK_RTC_IPG_GATE 33 46 #define IMX27_CLK_RTC_IPG_GATE 33
43 #define IMX27_CLK_PWM_IPG_GATE 34 47 #define IMX27_CLK_PWM_IPG_GATE 34
44 #define IMX27_CLK_OWIRE_IPG_GATE 35 48 #define IMX27_CLK_OWIRE_IPG_GATE 35
45 #define IMX27_CLK_LCDC_IPG_GATE 36 49 #define IMX27_CLK_LCDC_IPG_GATE 36
46 #define IMX27_CLK_KPP_IPG_GATE 37 50 #define IMX27_CLK_KPP_IPG_GATE 37
47 #define IMX27_CLK_IIM_IPG_GATE 38 51 #define IMX27_CLK_IIM_IPG_GATE 38
48 #define IMX27_CLK_I2C2_IPG_GATE 39 52 #define IMX27_CLK_I2C2_IPG_GATE 39
49 #define IMX27_CLK_I2C1_IPG_GATE 40 53 #define IMX27_CLK_I2C1_IPG_GATE 40
50 #define IMX27_CLK_GPT6_IPG_GATE 41 54 #define IMX27_CLK_GPT6_IPG_GATE 41
51 #define IMX27_CLK_GPT5_IPG_GATE 42 55 #define IMX27_CLK_GPT5_IPG_GATE 42
52 #define IMX27_CLK_GPT4_IPG_GATE 43 56 #define IMX27_CLK_GPT4_IPG_GATE 43
53 #define IMX27_CLK_GPT3_IPG_GATE 44 57 #define IMX27_CLK_GPT3_IPG_GATE 44
54 #define IMX27_CLK_GPT2_IPG_GATE 45 58 #define IMX27_CLK_GPT2_IPG_GATE 45
55 #define IMX27_CLK_GPT1_IPG_GATE 46 59 #define IMX27_CLK_GPT1_IPG_GATE 46
56 #define IMX27_CLK_GPIO_IPG_GATE 47 60 #define IMX27_CLK_GPIO_IPG_GATE 47
57 #define IMX27_CLK_FEC_IPG_GATE 48 61 #define IMX27_CLK_FEC_IPG_GATE 48
58 #define IMX27_CLK_EMMA_IPG_GATE 49 62 #define IMX27_CLK_EMMA_IPG_GATE 49
59 #define IMX27_CLK_DMA_IPG_GATE 50 63 #define IMX27_CLK_DMA_IPG_GATE 50
60 #define IMX27_CLK_CSPI3_IPG_GATE 51 64 #define IMX27_CLK_CSPI3_IPG_GATE 51
61 #define IMX27_CLK_CSPI2_IPG_GATE 52 65 #define IMX27_CLK_CSPI2_IPG_GATE 52
62 #define IMX27_CLK_CSPI1_IPG_GATE 53 66 #define IMX27_CLK_CSPI1_IPG_GATE 53
63 #define IMX27_CLK_NFC_BAUD_GATE 54 67 #define IMX27_CLK_NFC_BAUD_GATE 54
64 #define IMX27_CLK_SSI2_BAUD_GATE 55 68 #define IMX27_CLK_SSI2_BAUD_GATE 55
65 #define IMX27_CLK_SSI1_BAUD_GATE 56 69 #define IMX27_CLK_SSI1_BAUD_GATE 56
66 #define IMX27_CLK_VPU_BAUD_GATE 57 70 #define IMX27_CLK_VPU_BAUD_GATE 57
67 #define IMX27_CLK_PER4_GATE 58 71 #define IMX27_CLK_PER4_GATE 58
68 #define IMX27_CLK_PER3_GATE 59 72 #define IMX27_CLK_PER3_GATE 59
69 #define IMX27_CLK_PER2_GATE 60 73 #define IMX27_CLK_PER2_GATE 60
70 #define IMX27_CLK_PER1_GATE 61 74 #define IMX27_CLK_PER1_GATE 61
71 #define IMX27_CLK_USB_AHB_GATE 62 75 #define IMX27_CLK_USB_AHB_GATE 62
72 #define IMX27_CLK_SLCDC_AHB_GATE 63 76 #define IMX27_CLK_SLCDC_AHB_GATE 63
73 #define IMX27_CLK_SAHARA_AHB_GATE 64 77 #define IMX27_CLK_SAHARA_AHB_GATE 64
74 #define IMX27_CLK_LCDC_AHB_GATE 65 78 #define IMX27_CLK_LCDC_AHB_GATE 65
75 #define IMX27_CLK_VPU_AHB_GATE 66 79 #define IMX27_CLK_VPU_AHB_GATE 66
76 #define IMX27_CLK_FEC_AHB_GATE 67 80 #define IMX27_CLK_FEC_AHB_GATE 67
77 #define IMX27_CLK_EMMA_AHB_GATE 68 81 #define IMX27_CLK_EMMA_AHB_GATE 68
78 #define IMX27_CLK_EMI_AHB_GATE 69 82 #define IMX27_CLK_EMI_AHB_GATE 69
79 #define IMX27_CLK_DMA_AHB_GATE 70 83 #define IMX27_CLK_DMA_AHB_GATE 70
80 #define IMX27_CLK_CSI_AHB_GATE 71 84 #define IMX27_CLK_CSI_AHB_GATE 71
81 #define IMX27_CLK_BROM_AHB_GATE 72 85 #define IMX27_CLK_BROM_AHB_GATE 72
82 #define IMX27_CLK_ATA_AHB_GATE 73 86 #define IMX27_CLK_ATA_AHB_GATE 73
83 #define IMX27_CLK_WDOG_IPG_GATE 74 87 #define IMX27_CLK_WDOG_IPG_GATE 74
84 #define IMX27_CLK_USB_IPG_GATE 75 88 #define IMX27_CLK_USB_IPG_GATE 75
85 #define IMX27_CLK_UART6_IPG_GATE 76 89 #define IMX27_CLK_UART6_IPG_GATE 76
86 #define IMX27_CLK_UART5_IPG_GATE 77 90 #define IMX27_CLK_UART5_IPG_GATE 77
87 #define IMX27_CLK_UART4_IPG_GATE 78 91 #define IMX27_CLK_UART4_IPG_GATE 78
88 #define IMX27_CLK_UART3_IPG_GATE 79 92 #define IMX27_CLK_UART3_IPG_GATE 79
89 #define IMX27_CLK_UART2_IPG_GATE 80 93 #define IMX27_CLK_UART2_IPG_GATE 80
90 #define IMX27_CLK_UART1_IPG_GATE 81 94 #define IMX27_CLK_UART1_IPG_GATE 81
91 #define IMX27_CLK_CKIH_DIV1P5 82 95 #define IMX27_CLK_CKIH_DIV1P5 82
92 #define IMX27_CLK_FPM 83 96 #define IMX27_CLK_FPM 83
93 #define IMX27_CLK_MPLL_OSC_SEL 84 97 #define IMX27_CLK_MPLL_OSC_SEL 84
94 #define IMX27_CLK_MPLL_SEL 85 98 #define IMX27_CLK_MPLL_SEL 85
95 #define IMX27_CLK_SPLL_GATE 86 99 #define IMX27_CLK_SPLL_GATE 86
96 #define IMX27_CLK_MSHC_DIV 87 100 #define IMX27_CLK_MSHC_DIV 87
97 #define IMX27_CLK_RTIC_IPG_GATE 88 101 #define IMX27_CLK_RTIC_IPG_GATE 88
98 #define IMX27_CLK_MSHC_IPG_GATE 89 102 #define IMX27_CLK_MSHC_IPG_GATE 89
99 #define IMX27_CLK_RTIC_AHB_GATE 90 103 #define IMX27_CLK_RTIC_AHB_GATE 90
100 #define IMX27_CLK_MSHC_BAUD_GATE 91 104 #define IMX27_CLK_MSHC_BAUD_GATE 91
101 #define IMX27_CLK_CKIH_GATE 92 105 #define IMX27_CLK_CKIH_GATE 92
102 #define IMX27_CLK_MAX 93 106 #define IMX27_CLK_MAX 93
103 107
104 #endif 108 #endif
105 109
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