1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc 4 */ 5 6 #ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H 7 #define __DT_BINDINGS_CLOCK_IMX6QDL_H 8 9 #define IMX6QDL_CLK_DUMMY 10 #define IMX6QDL_CLK_CKIL 11 #define IMX6QDL_CLK_CKIH 12 #define IMX6QDL_CLK_OSC 13 #define IMX6QDL_CLK_PLL2_PFD0_352M 14 #define IMX6QDL_CLK_PLL2_PFD1_594M 15 #define IMX6QDL_CLK_PLL2_PFD2_396M 16 #define IMX6QDL_CLK_PLL3_PFD0_720M 17 #define IMX6QDL_CLK_PLL3_PFD1_540M 18 #define IMX6QDL_CLK_PLL3_PFD2_508M 19 #define IMX6QDL_CLK_PLL3_PFD3_454M 20 #define IMX6QDL_CLK_PLL2_198M 21 #define IMX6QDL_CLK_PLL3_120M 22 #define IMX6QDL_CLK_PLL3_80M 23 #define IMX6QDL_CLK_PLL3_60M 24 #define IMX6QDL_CLK_TWD 25 #define IMX6QDL_CLK_STEP 26 #define IMX6QDL_CLK_PLL1_SW 27 #define IMX6QDL_CLK_PERIPH_PRE 28 #define IMX6QDL_CLK_PERIPH2_PRE 29 #define IMX6QDL_CLK_PERIPH_CLK2_SEL 30 #define IMX6QDL_CLK_PERIPH2_CLK2_SEL 31 #define IMX6QDL_CLK_AXI_SEL 32 #define IMX6QDL_CLK_ESAI_SEL 33 #define IMX6QDL_CLK_ASRC_SEL 34 #define IMX6QDL_CLK_SPDIF_SEL 35 #define IMX6QDL_CLK_GPU2D_AXI 36 #define IMX6QDL_CLK_GPU3D_AXI 37 #define IMX6QDL_CLK_GPU2D_CORE_SEL 38 #define IMX6QDL_CLK_GPU3D_CORE_SEL 39 #define IMX6QDL_CLK_GPU3D_SHADER_SEL 40 #define IMX6QDL_CLK_IPU1_SEL 41 #define IMX6QDL_CLK_IPU2_SEL 42 #define IMX6QDL_CLK_LDB_DI0_SEL 43 #define IMX6QDL_CLK_LDB_DI1_SEL 44 #define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 45 #define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 46 #define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 47 #define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 48 #define IMX6QDL_CLK_IPU1_DI0_SEL 49 #define IMX6QDL_CLK_IPU1_DI1_SEL 50 #define IMX6QDL_CLK_IPU2_DI0_SEL 51 #define IMX6QDL_CLK_IPU2_DI1_SEL 52 #define IMX6QDL_CLK_HSI_TX_SEL 53 #define IMX6QDL_CLK_PCIE_AXI_SEL 54 #define IMX6QDL_CLK_SSI1_SEL 55 #define IMX6QDL_CLK_SSI2_SEL 56 #define IMX6QDL_CLK_SSI3_SEL 57 #define IMX6QDL_CLK_USDHC1_SEL 58 #define IMX6QDL_CLK_USDHC2_SEL 59 #define IMX6QDL_CLK_USDHC3_SEL 60 #define IMX6QDL_CLK_USDHC4_SEL 61 #define IMX6QDL_CLK_ENFC_SEL 62 #define IMX6QDL_CLK_EIM_SEL 63 #define IMX6QDL_CLK_EIM_SLOW_SEL 64 #define IMX6QDL_CLK_VDO_AXI_SEL 65 #define IMX6QDL_CLK_VPU_AXI_SEL 66 #define IMX6QDL_CLK_CKO1_SEL 67 #define IMX6QDL_CLK_PERIPH 68 #define IMX6QDL_CLK_PERIPH2 69 #define IMX6QDL_CLK_PERIPH_CLK2 70 #define IMX6QDL_CLK_PERIPH2_CLK2 71 #define IMX6QDL_CLK_IPG 72 #define IMX6QDL_CLK_IPG_PER 73 #define IMX6QDL_CLK_ESAI_PRED 74 #define IMX6QDL_CLK_ESAI_PODF 75 #define IMX6QDL_CLK_ASRC_PRED 76 #define IMX6QDL_CLK_ASRC_PODF 77 #define IMX6QDL_CLK_SPDIF_PRED 78 #define IMX6QDL_CLK_SPDIF_PODF 79 #define IMX6QDL_CLK_CAN_ROOT 80 #define IMX6QDL_CLK_ECSPI_ROOT 81 #define IMX6QDL_CLK_GPU2D_CORE_PODF 82 #define IMX6QDL_CLK_GPU3D_CORE_PODF 83 #define IMX6QDL_CLK_GPU3D_SHADER 84 #define IMX6QDL_CLK_IPU1_PODF 85 #define IMX6QDL_CLK_IPU2_PODF 86 #define IMX6QDL_CLK_LDB_DI0_PODF 87 #define IMX6QDL_CLK_LDB_DI1_PODF 88 #define IMX6QDL_CLK_IPU1_DI0_PRE 89 #define IMX6QDL_CLK_IPU1_DI1_PRE 90 #define IMX6QDL_CLK_IPU2_DI0_PRE 91 #define IMX6QDL_CLK_IPU2_DI1_PRE 92 #define IMX6QDL_CLK_HSI_TX_PODF 93 #define IMX6QDL_CLK_SSI1_PRED 94 #define IMX6QDL_CLK_SSI1_PODF 95 #define IMX6QDL_CLK_SSI2_PRED 96 #define IMX6QDL_CLK_SSI2_PODF 97 #define IMX6QDL_CLK_SSI3_PRED 98 #define IMX6QDL_CLK_SSI3_PODF 99 #define IMX6QDL_CLK_UART_SERIAL_PODF 100 #define IMX6QDL_CLK_USDHC1_PODF 101 #define IMX6QDL_CLK_USDHC2_PODF 102 #define IMX6QDL_CLK_USDHC3_PODF 103 #define IMX6QDL_CLK_USDHC4_PODF 104 #define IMX6QDL_CLK_ENFC_PRED 105 #define IMX6QDL_CLK_ENFC_PODF 106 #define IMX6QDL_CLK_EIM_PODF 107 #define IMX6QDL_CLK_EIM_SLOW_PODF 108 #define IMX6QDL_CLK_VPU_AXI_PODF 109 #define IMX6QDL_CLK_CKO1_PODF 110 #define IMX6QDL_CLK_AXI 111 #define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 112 #define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 113 #define IMX6QDL_CLK_ARM 114 #define IMX6QDL_CLK_AHB 115 #define IMX6QDL_CLK_APBH_DMA 116 #define IMX6QDL_CLK_ASRC 117 #define IMX6QDL_CLK_CAN1_IPG 118 #define IMX6QDL_CLK_CAN1_SERIAL 119 #define IMX6QDL_CLK_CAN2_IPG 120 #define IMX6QDL_CLK_CAN2_SERIAL 121 #define IMX6QDL_CLK_ECSPI1 122 #define IMX6QDL_CLK_ECSPI2 123 #define IMX6QDL_CLK_ECSPI3 124 #define IMX6QDL_CLK_ECSPI4 125 #define IMX6Q_CLK_ECSPI5 126 #define IMX6DL_CLK_I2C4 127 #define IMX6QDL_CLK_ENET 128 #define IMX6QDL_CLK_ESAI_EXTAL 129 #define IMX6QDL_CLK_GPT_IPG 130 #define IMX6QDL_CLK_GPT_IPG_PER 131 #define IMX6QDL_CLK_GPU2D_CORE 132 #define IMX6QDL_CLK_GPU3D_CORE 133 #define IMX6QDL_CLK_HDMI_IAHB 134 #define IMX6QDL_CLK_HDMI_ISFR 135 #define IMX6QDL_CLK_I2C1 136 #define IMX6QDL_CLK_I2C2 137 #define IMX6QDL_CLK_I2C3 138 #define IMX6QDL_CLK_IIM 139 #define IMX6QDL_CLK_ENFC 140 #define IMX6QDL_CLK_IPU1 141 #define IMX6QDL_CLK_IPU1_DI0 142 #define IMX6QDL_CLK_IPU1_DI1 143 #define IMX6QDL_CLK_IPU2 144 #define IMX6QDL_CLK_IPU2_DI0 145 #define IMX6QDL_CLK_LDB_DI0 146 #define IMX6QDL_CLK_LDB_DI1 147 #define IMX6QDL_CLK_IPU2_DI1 148 #define IMX6QDL_CLK_HSI_TX 149 #define IMX6QDL_CLK_MLB 150 #define IMX6QDL_CLK_MMDC_CH0_AXI 151 #define IMX6QDL_CLK_MMDC_CH1_AXI 152 #define IMX6QDL_CLK_OCRAM 153 #define IMX6QDL_CLK_OPENVG_AXI 154 #define IMX6QDL_CLK_PCIE_AXI 155 #define IMX6QDL_CLK_PWM1 156 #define IMX6QDL_CLK_PWM2 157 #define IMX6QDL_CLK_PWM3 158 #define IMX6QDL_CLK_PWM4 159 #define IMX6QDL_CLK_PER1_BCH 160 #define IMX6QDL_CLK_GPMI_BCH_APB 161 #define IMX6QDL_CLK_GPMI_BCH 162 #define IMX6QDL_CLK_GPMI_IO 163 #define IMX6QDL_CLK_GPMI_APB 164 #define IMX6QDL_CLK_SATA 165 #define IMX6QDL_CLK_SDMA 166 #define IMX6QDL_CLK_SPBA 167 #define IMX6QDL_CLK_SSI1 168 #define IMX6QDL_CLK_SSI2 169 #define IMX6QDL_CLK_SSI3 170 #define IMX6QDL_CLK_UART_IPG 171 #define IMX6QDL_CLK_UART_SERIAL 172 #define IMX6QDL_CLK_USBOH3 173 #define IMX6QDL_CLK_USDHC1 174 #define IMX6QDL_CLK_USDHC2 175 #define IMX6QDL_CLK_USDHC3 176 #define IMX6QDL_CLK_USDHC4 177 #define IMX6QDL_CLK_VDO_AXI 178 #define IMX6QDL_CLK_VPU_AXI 179 #define IMX6QDL_CLK_CKO1 180 #define IMX6QDL_CLK_PLL1_SYS 181 #define IMX6QDL_CLK_PLL2_BUS 182 #define IMX6QDL_CLK_PLL3_USB_OTG 183 #define IMX6QDL_CLK_PLL4_AUDIO 184 #define IMX6QDL_CLK_PLL5_VIDEO 185 #define IMX6QDL_CLK_PLL8_MLB 186 #define IMX6QDL_CLK_PLL7_USB_HOST 187 #define IMX6QDL_CLK_PLL6_ENET 188 #define IMX6QDL_CLK_SSI1_IPG 189 #define IMX6QDL_CLK_SSI2_IPG 190 #define IMX6QDL_CLK_SSI3_IPG 191 #define IMX6QDL_CLK_ROM 192 #define IMX6QDL_CLK_USBPHY1 193 #define IMX6QDL_CLK_USBPHY2 194 #define IMX6QDL_CLK_LDB_DI0_DIV_3_5 195 #define IMX6QDL_CLK_LDB_DI1_DIV_3_5 196 #define IMX6QDL_CLK_SATA_REF 197 #define IMX6QDL_CLK_SATA_REF_100M 198 #define IMX6QDL_CLK_PCIE_REF 199 #define IMX6QDL_CLK_PCIE_REF_125M 200 #define IMX6QDL_CLK_ENET_REF 201 #define IMX6QDL_CLK_USBPHY1_GATE 202 #define IMX6QDL_CLK_USBPHY2_GATE 203 #define IMX6QDL_CLK_PLL4_POST_DIV 204 #define IMX6QDL_CLK_PLL5_POST_DIV 205 #define IMX6QDL_CLK_PLL5_VIDEO_DIV 206 #define IMX6QDL_CLK_EIM_SLOW 207 #define IMX6QDL_CLK_SPDIF 208 #define IMX6QDL_CLK_CKO2_SEL 209 #define IMX6QDL_CLK_CKO2_PODF 210 #define IMX6QDL_CLK_CKO2 211 #define IMX6QDL_CLK_CKO 212 #define IMX6QDL_CLK_VDOA 213 #define IMX6QDL_CLK_PLL4_AUDIO_DIV 214 #define IMX6QDL_CLK_LVDS1_SEL 215 #define IMX6QDL_CLK_LVDS2_SEL 216 #define IMX6QDL_CLK_LVDS1_GATE 217 #define IMX6QDL_CLK_LVDS2_GATE 218 #define IMX6QDL_CLK_ESAI_IPG 219 #define IMX6QDL_CLK_ESAI_MEM 220 #define IMX6QDL_CLK_ASRC_IPG 221 #define IMX6QDL_CLK_ASRC_MEM 222 #define IMX6QDL_CLK_LVDS1_IN 223 #define IMX6QDL_CLK_LVDS2_IN 224 #define IMX6QDL_CLK_ANACLK1 225 #define IMX6QDL_CLK_ANACLK2 226 #define IMX6QDL_PLL1_BYPASS_SRC 227 #define IMX6QDL_PLL2_BYPASS_SRC 228 #define IMX6QDL_PLL3_BYPASS_SRC 229 #define IMX6QDL_PLL4_BYPASS_SRC 230 #define IMX6QDL_PLL5_BYPASS_SRC 231 #define IMX6QDL_PLL6_BYPASS_SRC 232 #define IMX6QDL_PLL7_BYPASS_SRC 233 #define IMX6QDL_CLK_PLL1 234 #define IMX6QDL_CLK_PLL2 235 #define IMX6QDL_CLK_PLL3 236 #define IMX6QDL_CLK_PLL4 237 #define IMX6QDL_CLK_PLL5 238 #define IMX6QDL_CLK_PLL6 239 #define IMX6QDL_CLK_PLL7 240 #define IMX6QDL_PLL1_BYPASS 241 #define IMX6QDL_PLL2_BYPASS 242 #define IMX6QDL_PLL3_BYPASS 243 #define IMX6QDL_PLL4_BYPASS 244 #define IMX6QDL_PLL5_BYPASS 245 #define IMX6QDL_PLL6_BYPASS 246 #define IMX6QDL_PLL7_BYPASS 247 #define IMX6QDL_CLK_GPT_3M 248 #define IMX6QDL_CLK_VIDEO_27M 249 #define IMX6QDL_CLK_MIPI_CORE_CFG 250 #define IMX6QDL_CLK_MIPI_IPG 251 #define IMX6QDL_CLK_CAAM_MEM 252 #define IMX6QDL_CLK_CAAM_ACLK 253 #define IMX6QDL_CLK_CAAM_IPG 254 #define IMX6QDL_CLK_SPDIF_GCLK 255 #define IMX6QDL_CLK_UART_SEL 256 #define IMX6QDL_CLK_IPG_PER_SEL 257 #define IMX6QDL_CLK_ECSPI_SEL 258 #define IMX6QDL_CLK_CAN_SEL 259 #define IMX6QDL_CLK_MMDC_CH1_AXI_CG 260 #define IMX6QDL_CLK_PRE0 261 #define IMX6QDL_CLK_PRE1 262 #define IMX6QDL_CLK_PRE2 263 #define IMX6QDL_CLK_PRE3 264 #define IMX6QDL_CLK_PRG0_AXI 265 #define IMX6QDL_CLK_PRG1_AXI 266 #define IMX6QDL_CLK_PRG0_APB 267 #define IMX6QDL_CLK_PRG1_APB 268 #define IMX6QDL_CLK_PRE_AXI 269 #define IMX6QDL_CLK_MLB_SEL 270 #define IMX6QDL_CLK_MLB_PODF 271 #define IMX6QDL_CLK_EPIT1 272 #define IMX6QDL_CLK_EPIT2 273 #define IMX6QDL_CLK_MMDC_P0_IPG 274 #define IMX6QDL_CLK_DCIC1 275 #define IMX6QDL_CLK_DCIC2 276 #define IMX6QDL_CLK_ENET_REF_SEL 277 #define IMX6QDL_CLK_ENET_REF_PAD 278 #define IMX6QDL_CLK_END 279 280 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ 281
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