1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 2 /* 3 * Copyright 2018 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7 #ifndef __DT_BINDINGS_CLOCK_IMX_H 8 #define __DT_BINDINGS_CLOCK_IMX_H 9 10 /* LPCG clocks */ 11 12 /* LSIO SS LPCG */ 13 #define IMX_LSIO_LPCG_PWM0_IPG_CLK 14 #define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 15 #define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 16 #define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 17 #define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 18 #define IMX_LSIO_LPCG_PWM1_IPG_CLK 19 #define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 20 #define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 21 #define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 22 #define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 23 #define IMX_LSIO_LPCG_PWM2_IPG_CLK 24 #define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 25 #define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 26 #define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 27 #define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 28 #define IMX_LSIO_LPCG_PWM3_IPG_CLK 29 #define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 30 #define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 31 #define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 32 #define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 33 #define IMX_LSIO_LPCG_PWM4_IPG_CLK 34 #define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 35 #define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 36 #define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 37 #define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 38 #define IMX_LSIO_LPCG_PWM5_IPG_CLK 39 #define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 40 #define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 41 #define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 42 #define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 43 #define IMX_LSIO_LPCG_PWM6_IPG_CLK 44 #define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 45 #define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 46 #define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 47 #define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 48 #define IMX_LSIO_LPCG_PWM7_IPG_CLK 49 #define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 50 #define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 51 #define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 52 #define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 53 #define IMX_LSIO_LPCG_GPT0_IPG_CLK 54 #define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 55 #define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 56 #define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 57 #define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 58 #define IMX_LSIO_LPCG_GPT1_IPG_CLK 59 #define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 60 #define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 61 #define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 62 #define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 63 #define IMX_LSIO_LPCG_GPT2_IPG_CLK 64 #define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 65 #define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 66 #define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 67 #define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 68 #define IMX_LSIO_LPCG_GPT3_IPG_CLK 69 #define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 70 #define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 71 #define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 72 #define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 73 #define IMX_LSIO_LPCG_GPT4_IPG_CLK 74 #define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 75 #define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 76 #define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 77 #define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 78 #define IMX_LSIO_LPCG_FSPI0_HCLK 79 #define IMX_LSIO_LPCG_FSPI0_IPG_CLK 80 #define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 81 #define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 82 #define IMX_LSIO_LPCG_FSPI1_HCLK 83 #define IMX_LSIO_LPCG_FSPI1_IPG_CLK 84 #define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 85 #define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 86 87 #define IMX_LSIO_LPCG_CLK_END 88 89 /* Connectivity SS LPCG */ 90 #define IMX_CONN_LPCG_SDHC0_IPG_CLK 91 #define IMX_CONN_LPCG_SDHC0_PER_CLK 92 #define IMX_CONN_LPCG_SDHC0_HCLK 93 #define IMX_CONN_LPCG_SDHC1_IPG_CLK 94 #define IMX_CONN_LPCG_SDHC1_PER_CLK 95 #define IMX_CONN_LPCG_SDHC1_HCLK 96 #define IMX_CONN_LPCG_SDHC2_IPG_CLK 97 #define IMX_CONN_LPCG_SDHC2_PER_CLK 98 #define IMX_CONN_LPCG_SDHC2_HCLK 99 #define IMX_CONN_LPCG_GPMI_APB_CLK 100 #define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 101 #define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 102 #define IMX_CONN_LPCG_GPMI_BCH_CLK 103 #define IMX_CONN_LPCG_APBHDMA_CLK 104 #define IMX_CONN_LPCG_ENET0_ROOT_CLK 105 #define IMX_CONN_LPCG_ENET0_TX_CLK 106 #define IMX_CONN_LPCG_ENET0_AHB_CLK 107 #define IMX_CONN_LPCG_ENET0_IPG_S_CLK 108 #define IMX_CONN_LPCG_ENET0_IPG_CLK 109 110 #define IMX_CONN_LPCG_ENET1_ROOT_CLK 111 #define IMX_CONN_LPCG_ENET1_TX_CLK 112 #define IMX_CONN_LPCG_ENET1_AHB_CLK 113 #define IMX_CONN_LPCG_ENET1_IPG_S_CLK 114 #define IMX_CONN_LPCG_ENET1_IPG_CLK 115 116 #define IMX_CONN_LPCG_CLK_END 117 118 /* ADMA SS LPCG */ 119 #define IMX_ADMA_LPCG_UART0_IPG_CLK 120 #define IMX_ADMA_LPCG_UART0_BAUD_CLK 121 #define IMX_ADMA_LPCG_UART1_IPG_CLK 122 #define IMX_ADMA_LPCG_UART1_BAUD_CLK 123 #define IMX_ADMA_LPCG_UART2_IPG_CLK 124 #define IMX_ADMA_LPCG_UART2_BAUD_CLK 125 #define IMX_ADMA_LPCG_UART3_IPG_CLK 126 #define IMX_ADMA_LPCG_UART3_BAUD_CLK 127 #define IMX_ADMA_LPCG_SPI0_IPG_CLK 128 #define IMX_ADMA_LPCG_SPI1_IPG_CLK 129 #define IMX_ADMA_LPCG_SPI2_IPG_CLK 130 #define IMX_ADMA_LPCG_SPI3_IPG_CLK 131 #define IMX_ADMA_LPCG_SPI0_CLK 132 #define IMX_ADMA_LPCG_SPI1_CLK 133 #define IMX_ADMA_LPCG_SPI2_CLK 134 #define IMX_ADMA_LPCG_SPI3_CLK 135 #define IMX_ADMA_LPCG_CAN0_IPG_CLK 136 #define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 137 #define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 138 #define IMX_ADMA_LPCG_CAN1_IPG_CLK 139 #define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 140 #define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 141 #define IMX_ADMA_LPCG_CAN2_IPG_CLK 142 #define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 143 #define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 144 #define IMX_ADMA_LPCG_I2C0_CLK 145 #define IMX_ADMA_LPCG_I2C1_CLK 146 #define IMX_ADMA_LPCG_I2C2_CLK 147 #define IMX_ADMA_LPCG_I2C3_CLK 148 #define IMX_ADMA_LPCG_I2C0_IPG_CLK 149 #define IMX_ADMA_LPCG_I2C1_IPG_CLK 150 #define IMX_ADMA_LPCG_I2C2_IPG_CLK 151 #define IMX_ADMA_LPCG_I2C3_IPG_CLK 152 #define IMX_ADMA_LPCG_FTM0_CLK 153 #define IMX_ADMA_LPCG_FTM1_CLK 154 #define IMX_ADMA_LPCG_FTM0_IPG_CLK 155 #define IMX_ADMA_LPCG_FTM1_IPG_CLK 156 #define IMX_ADMA_LPCG_PWM_HI_CLK 157 #define IMX_ADMA_LPCG_PWM_IPG_CLK 158 #define IMX_ADMA_LPCG_LCD_PIX_CLK 159 #define IMX_ADMA_LPCG_LCD_APB_CLK 160 #define IMX_ADMA_LPCG_DSP_ADB_CLK 161 #define IMX_ADMA_LPCG_DSP_IPG_CLK 162 #define IMX_ADMA_LPCG_DSP_CORE_CLK 163 #define IMX_ADMA_LPCG_OCRAM_IPG_CLK 164 165 #define IMX_ADMA_LPCG_CLK_END 166 167 #define IMX_ADMA_ACM_AUD_CLK0_SEL 168 #define IMX_ADMA_ACM_AUD_CLK1_SEL 169 #define IMX_ADMA_ACM_MCLKOUT0_SEL 170 #define IMX_ADMA_ACM_MCLKOUT1_SEL 171 #define IMX_ADMA_ACM_ESAI0_MCLK_SEL 172 #define IMX_ADMA_ACM_ESAI1_MCLK_SEL 173 #define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL 174 #define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL 175 #define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL 176 #define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL 177 #define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL 178 #define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL 179 #define IMX_ADMA_ACM_SAI0_MCLK_SEL 180 #define IMX_ADMA_ACM_SAI1_MCLK_SEL 181 #define IMX_ADMA_ACM_SAI2_MCLK_SEL 182 #define IMX_ADMA_ACM_SAI3_MCLK_SEL 183 #define IMX_ADMA_ACM_SAI4_MCLK_SEL 184 #define IMX_ADMA_ACM_SAI5_MCLK_SEL 185 #define IMX_ADMA_ACM_SAI6_MCLK_SEL 186 #define IMX_ADMA_ACM_SAI7_MCLK_SEL 187 #define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL 188 #define IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL 189 #define IMX_ADMA_ACM_MQS_TX_CLK_SEL 190 #define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL 191 #define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL 192 193 #define IMX_ADMA_ACM_CLK_END 194 195 #endif /* __DT_BINDINGS_CLOCK_IMX_H */ 196
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