1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright 2018 NXP 3 * Copyright 2018 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com> 4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */ 5 */
6 6
7 #ifndef __DT_BINDINGS_CLOCK_IMX_H 7 #ifndef __DT_BINDINGS_CLOCK_IMX_H
8 #define __DT_BINDINGS_CLOCK_IMX_H 8 #define __DT_BINDINGS_CLOCK_IMX_H
9 9
>> 10 /* SCU Clocks */
>> 11
>> 12 #define IMX_CLK_DUMMY 0
>> 13
>> 14 /* CPU */
>> 15 #define IMX_A35_CLK 1
>> 16
>> 17 /* LSIO SS */
>> 18 #define IMX_LSIO_MEM_CLK 2
>> 19 #define IMX_LSIO_BUS_CLK 3
>> 20 #define IMX_LSIO_PWM0_CLK 10
>> 21 #define IMX_LSIO_PWM1_CLK 11
>> 22 #define IMX_LSIO_PWM2_CLK 12
>> 23 #define IMX_LSIO_PWM3_CLK 13
>> 24 #define IMX_LSIO_PWM4_CLK 14
>> 25 #define IMX_LSIO_PWM5_CLK 15
>> 26 #define IMX_LSIO_PWM6_CLK 16
>> 27 #define IMX_LSIO_PWM7_CLK 17
>> 28 #define IMX_LSIO_GPT0_CLK 18
>> 29 #define IMX_LSIO_GPT1_CLK 19
>> 30 #define IMX_LSIO_GPT2_CLK 20
>> 31 #define IMX_LSIO_GPT3_CLK 21
>> 32 #define IMX_LSIO_GPT4_CLK 22
>> 33 #define IMX_LSIO_FSPI0_CLK 23
>> 34 #define IMX_LSIO_FSPI1_CLK 24
>> 35
>> 36 /* Connectivity SS */
>> 37 #define IMX_CONN_AXI_CLK_ROOT 30
>> 38 #define IMX_CONN_AHB_CLK_ROOT 31
>> 39 #define IMX_CONN_IPG_CLK_ROOT 32
>> 40 #define IMX_CONN_SDHC0_CLK 40
>> 41 #define IMX_CONN_SDHC1_CLK 41
>> 42 #define IMX_CONN_SDHC2_CLK 42
>> 43 #define IMX_CONN_ENET0_ROOT_CLK 43
>> 44 #define IMX_CONN_ENET0_BYPASS_CLK 44
>> 45 #define IMX_CONN_ENET0_RGMII_CLK 45
>> 46 #define IMX_CONN_ENET1_ROOT_CLK 46
>> 47 #define IMX_CONN_ENET1_BYPASS_CLK 47
>> 48 #define IMX_CONN_ENET1_RGMII_CLK 48
>> 49 #define IMX_CONN_GPMI_BCH_IO_CLK 49
>> 50 #define IMX_CONN_GPMI_BCH_CLK 50
>> 51 #define IMX_CONN_USB2_ACLK 51
>> 52 #define IMX_CONN_USB2_BUS_CLK 52
>> 53 #define IMX_CONN_USB2_LPM_CLK 53
>> 54
>> 55 /* HSIO SS */
>> 56 #define IMX_HSIO_AXI_CLK 60
>> 57 #define IMX_HSIO_PER_CLK 61
>> 58
>> 59 /* Display controller SS */
>> 60 #define IMX_DC_AXI_EXT_CLK 70
>> 61 #define IMX_DC_AXI_INT_CLK 71
>> 62 #define IMX_DC_CFG_CLK 72
>> 63 #define IMX_DC0_PLL0_CLK 80
>> 64 #define IMX_DC0_PLL1_CLK 81
>> 65 #define IMX_DC0_DISP0_CLK 82
>> 66 #define IMX_DC0_DISP1_CLK 83
>> 67
>> 68 /* MIPI-LVDS SS */
>> 69 #define IMX_MIPI_IPG_CLK 90
>> 70 #define IMX_MIPI0_PIXEL_CLK 100
>> 71 #define IMX_MIPI0_BYPASS_CLK 101
>> 72 #define IMX_MIPI0_LVDS_PIXEL_CLK 102
>> 73 #define IMX_MIPI0_LVDS_BYPASS_CLK 103
>> 74 #define IMX_MIPI0_LVDS_PHY_CLK 104
>> 75 #define IMX_MIPI0_I2C0_CLK 105
>> 76 #define IMX_MIPI0_I2C1_CLK 106
>> 77 #define IMX_MIPI0_PWM0_CLK 107
>> 78 #define IMX_MIPI1_PIXEL_CLK 108
>> 79 #define IMX_MIPI1_BYPASS_CLK 109
>> 80 #define IMX_MIPI1_LVDS_PIXEL_CLK 110
>> 81 #define IMX_MIPI1_LVDS_BYPASS_CLK 111
>> 82 #define IMX_MIPI1_LVDS_PHY_CLK 112
>> 83 #define IMX_MIPI1_I2C0_CLK 113
>> 84 #define IMX_MIPI1_I2C1_CLK 114
>> 85 #define IMX_MIPI1_PWM0_CLK 115
>> 86
>> 87 /* IMG SS */
>> 88 #define IMX_IMG_AXI_CLK 120
>> 89 #define IMX_IMG_IPG_CLK 121
>> 90 #define IMX_IMG_PXL_CLK 122
>> 91
>> 92 /* MIPI-CSI SS */
>> 93 #define IMX_CSI0_CORE_CLK 130
>> 94 #define IMX_CSI0_ESC_CLK 131
>> 95 #define IMX_CSI0_PWM0_CLK 132
>> 96 #define IMX_CSI0_I2C0_CLK 133
>> 97
>> 98 /* PARALLER CSI SS */
>> 99 #define IMX_PARALLEL_CSI_DPLL_CLK 140
>> 100 #define IMX_PARALLEL_CSI_PIXEL_CLK 141
>> 101 #define IMX_PARALLEL_CSI_MCLK_CLK 142
>> 102
>> 103 /* VPU SS */
>> 104 #define IMX_VPU_ENC_CLK 150
>> 105 #define IMX_VPU_DEC_CLK 151
>> 106
>> 107 /* GPU SS */
>> 108 #define IMX_GPU0_CORE_CLK 160
>> 109 #define IMX_GPU0_SHADER_CLK 161
>> 110
>> 111 /* ADMA SS */
>> 112 #define IMX_ADMA_IPG_CLK_ROOT 165
>> 113 #define IMX_ADMA_UART0_CLK 170
>> 114 #define IMX_ADMA_UART1_CLK 171
>> 115 #define IMX_ADMA_UART2_CLK 172
>> 116 #define IMX_ADMA_UART3_CLK 173
>> 117 #define IMX_ADMA_SPI0_CLK 174
>> 118 #define IMX_ADMA_SPI1_CLK 175
>> 119 #define IMX_ADMA_SPI2_CLK 176
>> 120 #define IMX_ADMA_SPI3_CLK 177
>> 121 #define IMX_ADMA_CAN0_CLK 178
>> 122 #define IMX_ADMA_CAN1_CLK 179
>> 123 #define IMX_ADMA_CAN2_CLK 180
>> 124 #define IMX_ADMA_I2C0_CLK 181
>> 125 #define IMX_ADMA_I2C1_CLK 182
>> 126 #define IMX_ADMA_I2C2_CLK 183
>> 127 #define IMX_ADMA_I2C3_CLK 184
>> 128 #define IMX_ADMA_FTM0_CLK 185
>> 129 #define IMX_ADMA_FTM1_CLK 186
>> 130 #define IMX_ADMA_ADC0_CLK 187
>> 131 #define IMX_ADMA_PWM_CLK 188
>> 132 #define IMX_ADMA_LCD_CLK 189
>> 133
>> 134 #define IMX_SCU_CLK_END 190
>> 135
10 /* LPCG clocks */ 136 /* LPCG clocks */
11 137
12 /* LSIO SS LPCG */ 138 /* LSIO SS LPCG */
13 #define IMX_LSIO_LPCG_PWM0_IPG_CLK 139 #define IMX_LSIO_LPCG_PWM0_IPG_CLK 0
14 #define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 140 #define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 1
15 #define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 141 #define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 2
16 #define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 142 #define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 3
17 #define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 143 #define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4
18 #define IMX_LSIO_LPCG_PWM1_IPG_CLK 144 #define IMX_LSIO_LPCG_PWM1_IPG_CLK 5
19 #define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 145 #define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 6
20 #define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 146 #define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 7
21 #define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 147 #define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 8
22 #define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 148 #define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9
23 #define IMX_LSIO_LPCG_PWM2_IPG_CLK 149 #define IMX_LSIO_LPCG_PWM2_IPG_CLK 10
24 #define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 150 #define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 11
25 #define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 151 #define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 12
26 #define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 152 #define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 13
27 #define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 153 #define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14
28 #define IMX_LSIO_LPCG_PWM3_IPG_CLK 154 #define IMX_LSIO_LPCG_PWM3_IPG_CLK 15
29 #define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 155 #define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 16
30 #define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 156 #define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 17
31 #define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 157 #define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 18
32 #define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 158 #define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19
33 #define IMX_LSIO_LPCG_PWM4_IPG_CLK 159 #define IMX_LSIO_LPCG_PWM4_IPG_CLK 20
34 #define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 160 #define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 21
35 #define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 161 #define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 22
36 #define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 162 #define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 23
37 #define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 163 #define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24
38 #define IMX_LSIO_LPCG_PWM5_IPG_CLK 164 #define IMX_LSIO_LPCG_PWM5_IPG_CLK 25
39 #define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 165 #define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 26
40 #define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 166 #define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 27
41 #define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 167 #define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 28
42 #define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 168 #define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29
43 #define IMX_LSIO_LPCG_PWM6_IPG_CLK 169 #define IMX_LSIO_LPCG_PWM6_IPG_CLK 30
44 #define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 170 #define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 31
45 #define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 171 #define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 32
46 #define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 172 #define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 33
47 #define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 173 #define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34
48 #define IMX_LSIO_LPCG_PWM7_IPG_CLK 174 #define IMX_LSIO_LPCG_PWM7_IPG_CLK 35
49 #define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 175 #define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 36
50 #define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 176 #define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 37
51 #define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 177 #define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 38
52 #define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 178 #define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39
53 #define IMX_LSIO_LPCG_GPT0_IPG_CLK 179 #define IMX_LSIO_LPCG_GPT0_IPG_CLK 40
54 #define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 180 #define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 41
55 #define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 181 #define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 42
56 #define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 182 #define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 43
57 #define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 183 #define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44
58 #define IMX_LSIO_LPCG_GPT1_IPG_CLK 184 #define IMX_LSIO_LPCG_GPT1_IPG_CLK 45
59 #define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 185 #define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 46
60 #define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 186 #define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 47
61 #define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 187 #define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 48
62 #define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 188 #define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49
63 #define IMX_LSIO_LPCG_GPT2_IPG_CLK 189 #define IMX_LSIO_LPCG_GPT2_IPG_CLK 50
64 #define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 190 #define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 51
65 #define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 191 #define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 52
66 #define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 192 #define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 53
67 #define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 193 #define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54
68 #define IMX_LSIO_LPCG_GPT3_IPG_CLK 194 #define IMX_LSIO_LPCG_GPT3_IPG_CLK 55
69 #define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 195 #define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 56
70 #define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 196 #define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 57
71 #define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 197 #define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 58
72 #define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 198 #define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59
73 #define IMX_LSIO_LPCG_GPT4_IPG_CLK 199 #define IMX_LSIO_LPCG_GPT4_IPG_CLK 60
74 #define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 200 #define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 61
75 #define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 201 #define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 62
76 #define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 202 #define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 63
77 #define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 203 #define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64
78 #define IMX_LSIO_LPCG_FSPI0_HCLK 204 #define IMX_LSIO_LPCG_FSPI0_HCLK 65
79 #define IMX_LSIO_LPCG_FSPI0_IPG_CLK 205 #define IMX_LSIO_LPCG_FSPI0_IPG_CLK 66
80 #define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 206 #define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 67
81 #define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 207 #define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 68
82 #define IMX_LSIO_LPCG_FSPI1_HCLK 208 #define IMX_LSIO_LPCG_FSPI1_HCLK 69
83 #define IMX_LSIO_LPCG_FSPI1_IPG_CLK 209 #define IMX_LSIO_LPCG_FSPI1_IPG_CLK 70
84 #define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 210 #define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 71
85 #define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 211 #define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 72
86 212
87 #define IMX_LSIO_LPCG_CLK_END 213 #define IMX_LSIO_LPCG_CLK_END 73
88 214
89 /* Connectivity SS LPCG */ 215 /* Connectivity SS LPCG */
90 #define IMX_CONN_LPCG_SDHC0_IPG_CLK 216 #define IMX_CONN_LPCG_SDHC0_IPG_CLK 0
91 #define IMX_CONN_LPCG_SDHC0_PER_CLK 217 #define IMX_CONN_LPCG_SDHC0_PER_CLK 1
92 #define IMX_CONN_LPCG_SDHC0_HCLK 218 #define IMX_CONN_LPCG_SDHC0_HCLK 2
93 #define IMX_CONN_LPCG_SDHC1_IPG_CLK 219 #define IMX_CONN_LPCG_SDHC1_IPG_CLK 3
94 #define IMX_CONN_LPCG_SDHC1_PER_CLK 220 #define IMX_CONN_LPCG_SDHC1_PER_CLK 4
95 #define IMX_CONN_LPCG_SDHC1_HCLK 221 #define IMX_CONN_LPCG_SDHC1_HCLK 5
96 #define IMX_CONN_LPCG_SDHC2_IPG_CLK 222 #define IMX_CONN_LPCG_SDHC2_IPG_CLK 6
97 #define IMX_CONN_LPCG_SDHC2_PER_CLK 223 #define IMX_CONN_LPCG_SDHC2_PER_CLK 7
98 #define IMX_CONN_LPCG_SDHC2_HCLK 224 #define IMX_CONN_LPCG_SDHC2_HCLK 8
99 #define IMX_CONN_LPCG_GPMI_APB_CLK 225 #define IMX_CONN_LPCG_GPMI_APB_CLK 9
100 #define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 226 #define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 10
101 #define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 227 #define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 11
102 #define IMX_CONN_LPCG_GPMI_BCH_CLK 228 #define IMX_CONN_LPCG_GPMI_BCH_CLK 12
103 #define IMX_CONN_LPCG_APBHDMA_CLK 229 #define IMX_CONN_LPCG_APBHDMA_CLK 13
104 #define IMX_CONN_LPCG_ENET0_ROOT_CLK 230 #define IMX_CONN_LPCG_ENET0_ROOT_CLK 14
105 #define IMX_CONN_LPCG_ENET0_TX_CLK 231 #define IMX_CONN_LPCG_ENET0_TX_CLK 15
106 #define IMX_CONN_LPCG_ENET0_AHB_CLK 232 #define IMX_CONN_LPCG_ENET0_AHB_CLK 16
107 #define IMX_CONN_LPCG_ENET0_IPG_S_CLK 233 #define IMX_CONN_LPCG_ENET0_IPG_S_CLK 17
108 #define IMX_CONN_LPCG_ENET0_IPG_CLK 234 #define IMX_CONN_LPCG_ENET0_IPG_CLK 18
109 235
110 #define IMX_CONN_LPCG_ENET1_ROOT_CLK 236 #define IMX_CONN_LPCG_ENET1_ROOT_CLK 19
111 #define IMX_CONN_LPCG_ENET1_TX_CLK 237 #define IMX_CONN_LPCG_ENET1_TX_CLK 20
112 #define IMX_CONN_LPCG_ENET1_AHB_CLK 238 #define IMX_CONN_LPCG_ENET1_AHB_CLK 21
113 #define IMX_CONN_LPCG_ENET1_IPG_S_CLK 239 #define IMX_CONN_LPCG_ENET1_IPG_S_CLK 22
114 #define IMX_CONN_LPCG_ENET1_IPG_CLK 240 #define IMX_CONN_LPCG_ENET1_IPG_CLK 23
115 241
116 #define IMX_CONN_LPCG_CLK_END 242 #define IMX_CONN_LPCG_CLK_END 24
117 243
118 /* ADMA SS LPCG */ 244 /* ADMA SS LPCG */
119 #define IMX_ADMA_LPCG_UART0_IPG_CLK 245 #define IMX_ADMA_LPCG_UART0_IPG_CLK 0
120 #define IMX_ADMA_LPCG_UART0_BAUD_CLK 246 #define IMX_ADMA_LPCG_UART0_BAUD_CLK 1
121 #define IMX_ADMA_LPCG_UART1_IPG_CLK 247 #define IMX_ADMA_LPCG_UART1_IPG_CLK 2
122 #define IMX_ADMA_LPCG_UART1_BAUD_CLK 248 #define IMX_ADMA_LPCG_UART1_BAUD_CLK 3
123 #define IMX_ADMA_LPCG_UART2_IPG_CLK 249 #define IMX_ADMA_LPCG_UART2_IPG_CLK 4
124 #define IMX_ADMA_LPCG_UART2_BAUD_CLK 250 #define IMX_ADMA_LPCG_UART2_BAUD_CLK 5
125 #define IMX_ADMA_LPCG_UART3_IPG_CLK 251 #define IMX_ADMA_LPCG_UART3_IPG_CLK 6
126 #define IMX_ADMA_LPCG_UART3_BAUD_CLK 252 #define IMX_ADMA_LPCG_UART3_BAUD_CLK 7
127 #define IMX_ADMA_LPCG_SPI0_IPG_CLK 253 #define IMX_ADMA_LPCG_SPI0_IPG_CLK 8
128 #define IMX_ADMA_LPCG_SPI1_IPG_CLK 254 #define IMX_ADMA_LPCG_SPI1_IPG_CLK 9
129 #define IMX_ADMA_LPCG_SPI2_IPG_CLK 255 #define IMX_ADMA_LPCG_SPI2_IPG_CLK 10
130 #define IMX_ADMA_LPCG_SPI3_IPG_CLK 256 #define IMX_ADMA_LPCG_SPI3_IPG_CLK 11
131 #define IMX_ADMA_LPCG_SPI0_CLK 257 #define IMX_ADMA_LPCG_SPI0_CLK 12
132 #define IMX_ADMA_LPCG_SPI1_CLK 258 #define IMX_ADMA_LPCG_SPI1_CLK 13
133 #define IMX_ADMA_LPCG_SPI2_CLK 259 #define IMX_ADMA_LPCG_SPI2_CLK 14
134 #define IMX_ADMA_LPCG_SPI3_CLK 260 #define IMX_ADMA_LPCG_SPI3_CLK 15
135 #define IMX_ADMA_LPCG_CAN0_IPG_CLK 261 #define IMX_ADMA_LPCG_CAN0_IPG_CLK 16
136 #define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 262 #define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 17
137 #define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 263 #define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 18
138 #define IMX_ADMA_LPCG_CAN1_IPG_CLK 264 #define IMX_ADMA_LPCG_CAN1_IPG_CLK 19
139 #define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 265 #define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 20
140 #define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 266 #define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 21
141 #define IMX_ADMA_LPCG_CAN2_IPG_CLK 267 #define IMX_ADMA_LPCG_CAN2_IPG_CLK 22
142 #define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 268 #define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 23
143 #define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 269 #define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 24
144 #define IMX_ADMA_LPCG_I2C0_CLK 270 #define IMX_ADMA_LPCG_I2C0_CLK 25
145 #define IMX_ADMA_LPCG_I2C1_CLK 271 #define IMX_ADMA_LPCG_I2C1_CLK 26
146 #define IMX_ADMA_LPCG_I2C2_CLK 272 #define IMX_ADMA_LPCG_I2C2_CLK 27
147 #define IMX_ADMA_LPCG_I2C3_CLK 273 #define IMX_ADMA_LPCG_I2C3_CLK 28
148 #define IMX_ADMA_LPCG_I2C0_IPG_CLK 274 #define IMX_ADMA_LPCG_I2C0_IPG_CLK 29
149 #define IMX_ADMA_LPCG_I2C1_IPG_CLK 275 #define IMX_ADMA_LPCG_I2C1_IPG_CLK 30
150 #define IMX_ADMA_LPCG_I2C2_IPG_CLK 276 #define IMX_ADMA_LPCG_I2C2_IPG_CLK 31
151 #define IMX_ADMA_LPCG_I2C3_IPG_CLK 277 #define IMX_ADMA_LPCG_I2C3_IPG_CLK 32
152 #define IMX_ADMA_LPCG_FTM0_CLK 278 #define IMX_ADMA_LPCG_FTM0_CLK 33
153 #define IMX_ADMA_LPCG_FTM1_CLK 279 #define IMX_ADMA_LPCG_FTM1_CLK 34
154 #define IMX_ADMA_LPCG_FTM0_IPG_CLK 280 #define IMX_ADMA_LPCG_FTM0_IPG_CLK 35
155 #define IMX_ADMA_LPCG_FTM1_IPG_CLK 281 #define IMX_ADMA_LPCG_FTM1_IPG_CLK 36
156 #define IMX_ADMA_LPCG_PWM_HI_CLK 282 #define IMX_ADMA_LPCG_PWM_HI_CLK 37
157 #define IMX_ADMA_LPCG_PWM_IPG_CLK 283 #define IMX_ADMA_LPCG_PWM_IPG_CLK 38
158 #define IMX_ADMA_LPCG_LCD_PIX_CLK 284 #define IMX_ADMA_LPCG_LCD_PIX_CLK 39
159 #define IMX_ADMA_LPCG_LCD_APB_CLK 285 #define IMX_ADMA_LPCG_LCD_APB_CLK 40
160 #define IMX_ADMA_LPCG_DSP_ADB_CLK 286 #define IMX_ADMA_LPCG_DSP_ADB_CLK 41
161 #define IMX_ADMA_LPCG_DSP_IPG_CLK 287 #define IMX_ADMA_LPCG_DSP_IPG_CLK 42
162 #define IMX_ADMA_LPCG_DSP_CORE_CLK 288 #define IMX_ADMA_LPCG_DSP_CORE_CLK 43
163 #define IMX_ADMA_LPCG_OCRAM_IPG_CLK 289 #define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44
164 290
165 #define IMX_ADMA_LPCG_CLK_END 291 #define IMX_ADMA_LPCG_CLK_END 45
166 <<
167 #define IMX_ADMA_ACM_AUD_CLK0_SEL <<
168 #define IMX_ADMA_ACM_AUD_CLK1_SEL <<
169 #define IMX_ADMA_ACM_MCLKOUT0_SEL <<
170 #define IMX_ADMA_ACM_MCLKOUT1_SEL <<
171 #define IMX_ADMA_ACM_ESAI0_MCLK_SEL <<
172 #define IMX_ADMA_ACM_ESAI1_MCLK_SEL <<
173 #define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL <<
174 #define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL <<
175 #define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL <<
176 #define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL <<
177 #define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL <<
178 #define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL <<
179 #define IMX_ADMA_ACM_SAI0_MCLK_SEL <<
180 #define IMX_ADMA_ACM_SAI1_MCLK_SEL <<
181 #define IMX_ADMA_ACM_SAI2_MCLK_SEL <<
182 #define IMX_ADMA_ACM_SAI3_MCLK_SEL <<
183 #define IMX_ADMA_ACM_SAI4_MCLK_SEL <<
184 #define IMX_ADMA_ACM_SAI5_MCLK_SEL <<
185 #define IMX_ADMA_ACM_SAI6_MCLK_SEL <<
186 #define IMX_ADMA_ACM_SAI7_MCLK_SEL <<
187 #define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL <<
188 #define IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL <<
189 #define IMX_ADMA_ACM_MQS_TX_CLK_SEL <<
190 #define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL <<
191 #define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL <<
192 <<
193 #define IMX_ADMA_ACM_CLK_END <<
194 292
195 #endif /* __DT_BINDINGS_CLOCK_IMX_H */ 293 #endif /* __DT_BINDINGS_CLOCK_IMX_H */
196 294
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