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TOMOYO Linux Cross Reference
Linux/include/dt-bindings/clock/imx8mm-clock.h

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Diff markup

Differences between /include/dt-bindings/clock/imx8mm-clock.h (Version linux-6.12-rc7) and /include/dt-bindings/clock/imx8mm-clock.h (Version linux-4.9.337)


  1 /* SPDX-License-Identifier: GPL-2.0 */              1 
  2 /*                                                
  3  * Copyright 2017-2018 NXP                        
  4  */                                               
  5                                                   
  6 #ifndef __DT_BINDINGS_CLOCK_IMX8MM_H              
  7 #define __DT_BINDINGS_CLOCK_IMX8MM_H              
  8                                                   
  9 #define IMX8MM_CLK_DUMMY                          
 10 #define IMX8MM_CLK_32K                            
 11 #define IMX8MM_CLK_24M                            
 12 #define IMX8MM_OSC_HDMI_CLK                       
 13 #define IMX8MM_CLK_EXT1                           
 14 #define IMX8MM_CLK_EXT2                           
 15 #define IMX8MM_CLK_EXT3                           
 16 #define IMX8MM_CLK_EXT4                           
 17 #define IMX8MM_AUDIO_PLL1_REF_SEL                 
 18 #define IMX8MM_AUDIO_PLL2_REF_SEL                 
 19 #define IMX8MM_VIDEO_PLL1_REF_SEL                 
 20 #define IMX8MM_DRAM_PLL_REF_SEL                   
 21 #define IMX8MM_GPU_PLL_REF_SEL                    
 22 #define IMX8MM_VPU_PLL_REF_SEL                    
 23 #define IMX8MM_ARM_PLL_REF_SEL                    
 24 #define IMX8MM_SYS_PLL1_REF_SEL                   
 25 #define IMX8MM_SYS_PLL2_REF_SEL                   
 26 #define IMX8MM_SYS_PLL3_REF_SEL                   
 27 #define IMX8MM_AUDIO_PLL1                         
 28 #define IMX8MM_AUDIO_PLL2                         
 29 #define IMX8MM_VIDEO_PLL1                         
 30 #define IMX8MM_DRAM_PLL                           
 31 #define IMX8MM_GPU_PLL                            
 32 #define IMX8MM_VPU_PLL                            
 33 #define IMX8MM_ARM_PLL                            
 34 #define IMX8MM_SYS_PLL1                           
 35 #define IMX8MM_SYS_PLL2                           
 36 #define IMX8MM_SYS_PLL3                           
 37 #define IMX8MM_AUDIO_PLL1_BYPASS                  
 38 #define IMX8MM_AUDIO_PLL2_BYPASS                  
 39 #define IMX8MM_VIDEO_PLL1_BYPASS                  
 40 #define IMX8MM_DRAM_PLL_BYPASS                    
 41 #define IMX8MM_GPU_PLL_BYPASS                     
 42 #define IMX8MM_VPU_PLL_BYPASS                     
 43 #define IMX8MM_ARM_PLL_BYPASS                     
 44 #define IMX8MM_SYS_PLL1_BYPASS                    
 45 #define IMX8MM_SYS_PLL2_BYPASS                    
 46 #define IMX8MM_SYS_PLL3_BYPASS                    
 47 #define IMX8MM_AUDIO_PLL1_OUT                     
 48 #define IMX8MM_AUDIO_PLL2_OUT                     
 49 #define IMX8MM_VIDEO_PLL1_OUT                     
 50 #define IMX8MM_DRAM_PLL_OUT                       
 51 #define IMX8MM_GPU_PLL_OUT                        
 52 #define IMX8MM_VPU_PLL_OUT                        
 53 #define IMX8MM_ARM_PLL_OUT                        
 54 #define IMX8MM_SYS_PLL1_OUT                       
 55 #define IMX8MM_SYS_PLL2_OUT                       
 56 #define IMX8MM_SYS_PLL3_OUT                       
 57 #define IMX8MM_SYS_PLL1_40M                       
 58 #define IMX8MM_SYS_PLL1_80M                       
 59 #define IMX8MM_SYS_PLL1_100M                      
 60 #define IMX8MM_SYS_PLL1_133M                      
 61 #define IMX8MM_SYS_PLL1_160M                      
 62 #define IMX8MM_SYS_PLL1_200M                      
 63 #define IMX8MM_SYS_PLL1_266M                      
 64 #define IMX8MM_SYS_PLL1_400M                      
 65 #define IMX8MM_SYS_PLL1_800M                      
 66 #define IMX8MM_SYS_PLL2_50M                       
 67 #define IMX8MM_SYS_PLL2_100M                      
 68 #define IMX8MM_SYS_PLL2_125M                      
 69 #define IMX8MM_SYS_PLL2_166M                      
 70 #define IMX8MM_SYS_PLL2_200M                      
 71 #define IMX8MM_SYS_PLL2_250M                      
 72 #define IMX8MM_SYS_PLL2_333M                      
 73 #define IMX8MM_SYS_PLL2_500M                      
 74 #define IMX8MM_SYS_PLL2_1000M                     
 75                                                   
 76 /* core */                                        
 77 #define IMX8MM_CLK_A53_SRC                        
 78 #define IMX8MM_CLK_M4_SRC                         
 79 #define IMX8MM_CLK_VPU_SRC                        
 80 #define IMX8MM_CLK_GPU3D_SRC                      
 81 #define IMX8MM_CLK_GPU2D_SRC                      
 82 #define IMX8MM_CLK_A53_CG                         
 83 #define IMX8MM_CLK_M4_CG                          
 84 #define IMX8MM_CLK_VPU_CG                         
 85 #define IMX8MM_CLK_GPU3D_CG                       
 86 #define IMX8MM_CLK_GPU2D_CG                       
 87 #define IMX8MM_CLK_A53_DIV                        
 88 #define IMX8MM_CLK_M4_DIV                         
 89 #define IMX8MM_CLK_VPU_DIV                        
 90 #define IMX8MM_CLK_GPU3D_DIV                      
 91 #define IMX8MM_CLK_GPU2D_DIV                      
 92                                                   
 93 /* bus */                                         
 94 #define IMX8MM_CLK_MAIN_AXI                       
 95 #define IMX8MM_CLK_ENET_AXI                       
 96 #define IMX8MM_CLK_NAND_USDHC_BUS                 
 97 #define IMX8MM_CLK_VPU_BUS                        
 98 #define IMX8MM_CLK_DISP_AXI                       
 99 #define IMX8MM_CLK_DISP_APB                       
100 #define IMX8MM_CLK_DISP_RTRM                      
101 #define IMX8MM_CLK_USB_BUS                        
102 #define IMX8MM_CLK_GPU_AXI                        
103 #define IMX8MM_CLK_GPU_AHB                        
104 #define IMX8MM_CLK_NOC                            
105 #define IMX8MM_CLK_NOC_APB                        
106                                                   
107 #define IMX8MM_CLK_AHB                            
108 #define IMX8MM_CLK_AUDIO_AHB                      
109 #define IMX8MM_CLK_IPG_ROOT                       
110 #define IMX8MM_CLK_IPG_AUDIO_ROOT                 
111                                                   
112 #define IMX8MM_CLK_DRAM_ALT                       
113 #define IMX8MM_CLK_DRAM_APB                       
114 #define IMX8MM_CLK_VPU_G1                         
115 #define IMX8MM_CLK_VPU_G2                         
116 #define IMX8MM_CLK_DISP_DTRC                      
117 #define IMX8MM_CLK_DISP_DC8000                    
118 #define IMX8MM_CLK_PCIE1_CTRL                     
119 #define IMX8MM_CLK_PCIE1_PHY                      
120 #define IMX8MM_CLK_PCIE1_AUX                      
121 #define IMX8MM_CLK_DC_PIXEL                       
122 #define IMX8MM_CLK_LCDIF_PIXEL                    
123 #define IMX8MM_CLK_SAI1                           
124 #define IMX8MM_CLK_SAI2                           
125 #define IMX8MM_CLK_SAI3                           
126 #define IMX8MM_CLK_SAI4                           
127 #define IMX8MM_CLK_SAI5                           
128 #define IMX8MM_CLK_SAI6                           
129 #define IMX8MM_CLK_SPDIF1                         
130 #define IMX8MM_CLK_SPDIF2                         
131 #define IMX8MM_CLK_ENET_REF                       
132 #define IMX8MM_CLK_ENET_TIMER                     
133 #define IMX8MM_CLK_ENET_PHY_REF                   
134 #define IMX8MM_CLK_NAND                           
135 #define IMX8MM_CLK_QSPI                           
136 #define IMX8MM_CLK_USDHC1                         
137 #define IMX8MM_CLK_USDHC2                         
138 #define IMX8MM_CLK_I2C1                           
139 #define IMX8MM_CLK_I2C2                           
140 #define IMX8MM_CLK_I2C3                           
141 #define IMX8MM_CLK_I2C4                           
142 #define IMX8MM_CLK_UART1                          
143 #define IMX8MM_CLK_UART2                          
144 #define IMX8MM_CLK_UART3                          
145 #define IMX8MM_CLK_UART4                          
146 #define IMX8MM_CLK_USB_CORE_REF                   
147 #define IMX8MM_CLK_USB_PHY_REF                    
148 #define IMX8MM_CLK_ECSPI1                         
149 #define IMX8MM_CLK_ECSPI2                         
150 #define IMX8MM_CLK_PWM1                           
151 #define IMX8MM_CLK_PWM2                           
152 #define IMX8MM_CLK_PWM3                           
153 #define IMX8MM_CLK_PWM4                           
154 #define IMX8MM_CLK_GPT1                           
155 #define IMX8MM_CLK_WDOG                           
156 #define IMX8MM_CLK_WRCLK                          
157 #define IMX8MM_CLK_DSI_CORE                       
158 #define IMX8MM_CLK_DSI_PHY_REF                    
159 #define IMX8MM_CLK_DSI_DBI                        
160 #define IMX8MM_CLK_USDHC3                         
161 #define IMX8MM_CLK_CSI1_CORE                      
162 #define IMX8MM_CLK_CSI1_PHY_REF                   
163 #define IMX8MM_CLK_CSI1_ESC                       
164 #define IMX8MM_CLK_CSI2_CORE                      
165 #define IMX8MM_CLK_CSI2_PHY_REF                   
166 #define IMX8MM_CLK_CSI2_ESC                       
167 #define IMX8MM_CLK_PCIE2_CTRL                     
168 #define IMX8MM_CLK_PCIE2_PHY                      
169 #define IMX8MM_CLK_PCIE2_AUX                      
170 #define IMX8MM_CLK_ECSPI3                         
171 #define IMX8MM_CLK_PDM                            
172 #define IMX8MM_CLK_VPU_H1                         
173 #define IMX8MM_CLK_CLKO1                          
174                                                   
175 #define IMX8MM_CLK_ECSPI1_ROOT                    
176 #define IMX8MM_CLK_ECSPI2_ROOT                    
177 #define IMX8MM_CLK_ECSPI3_ROOT                    
178 #define IMX8MM_CLK_ENET1_ROOT                     
179 #define IMX8MM_CLK_GPT1_ROOT                      
180 #define IMX8MM_CLK_I2C1_ROOT                      
181 #define IMX8MM_CLK_I2C2_ROOT                      
182 #define IMX8MM_CLK_I2C3_ROOT                      
183 #define IMX8MM_CLK_I2C4_ROOT                      
184 #define IMX8MM_CLK_OCOTP_ROOT                     
185 #define IMX8MM_CLK_PCIE1_ROOT                     
186 #define IMX8MM_CLK_PWM1_ROOT                      
187 #define IMX8MM_CLK_PWM2_ROOT                      
188 #define IMX8MM_CLK_PWM3_ROOT                      
189 #define IMX8MM_CLK_PWM4_ROOT                      
190 #define IMX8MM_CLK_QSPI_ROOT                      
191 #define IMX8MM_CLK_NAND_ROOT                      
192 #define IMX8MM_CLK_SAI1_ROOT                      
193 #define IMX8MM_CLK_SAI1_IPG                       
194 #define IMX8MM_CLK_SAI2_ROOT                      
195 #define IMX8MM_CLK_SAI2_IPG                       
196 #define IMX8MM_CLK_SAI3_ROOT                      
197 #define IMX8MM_CLK_SAI3_IPG                       
198 #define IMX8MM_CLK_SAI4_ROOT                      
199 #define IMX8MM_CLK_SAI4_IPG                       
200 #define IMX8MM_CLK_SAI5_ROOT                      
201 #define IMX8MM_CLK_SAI5_IPG                       
202 #define IMX8MM_CLK_SAI6_ROOT                      
203 #define IMX8MM_CLK_SAI6_IPG                       
204 #define IMX8MM_CLK_UART1_ROOT                     
205 #define IMX8MM_CLK_UART2_ROOT                     
206 #define IMX8MM_CLK_UART3_ROOT                     
207 #define IMX8MM_CLK_UART4_ROOT                     
208 #define IMX8MM_CLK_USB1_CTRL_ROOT                 
209 #define IMX8MM_CLK_GPU3D_ROOT                     
210 #define IMX8MM_CLK_USDHC1_ROOT                    
211 #define IMX8MM_CLK_USDHC2_ROOT                    
212 #define IMX8MM_CLK_WDOG1_ROOT                     
213 #define IMX8MM_CLK_WDOG2_ROOT                     
214 #define IMX8MM_CLK_WDOG3_ROOT                     
215 #define IMX8MM_CLK_VPU_G1_ROOT                    
216 #define IMX8MM_CLK_GPU_BUS_ROOT                   
217 #define IMX8MM_CLK_VPU_H1_ROOT                    
218 #define IMX8MM_CLK_VPU_G2_ROOT                    
219 #define IMX8MM_CLK_PDM_ROOT                       
220 #define IMX8MM_CLK_DISP_ROOT                      
221 #define IMX8MM_CLK_DISP_AXI_ROOT                  
222 #define IMX8MM_CLK_DISP_APB_ROOT                  
223 #define IMX8MM_CLK_DISP_RTRM_ROOT                 
224 #define IMX8MM_CLK_USDHC3_ROOT                    
225 #define IMX8MM_CLK_TMU_ROOT                       
226 #define IMX8MM_CLK_VPU_DEC_ROOT                   
227 #define IMX8MM_CLK_SDMA1_ROOT                     
228 #define IMX8MM_CLK_SDMA2_ROOT                     
229 #define IMX8MM_CLK_SDMA3_ROOT                     
230 #define IMX8MM_CLK_GPT_3M                         
231 #define IMX8MM_CLK_ARM                            
232 #define IMX8MM_CLK_PDM_IPG                        
233 #define IMX8MM_CLK_GPU2D_ROOT                     
234 #define IMX8MM_CLK_MU_ROOT                        
235 #define IMX8MM_CLK_CSI1_ROOT                      
236                                                   
237 #define IMX8MM_CLK_DRAM_CORE                      
238 #define IMX8MM_CLK_DRAM_ALT_ROOT                  
239                                                   
240 #define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK     
241                                                   
242 #define IMX8MM_CLK_GPIO1_ROOT                     
243 #define IMX8MM_CLK_GPIO2_ROOT                     
244 #define IMX8MM_CLK_GPIO3_ROOT                     
245 #define IMX8MM_CLK_GPIO4_ROOT                     
246 #define IMX8MM_CLK_GPIO5_ROOT                     
247                                                   
248 #define IMX8MM_CLK_SNVS_ROOT                      
249 #define IMX8MM_CLK_GIC                            
250                                                   
251 #define IMX8MM_SYS_PLL1_40M_CG                    
252 #define IMX8MM_SYS_PLL1_80M_CG                    
253 #define IMX8MM_SYS_PLL1_100M_CG                   
254 #define IMX8MM_SYS_PLL1_133M_CG                   
255 #define IMX8MM_SYS_PLL1_160M_CG                   
256 #define IMX8MM_SYS_PLL1_200M_CG                   
257 #define IMX8MM_SYS_PLL1_266M_CG                   
258 #define IMX8MM_SYS_PLL1_400M_CG                   
259 #define IMX8MM_SYS_PLL2_50M_CG                    
260 #define IMX8MM_SYS_PLL2_100M_CG                   
261 #define IMX8MM_SYS_PLL2_125M_CG                   
262 #define IMX8MM_SYS_PLL2_166M_CG                   
263 #define IMX8MM_SYS_PLL2_200M_CG                   
264 #define IMX8MM_SYS_PLL2_250M_CG                   
265 #define IMX8MM_SYS_PLL2_333M_CG                   
266 #define IMX8MM_SYS_PLL2_500M_CG                   
267                                                   
268 #define IMX8MM_CLK_M4_CORE                        
269 #define IMX8MM_CLK_VPU_CORE                       
270 #define IMX8MM_CLK_GPU3D_CORE                     
271 #define IMX8MM_CLK_GPU2D_CORE                     
272                                                   
273 #define IMX8MM_CLK_CLKO2                          
274                                                   
275 #define IMX8MM_CLK_A53_CORE                       
276                                                   
277 #define IMX8MM_CLK_CLKOUT1_SEL                    
278 #define IMX8MM_CLK_CLKOUT1_DIV                    
279 #define IMX8MM_CLK_CLKOUT1                        
280 #define IMX8MM_CLK_CLKOUT2_SEL                    
281 #define IMX8MM_CLK_CLKOUT2_DIV                    
282 #define IMX8MM_CLK_CLKOUT2                        
283                                                   
284 #define IMX8MM_CLK_END                            
285                                                   
286 #endif                                            
287                                                   

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