1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * Copyright 2018-2019 NXP 4 */ 5 6 #ifndef __DT_BINDINGS_CLOCK_IMX8MN_H 7 #define __DT_BINDINGS_CLOCK_IMX8MN_H 8 9 #define IMX8MN_CLK_DUMMY 10 #define IMX8MN_CLK_32K 11 #define IMX8MN_CLK_24M 12 #define IMX8MN_OSC_HDMI_CLK 13 #define IMX8MN_CLK_EXT1 14 #define IMX8MN_CLK_EXT2 15 #define IMX8MN_CLK_EXT3 16 #define IMX8MN_CLK_EXT4 17 #define IMX8MN_AUDIO_PLL1_REF_SEL 18 #define IMX8MN_AUDIO_PLL2_REF_SEL 19 #define IMX8MN_VIDEO_PLL_REF_SEL 20 #define IMX8MN_VIDEO_PLL1_REF_SEL 21 #define IMX8MN_DRAM_PLL_REF_SEL 22 #define IMX8MN_GPU_PLL_REF_SEL 23 #define IMX8MN_M7_ALT_PLL_REF_SEL 24 #define IMX8MN_VPU_PLL_REF_SEL 25 #define IMX8MN_ARM_PLL_REF_SEL 26 #define IMX8MN_SYS_PLL1_REF_SEL 27 #define IMX8MN_SYS_PLL2_REF_SEL 28 #define IMX8MN_SYS_PLL3_REF_SEL 29 #define IMX8MN_AUDIO_PLL1 30 #define IMX8MN_AUDIO_PLL2 31 #define IMX8MN_VIDEO_PLL 32 #define IMX8MN_VIDEO_PLL1 33 #define IMX8MN_DRAM_PLL 34 #define IMX8MN_GPU_PLL 35 #define IMX8MN_M7_ALT_PLL 36 #define IMX8MN_VPU_PLL 37 #define IMX8MN_ARM_PLL 38 #define IMX8MN_SYS_PLL1 39 #define IMX8MN_SYS_PLL2 40 #define IMX8MN_SYS_PLL3 41 #define IMX8MN_AUDIO_PLL1_BYPASS 42 #define IMX8MN_AUDIO_PLL2_BYPASS 43 #define IMX8MN_VIDEO_PLL_BYPASS 44 #define IMX8MN_VIDEO_PLL1_BYPASS 45 #define IMX8MN_DRAM_PLL_BYPASS 46 #define IMX8MN_GPU_PLL_BYPASS 47 #define IMX8MN_M7_ALT_PLL_BYPASS 48 #define IMX8MN_VPU_PLL_BYPASS 49 #define IMX8MN_ARM_PLL_BYPASS 50 #define IMX8MN_SYS_PLL1_BYPASS 51 #define IMX8MN_SYS_PLL2_BYPASS 52 #define IMX8MN_SYS_PLL3_BYPASS 53 #define IMX8MN_AUDIO_PLL1_OUT 54 #define IMX8MN_AUDIO_PLL2_OUT 55 #define IMX8MN_VIDEO_PLL_OUT 56 #define IMX8MN_VIDEO_PLL1_OUT 57 #define IMX8MN_DRAM_PLL_OUT 58 #define IMX8MN_GPU_PLL_OUT 59 #define IMX8MN_M7_ALT_PLL_OUT 60 #define IMX8MN_VPU_PLL_OUT 61 #define IMX8MN_ARM_PLL_OUT 62 #define IMX8MN_SYS_PLL1_OUT 63 #define IMX8MN_SYS_PLL2_OUT 64 #define IMX8MN_SYS_PLL3_OUT 65 #define IMX8MN_SYS_PLL1_40M 66 #define IMX8MN_SYS_PLL1_80M 67 #define IMX8MN_SYS_PLL1_100M 68 #define IMX8MN_SYS_PLL1_133M 69 #define IMX8MN_SYS_PLL1_160M 70 #define IMX8MN_SYS_PLL1_200M 71 #define IMX8MN_SYS_PLL1_266M 72 #define IMX8MN_SYS_PLL1_400M 73 #define IMX8MN_SYS_PLL1_800M 74 #define IMX8MN_SYS_PLL2_50M 75 #define IMX8MN_SYS_PLL2_100M 76 #define IMX8MN_SYS_PLL2_125M 77 #define IMX8MN_SYS_PLL2_166M 78 #define IMX8MN_SYS_PLL2_200M 79 #define IMX8MN_SYS_PLL2_250M 80 #define IMX8MN_SYS_PLL2_333M 81 #define IMX8MN_SYS_PLL2_500M 82 #define IMX8MN_SYS_PLL2_1000M 83 84 /* CORE CLOCK ROOT */ 85 #define IMX8MN_CLK_A53_SRC 86 #define IMX8MN_CLK_GPU_CORE_SRC 87 #define IMX8MN_CLK_GPU_SHADER_SRC 88 #define IMX8MN_CLK_A53_CG 89 #define IMX8MN_CLK_GPU_CORE_CG 90 #define IMX8MN_CLK_GPU_SHADER_CG 91 #define IMX8MN_CLK_A53_DIV 92 #define IMX8MN_CLK_GPU_CORE_DIV 93 #define IMX8MN_CLK_GPU_SHADER_DIV 94 95 /* BUS CLOCK ROOT */ 96 #define IMX8MN_CLK_MAIN_AXI 97 #define IMX8MN_CLK_ENET_AXI 98 #define IMX8MN_CLK_NAND_USDHC_BUS 99 #define IMX8MN_CLK_DISP_AXI 100 #define IMX8MN_CLK_DISP_APB 101 #define IMX8MN_CLK_USB_BUS 102 #define IMX8MN_CLK_GPU_AXI 103 #define IMX8MN_CLK_GPU_AHB 104 #define IMX8MN_CLK_NOC 105 #define IMX8MN_CLK_AHB 106 #define IMX8MN_CLK_AUDIO_AHB 107 108 /* IPG CLOCK ROOT */ 109 #define IMX8MN_CLK_IPG_ROOT 110 #define IMX8MN_CLK_IPG_AUDIO_ROOT 111 112 /* IP */ 113 #define IMX8MN_CLK_DRAM_CORE 114 #define IMX8MN_CLK_DRAM_ALT 115 #define IMX8MN_CLK_DRAM_APB 116 #define IMX8MN_CLK_DRAM_ALT_ROOT 117 #define IMX8MN_CLK_DISP_PIXEL 118 #define IMX8MN_CLK_SAI2 119 #define IMX8MN_CLK_SAI3 120 #define IMX8MN_CLK_SAI5 121 #define IMX8MN_CLK_SAI6 122 #define IMX8MN_CLK_SPDIF1 123 #define IMX8MN_CLK_ENET_REF 124 #define IMX8MN_CLK_ENET_TIMER 125 #define IMX8MN_CLK_ENET_PHY_REF 126 #define IMX8MN_CLK_NAND 127 #define IMX8MN_CLK_QSPI 128 #define IMX8MN_CLK_USDHC1 129 #define IMX8MN_CLK_USDHC2 130 #define IMX8MN_CLK_I2C1 131 #define IMX8MN_CLK_I2C2 132 #define IMX8MN_CLK_I2C3 133 #define IMX8MN_CLK_I2C4 134 #define IMX8MN_CLK_UART1 135 #define IMX8MN_CLK_UART2 136 #define IMX8MN_CLK_UART3 137 #define IMX8MN_CLK_UART4 138 #define IMX8MN_CLK_USB_CORE_REF 139 #define IMX8MN_CLK_USB_PHY_REF 140 #define IMX8MN_CLK_ECSPI1 141 #define IMX8MN_CLK_ECSPI2 142 #define IMX8MN_CLK_PWM1 143 #define IMX8MN_CLK_PWM2 144 #define IMX8MN_CLK_PWM3 145 #define IMX8MN_CLK_PWM4 146 #define IMX8MN_CLK_WDOG 147 #define IMX8MN_CLK_WRCLK 148 #define IMX8MN_CLK_CLKO1 149 #define IMX8MN_CLK_CLKO2 150 #define IMX8MN_CLK_DSI_CORE 151 #define IMX8MN_CLK_DSI_PHY_REF 152 #define IMX8MN_CLK_DSI_DBI 153 #define IMX8MN_CLK_USDHC3 154 #define IMX8MN_CLK_CAMERA_PIXEL 155 #define IMX8MN_CLK_CSI1_PHY_REF 156 #define IMX8MN_CLK_CSI2_PHY_REF 157 #define IMX8MN_CLK_CSI2_ESC 158 #define IMX8MN_CLK_ECSPI3 159 #define IMX8MN_CLK_PDM 160 #define IMX8MN_CLK_SAI7 161 162 #define IMX8MN_CLK_ECSPI1_ROOT 163 #define IMX8MN_CLK_ECSPI2_ROOT 164 #define IMX8MN_CLK_ECSPI3_ROOT 165 #define IMX8MN_CLK_ENET1_ROOT 166 #define IMX8MN_CLK_GPIO1_ROOT 167 #define IMX8MN_CLK_GPIO2_ROOT 168 #define IMX8MN_CLK_GPIO3_ROOT 169 #define IMX8MN_CLK_GPIO4_ROOT 170 #define IMX8MN_CLK_GPIO5_ROOT 171 #define IMX8MN_CLK_I2C1_ROOT 172 #define IMX8MN_CLK_I2C2_ROOT 173 #define IMX8MN_CLK_I2C3_ROOT 174 #define IMX8MN_CLK_I2C4_ROOT 175 #define IMX8MN_CLK_MU_ROOT 176 #define IMX8MN_CLK_OCOTP_ROOT 177 #define IMX8MN_CLK_PWM1_ROOT 178 #define IMX8MN_CLK_PWM2_ROOT 179 #define IMX8MN_CLK_PWM3_ROOT 180 #define IMX8MN_CLK_PWM4_ROOT 181 #define IMX8MN_CLK_QSPI_ROOT 182 #define IMX8MN_CLK_NAND_ROOT 183 #define IMX8MN_CLK_SAI2_ROOT 184 #define IMX8MN_CLK_SAI2_IPG 185 #define IMX8MN_CLK_SAI3_ROOT 186 #define IMX8MN_CLK_SAI3_IPG 187 #define IMX8MN_CLK_SAI5_ROOT 188 #define IMX8MN_CLK_SAI5_IPG 189 #define IMX8MN_CLK_SAI6_ROOT 190 #define IMX8MN_CLK_SAI6_IPG 191 #define IMX8MN_CLK_SAI7_ROOT 192 #define IMX8MN_CLK_SAI7_IPG 193 #define IMX8MN_CLK_SDMA1_ROOT 194 #define IMX8MN_CLK_SDMA2_ROOT 195 #define IMX8MN_CLK_UART1_ROOT 196 #define IMX8MN_CLK_UART2_ROOT 197 #define IMX8MN_CLK_UART3_ROOT 198 #define IMX8MN_CLK_UART4_ROOT 199 #define IMX8MN_CLK_USB1_CTRL_ROOT 200 #define IMX8MN_CLK_USDHC1_ROOT 201 #define IMX8MN_CLK_USDHC2_ROOT 202 #define IMX8MN_CLK_WDOG1_ROOT 203 #define IMX8MN_CLK_WDOG2_ROOT 204 #define IMX8MN_CLK_WDOG3_ROOT 205 #define IMX8MN_CLK_GPU_BUS_ROOT 206 #define IMX8MN_CLK_ASRC_ROOT 207 #define IMX8MN_CLK_GPU3D_ROOT 208 #define IMX8MN_CLK_PDM_ROOT 209 #define IMX8MN_CLK_PDM_IPG 210 #define IMX8MN_CLK_DISP_AXI_ROOT 211 #define IMX8MN_CLK_DISP_APB_ROOT 212 #define IMX8MN_CLK_DISP_PIXEL_ROOT 213 #define IMX8MN_CLK_CAMERA_PIXEL_ROOT 214 #define IMX8MN_CLK_USDHC3_ROOT 215 #define IMX8MN_CLK_SDMA3_ROOT 216 #define IMX8MN_CLK_TMU_ROOT 217 #define IMX8MN_CLK_ARM 218 #define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 219 #define IMX8MN_CLK_GPU_CORE_ROOT 220 #define IMX8MN_CLK_GIC 221 222 #define IMX8MN_SYS_PLL1_40M_CG 223 #define IMX8MN_SYS_PLL1_80M_CG 224 #define IMX8MN_SYS_PLL1_100M_CG 225 #define IMX8MN_SYS_PLL1_133M_CG 226 #define IMX8MN_SYS_PLL1_160M_CG 227 #define IMX8MN_SYS_PLL1_200M_CG 228 #define IMX8MN_SYS_PLL1_266M_CG 229 #define IMX8MN_SYS_PLL1_400M_CG 230 #define IMX8MN_SYS_PLL2_50M_CG 231 #define IMX8MN_SYS_PLL2_100M_CG 232 #define IMX8MN_SYS_PLL2_125M_CG 233 #define IMX8MN_SYS_PLL2_166M_CG 234 #define IMX8MN_SYS_PLL2_200M_CG 235 #define IMX8MN_SYS_PLL2_250M_CG 236 #define IMX8MN_SYS_PLL2_333M_CG 237 #define IMX8MN_SYS_PLL2_500M_CG 238 239 #define IMX8MN_CLK_SNVS_ROOT 240 #define IMX8MN_CLK_GPU_CORE 241 #define IMX8MN_CLK_GPU_SHADER 242 243 #define IMX8MN_CLK_A53_CORE 244 245 #define IMX8MN_CLK_CLKOUT1_SEL 246 #define IMX8MN_CLK_CLKOUT1_DIV 247 #define IMX8MN_CLK_CLKOUT1 248 #define IMX8MN_CLK_CLKOUT2_SEL 249 #define IMX8MN_CLK_CLKOUT2_DIV 250 #define IMX8MN_CLK_CLKOUT2 251 252 #define IMX8MN_CLK_M7_CORE 253 254 #define IMX8MN_CLK_GPT_3M 255 #define IMX8MN_CLK_GPT1 256 #define IMX8MN_CLK_GPT1_ROOT 257 #define IMX8MN_CLK_GPT2 258 #define IMX8MN_CLK_GPT2_ROOT 259 #define IMX8MN_CLK_GPT3 260 #define IMX8MN_CLK_GPT3_ROOT 261 #define IMX8MN_CLK_GPT4 262 #define IMX8MN_CLK_GPT4_ROOT 263 #define IMX8MN_CLK_GPT5 264 #define IMX8MN_CLK_GPT5_ROOT 265 #define IMX8MN_CLK_GPT6 266 #define IMX8MN_CLK_GPT6_ROOT 267 268 #define IMX8MN_CLK_END 269 270 #endif 271
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