1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 2 /* 3 * Copyright 2018-2019 NXP 3 * Copyright 2018-2019 NXP 4 */ 4 */ 5 5 6 #ifndef __DT_BINDINGS_CLOCK_IMX8MN_H 6 #ifndef __DT_BINDINGS_CLOCK_IMX8MN_H 7 #define __DT_BINDINGS_CLOCK_IMX8MN_H 7 #define __DT_BINDINGS_CLOCK_IMX8MN_H 8 8 9 #define IMX8MN_CLK_DUMMY 9 #define IMX8MN_CLK_DUMMY 0 10 #define IMX8MN_CLK_32K 10 #define IMX8MN_CLK_32K 1 11 #define IMX8MN_CLK_24M 11 #define IMX8MN_CLK_24M 2 12 #define IMX8MN_OSC_HDMI_CLK 12 #define IMX8MN_OSC_HDMI_CLK 3 13 #define IMX8MN_CLK_EXT1 13 #define IMX8MN_CLK_EXT1 4 14 #define IMX8MN_CLK_EXT2 14 #define IMX8MN_CLK_EXT2 5 15 #define IMX8MN_CLK_EXT3 15 #define IMX8MN_CLK_EXT3 6 16 #define IMX8MN_CLK_EXT4 16 #define IMX8MN_CLK_EXT4 7 17 #define IMX8MN_AUDIO_PLL1_REF_SEL 17 #define IMX8MN_AUDIO_PLL1_REF_SEL 8 18 #define IMX8MN_AUDIO_PLL2_REF_SEL 18 #define IMX8MN_AUDIO_PLL2_REF_SEL 9 19 #define IMX8MN_VIDEO_PLL_REF_SEL !! 19 #define IMX8MN_VIDEO_PLL1_REF_SEL 10 20 #define IMX8MN_VIDEO_PLL1_REF_SEL << 21 #define IMX8MN_DRAM_PLL_REF_SEL 20 #define IMX8MN_DRAM_PLL_REF_SEL 11 22 #define IMX8MN_GPU_PLL_REF_SEL 21 #define IMX8MN_GPU_PLL_REF_SEL 12 23 #define IMX8MN_M7_ALT_PLL_REF_SEL !! 22 #define IMX8MN_VPU_PLL_REF_SEL 13 24 #define IMX8MN_VPU_PLL_REF_SEL << 25 #define IMX8MN_ARM_PLL_REF_SEL 23 #define IMX8MN_ARM_PLL_REF_SEL 14 26 #define IMX8MN_SYS_PLL1_REF_SEL 24 #define IMX8MN_SYS_PLL1_REF_SEL 15 27 #define IMX8MN_SYS_PLL2_REF_SEL 25 #define IMX8MN_SYS_PLL2_REF_SEL 16 28 #define IMX8MN_SYS_PLL3_REF_SEL 26 #define IMX8MN_SYS_PLL3_REF_SEL 17 29 #define IMX8MN_AUDIO_PLL1 27 #define IMX8MN_AUDIO_PLL1 18 30 #define IMX8MN_AUDIO_PLL2 28 #define IMX8MN_AUDIO_PLL2 19 31 #define IMX8MN_VIDEO_PLL !! 29 #define IMX8MN_VIDEO_PLL1 20 32 #define IMX8MN_VIDEO_PLL1 << 33 #define IMX8MN_DRAM_PLL 30 #define IMX8MN_DRAM_PLL 21 34 #define IMX8MN_GPU_PLL 31 #define IMX8MN_GPU_PLL 22 35 #define IMX8MN_M7_ALT_PLL !! 32 #define IMX8MN_VPU_PLL 23 36 #define IMX8MN_VPU_PLL << 37 #define IMX8MN_ARM_PLL 33 #define IMX8MN_ARM_PLL 24 38 #define IMX8MN_SYS_PLL1 34 #define IMX8MN_SYS_PLL1 25 39 #define IMX8MN_SYS_PLL2 35 #define IMX8MN_SYS_PLL2 26 40 #define IMX8MN_SYS_PLL3 36 #define IMX8MN_SYS_PLL3 27 41 #define IMX8MN_AUDIO_PLL1_BYPASS 37 #define IMX8MN_AUDIO_PLL1_BYPASS 28 42 #define IMX8MN_AUDIO_PLL2_BYPASS 38 #define IMX8MN_AUDIO_PLL2_BYPASS 29 43 #define IMX8MN_VIDEO_PLL_BYPASS !! 39 #define IMX8MN_VIDEO_PLL1_BYPASS 30 44 #define IMX8MN_VIDEO_PLL1_BYPASS << 45 #define IMX8MN_DRAM_PLL_BYPASS 40 #define IMX8MN_DRAM_PLL_BYPASS 31 46 #define IMX8MN_GPU_PLL_BYPASS 41 #define IMX8MN_GPU_PLL_BYPASS 32 47 #define IMX8MN_M7_ALT_PLL_BYPASS !! 42 #define IMX8MN_VPU_PLL_BYPASS 33 48 #define IMX8MN_VPU_PLL_BYPASS << 49 #define IMX8MN_ARM_PLL_BYPASS 43 #define IMX8MN_ARM_PLL_BYPASS 34 50 #define IMX8MN_SYS_PLL1_BYPASS 44 #define IMX8MN_SYS_PLL1_BYPASS 35 51 #define IMX8MN_SYS_PLL2_BYPASS 45 #define IMX8MN_SYS_PLL2_BYPASS 36 52 #define IMX8MN_SYS_PLL3_BYPASS 46 #define IMX8MN_SYS_PLL3_BYPASS 37 53 #define IMX8MN_AUDIO_PLL1_OUT 47 #define IMX8MN_AUDIO_PLL1_OUT 38 54 #define IMX8MN_AUDIO_PLL2_OUT 48 #define IMX8MN_AUDIO_PLL2_OUT 39 55 #define IMX8MN_VIDEO_PLL_OUT !! 49 #define IMX8MN_VIDEO_PLL1_OUT 40 56 #define IMX8MN_VIDEO_PLL1_OUT << 57 #define IMX8MN_DRAM_PLL_OUT 50 #define IMX8MN_DRAM_PLL_OUT 41 58 #define IMX8MN_GPU_PLL_OUT 51 #define IMX8MN_GPU_PLL_OUT 42 59 #define IMX8MN_M7_ALT_PLL_OUT !! 52 #define IMX8MN_VPU_PLL_OUT 43 60 #define IMX8MN_VPU_PLL_OUT << 61 #define IMX8MN_ARM_PLL_OUT 53 #define IMX8MN_ARM_PLL_OUT 44 62 #define IMX8MN_SYS_PLL1_OUT 54 #define IMX8MN_SYS_PLL1_OUT 45 63 #define IMX8MN_SYS_PLL2_OUT 55 #define IMX8MN_SYS_PLL2_OUT 46 64 #define IMX8MN_SYS_PLL3_OUT 56 #define IMX8MN_SYS_PLL3_OUT 47 65 #define IMX8MN_SYS_PLL1_40M 57 #define IMX8MN_SYS_PLL1_40M 48 66 #define IMX8MN_SYS_PLL1_80M 58 #define IMX8MN_SYS_PLL1_80M 49 67 #define IMX8MN_SYS_PLL1_100M 59 #define IMX8MN_SYS_PLL1_100M 50 68 #define IMX8MN_SYS_PLL1_133M 60 #define IMX8MN_SYS_PLL1_133M 51 69 #define IMX8MN_SYS_PLL1_160M 61 #define IMX8MN_SYS_PLL1_160M 52 70 #define IMX8MN_SYS_PLL1_200M 62 #define IMX8MN_SYS_PLL1_200M 53 71 #define IMX8MN_SYS_PLL1_266M 63 #define IMX8MN_SYS_PLL1_266M 54 72 #define IMX8MN_SYS_PLL1_400M 64 #define IMX8MN_SYS_PLL1_400M 55 73 #define IMX8MN_SYS_PLL1_800M 65 #define IMX8MN_SYS_PLL1_800M 56 74 #define IMX8MN_SYS_PLL2_50M 66 #define IMX8MN_SYS_PLL2_50M 57 75 #define IMX8MN_SYS_PLL2_100M 67 #define IMX8MN_SYS_PLL2_100M 58 76 #define IMX8MN_SYS_PLL2_125M 68 #define IMX8MN_SYS_PLL2_125M 59 77 #define IMX8MN_SYS_PLL2_166M 69 #define IMX8MN_SYS_PLL2_166M 60 78 #define IMX8MN_SYS_PLL2_200M 70 #define IMX8MN_SYS_PLL2_200M 61 79 #define IMX8MN_SYS_PLL2_250M 71 #define IMX8MN_SYS_PLL2_250M 62 80 #define IMX8MN_SYS_PLL2_333M 72 #define IMX8MN_SYS_PLL2_333M 63 81 #define IMX8MN_SYS_PLL2_500M 73 #define IMX8MN_SYS_PLL2_500M 64 82 #define IMX8MN_SYS_PLL2_1000M 74 #define IMX8MN_SYS_PLL2_1000M 65 83 75 84 /* CORE CLOCK ROOT */ 76 /* CORE CLOCK ROOT */ 85 #define IMX8MN_CLK_A53_SRC 77 #define IMX8MN_CLK_A53_SRC 66 86 #define IMX8MN_CLK_GPU_CORE_SRC 78 #define IMX8MN_CLK_GPU_CORE_SRC 67 87 #define IMX8MN_CLK_GPU_SHADER_SRC 79 #define IMX8MN_CLK_GPU_SHADER_SRC 68 88 #define IMX8MN_CLK_A53_CG 80 #define IMX8MN_CLK_A53_CG 69 89 #define IMX8MN_CLK_GPU_CORE_CG 81 #define IMX8MN_CLK_GPU_CORE_CG 70 90 #define IMX8MN_CLK_GPU_SHADER_CG 82 #define IMX8MN_CLK_GPU_SHADER_CG 71 91 #define IMX8MN_CLK_A53_DIV 83 #define IMX8MN_CLK_A53_DIV 72 92 #define IMX8MN_CLK_GPU_CORE_DIV 84 #define IMX8MN_CLK_GPU_CORE_DIV 73 93 #define IMX8MN_CLK_GPU_SHADER_DIV 85 #define IMX8MN_CLK_GPU_SHADER_DIV 74 94 86 95 /* BUS CLOCK ROOT */ 87 /* BUS CLOCK ROOT */ 96 #define IMX8MN_CLK_MAIN_AXI 88 #define IMX8MN_CLK_MAIN_AXI 75 97 #define IMX8MN_CLK_ENET_AXI 89 #define IMX8MN_CLK_ENET_AXI 76 98 #define IMX8MN_CLK_NAND_USDHC_BUS 90 #define IMX8MN_CLK_NAND_USDHC_BUS 77 99 #define IMX8MN_CLK_DISP_AXI 91 #define IMX8MN_CLK_DISP_AXI 78 100 #define IMX8MN_CLK_DISP_APB 92 #define IMX8MN_CLK_DISP_APB 79 101 #define IMX8MN_CLK_USB_BUS 93 #define IMX8MN_CLK_USB_BUS 80 102 #define IMX8MN_CLK_GPU_AXI 94 #define IMX8MN_CLK_GPU_AXI 81 103 #define IMX8MN_CLK_GPU_AHB 95 #define IMX8MN_CLK_GPU_AHB 82 104 #define IMX8MN_CLK_NOC 96 #define IMX8MN_CLK_NOC 83 105 #define IMX8MN_CLK_AHB 97 #define IMX8MN_CLK_AHB 84 106 #define IMX8MN_CLK_AUDIO_AHB 98 #define IMX8MN_CLK_AUDIO_AHB 85 107 99 108 /* IPG CLOCK ROOT */ 100 /* IPG CLOCK ROOT */ 109 #define IMX8MN_CLK_IPG_ROOT 101 #define IMX8MN_CLK_IPG_ROOT 86 110 #define IMX8MN_CLK_IPG_AUDIO_ROOT 102 #define IMX8MN_CLK_IPG_AUDIO_ROOT 87 111 103 112 /* IP */ 104 /* IP */ 113 #define IMX8MN_CLK_DRAM_CORE 105 #define IMX8MN_CLK_DRAM_CORE 88 114 #define IMX8MN_CLK_DRAM_ALT 106 #define IMX8MN_CLK_DRAM_ALT 89 115 #define IMX8MN_CLK_DRAM_APB 107 #define IMX8MN_CLK_DRAM_APB 90 116 #define IMX8MN_CLK_DRAM_ALT_ROOT 108 #define IMX8MN_CLK_DRAM_ALT_ROOT 91 117 #define IMX8MN_CLK_DISP_PIXEL 109 #define IMX8MN_CLK_DISP_PIXEL 92 118 #define IMX8MN_CLK_SAI2 110 #define IMX8MN_CLK_SAI2 93 119 #define IMX8MN_CLK_SAI3 111 #define IMX8MN_CLK_SAI3 94 120 #define IMX8MN_CLK_SAI5 112 #define IMX8MN_CLK_SAI5 95 121 #define IMX8MN_CLK_SAI6 113 #define IMX8MN_CLK_SAI6 96 122 #define IMX8MN_CLK_SPDIF1 114 #define IMX8MN_CLK_SPDIF1 97 123 #define IMX8MN_CLK_ENET_REF 115 #define IMX8MN_CLK_ENET_REF 98 124 #define IMX8MN_CLK_ENET_TIMER 116 #define IMX8MN_CLK_ENET_TIMER 99 125 #define IMX8MN_CLK_ENET_PHY_REF 117 #define IMX8MN_CLK_ENET_PHY_REF 100 126 #define IMX8MN_CLK_NAND 118 #define IMX8MN_CLK_NAND 101 127 #define IMX8MN_CLK_QSPI 119 #define IMX8MN_CLK_QSPI 102 128 #define IMX8MN_CLK_USDHC1 120 #define IMX8MN_CLK_USDHC1 103 129 #define IMX8MN_CLK_USDHC2 121 #define IMX8MN_CLK_USDHC2 104 130 #define IMX8MN_CLK_I2C1 122 #define IMX8MN_CLK_I2C1 105 131 #define IMX8MN_CLK_I2C2 123 #define IMX8MN_CLK_I2C2 106 132 #define IMX8MN_CLK_I2C3 124 #define IMX8MN_CLK_I2C3 107 133 #define IMX8MN_CLK_I2C4 125 #define IMX8MN_CLK_I2C4 108 134 #define IMX8MN_CLK_UART1 126 #define IMX8MN_CLK_UART1 109 135 #define IMX8MN_CLK_UART2 127 #define IMX8MN_CLK_UART2 110 136 #define IMX8MN_CLK_UART3 128 #define IMX8MN_CLK_UART3 111 137 #define IMX8MN_CLK_UART4 129 #define IMX8MN_CLK_UART4 112 138 #define IMX8MN_CLK_USB_CORE_REF 130 #define IMX8MN_CLK_USB_CORE_REF 113 139 #define IMX8MN_CLK_USB_PHY_REF 131 #define IMX8MN_CLK_USB_PHY_REF 114 140 #define IMX8MN_CLK_ECSPI1 132 #define IMX8MN_CLK_ECSPI1 115 141 #define IMX8MN_CLK_ECSPI2 133 #define IMX8MN_CLK_ECSPI2 116 142 #define IMX8MN_CLK_PWM1 134 #define IMX8MN_CLK_PWM1 117 143 #define IMX8MN_CLK_PWM2 135 #define IMX8MN_CLK_PWM2 118 144 #define IMX8MN_CLK_PWM3 136 #define IMX8MN_CLK_PWM3 119 145 #define IMX8MN_CLK_PWM4 137 #define IMX8MN_CLK_PWM4 120 146 #define IMX8MN_CLK_WDOG 138 #define IMX8MN_CLK_WDOG 121 147 #define IMX8MN_CLK_WRCLK 139 #define IMX8MN_CLK_WRCLK 122 148 #define IMX8MN_CLK_CLKO1 140 #define IMX8MN_CLK_CLKO1 123 149 #define IMX8MN_CLK_CLKO2 141 #define IMX8MN_CLK_CLKO2 124 150 #define IMX8MN_CLK_DSI_CORE 142 #define IMX8MN_CLK_DSI_CORE 125 151 #define IMX8MN_CLK_DSI_PHY_REF 143 #define IMX8MN_CLK_DSI_PHY_REF 126 152 #define IMX8MN_CLK_DSI_DBI 144 #define IMX8MN_CLK_DSI_DBI 127 153 #define IMX8MN_CLK_USDHC3 145 #define IMX8MN_CLK_USDHC3 128 154 #define IMX8MN_CLK_CAMERA_PIXEL 146 #define IMX8MN_CLK_CAMERA_PIXEL 129 155 #define IMX8MN_CLK_CSI1_PHY_REF 147 #define IMX8MN_CLK_CSI1_PHY_REF 130 156 #define IMX8MN_CLK_CSI2_PHY_REF 148 #define IMX8MN_CLK_CSI2_PHY_REF 131 157 #define IMX8MN_CLK_CSI2_ESC 149 #define IMX8MN_CLK_CSI2_ESC 132 158 #define IMX8MN_CLK_ECSPI3 150 #define IMX8MN_CLK_ECSPI3 133 159 #define IMX8MN_CLK_PDM 151 #define IMX8MN_CLK_PDM 134 160 #define IMX8MN_CLK_SAI7 152 #define IMX8MN_CLK_SAI7 135 161 153 162 #define IMX8MN_CLK_ECSPI1_ROOT 154 #define IMX8MN_CLK_ECSPI1_ROOT 136 163 #define IMX8MN_CLK_ECSPI2_ROOT 155 #define IMX8MN_CLK_ECSPI2_ROOT 137 164 #define IMX8MN_CLK_ECSPI3_ROOT 156 #define IMX8MN_CLK_ECSPI3_ROOT 138 165 #define IMX8MN_CLK_ENET1_ROOT 157 #define IMX8MN_CLK_ENET1_ROOT 139 166 #define IMX8MN_CLK_GPIO1_ROOT 158 #define IMX8MN_CLK_GPIO1_ROOT 140 167 #define IMX8MN_CLK_GPIO2_ROOT 159 #define IMX8MN_CLK_GPIO2_ROOT 141 168 #define IMX8MN_CLK_GPIO3_ROOT 160 #define IMX8MN_CLK_GPIO3_ROOT 142 169 #define IMX8MN_CLK_GPIO4_ROOT 161 #define IMX8MN_CLK_GPIO4_ROOT 143 170 #define IMX8MN_CLK_GPIO5_ROOT 162 #define IMX8MN_CLK_GPIO5_ROOT 144 171 #define IMX8MN_CLK_I2C1_ROOT 163 #define IMX8MN_CLK_I2C1_ROOT 145 172 #define IMX8MN_CLK_I2C2_ROOT 164 #define IMX8MN_CLK_I2C2_ROOT 146 173 #define IMX8MN_CLK_I2C3_ROOT 165 #define IMX8MN_CLK_I2C3_ROOT 147 174 #define IMX8MN_CLK_I2C4_ROOT 166 #define IMX8MN_CLK_I2C4_ROOT 148 175 #define IMX8MN_CLK_MU_ROOT 167 #define IMX8MN_CLK_MU_ROOT 149 176 #define IMX8MN_CLK_OCOTP_ROOT 168 #define IMX8MN_CLK_OCOTP_ROOT 150 177 #define IMX8MN_CLK_PWM1_ROOT 169 #define IMX8MN_CLK_PWM1_ROOT 151 178 #define IMX8MN_CLK_PWM2_ROOT 170 #define IMX8MN_CLK_PWM2_ROOT 152 179 #define IMX8MN_CLK_PWM3_ROOT 171 #define IMX8MN_CLK_PWM3_ROOT 153 180 #define IMX8MN_CLK_PWM4_ROOT 172 #define IMX8MN_CLK_PWM4_ROOT 154 181 #define IMX8MN_CLK_QSPI_ROOT 173 #define IMX8MN_CLK_QSPI_ROOT 155 182 #define IMX8MN_CLK_NAND_ROOT 174 #define IMX8MN_CLK_NAND_ROOT 156 183 #define IMX8MN_CLK_SAI2_ROOT 175 #define IMX8MN_CLK_SAI2_ROOT 157 184 #define IMX8MN_CLK_SAI2_IPG 176 #define IMX8MN_CLK_SAI2_IPG 158 185 #define IMX8MN_CLK_SAI3_ROOT 177 #define IMX8MN_CLK_SAI3_ROOT 159 186 #define IMX8MN_CLK_SAI3_IPG 178 #define IMX8MN_CLK_SAI3_IPG 160 187 #define IMX8MN_CLK_SAI5_ROOT 179 #define IMX8MN_CLK_SAI5_ROOT 161 188 #define IMX8MN_CLK_SAI5_IPG 180 #define IMX8MN_CLK_SAI5_IPG 162 189 #define IMX8MN_CLK_SAI6_ROOT 181 #define IMX8MN_CLK_SAI6_ROOT 163 190 #define IMX8MN_CLK_SAI6_IPG 182 #define IMX8MN_CLK_SAI6_IPG 164 191 #define IMX8MN_CLK_SAI7_ROOT 183 #define IMX8MN_CLK_SAI7_ROOT 165 192 #define IMX8MN_CLK_SAI7_IPG 184 #define IMX8MN_CLK_SAI7_IPG 166 193 #define IMX8MN_CLK_SDMA1_ROOT 185 #define IMX8MN_CLK_SDMA1_ROOT 167 194 #define IMX8MN_CLK_SDMA2_ROOT 186 #define IMX8MN_CLK_SDMA2_ROOT 168 195 #define IMX8MN_CLK_UART1_ROOT 187 #define IMX8MN_CLK_UART1_ROOT 169 196 #define IMX8MN_CLK_UART2_ROOT 188 #define IMX8MN_CLK_UART2_ROOT 170 197 #define IMX8MN_CLK_UART3_ROOT 189 #define IMX8MN_CLK_UART3_ROOT 171 198 #define IMX8MN_CLK_UART4_ROOT 190 #define IMX8MN_CLK_UART4_ROOT 172 199 #define IMX8MN_CLK_USB1_CTRL_ROOT 191 #define IMX8MN_CLK_USB1_CTRL_ROOT 173 200 #define IMX8MN_CLK_USDHC1_ROOT 192 #define IMX8MN_CLK_USDHC1_ROOT 174 201 #define IMX8MN_CLK_USDHC2_ROOT 193 #define IMX8MN_CLK_USDHC2_ROOT 175 202 #define IMX8MN_CLK_WDOG1_ROOT 194 #define IMX8MN_CLK_WDOG1_ROOT 176 203 #define IMX8MN_CLK_WDOG2_ROOT 195 #define IMX8MN_CLK_WDOG2_ROOT 177 204 #define IMX8MN_CLK_WDOG3_ROOT 196 #define IMX8MN_CLK_WDOG3_ROOT 178 205 #define IMX8MN_CLK_GPU_BUS_ROOT 197 #define IMX8MN_CLK_GPU_BUS_ROOT 179 206 #define IMX8MN_CLK_ASRC_ROOT 198 #define IMX8MN_CLK_ASRC_ROOT 180 207 #define IMX8MN_CLK_GPU3D_ROOT 199 #define IMX8MN_CLK_GPU3D_ROOT 181 208 #define IMX8MN_CLK_PDM_ROOT 200 #define IMX8MN_CLK_PDM_ROOT 182 209 #define IMX8MN_CLK_PDM_IPG 201 #define IMX8MN_CLK_PDM_IPG 183 210 #define IMX8MN_CLK_DISP_AXI_ROOT 202 #define IMX8MN_CLK_DISP_AXI_ROOT 184 211 #define IMX8MN_CLK_DISP_APB_ROOT 203 #define IMX8MN_CLK_DISP_APB_ROOT 185 212 #define IMX8MN_CLK_DISP_PIXEL_ROOT 204 #define IMX8MN_CLK_DISP_PIXEL_ROOT 186 213 #define IMX8MN_CLK_CAMERA_PIXEL_ROOT 205 #define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187 214 #define IMX8MN_CLK_USDHC3_ROOT 206 #define IMX8MN_CLK_USDHC3_ROOT 188 215 #define IMX8MN_CLK_SDMA3_ROOT 207 #define IMX8MN_CLK_SDMA3_ROOT 189 216 #define IMX8MN_CLK_TMU_ROOT 208 #define IMX8MN_CLK_TMU_ROOT 190 217 #define IMX8MN_CLK_ARM 209 #define IMX8MN_CLK_ARM 191 218 #define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 210 #define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192 219 #define IMX8MN_CLK_GPU_CORE_ROOT 211 #define IMX8MN_CLK_GPU_CORE_ROOT 193 220 #define IMX8MN_CLK_GIC 212 #define IMX8MN_CLK_GIC 194 221 213 222 #define IMX8MN_SYS_PLL1_40M_CG 214 #define IMX8MN_SYS_PLL1_40M_CG 195 223 #define IMX8MN_SYS_PLL1_80M_CG 215 #define IMX8MN_SYS_PLL1_80M_CG 196 224 #define IMX8MN_SYS_PLL1_100M_CG 216 #define IMX8MN_SYS_PLL1_100M_CG 197 225 #define IMX8MN_SYS_PLL1_133M_CG 217 #define IMX8MN_SYS_PLL1_133M_CG 198 226 #define IMX8MN_SYS_PLL1_160M_CG 218 #define IMX8MN_SYS_PLL1_160M_CG 199 227 #define IMX8MN_SYS_PLL1_200M_CG 219 #define IMX8MN_SYS_PLL1_200M_CG 200 228 #define IMX8MN_SYS_PLL1_266M_CG 220 #define IMX8MN_SYS_PLL1_266M_CG 201 229 #define IMX8MN_SYS_PLL1_400M_CG 221 #define IMX8MN_SYS_PLL1_400M_CG 202 230 #define IMX8MN_SYS_PLL2_50M_CG 222 #define IMX8MN_SYS_PLL2_50M_CG 203 231 #define IMX8MN_SYS_PLL2_100M_CG 223 #define IMX8MN_SYS_PLL2_100M_CG 204 232 #define IMX8MN_SYS_PLL2_125M_CG 224 #define IMX8MN_SYS_PLL2_125M_CG 205 233 #define IMX8MN_SYS_PLL2_166M_CG 225 #define IMX8MN_SYS_PLL2_166M_CG 206 234 #define IMX8MN_SYS_PLL2_200M_CG 226 #define IMX8MN_SYS_PLL2_200M_CG 207 235 #define IMX8MN_SYS_PLL2_250M_CG 227 #define IMX8MN_SYS_PLL2_250M_CG 208 236 #define IMX8MN_SYS_PLL2_333M_CG 228 #define IMX8MN_SYS_PLL2_333M_CG 209 237 #define IMX8MN_SYS_PLL2_500M_CG 229 #define IMX8MN_SYS_PLL2_500M_CG 210 238 230 239 #define IMX8MN_CLK_SNVS_ROOT 231 #define IMX8MN_CLK_SNVS_ROOT 211 240 #define IMX8MN_CLK_GPU_CORE 232 #define IMX8MN_CLK_GPU_CORE 212 241 #define IMX8MN_CLK_GPU_SHADER 233 #define IMX8MN_CLK_GPU_SHADER 213 242 234 243 #define IMX8MN_CLK_A53_CORE 235 #define IMX8MN_CLK_A53_CORE 214 244 236 245 #define IMX8MN_CLK_CLKOUT1_SEL !! 237 #define IMX8MN_CLK_END 215 246 #define IMX8MN_CLK_CLKOUT1_DIV << 247 #define IMX8MN_CLK_CLKOUT1 << 248 #define IMX8MN_CLK_CLKOUT2_SEL << 249 #define IMX8MN_CLK_CLKOUT2_DIV << 250 #define IMX8MN_CLK_CLKOUT2 << 251 << 252 #define IMX8MN_CLK_M7_CORE << 253 << 254 #define IMX8MN_CLK_GPT_3M << 255 #define IMX8MN_CLK_GPT1 << 256 #define IMX8MN_CLK_GPT1_ROOT << 257 #define IMX8MN_CLK_GPT2 << 258 #define IMX8MN_CLK_GPT2_ROOT << 259 #define IMX8MN_CLK_GPT3 << 260 #define IMX8MN_CLK_GPT3_ROOT << 261 #define IMX8MN_CLK_GPT4 << 262 #define IMX8MN_CLK_GPT4_ROOT << 263 #define IMX8MN_CLK_GPT5 << 264 #define IMX8MN_CLK_GPT5_ROOT << 265 #define IMX8MN_CLK_GPT6 << 266 #define IMX8MN_CLK_GPT6_ROOT << 267 << 268 #define IMX8MN_CLK_END << 269 238 270 #endif 239 #endif 271 240
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