1 /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ 1 /* SPDX-License-Identifier: GPL-2.0+ OR MIT */
2 /* 2 /*
3 * Copyright 2022 NXP 3 * Copyright 2022 NXP
4 */ 4 */
5 5
6 #ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H 6 #ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H
7 #define __DT_BINDINGS_CLOCK_IMX93_CLK_H 7 #define __DT_BINDINGS_CLOCK_IMX93_CLK_H
8 8
9 #define IMX93_CLK_DUMMY 0 9 #define IMX93_CLK_DUMMY 0
10 #define IMX93_CLK_24M 1 10 #define IMX93_CLK_24M 1
11 #define IMX93_CLK_EXT1 2 11 #define IMX93_CLK_EXT1 2
12 #define IMX93_CLK_SYS_PLL_PFD0 3 12 #define IMX93_CLK_SYS_PLL_PFD0 3
13 #define IMX93_CLK_SYS_PLL_PFD0_DIV2 4 13 #define IMX93_CLK_SYS_PLL_PFD0_DIV2 4
14 #define IMX93_CLK_SYS_PLL_PFD1 5 14 #define IMX93_CLK_SYS_PLL_PFD1 5
15 #define IMX93_CLK_SYS_PLL_PFD1_DIV2 6 15 #define IMX93_CLK_SYS_PLL_PFD1_DIV2 6
16 #define IMX93_CLK_SYS_PLL_PFD2 7 16 #define IMX93_CLK_SYS_PLL_PFD2 7
17 #define IMX93_CLK_SYS_PLL_PFD2_DIV2 8 17 #define IMX93_CLK_SYS_PLL_PFD2_DIV2 8
18 #define IMX93_CLK_AUDIO_PLL 9 18 #define IMX93_CLK_AUDIO_PLL 9
19 #define IMX93_CLK_VIDEO_PLL 10 19 #define IMX93_CLK_VIDEO_PLL 10
20 #define IMX93_CLK_A55_PERIPH 11 20 #define IMX93_CLK_A55_PERIPH 11
21 #define IMX93_CLK_A55_MTR_BUS 12 21 #define IMX93_CLK_A55_MTR_BUS 12
22 #define IMX93_CLK_A55 13 22 #define IMX93_CLK_A55 13
23 #define IMX93_CLK_M33 14 23 #define IMX93_CLK_M33 14
24 #define IMX93_CLK_BUS_WAKEUP 15 24 #define IMX93_CLK_BUS_WAKEUP 15
25 #define IMX93_CLK_BUS_AON 16 25 #define IMX93_CLK_BUS_AON 16
26 #define IMX93_CLK_WAKEUP_AXI 17 26 #define IMX93_CLK_WAKEUP_AXI 17
27 #define IMX93_CLK_SWO_TRACE 18 27 #define IMX93_CLK_SWO_TRACE 18
28 #define IMX93_CLK_M33_SYSTICK 19 28 #define IMX93_CLK_M33_SYSTICK 19
29 #define IMX93_CLK_FLEXIO1 20 29 #define IMX93_CLK_FLEXIO1 20
30 #define IMX93_CLK_FLEXIO2 21 30 #define IMX93_CLK_FLEXIO2 21
>> 31 #define IMX93_CLK_LPIT1 22
>> 32 #define IMX93_CLK_LPIT2 23
31 #define IMX93_CLK_LPTMR1 24 33 #define IMX93_CLK_LPTMR1 24
32 #define IMX93_CLK_LPTMR2 25 34 #define IMX93_CLK_LPTMR2 25
>> 35 #define IMX93_CLK_TPM1 26
33 #define IMX93_CLK_TPM2 27 36 #define IMX93_CLK_TPM2 27
>> 37 #define IMX93_CLK_TPM3 28
34 #define IMX93_CLK_TPM4 29 38 #define IMX93_CLK_TPM4 29
35 #define IMX93_CLK_TPM5 30 39 #define IMX93_CLK_TPM5 30
36 #define IMX93_CLK_TPM6 31 40 #define IMX93_CLK_TPM6 31
37 #define IMX93_CLK_FLEXSPI1 32 41 #define IMX93_CLK_FLEXSPI1 32
38 #define IMX93_CLK_CAN1 33 42 #define IMX93_CLK_CAN1 33
39 #define IMX93_CLK_CAN2 34 43 #define IMX93_CLK_CAN2 34
40 #define IMX93_CLK_LPUART1 35 44 #define IMX93_CLK_LPUART1 35
41 #define IMX93_CLK_LPUART2 36 45 #define IMX93_CLK_LPUART2 36
42 #define IMX93_CLK_LPUART3 37 46 #define IMX93_CLK_LPUART3 37
43 #define IMX93_CLK_LPUART4 38 47 #define IMX93_CLK_LPUART4 38
44 #define IMX93_CLK_LPUART5 39 48 #define IMX93_CLK_LPUART5 39
45 #define IMX93_CLK_LPUART6 40 49 #define IMX93_CLK_LPUART6 40
46 #define IMX93_CLK_LPUART7 41 50 #define IMX93_CLK_LPUART7 41
47 #define IMX93_CLK_LPUART8 42 51 #define IMX93_CLK_LPUART8 42
48 #define IMX93_CLK_LPI2C1 43 52 #define IMX93_CLK_LPI2C1 43
49 #define IMX93_CLK_LPI2C2 44 53 #define IMX93_CLK_LPI2C2 44
50 #define IMX93_CLK_LPI2C3 45 54 #define IMX93_CLK_LPI2C3 45
51 #define IMX93_CLK_LPI2C4 46 55 #define IMX93_CLK_LPI2C4 46
52 #define IMX93_CLK_LPI2C5 47 56 #define IMX93_CLK_LPI2C5 47
53 #define IMX93_CLK_LPI2C6 48 57 #define IMX93_CLK_LPI2C6 48
54 #define IMX93_CLK_LPI2C7 49 58 #define IMX93_CLK_LPI2C7 49
55 #define IMX93_CLK_LPI2C8 50 59 #define IMX93_CLK_LPI2C8 50
56 #define IMX93_CLK_LPSPI1 51 60 #define IMX93_CLK_LPSPI1 51
57 #define IMX93_CLK_LPSPI2 52 61 #define IMX93_CLK_LPSPI2 52
58 #define IMX93_CLK_LPSPI3 53 62 #define IMX93_CLK_LPSPI3 53
59 #define IMX93_CLK_LPSPI4 54 63 #define IMX93_CLK_LPSPI4 54
60 #define IMX93_CLK_LPSPI5 55 64 #define IMX93_CLK_LPSPI5 55
61 #define IMX93_CLK_LPSPI6 56 65 #define IMX93_CLK_LPSPI6 56
62 #define IMX93_CLK_LPSPI7 57 66 #define IMX93_CLK_LPSPI7 57
63 #define IMX93_CLK_LPSPI8 58 67 #define IMX93_CLK_LPSPI8 58
64 #define IMX93_CLK_I3C1 59 68 #define IMX93_CLK_I3C1 59
65 #define IMX93_CLK_I3C2 60 69 #define IMX93_CLK_I3C2 60
66 #define IMX93_CLK_USDHC1 61 70 #define IMX93_CLK_USDHC1 61
67 #define IMX93_CLK_USDHC2 62 71 #define IMX93_CLK_USDHC2 62
68 #define IMX93_CLK_USDHC3 63 72 #define IMX93_CLK_USDHC3 63
69 #define IMX93_CLK_SAI1 64 73 #define IMX93_CLK_SAI1 64
70 #define IMX93_CLK_SAI2 65 74 #define IMX93_CLK_SAI2 65
71 #define IMX93_CLK_SAI3 66 75 #define IMX93_CLK_SAI3 66
72 #define IMX93_CLK_CCM_CKO1 67 76 #define IMX93_CLK_CCM_CKO1 67
73 #define IMX93_CLK_CCM_CKO2 68 77 #define IMX93_CLK_CCM_CKO2 68
74 #define IMX93_CLK_CCM_CKO3 69 78 #define IMX93_CLK_CCM_CKO3 69
75 #define IMX93_CLK_CCM_CKO4 70 79 #define IMX93_CLK_CCM_CKO4 70
76 #define IMX93_CLK_HSIO 71 80 #define IMX93_CLK_HSIO 71
77 #define IMX93_CLK_HSIO_USB_TEST_60M 72 81 #define IMX93_CLK_HSIO_USB_TEST_60M 72
78 #define IMX93_CLK_HSIO_ACSCAN_80M 73 82 #define IMX93_CLK_HSIO_ACSCAN_80M 73
79 #define IMX93_CLK_HSIO_ACSCAN_480M 74 83 #define IMX93_CLK_HSIO_ACSCAN_480M 74
80 #define IMX93_CLK_ML_APB 75 84 #define IMX93_CLK_ML_APB 75
81 #define IMX93_CLK_ML 76 85 #define IMX93_CLK_ML 76
82 #define IMX93_CLK_MEDIA_AXI 77 86 #define IMX93_CLK_MEDIA_AXI 77
83 #define IMX93_CLK_MEDIA_APB 78 87 #define IMX93_CLK_MEDIA_APB 78
84 #define IMX93_CLK_MEDIA_LDB 79 88 #define IMX93_CLK_MEDIA_LDB 79
85 #define IMX93_CLK_MEDIA_DISP_PIX 80 89 #define IMX93_CLK_MEDIA_DISP_PIX 80
86 #define IMX93_CLK_CAM_PIX 81 90 #define IMX93_CLK_CAM_PIX 81
87 #define IMX93_CLK_MIPI_TEST_BYTE 82 91 #define IMX93_CLK_MIPI_TEST_BYTE 82
88 #define IMX93_CLK_MIPI_PHY_CFG 83 92 #define IMX93_CLK_MIPI_PHY_CFG 83
89 #define IMX93_CLK_ADC 84 93 #define IMX93_CLK_ADC 84
90 #define IMX93_CLK_PDM 85 94 #define IMX93_CLK_PDM 85
91 #define IMX93_CLK_TSTMR1 86 95 #define IMX93_CLK_TSTMR1 86
92 #define IMX93_CLK_TSTMR2 87 96 #define IMX93_CLK_TSTMR2 87
93 #define IMX93_CLK_MQS1 88 97 #define IMX93_CLK_MQS1 88
94 #define IMX93_CLK_MQS2 89 98 #define IMX93_CLK_MQS2 89
95 #define IMX93_CLK_AUDIO_XCVR 90 99 #define IMX93_CLK_AUDIO_XCVR 90
96 #define IMX93_CLK_SPDIF 91 100 #define IMX93_CLK_SPDIF 91
97 #define IMX93_CLK_ENET 92 101 #define IMX93_CLK_ENET 92
98 #define IMX93_CLK_ENET_TIMER1 93 102 #define IMX93_CLK_ENET_TIMER1 93
99 #define IMX93_CLK_ENET_TIMER2 94 103 #define IMX93_CLK_ENET_TIMER2 94
100 #define IMX93_CLK_ENET_REF 95 104 #define IMX93_CLK_ENET_REF 95
101 #define IMX93_CLK_ENET_REF_PHY 96 105 #define IMX93_CLK_ENET_REF_PHY 96
102 #define IMX93_CLK_I3C1_SLOW 97 106 #define IMX93_CLK_I3C1_SLOW 97
103 #define IMX93_CLK_I3C2_SLOW 98 107 #define IMX93_CLK_I3C2_SLOW 98
104 #define IMX93_CLK_USB_PHY_BURUNIN 99 108 #define IMX93_CLK_USB_PHY_BURUNIN 99
105 #define IMX93_CLK_PAL_CAME_SCAN 100 109 #define IMX93_CLK_PAL_CAME_SCAN 100
106 #define IMX93_CLK_A55_GATE 101 110 #define IMX93_CLK_A55_GATE 101
107 #define IMX93_CLK_CM33_GATE 102 111 #define IMX93_CLK_CM33_GATE 102
108 #define IMX93_CLK_ADC1_GATE 103 112 #define IMX93_CLK_ADC1_GATE 103
109 #define IMX93_CLK_WDOG1_GATE 104 113 #define IMX93_CLK_WDOG1_GATE 104
110 #define IMX93_CLK_WDOG2_GATE 105 114 #define IMX93_CLK_WDOG2_GATE 105
111 #define IMX93_CLK_WDOG3_GATE 106 115 #define IMX93_CLK_WDOG3_GATE 106
112 #define IMX93_CLK_WDOG4_GATE 107 116 #define IMX93_CLK_WDOG4_GATE 107
113 #define IMX93_CLK_WDOG5_GATE 108 117 #define IMX93_CLK_WDOG5_GATE 108
114 #define IMX93_CLK_SEMA1_GATE 109 118 #define IMX93_CLK_SEMA1_GATE 109
115 #define IMX93_CLK_SEMA2_GATE 110 119 #define IMX93_CLK_SEMA2_GATE 110
116 #define IMX93_CLK_MU_A_GATE 111 120 #define IMX93_CLK_MU_A_GATE 111
117 #define IMX93_CLK_MU_B_GATE 112 121 #define IMX93_CLK_MU_B_GATE 112
118 #define IMX93_CLK_EDMA1_GATE 113 122 #define IMX93_CLK_EDMA1_GATE 113
119 #define IMX93_CLK_EDMA2_GATE 114 123 #define IMX93_CLK_EDMA2_GATE 114
120 #define IMX93_CLK_FLEXSPI1_GATE 115 124 #define IMX93_CLK_FLEXSPI1_GATE 115
121 #define IMX93_CLK_GPIO1_GATE 116 125 #define IMX93_CLK_GPIO1_GATE 116
122 #define IMX93_CLK_GPIO2_GATE 117 126 #define IMX93_CLK_GPIO2_GATE 117
123 #define IMX93_CLK_GPIO3_GATE 118 127 #define IMX93_CLK_GPIO3_GATE 118
124 #define IMX93_CLK_GPIO4_GATE 119 128 #define IMX93_CLK_GPIO4_GATE 119
125 #define IMX93_CLK_FLEXIO1_GATE 120 129 #define IMX93_CLK_FLEXIO1_GATE 120
126 #define IMX93_CLK_FLEXIO2_GATE 121 130 #define IMX93_CLK_FLEXIO2_GATE 121
127 #define IMX93_CLK_LPIT1_GATE 122 131 #define IMX93_CLK_LPIT1_GATE 122
128 #define IMX93_CLK_LPIT2_GATE 123 132 #define IMX93_CLK_LPIT2_GATE 123
129 #define IMX93_CLK_LPTMR1_GATE 124 133 #define IMX93_CLK_LPTMR1_GATE 124
130 #define IMX93_CLK_LPTMR2_GATE 125 134 #define IMX93_CLK_LPTMR2_GATE 125
131 #define IMX93_CLK_TPM1_GATE 126 135 #define IMX93_CLK_TPM1_GATE 126
132 #define IMX93_CLK_TPM2_GATE 127 136 #define IMX93_CLK_TPM2_GATE 127
133 #define IMX93_CLK_TPM3_GATE 128 137 #define IMX93_CLK_TPM3_GATE 128
134 #define IMX93_CLK_TPM4_GATE 129 138 #define IMX93_CLK_TPM4_GATE 129
135 #define IMX93_CLK_TPM5_GATE 130 139 #define IMX93_CLK_TPM5_GATE 130
136 #define IMX93_CLK_TPM6_GATE 131 140 #define IMX93_CLK_TPM6_GATE 131
137 #define IMX93_CLK_CAN1_GATE 132 141 #define IMX93_CLK_CAN1_GATE 132
138 #define IMX93_CLK_CAN2_GATE 133 142 #define IMX93_CLK_CAN2_GATE 133
139 #define IMX93_CLK_LPUART1_GATE 134 143 #define IMX93_CLK_LPUART1_GATE 134
140 #define IMX93_CLK_LPUART2_GATE 135 144 #define IMX93_CLK_LPUART2_GATE 135
141 #define IMX93_CLK_LPUART3_GATE 136 145 #define IMX93_CLK_LPUART3_GATE 136
142 #define IMX93_CLK_LPUART4_GATE 137 146 #define IMX93_CLK_LPUART4_GATE 137
143 #define IMX93_CLK_LPUART5_GATE 138 147 #define IMX93_CLK_LPUART5_GATE 138
144 #define IMX93_CLK_LPUART6_GATE 139 148 #define IMX93_CLK_LPUART6_GATE 139
145 #define IMX93_CLK_LPUART7_GATE 140 149 #define IMX93_CLK_LPUART7_GATE 140
146 #define IMX93_CLK_LPUART8_GATE 141 150 #define IMX93_CLK_LPUART8_GATE 141
147 #define IMX93_CLK_LPI2C1_GATE 142 151 #define IMX93_CLK_LPI2C1_GATE 142
148 #define IMX93_CLK_LPI2C2_GATE 143 152 #define IMX93_CLK_LPI2C2_GATE 143
149 #define IMX93_CLK_LPI2C3_GATE 144 153 #define IMX93_CLK_LPI2C3_GATE 144
150 #define IMX93_CLK_LPI2C4_GATE 145 154 #define IMX93_CLK_LPI2C4_GATE 145
151 #define IMX93_CLK_LPI2C5_GATE 146 155 #define IMX93_CLK_LPI2C5_GATE 146
152 #define IMX93_CLK_LPI2C6_GATE 147 156 #define IMX93_CLK_LPI2C6_GATE 147
153 #define IMX93_CLK_LPI2C7_GATE 148 157 #define IMX93_CLK_LPI2C7_GATE 148
154 #define IMX93_CLK_LPI2C8_GATE 149 158 #define IMX93_CLK_LPI2C8_GATE 149
155 #define IMX93_CLK_LPSPI1_GATE 150 159 #define IMX93_CLK_LPSPI1_GATE 150
156 #define IMX93_CLK_LPSPI2_GATE 151 160 #define IMX93_CLK_LPSPI2_GATE 151
157 #define IMX93_CLK_LPSPI3_GATE 152 161 #define IMX93_CLK_LPSPI3_GATE 152
158 #define IMX93_CLK_LPSPI4_GATE 153 162 #define IMX93_CLK_LPSPI4_GATE 153
159 #define IMX93_CLK_LPSPI5_GATE 154 163 #define IMX93_CLK_LPSPI5_GATE 154
160 #define IMX93_CLK_LPSPI6_GATE 155 164 #define IMX93_CLK_LPSPI6_GATE 155
161 #define IMX93_CLK_LPSPI7_GATE 156 165 #define IMX93_CLK_LPSPI7_GATE 156
162 #define IMX93_CLK_LPSPI8_GATE 157 166 #define IMX93_CLK_LPSPI8_GATE 157
163 #define IMX93_CLK_I3C1_GATE 158 167 #define IMX93_CLK_I3C1_GATE 158
164 #define IMX93_CLK_I3C2_GATE 159 168 #define IMX93_CLK_I3C2_GATE 159
165 #define IMX93_CLK_USDHC1_GATE 160 169 #define IMX93_CLK_USDHC1_GATE 160
166 #define IMX93_CLK_USDHC2_GATE 161 170 #define IMX93_CLK_USDHC2_GATE 161
167 #define IMX93_CLK_USDHC3_GATE 162 171 #define IMX93_CLK_USDHC3_GATE 162
168 #define IMX93_CLK_SAI1_GATE 163 172 #define IMX93_CLK_SAI1_GATE 163
169 #define IMX93_CLK_SAI2_GATE 164 173 #define IMX93_CLK_SAI2_GATE 164
170 #define IMX93_CLK_SAI3_GATE 165 174 #define IMX93_CLK_SAI3_GATE 165
171 #define IMX93_CLK_MIPI_CSI_GATE 166 175 #define IMX93_CLK_MIPI_CSI_GATE 166
172 #define IMX93_CLK_MIPI_DSI_GATE 167 176 #define IMX93_CLK_MIPI_DSI_GATE 167
173 #define IMX93_CLK_LVDS_GATE 168 177 #define IMX93_CLK_LVDS_GATE 168
174 #define IMX93_CLK_LCDIF_GATE 169 178 #define IMX93_CLK_LCDIF_GATE 169
175 #define IMX93_CLK_PXP_GATE 170 179 #define IMX93_CLK_PXP_GATE 170
176 #define IMX93_CLK_ISI_GATE 171 180 #define IMX93_CLK_ISI_GATE 171
177 #define IMX93_CLK_NIC_MEDIA_GATE 172 181 #define IMX93_CLK_NIC_MEDIA_GATE 172
178 #define IMX93_CLK_USB_CONTROLLER_GATE 173 182 #define IMX93_CLK_USB_CONTROLLER_GATE 173
179 #define IMX93_CLK_USB_TEST_60M_GATE 174 183 #define IMX93_CLK_USB_TEST_60M_GATE 174
180 #define IMX93_CLK_HSIO_TROUT_24M_GATE 175 184 #define IMX93_CLK_HSIO_TROUT_24M_GATE 175
181 #define IMX93_CLK_PDM_GATE 176 185 #define IMX93_CLK_PDM_GATE 176
182 #define IMX93_CLK_MQS1_GATE 177 186 #define IMX93_CLK_MQS1_GATE 177
183 #define IMX93_CLK_MQS2_GATE 178 187 #define IMX93_CLK_MQS2_GATE 178
184 #define IMX93_CLK_AUD_XCVR_GATE 179 188 #define IMX93_CLK_AUD_XCVR_GATE 179
185 #define IMX93_CLK_SPDIF_GATE 180 189 #define IMX93_CLK_SPDIF_GATE 180
186 #define IMX93_CLK_HSIO_32K_GATE 181 190 #define IMX93_CLK_HSIO_32K_GATE 181
187 #define IMX93_CLK_ENET1_GATE 182 191 #define IMX93_CLK_ENET1_GATE 182
188 #define IMX93_CLK_ENET_QOS_GATE 183 192 #define IMX93_CLK_ENET_QOS_GATE 183
189 #define IMX93_CLK_SYS_CNT_GATE 184 193 #define IMX93_CLK_SYS_CNT_GATE 184
190 #define IMX93_CLK_TSTMR1_GATE 185 194 #define IMX93_CLK_TSTMR1_GATE 185
191 #define IMX93_CLK_TSTMR2_GATE 186 195 #define IMX93_CLK_TSTMR2_GATE 186
192 #define IMX93_CLK_TMC_GATE 187 196 #define IMX93_CLK_TMC_GATE 187
193 #define IMX93_CLK_PMRO_GATE 188 197 #define IMX93_CLK_PMRO_GATE 188
194 #define IMX93_CLK_32K 189 198 #define IMX93_CLK_32K 189
195 #define IMX93_CLK_SAI1_IPG 190 199 #define IMX93_CLK_SAI1_IPG 190
196 #define IMX93_CLK_SAI2_IPG 191 200 #define IMX93_CLK_SAI2_IPG 191
197 #define IMX93_CLK_SAI3_IPG 192 201 #define IMX93_CLK_SAI3_IPG 192
198 #define IMX93_CLK_MU1_A_GATE 193 202 #define IMX93_CLK_MU1_A_GATE 193
199 #define IMX93_CLK_MU1_B_GATE 194 203 #define IMX93_CLK_MU1_B_GATE 194
200 #define IMX93_CLK_MU2_A_GATE 195 204 #define IMX93_CLK_MU2_A_GATE 195
201 #define IMX93_CLK_MU2_B_GATE 196 205 #define IMX93_CLK_MU2_B_GATE 196
202 #define IMX93_CLK_NIC_AXI 197 !! 206 #define IMX93_CLK_END 197
203 #define IMX93_CLK_ARM_PLL 198 <<
204 #define IMX93_CLK_A55_SEL 199 <<
205 #define IMX93_CLK_A55_CORE 200 <<
206 #define IMX93_CLK_PDM_IPG 201 <<
207 #define IMX93_CLK_END 202 <<
208 207
209 #endif 208 #endif
210 209
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